US3771220A - Method of making a plated wire array - Google Patents

Abstract

The purpose of the invention is to produce a plated wire array mat which is simpler to fabricate, permits higher packing densities, and reduces the required strap drive currents over the present array mat techniques. The structure permits the positioning of ferrite keeper material in closely adjacent and fully surrounded relationship to the plated wire so as to minimize straying magnetic fields, thereby allowing higher packing densities and lower drive currents to be used. The fabrication technique utilizes highly precise photographic techniques to build a simple tunnel structure array utilizing photolithic layers, exposure, and wash thereof to achieve the desired structural relationship.

Description

United States Patent [1 1 Shannon et al.

[ Nov. 13, 1973 METHOD OF MAKING A PLATED wnu:

ARRAY [75] Inventors: Joseph A. Shannon, Akron; Anthony M. Apicella, Massillon; John T. Franks, Jr., Tallmadge, all of Ohio [73] Assignee: Goodyear Aerospace Corporation,

Akron, Ohio [22] Filed: May 5,1972

21 Appl. No.: 250,708

[52] US. Cl. 29/604, 340/174 PW, 340/174 BC [51] Int. Cl. H01! 7/06 [58] Field of Search 29/604, 625;

340/174 PW, l74 TF, 174 BC, 174 MA [56] References Cited UNITED STATES PATENTS 3,708,874 1/1973 Parks 29/604 3,604,109 9/1971 Crimmins.. 29/604 3,559,284 2/l97l Neuhaus... 29/604 5/1972 Olyphant, Jr. et al... 340/174 PW X 2/1973 Shaheen et al. 29/604 Primary Examiner-Charles W. Lanham Assistant Examiner-Carl E. Hall Attorney-J. G. Pere [57] ABSTRACT The purpose of the invention is to produce a plated wire array mat which is simpler to fabricate, permits higher packing densities, and reduces the required strap drive currents over the present array mat techniques. The structure permits the positioning of ferrite keeper material in closely adjacent and fully surrounded relationship to the plated wire so. as to minimize straying magnetic fields, thereby allowing higher packing densities and lower drive currents to be used. The fabrication technique utilizes highly precise photographic techniques to build a simple tunnel structure array utilizing photolithic layers, exposure, and wash thereof toachieve the desired structural relationship.

4 Claims, 12 Drawing Figures IIIIIIII/II/I II p Y III/ III/III III/Il/JIII/I/ 1 METHOD OF MAKING A PLATED WIRE ARRAY Heretofore, it has been known that one of the difficulties in forming plated wire memories is manufacture of the tunnel structure to receive the plated wires and actually positioning the plated wires into the tunnel structure without damaging the wires and the delicate plating thereon. The problems heretofore have led to slow fabrication, high damage to the plated wire, and thus, extremely high plated wire memory expense. Further, with the techniques known heretofore, the reliability of the platedwire memories made in the conventional way has been quite low because of the damage occurring to the plated wires being positioned in the tunnel structure.

The basic object of the present invention is to improve upon and avoid the problems inherent in the prior art structures by producing a tunnel structure for plated wire which permits precise alignment of the plated wire so that higher packing densities may be obtained, with greatly reduced damage to the plated wires, and thereby, much greater reliability of the finished memory structure.

A further object of the invention is to provide a lower characteristic impedance of the plated wire strap drivers thus reducing the drive voltage and current requirements.

A further object of the invention is to provide a plated wire memory structure which has reduced propogation delay resulting in maximum operating speed, low losses resulting in fast rise time of the bits, and a more intimate relationship of keeper material to eliminate negative adjacent bit disturb pulses.

A further object of the invention is to achieve a short wire length thereby further reducing propogation delay, increasing memory speed, reducing signal attenuation, and achieving a lower cost per bit because of the shorter plated wire lengths achieved by the higher packing density.

A further object of the invention is to enhance the mechanical construction of the units to in effect make it substantially semi-automatic thereby reducing costs, which techniques further substantially eliminate abrasion of the wire, thereby incurring fewer bit failures.

A further object of the process of the invention is to eliminate the conventional closed tunnels heretofore known in tunnel structures, thereby allowing higher packing densities in the wire direction, and achieving a substantially automated fabrication.

The aforesaid and other objects of the invention which will become apparent as the description proceeds are achieved by utilizing a copper clad base structure into which plated wires are directly placed to form an array mat. The structure has grooves which are formed by a photographic etching technique, but which grooves are really a plurality of posts formed in a grid type pattern on the copper clad base. When the base is etched, plated wires may be placed appropriately with respect to the post structure by vacuum technique, and with the aid of a microscope so that abrasion to the plated wire is sbustantially eliminated. The circuitry for the straps, strap take off pads and wire terminations and takeoffs are etched onto the copper clad base structure. The wires are then soldered or welded into place. The top half of the structure is then positioned, which conforms exactly in alignment with the bottom half, except that the posts are not present. The structure is then sprayed with keeper material completing the assembly. This assembly permits automated welding and soldering techniques to be utilized, thereby permitting simpler and faster assembly of array mats, much tighter packing densities of the plated wire, and reduces the strap drive current.

For a better understanding of the invention, reference should be had to the accompanying drawings wherein:

FIG. 1 is a greatly enlarged crosssectional illustration of the resultant plated wire array made in accordance with the techniques of the invention;

FIG. 2 is a cross-sectional illustration of the first laminate configuration comprising the first step of the process of the invention;

FIGS. 3 and 4 are greatly enlarged broken away plan views of negatives utilized to expose the laminate of FIG. 2;

FIG. 5 is a greatly enarged cross-sectional illustration of the laminate of FIG. 2 after it has been exposed with the negatives of FIGS. 3 and 4, and developed;

FIG. 6 is a greatly enlarged cross-sectional illustration showing the next step in the process. of the invention as continuing from FIG. 5;

FIG. 7 is an enlarged plan view of negative No. 3 with which the additional layer in FIG. 6 is exposed;

FIG. 8 is a greatly enlarged cross-sectional view of the embodiment of FIG. 6 after it has been exposed with the negative of FIG. 7 and developed;

FIG. 9 is a greatly enlarged cross-sectional view illustrating a top laminate and its association with the laminate of FIG. 8;

FIG. 10 is a greatly enlarged cross-sectional illustration of the embodiment of FIG. 9 with the metal layer having been appropriately acid etched, and showing the plated wires in position;

plated wires are positioned into the laminate structure, and the final assembly takes place;

FIG. 12 is a cross-sectional view of the laminated structure mounted adjacent a printed circuit board.

With reference to the embodiment of the invention illustrated in FIG. 1 of the drawings, thenumeral 10 represents a brass layer between 0.0005 to 0.005 inch thickness, and an arbitrary length and width depending upon the exact size of the plated wire array structure desired to be fabricated. The numerals 12 and 14 identify layers of photolithic film having a thickness of between 0.0005 to 0.00075 inch thickness, which is coated by appropriate techniques to the brass base layer 10.

The invention contemplates that the layer 12 will be exposed with negative 1 illustrated in FIG. 3 over sub- IG-.11 isapsrsa stivqyiw illu o tbs.

stantially its entire surface, and layer 14 is exposed with negative 2 over substantially its entire surface. Negatives l and 2 both contain take off wire artwork in the conventional manner, but this is omitted from FIGS. 3 and 4 because it is well known and understood by those skilled in the art. The take off wires are shown in FIG. 1 1 and are more fully described hereinafter. It is anticipated that both negatives 1 and 2 will be provided with appropriate registration holes such as aldus, or the like, so that exact registration will occur with these patterns on both of layers 12 and 14. The invention contemplates that the opaque lines of negative I illustrated by numeral 16 will have a width of about 0.010 inch while the clear lines illustrated by numeral 18 will have a width of approximately 0.005 inch. This same space relationship will apply to opaque lines 16a and clear lines 18a in negative 2. In other words, these lines should have exactly the same space relationship between negatives 1 and 2, even though it does not have to be the 0.005 to 0.010 inch relationship described above. The other distinguishing characteristic to negative 2 is a plurality of clear cross lines 20 which are aligned laterally with each other and have a spacing of apprximately 0.010 inch from center to center. The purpose of cross lines 20 shall become apparent as the description proceeds. The cross lines 20 will have a width about half the width of the clear lines l8 and 18a.

In order to further enhance the extreme accuracy of the artwork, the invention contemplates that both negatives l and 2 are made from the same piece of artwork, with the only differences being the cross lines 20 added in negative 2, and the usual printed circuit board offset at the ends of the lines to permit soldering between upper and lower straps. With the use of the proper aldus registration holes, extreme accuracy between the top and bottom exposure of the photolithic layers 12 and 14 is achieved.

One other slight difference is believed important with respect to negative 2, and that is that it is made from the same artwork as negative 1, except the emulsion is reversed, whereby the emulsion side of the artwork is always toward the brass base layer 10 when it is positioned to achieve a contact printed relationship by light exposure in the normal contact printed technique. This insures less discrepancy in the contact printing, and thereby, greater accuracy.

It is thus seen that when the laminate structure of FIG. 2 is exposed by contact printing techniques with negatives 1 and 2, and these photolithic layers 12 and 14 then developed, a plurality of longitudinally extending ribs 22 are formed on the top surface of base layer 10, and ribs 24 on the bottom layer of base layer 10 with small cross ridges 26 extending between ribs 24 on the bottom.

The next step in the process is to add a photolithic layer 28 on top of the ribs 22, and expose this by contact printing with negative 3 of FIG. 7. This step is illustrated in FIG. 6. It should be pointed out that the artwork of negative 3 comprises a series of clear rectangles 30 carried in a grid-like pattern arranged on an opaque background 32. The negative 3 is likewise aligned with the appropriate aldus registration holes, and squares 30 fall in direct longitudinal alignment with the ribs 22, and in direct lateral alignment with the ribs 26 formed by the clear portions 20 of negative 2 as seen in FIG. 4. Therefore, when layer 28 is developed, a plurality of posts 34 are formed on top of ribs 22 in exact registration with cross ribs 26 and of the same width thereof to achieve a grid-like post network.

The invention contemplates that one or more additional layers 28 of FIG. 6 may then be added, appropriately exposed with negative 3, developed, so as to build the posts to a height of about 0.005 inch or to a height of substantially the diameter of the plated wire. Usually the invention contemplates that the plated wire will be of about 0.005 inch diameter, but as techniques develop in the future, the diameter of the plated wire may reduce in size, to 0.002 inch for example, and hence the post pattern should be built in height to substantially the diameter of the plated wire.

The next step in the fabrication technique is to provide a top or cover laminate which coincides exactly with the laminate of FIG. 8 except that posts 34 have not been fabricated thereupon. However, the same artwork is utilized so that exact registration occurs. Again, the same negative reversing takes place, however, so that the best contact printing techniques are still utilized. FIG. 9 illustrates this top laminate with brass layer 40, top photolithic layer 42 exposed with negative 2 and bottom photolithic layer 44 exposed with negative 1, and developed. The ribs 42 and 43 formed on the top of brass layer 40 thus fall into exactregistered alignment with the posts formed and associated with brass base layer 10, all as seen in FIG. 9.

The next step is accomplished by normally mounting the base structure indicated generally by numeral 50 in FIG. 11, but comprising that portion indicated by bracketed numeral 50 in FIG. 10 to a conventional glass epoxy printed circuit board indicated by numeral 52, at a central cutout square or rectangular portion 52a of such board, all is clearly shown in FIG. 12. The board 52 has strap takeoff lines 54 formed thereon utilizing conventional printed circuit techniques, and plated wire takeoff lines 56, which cooperate with V- shaped grooves 58 formed by photolithic raised ribs 58a onto the board 52 and which then receive the plated wire from the composite laminate 50 which is positioned to cover or overlay the opening 520 and held in position by an adhesive layer 59 at this point of fabrication. The overlay relation of laminate 50 to the board 52 is better seen in the cross-sectional view of FIG. 12.

The next step is then to actually etch the brass layers 10 and 40 so as to in effect form a plurality of brass straps 10a to the layer 10 andstraps 40a of the layer 40, all as seen in FIG. 10. It should be noted, however, that at this point the straps 10a and 40a are held in their lateral relationship by the cross ridges 26 and 43. With etching of the copper clad or brass base accomplished as shown in FIG. 10, the bottom laminated section with the posts formed thereon is then completed so as to allow positioning of the plated wire between the post patterns.

PLATED WIRE POSITIONING The plated wires are then cut to a predetermined length indicated as distance 60 at the bottom of board 52 in FIG. 11 which distance extends from the ends of the grooves 58 across the full width of openings 52a. It should be pointed out that the grooves 58 come into exact alignment with the space between the posts 34 on the composite laminate 50. Hence, plated wire layed down in the grooves established by the posts 34 on the laminate 50 will coincide and align with the grooves 58 on board 52. The laminate 50 is positioned so that the level from the bottom of the grooves 58 coincides with the plane defined by the top surface of the ribs 22 whereby when the plated wires are exactly aligned they will take the position illustrated in FIGS. 1, l0, and 12 with an exact straight supported alignment from their relationship through the post pattern 34 into the grooves 58.

Normally, the invention contemplates that the wires, indicated by numeral in FIGS. 10 and 12 will be manually positioned with the aid of a microscope to get the wires into the proper groove defined by the gridlike configuration of posts 34. It may be of assistance in actually positioning the plated wires to utilize a hon-. eycomb configuration illustrated by numeral 72 over which the printed circuit board 52 is positioned with a vacuum being drawn through the honeycomb 72 which covers the entire open surface of opening 52a so that the plated wires are sucked by the vacuum down into and held in position in the grooves established by posts 34 and the grooves 58. The honeycomb 72 extends into the opening 52a and actually supports the bottom of substrate 50 so it maintains its aligned relation with the board 52 without sagging. It is not necessary to utilize the vacuum hold down technique, although it does simplify fabrication since the plated wires are so small that they do tend to perhaps fall out of position even upon a breeze through the area of fabrication.

With the plated wires appropriately positioned, a small weld is then made at point 59 between the wire takeoffs 56 formed by printed circuit techniques on board 52 and the end of the plated wires in groove 58, all as best seen in FIG. 11. The top laminate indicated generally by numeral 75 in FIG. is then accurately positioned over the top of the plated wire so that the ribs 40a lie exactly on the top of the post 34 whereby the strap defined by the combination of ribs 10a and 40a are in exact vertical alignment over the exact same portion of the plated wire with which they are respectively associated. The technique of then forming the actual loop between brass ribs 10a and 40a is very simply accomplished by connecting the appropriate takeoff wires 54 so as to achieve the looped configuration well known and understood by those skilled in the art to provide the read and interrogate functions for a memory configuration of a general purpose digital computer, or an associative memory bank.

The fabrication is completed by achieving the configuration shown in FIG. 1 which includes filling all voids between the post pattern and the etched out brass portions of the base layers 10 and 40 with a ferrite keeper material indicated generally in FIG. 1 by numeral 80. Note that the other component layers of FIG. 1 are not seen because of the cross-sectional view taken to show the ferrite keeper material in the void positions, but that they .are indicated by dotted lines and the appropriate numbers associated therewith.

The invention contemplates that the exposed portions of the board 52 in FIG. l2-will be masked off so that the ferrite keeper in effect only covers the plated wire array filling the open space 52a. The keeper material layer 80 will have a thickness of between 0.005 to 0.010 inch. The preferable material that has been successfully utilized is an Electronic Memories and Magnetics H material which can be purchased commercially, but we have found that it is necessary to grind it to a finer configuration to pass through a 325 mesh standard screen from about the 60 mesh configuration which it is when purchased commercially. The H material when ground to this configuration is then mixed with acetone and sprayed from a conventional paint spray gun onto each side to form the matrix configuration shown in FIG. 1 which substantially fills all voids and places the keeper material in intimate relationship with the plated wire and the driving straps. It is this intimate relationship and in effect the full surrounding of the plated wire and the driving straps that allows the closer packing density, lower driving currents, and the like because the ferrite keeper reduces the magnetic field spreading which is normally present in a conventional tunnel structure configuration for plated wire arrays.

In order to hold the ferrite keeper in position, a spray layer 82 is added to each surface. The layer 82 that we have found most effective is some type of water soluble spray that tends to be sticky and somewhat cohesive with the keeper material 80, and which is at least partially absorbed into the exposed surfaces thereof to tend to achieve the matrix configuration. A typical spray that we have found quite effective is Sauve hair spray as made by Helene Curtis; however, it is clearly intended that other suitable spray layers might be appropriately utilized. The laminate configuration of the plated wire array is then completed by adding a metadlic layer 84 which preferably might be a 0.001 inch copper foil adhesively adhered to act as a ground plane.

Hence, it should be understood that the fabrication technique provides a unique plated wire memory array which is able to have the wires positioned on 0.010 inch centers, and which conceivably if wire sizes reduce could go to smaller configurations'Further with the techniques of the invention the straps are positioned on 0.015 centers so that bit density can be greatly increased, and drive currents and power requirements greatly reduced. This is achieved by the use of the ferrite keeper to completely surround the wires and straps as shown in FIG. 1 so that all flux is maintained for working on the particular bit of the plated wire, rather than being dispersed into space.

While a ferrite keeper appears to be best, any high resistivity, high permeability material which would perform the same magnetic flux absorbing features could also be utilized, such as for example, carbonyl iron, or any other appropriate material having the properties defined above.

It is important with respect to the ferrite keeper that the particle size be reduced, but not necessarily to a completely powdered configuration. It appears that the particles must have some size in order to achieve a clinging relationship when they are sprayed into position to the nooks and crannies formed in laminate sections 50 and 75. We have found that a completely p'owdered configuration tends to separate and blow off quickly and the intimate contact relationship desired is not achieved. Further, as the particles are broken down to an extremely fine size, the permeabilities thereof are greatly reduced. Hence, as small a particle size as possible without affecting the permeability or the sticking characteristics of the ferrite is the desirable configuration.

Therefore, it should be understood that the invention provides the following advantages in a plated memory array:

l. A lower characteristic impedance of the straps thereby reducing drive voltage requirements.

2. A lower strap currentrequirements thus reducing the power requirements.

3. Reduced propogation delay resulting in maximum operating speed of the system.

4. Low flux and hysteresis losses because of the ferrite keeper resulting in fast rise times.

5. A close spacing (adjacent at .015 inch strap center configuration) results in lower drive currents.

6. Close spacing and the ferrite keeper geometry eliminates adjacent bit disturbances thereby giving more reliable signal outputs.

7. Elimination of adjacent bit disturbs allow higher packing-densities.

The following advantages are inherent in the type of wire which might be utilized in this plated wire array:

. l. A lower characteristic impedance thus reducing the write voltage requirements.

2. Low losses resulting in a fast switching of the signal within the wire.

3. The ferrite keeper isolation reduces interwire coupling.

4. A short wire length reduces propogation delay.

5. A reduced propogation delay results in faster operating speeds.

6. The short wire line reduces noise pickup. 7. The short line reduces signal attenuation.

8. A lower cost per bit is achieved because of the shorter plated wire lengths.

The following mechanical improvements are achieved by utilizing the process to manufacture the structure defined above:

1. Elimination of tunnels results in no abrasion of the plated wire, and thus fewer bit failures. 2. The smaller structure results in a higher mechanical strength to the plated circuit board and the wire array. 3. The elimination of the tunnels results in a higher packing density in the wire direction. A 0.010 inch center to center wire spacing and 0.015 inch center to center strap spacing has not been possible heretofore. 4. A substantially completely automated fabrication is possible because of the tunnel elimination. To this end, automatic welding at point 59 between the plated wire and the takeoff can be accomplished, as well as an automatic welding of the takeoff wires 54 associated with the straps. 5. A single source artwork results in no alignment problems between the wires and the posts, this insuring extreme accuracy and high reliability of the operating array.

While in accordance with the patent statutes only the best known embodiments of the invention have been illustrated and described in detail, it is to be understood that the invention is not limited thereto or thereby, but that the inventive scope is defined in the appended claims.

What is claimed is: l. A'method for forming a plated wire memory array consisting of the steps of a. forming a first plurality of parallel spaced ribs of insulative film onto a first thin conductive metal base; i

b. forming a grid-like pattern of posts on said base, said posts rising from top surfaces of said ribs in substantially uniformly spaced relationship to each other, said posts having substantially the same height as the diameter of-the plated wires which are to be subsequently positioned therebetween;

c. etching said first metal base to remove the metal exposed between said first plurality of ribs so as to form a first plurality of parallel, spaced straps from said first base;

d. maintaining said ribs and said straps in the spatial relationship in which they were formed;

e. positioning plated wires between the posts in substantially parallel relationship to each other and substantially perpendicular to the ribs;

f. performing the operations of steps (a), (c) and (d) on a second thin conductive metal base thereby providing a second plurality of parallel, spaced ribs of-insulative film and a second plurality-of parallel, spaced straps; I

g. positioning the substrate developed by step (e) into operatively aligned position on top of the posts with said second plurality of ribs adjacent said posts and aligned with said first plurality of ribs;

h. positioning a high permeability, high resistivity material into all voids of the composite so as to substantially completely surround the plated wires and the electrically conductive straps;

i. forming a ground plane for the keeper material;

j. electrically connecting corresponding straps of said first and second pluralities of straps at one end so as to form electrically conductive loops from respective pairs of straps around the plated wires associated in perpendicular relationship thereto.

2. A method according to claim 1 where the plated wire has a diameter of approxiamtely 0.005 inch and the heightv and spacing between posts is substantially 0.005 inch.

3. A method according to claim 2 where the keeper material is a ferrite keeper having the ability to pass a 325 mesh, and includes a step of spraying the keeper with an acetone solvent associated therewith into intimate position with the plated wires and the straps.

4. A method according to claim 3 which includes a step of spraying a holding coating of a water soluble absorbent type material onto the exterior of the keeper material to hold it into intimate relation with the plate wire and straps.

* t: t i i

Claims (4)

1. A method for forming a plated wire memory array consisting of the steps of a. forming a first plurality of parallel spaced ribs of insulative film onto a first thin conductive metal base; b. forming a grid-like pattern of posts on said base, said posts rising from top surfaces of said ribs in substantially uniformly spaced relationship to each other, said posts having substantially the same height as the diameter of the plated wires which are to be subsequently positioned therebetween; c. etching said first metal base to remove the metal exposed between said first plurality of ribs so as to form a first plurality of parallel, spaced straps from said first base; d. maintaining said ribs and said straps in the spatial relationship in which they were formed; e. positioning plated wires between the posts in substantially parallel relationship to each other and substantially perpendicular to the ribs; f. performing the operations of steps (a), (c) and (d) on a second thin conductive metal base thereby providing a second plurality of parallel, spaced ribs of insulative film and a second plurality of parallel, spaced straps; g. positioning the substrate developed by step (e) into operatively aligned position on top of the posts with said second plurality of ribs adjacent said posts and aligned with said first plurality of ribs; h. positioning a high permeability, high resistivity material into all voids of the composite so as to substantially completely surround the plated wires and the electrically conductive straps; i. forming a ground plane for the keeper material; j. electrically connecting corresponding straps of said first and second pluralities of straps at one end so as to form electrically conductive loops from respective pairs of straps around the plated wires associated in perpendicular relationship thereto.

2. A method according to claim 1 where the plated wire has a diameter of approxiamtely 0.005 inch and the height and spacing between posts is substantially 0.005 inch.

3. A method according to claim 2 where the keeper material is a ferrite keeper having the ability to pass a 325 mesh, and includes a step of spraying the keeper with an acetone solvent associated therewith into intimate position with the plated wires and the straps.

4. A method according to claim 3 which includes a step of spraying a holding coating of a water soluble absorbent-type material onto the exterior of the keeper material to hold it into intimate relation with the plated wire and straps.

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