US3710029A - Switching arrangement for a data processing installation - Google Patents

Switching arrangement for a data processing installation Download PDF

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Publication number
US3710029A
US3710029A US00104275A US3710029DA US3710029A US 3710029 A US3710029 A US 3710029A US 00104275 A US00104275 A US 00104275A US 3710029D A US3710029D A US 3710029DA US 3710029 A US3710029 A US 3710029A
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Prior art keywords
register
auxiliary storage
address
word
storage
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Expired - Lifetime
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US00104275A
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English (en)
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G Grossman
H Moder
R Schubert
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Siemens AG
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Siemens AG
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
    • H04L12/52—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme

Definitions

  • a program controlled data processing installation including program control units for carrying out the necessary system operations and memory storage devices for storing the necessary programs.
  • the program control unit includes primary registers and an auxiliary storage unit including secondary registers to which immediate access is not required.
  • the auxiliary storage unit is connected to the primary registers so that operations required by system commands may be carried out.
  • Prior art information processing installations and especially telephone exchange installations have been constructed as program controlled systems. Installations of this type include a line connection unit, at least one program control unit and a command unit over which operators have access to the system. If within such a system two simultaneously operating program control units are utilized, then when one of the program control units breaks down the other can take over its tasks, but with a diminished speed of operation of the system.
  • the programs to be carried out by the program control units are normally stored in duplicate memory storage units for reasons of safety.
  • the program control For carrying out standard commands, organization commands, and wired special commands, the program control requires a series of registers, whose arrangement and interconnection determines the necessary technical switching expense and the working speed of the program control. It is possible to incorporate in a given cell of the storage unit registers which are not required for each command for example, multiple purpose registers and masking registers and to build into the program control only the most commonly required registers for example the accumulator and the command counter register. However, this would be very expensive and a poor solution. All commands which pertain to a register in the storage unit would require additional storage cycles and thereby periodically encumber the storage and the program control. The capacity of the installation would thereby be undesirably decreased. If on the other hand, one includes all registers having individual trigger stages in the program control, then the register contents are immediately accessable without a storage cycle. In this case, however, the circuitry expense is quite high.
  • An object of this invention is to provide a register arrangement which avoids the described disadvantages.
  • registers within a program control unit to which simultaneous access is not necessary are combined in an auxiliary storage unit so that each storage cell receives the contents of a register.
  • This auxiliary storage unit is connected to the program control unit and is connected with registers within the program control unit to provide the elementary operations which are necessary for carrying out commands.
  • FIG. 1 shows an information processing installation in which this invention may be used.
  • FIG. 2 shows the block circuit diagram of a program control unit ofthe system of FIG. I.
  • FIGS. 3a and 3b show the registers utilized for elementary operations of the program control unit of this invention and their interconnections.
  • FIGS. 4a and 4b show an alternative embodiment of the register arrangement of FIG. 3 which is responsive to sign commands.
  • FIG. I The information processing installation of FIG. I is a program controlled system including a line connection unit L, program control units P, and P, and a command unit K over which operators have access to the system.
  • the programs to be carried out by the program control units P, and P, are stored in duplicate memory units Sp, and Sp, for reasons of safety.
  • the program control unit of this invention includes elementary operations registers R, an operation flow control OS and a program selection control PW.
  • the operation flow control OS controls the program control unit P in response to commands from a command decoder (not shown).
  • the program selection control PW selects one of many programs which may be called for simultaneously to be carried out. Therefore, it must decide which programs of high priority can interrupt programs of lower priority.
  • the present invention pertains to the elementary operations registers and their interconnections.
  • FIG. 3 is divided into the FIGS. 3A and 3B, of which figure 3B connects with the right of FIG. 3A. The same is true of FIGS. 4A and 4B.
  • the two memory or storage units Sp, and Sp, are shown at the bottom of FIG. 3.
  • the addresses for the selection of a certain storage cell are contained in the address register ADR.
  • An address for example, the contents of the command counter register BR is stored in the address register ADR until the storage unit accepts the address.
  • the address register ADR receives from the I adder AD the command address increased by 1", from the intermediate register ZR the indicated address and from the word register WR the substituted addresses.
  • the word which is to be written into the storage units Sp, and/or Sp,, or the word which has been read is stored in the word register WR.
  • the word register WR serves as an intermediate register in traffic with the two storage memories Sp, and Sp, and in carrying out steps within the program control P. It is therefore connected with most of the other registers. Connections having the length of a complete storage word for example, 24 bits are shown as thick lines; connections of less than word length for example of address length, i.e., 15 bits are shown by thin lines. Control leads from and to the operation flow control 08, by means of which the transmission paths between the registers are opened and closed, are not shown for the sake of clarity.
  • the storage words read from the storage cells are compared to each other in the word compare WV. If a difference is found, there has been an error, which is reported by a signal to the operation running control 08.
  • the storage selection register SR which is to be loaded over the word register WR thereby indicates what is to be taken from the storage. Two bits of the storage selection register SR indicate whether commands are to be read from storage Sp, or Sp, or from both storages simultaneously; two further bits determine whether data should be exchanged with only one of the two storages or with both at the same time.
  • FIG. 3B shows the auxiliary storage ZS and its connections with the registers of the program control P.
  • the auxiliary storage is realized as a matrix storage device. It includes 16 storage cells, each having an ad dress length of bits. Each of these cells can be selected using coordinates X, through X and Y, through Y,. The contents of these storage cells can be read out without destruction, or changed. To carry out a change, the storage operations write" and/or "erase can be carried out. [n the operations and", or", the contents of a cell of the auxiliary storage ZS are linked in the sense of the logical and" or logical or” with the contents of a register outside of the auxiliary storage.
  • the auxiliary storage ZS includes the following registers: seven multipurpose registers, two masking registers, two priority status registers, two command counter registers, two intermediate storage registers and the address part of the command register. Of these registers, the masking register and priority status register as well as one command counter register and the intermediate storage registers are utilized for organization commands, while the remaining registers are used to carry out standard commands. All of the multipurpose registers can be used for indexing, and address computing, and partially for the solution of special tasks.
  • the masking registers make it possible to determine in which of a plurality of program control units a selected program should run.
  • the masking registers can also be used to protect a program being run from interruption by certain other programs.
  • the masking registers contain sample bits whose places in each case are assigned a certain priority. Each l" stored in the masking register has the effect that programs having a priority assigned to this place may interrupt other programs.
  • a priority status register stores the priority of a program currently running within the program control. This priority is to be compared with the priority of each later called up program. The result of the comparison determines whether the called up program has a higher priority than the currently running program and therefore may interrupt the running program. In the case ofa program interruption, intermediate storage registers store the contents of otherwise occupied registers.
  • the command counter register BR stores the cell address increased by one of the storage cell command address currently in process.
  • the command counter register BR is interrogated, its contents are transferred to the address register D, and the contents increased by one are written back in the auxiliary storage ZS.
  • a further cell of the auxiliary storage ZS takes up the address part of the command when the given address must be retained while carrying out the command.
  • the operating part of the command is in each case read by a previously designated register DR outside of the auxiliary storage and is decoded by a command decoder (not shown), which then controls the operation control OS. If the operating part of the command word for example, the bits 18 through 21 of the command word contains the address of a cell of the auxiliary storage ZS then these are decoded in the address decoder D and transferred to the block address register BA.
  • the storage cell is selected thereby using the coordinates X and Y as is usually done in a core storage device.
  • the address portion of a command is transmitted over the connection WR-ZS to the storage cell to which it is directed.
  • the auxiliary storage ZS is addressed when a register contained therein is to be filled.
  • the address decoder D has a second input through which the auxiliary storage ZS can be addressed directly from the word register WR avoiding command register BR.
  • the address data of the requested cell in the auxiliary storage ZS is taken in this case from the index of the command word for example, from bits 1 through 4 of the command word.
  • the decoded address of the desired cell is transferred as described to the block address register BA and used for the selection of the addressed storage cell of auxiliary storage ZS.
  • the contents of the selected storage cell are then added in the adder ADD to the address part of the command stored in the word register WR. For this purpose, it is routed to the adder ADD over a selection circuit AU; the command which is in the word register WR, is also routed to the adder ADD over input circuit BK.
  • a and B can be added or subtracted.
  • A can be the contents of the accumulator AK (15 or 24 bits) or the contents of a cell of the auxiliary storage ZS (15 bits).
  • B is the contents of the word register WR (l5 or 24 bits).
  • An addition overrun is indicated by the overrun register UE which is interrogated after the addition.
  • the result of the addition is stored in the accumulator AK or in the intermediate storage ZR. In the case of an indication, the addition results are stored in the intermediate storage ZR. From there it is transferred to the word register WR, the address register ADR and to a call of the auxiliary storage ZS.
  • each cell is selected by means of the address given in the operating part of the command word. This cell then stores the address part of the command word.
  • the direct connection between the intermediate register ZR and the auxiliary storage ZS can, however, be omitted if time requirements allow.
  • the contents of the intermediate storage are then transferred to the auxiliary storage ZS through the word register WR. For this reason the connection between the intermediate register ZR and the auxiliary storage register ZS is shown as a dotted line.
  • the result of the addition or subtraction between the contents of a cell of the auxiliary storage ZS and the contents of the word register WR can also be stored in the accumulator AK and be further processed therein.
  • a complete storage word of the program can be processed.
  • the accumulators contents can be shifted to the left or right, and are shifted around under the control of a shifting displacement counter which is divided into a forward and a backward counter.
  • the logical connections AND, OR, and EX- CLUSIVE OR between the contents of the accumulator AK and of the word register WR are provided by input logic EL arrayed between the accumulator and the word register.
  • the dotted line connection between the accumulator output AK and input logic EL can be omitted if the accumulator is designed in accord with the disclosure in the German Pat. application No. P 18 00 948.8.
  • a sign selection circuit can select one of four signs in the contents of the word register WR or the advance counter V and transfer it into bits through of the accumulator AK.
  • each storage word includes four signs, each having six bits.
  • the sign which is in the bits 10 through 15 of the accumulator is stored in the four sign places 1 through 4 of the intermediate register ZR the intermediate register then contains four identical signs and can be transferred to the word register WR.
  • the sign is transferred to one of the four sign places of a storage cell.
  • the l adder AD is utilized to effect a rapid change of an address by l".
  • the output register are serves as an intermediate storage device to quickly free the auxiliary storage ZS after reading out the contents of a cell. An intermediate storage device is also necessary if the adder result is to be rewritten into the auxiliary storage ZS.
  • the output register AR thereafter fulfills the task of a word register in the known core storage. The contents of the output register can thus be passed on unchanged, increased by 1", decreased by l or increased by "2".
  • a direct connection is also provided between the output of the auxiliary storage ZS and the word register WR.
  • the contents of a cell of auxiliary storage ZS can be transferred to the storage Sp over this connection.
  • FIGS. 4A and 4B show an embodiment including the intermediate storage register ZR, to the output of which is connected a sign distributor ZT which receives four signs of six parallel bits from the accumulator and applies the signs in series to the intermediate register ZR.
  • a sign can be transferred from one of the four signed places of the accumulator AK to one of the four signed places of the intermediate register ZR.
  • a certain sign is to be detected (for example an end sign)
  • this sign is transferred to an end signed register EZ as disclosed in application No. P 15 49 534.8.
  • Each sign which passes through the signed distributor is compared in a sign comparison device ZV with the contents of the end signed register E2.
  • the sign comparison device ZV upon detecting the same sign sends a signal to the operation flow control 08.
  • the working speed of the program control depends upon how often the program control must achieve access to the storage during a program.
  • data need be exchanged between the storage and the program control only at the beginning and end of a process. If multiple banks of registers are used, then the data which characterizes the momentary condition of a program can be stored in the program control even in case of a program interruption.
  • the program control can then be simultaneously occupied by as many users or programs as there are banks of registers provided.
  • the operation of information exchange from the storage to the program control and vice versa is then eliminated or can be consolidated in one large or in a plurality of small auxiliary storages.
  • a data processing installation comprising:
  • a storage means for storing data and programs including program commands necessary for operation of the installation, and a program control unit including a plurality of primary registers and a first auxiliary storage unit including a plurality of secondary registers to which simultaneous access is not necessary, said auxiliary storage unit being connected to said primary registers so that elementary operations required by said program commands can be carried out.
  • auxiliary storage is a matrix storage device.
  • said program control unit includes a second auxiliary storage means comprising a plurality of intermediate registers adapted to store the data of a program interrupted during processing.
  • a device as claimed in claim 1 including means for addressing storage cells of said auxiliary storage unit (ZS), said address register for addressing one of said cells, an address decoder (AD) controlling said block address register, and a command register (BR) for reading an operation part of one of said commands, the output of this command register being coupled through said address decoder to said clock address register.
  • ZS auxiliary storage unit
  • AD address decoder
  • BR command register
  • a device as claimed in claim 5 including a word register (WR) coupled between said auxiliary storage unit and said address decoder and including means for transferring an output on an index register to said address decoder in response to an indication.
  • WR word register
  • a device as claimed in claim 1 including means for effecting a rapid change of the cell storage address in said auxiliary storage comprising an output register (AR) connected to an output of the auxiliary storage (ZS) and adapted to serve as an intermediate storage device, an address register (ADR) for storing a cell storage address until requested by said auxiliary storage devise and a l adder device connected to the output of said output register and inputs of said auxiliary storage and said address register for effecting change in the cell address in said auxiliary storage device by l 8.
  • AR output register
  • ZS auxiliary storage
  • ADR address register
  • a device as claimed in claim 1 including a word register (WR) for storing the command word being operated on, an adder (ADD) including a first input (B) connected through an input circuit (BK) to said word register, a second input (A) connected through a selection devise (AU) to a cell of said auxiliary storage unit (ZS) and means for summing the contents of said auxiliary storage unit cell and said word register, and means for storing the result of said addition including an accumulator (AK) and an intermediate, register (ZR), the storage area depending on the result of said addition.
  • ADD adder
  • BK input circuit
  • A input
  • AU selection devise
  • ZS auxiliary storage unit
  • AK accumulator
  • ZR intermediate, register
  • a device as claimed in claim 7 including a word register (WR) for storing the command word being operated on, an adder (ADD) including a first input (B) connected through an input circuit (BK) to said word register, a second input (A) connected through a selection device (AU) to a cell of said auxiliary storage unit (ZS) and means for summing the contents of said auxiliary storage unit cell and said word register, and means for storing the result of said addition including an accumulator (AK) and an intermediate register (ZR), the storage area depending on the result of said addition.
  • ADD adder
  • BK input circuit
  • A input
  • AU selection device
  • ZS auxiliary storage unit
  • ZR intermediate register
  • a device as claimed in claim 9 wherein said intermediate register (ZR) is directly connected with said address register (ADR) and said word register (WR) so that said output register (AR) and l"adder (AD) are bypassed.
  • a device as claimed in claim 10 including a sign distributor (ZT) for reading signs from said accumulator in parallel and applying the signs to an intermediate register in series, and wherein said intermediate register is coupled between an output of said adder (ADD) and an input of said accumulator (AK).
  • ZT sign distributor

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
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US00104275A 1970-01-08 1971-01-06 Switching arrangement for a data processing installation Expired - Lifetime US3710029A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19702000608 DE2000608C3 (de) 1970-01-08 1970-01-08 Schaltungsanordnung fuer eine Nachrichtenverarbeitungs-,insbesondere fuer eine Nachrichtenvermittlungsanlage

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US (1) US3710029A (de)
BE (1) BE761371A (de)
CA (1) CA940639A (de)
CH (1) CH531214A (de)
DE (1) DE2000608C3 (de)
FR (1) FR2073181A5 (de)
GB (1) GB1332031A (de)
LU (1) LU62375A1 (de)
NL (1) NL7018962A (de)
SE (1) SE412476B (de)
ZA (1) ZA7176B (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3787633A (en) * 1972-11-30 1974-01-22 Gte Automatic Electric Lab Inc Multiplexing arrangement for a communication switching system
US3941936A (en) * 1973-10-19 1976-03-02 International Standard Electric Corporation Telecommunication system using TDM switching
US4028676A (en) * 1974-08-22 1977-06-07 Siemens-Albis Aktiengesellschaft Control of peripheral apparatus in telecommunication
EP0330475A2 (de) * 1988-02-24 1989-08-30 Fujitsu Limited Konfigurationssteuerungssystem

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911405A (en) * 1974-03-20 1975-10-07 Sperry Rand Corp General purpose edit unit
DE3629626A1 (de) * 1986-08-30 1988-03-03 Fichtel & Sachs Ag Antriebsnabe fuer fahrraeder od. dgl.

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1292210B (de) * 1967-03-21 1969-04-10 Standard Elektrik Lorenz Ag Schaltungsanordnung fuer Steuerschaltungen mit Steuerprogrammen und Kommandowerken, in Fernmelde-, insbesondere Fernsprechvermittlungsanlagen
US3478173A (en) * 1965-06-30 1969-11-11 Ericsson Telefon Ab L M Electronically controlled telecommunication system
US3585306A (en) * 1968-05-16 1971-06-15 Bell Telephone Labor Inc Tandem office time division switching system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3478173A (en) * 1965-06-30 1969-11-11 Ericsson Telefon Ab L M Electronically controlled telecommunication system
DE1292210B (de) * 1967-03-21 1969-04-10 Standard Elektrik Lorenz Ag Schaltungsanordnung fuer Steuerschaltungen mit Steuerprogrammen und Kommandowerken, in Fernmelde-, insbesondere Fernsprechvermittlungsanlagen
US3585306A (en) * 1968-05-16 1971-06-15 Bell Telephone Labor Inc Tandem office time division switching system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3787633A (en) * 1972-11-30 1974-01-22 Gte Automatic Electric Lab Inc Multiplexing arrangement for a communication switching system
US3941936A (en) * 1973-10-19 1976-03-02 International Standard Electric Corporation Telecommunication system using TDM switching
US4028676A (en) * 1974-08-22 1977-06-07 Siemens-Albis Aktiengesellschaft Control of peripheral apparatus in telecommunication
EP0330475A2 (de) * 1988-02-24 1989-08-30 Fujitsu Limited Konfigurationssteuerungssystem
EP0330475A3 (de) * 1988-02-24 1991-12-04 Fujitsu Limited Konfigurationssteuerungssystem

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CA940639A (en) 1974-01-22
DE2000608B2 (de) 1972-12-07
SE412476B (sv) 1980-03-03
GB1332031A (en) 1973-10-03
FR2073181A5 (fr) 1971-09-24
ZA7176B (en) 1971-10-27
DE2000608C3 (de) 1973-07-12
LU62375A1 (de) 1971-07-30
DE2000608A1 (de) 1971-07-22
NL7018962A (de) 1971-07-12
BE761371A (fr) 1971-07-08
CH531214A (de) 1972-11-30

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