US3676727A - Diode-array target including isolating low resistivity regions - Google Patents

Abstract

The specification describes an improved diode array target for an electron beam storage tube. The target is an improvement of the device described in U.S. Pat. Nos. 3,403,284 and 3,419,746. The target is modified so as to include an N layer in the surface region of the semiconductor substrate between the diodes. This layer serves to isolate the diodes, to reduce the dark current generation, and to increase the resolution of the camera tube.

Description

tates atet [is] 3,676,727 Dalton et a1. July 11, 1972 s41 DIODE-ARRAY TARGET INCLUDING 3,483,421 12/1969 Hogan ..313/66 x ISOLATING LQW RESISTIVITY 3,517,246 6/1970 Chester et a]... ..314/66 3,548,233 12/1970 Cave et a1 313/65 AB REGIONS 3,252,030 5/1966 Cawein.... ..313/66 [72] Inventors: John Vincent Dalton, Oldwick, N..l.; Ed- 3,307,984 3/1967 Frazier ..317/234 X ward Franklin Labuda, Allentown, Pa. 3,309,245 3/1967 l-laenichen ...317/235 AG Assignee: Bell Telephone Laboratories Incorporated, 3,403,284 9/1968 Buck et a1. ..250/21 1 .1 X

Murray Primary ExaminerRobert Sega] [22] Filed: March 30, 1970 Attorney-R. J. Guenther and Arthur J. Torsiglieri [21] App]. No.: 23,871 [57] ABSTRACT The specification describes an improved diode array target for if 33$ an electron beam storage tube. The target is an improvement i J 1 31'3/65 AB 66 of the device described in us. Pat. Nos. 3,403,284 and le 0 arc 3,419,746 The target is modified so as to include an N+ layer 56 R fe Cited in the surface region of the semiconductor substrate between 1 e the diodes. This layer serves to isolate the diodes, to reduce UNITED STATES PATENTS the dark current generation, and to increase the resolution of the camera tube. 3,419,746 12/1968 Crowell et a1. ..313/65 AB 3,448,349 6/1969 Sumner ..317/234 5 Claims, 5 Drawing figures PKTE'N TEDJUL 1 1 I972 FIG.

FIG, 3A (PRIOR ART) FIG 3B A w B .AA 1/ 0L m III 0 \t s x T 2 W 1% W a w PJLINPFE ATTORNEY DIODE-ARRAY TARGET INCLUDING ISOLATING LOW RESISTIVITY REGIONS This invention relates to semiconductor diode-array targets for electron beam camera tubes.

The diode-array camera tube described and claimed in U.S. Pat. No. 3,403,284 issued to T. M. Buck, M. H. Crowell and E. I. Gordon on Sept. 24, 1968 and US. Pat. No. 3,419,746 issued to M. H. Crowell, J. V. Dalton, E. I. Gordon and E. F. Labuda on Dec. 31, 1968 is well known in the art and is an established commercial device. However, efforts are being continued to improve its performance, and the invention described herein provides three improvements in performance. It reduces the dark current of the camera tube; it provides better isolation between diodes; and it improves the resolution of the camera tube.

In all camera tubes that relay on a charge storage mechanism the problem of dark current is inherent. Techniques for reducing dark current are continually being sought.

The major source of dark current in the diode-array target is usually the recombination-generation centers located at the silicon-silicon dioxide interface. These centers contribute to the dark current only when the semiconductor at this interface is depleted.

Assume that a voltage V is the target voltage at which the semiconductor starts to deplete. For target voltages less than V,,, the dark current is low, the surface is not depleted, and the dark current in this voltage range is due to recombinationgeneration centers located in the bulk of the semiconductor. As the target voltage is raised above V there is a rapid increase in dark current followed by a sharp saturation at a voltage V For voltages above V the surface is depleting and the rapid increase in dark current is due to the recombinationgeneration centers located at the silicon-silicon dioxide interface which can now contribute to the dark current. The dark current saturates when the entire interface is fully depleted and all the surface recombination-generation centers are contributing. Note that any technique which leads to a higher saturation voltage V, will for lower target voltages yield a lower dark current.

Another problem that can occur for target voltages greater than V, is that isolation between diodes can be lost if one of the diodes can act as a source of minority carriers. For instance, this could happen if a diode has a very high leakage current due to some sort of defect in the vicinity of the diode. Such a diode would not remain reverse biased during the frame time and could act as a source of minority carriers, the result being the formation of a channel between thiS diode and other neighboring diodes. This effect will be recognized as similar to that which occurs in the well-known insulated gate field effect transistor when the source and drain are electrically connected together by a channel by the application of an appropriate gate voltage. Again any technique which leads to a higher V will tend to inhibit this problem.

According to the invention, the foregoing difficulties are substantially overcome by diffusing additional impurities into those surface regions of the semiconductor surrounding the diodes. This low resistivity surface layer has the effect of increasing the saturation voltage V thereby reducing the dark current for voltages less than V, and inhibiting the formation of an inversion layer or channel in this voltage range.

The incorporation of a low resistivity layer at the silicon-silicon dioxide interface will also improve the resolution of the diode-array target. The resolution ofa normal target is limited by lateral diffusion of the minority carriers as they diffuse from the light incident surface towards the depletion regions of the diodes. The thicker the target the greater the loss of resolution. If the depletion regions of the diodes could be pushed back to the light incident surface, the minority carriers created by the incident photons would be in a strong electric field region and there would be no possibility of lateral diffusion. In a typical diode-array target, the nominal resistivity of the substrate is =lQ-cm, and with this resistivity the use of a target voltage high enough to push the depletion regions to the light incident surface is not practical. A much higher substrate resistivity cannot be used because then the target capacitance would be too small to provide the magnitude of the video signal usually required. With the low resistivity region, a much higher substrate resistivity can be used since most of the target capacitance will consist of that provided by the low resistivity region surrounding the p-regions of the diodes. With this structure, for a given target voltage, the depletion regions of the diodes will extend further back towards the light incident surface than in a conventional target with a homogeneous substrate resistivity.

For example, if the depth of the low resistivity region is 2;; and the diode diameter is 8 then to obtain the same target capacitance as that provided by a homogeneous lOfl-cm substrate, assuming the major contribution to the target capacitance is the diode capacitance, a lfl-cm surface region is possible with a substrate resistivity of =l00fl-cm. Then for a given target voltage, the depletion regions in the new structure will extend back -33 times as far as in the conventional target with a unifonn lOQ-cm substrate.

This improved resolution performance could be very important for targets designed to operate in the wavelength range of 0.95 to 1.10 In this range, the absorption coefficient of Si decreases rapidly with increasing wavelength, and to achieve a useable sensitivity, the target must be made relatively thick. As a result, the resolution with a conventional target structure would be very poor.

One limit to the improvement in resolution that can be obtained with a thick target and a low resistivity surface layer is the requirement that the capacitance between diodes be small compared to the capacitance between the diodes and the undepleted substrate. If this is not the case, the ability to produce a potential profile on the diode side of the array will be lost. This becomes a problem with thick targets because as the depletion regions of the diodes are pushed back to the light incident surface, the depletion regions of adjacent diodes may merge underneath the low resistivity region causing the capacitance between the diodes and the undepleted substrate to become small. To prevent this from occurring, the low resistivity region can be made to extend back to the light incident surface at isolated regions between the diodes, thus preventing the depletion regions from adjacent diodes from merging.

These and other aspects of the invention will be explained more fully in the following detailed description. In the drawmg:

FIG. 1 is a schematic view of a camera tube incorporating the improved target;

FIG. 2 is a front sectional view showing, the target of FIG. 1;

FIGS. 3A and 3B are schematic representations illustrating the separation between contiguous depletion regions in the prior art structure (FIG. 3A) and the structure of the invention (FIGS. 38 and 3C).

An exemplary electron beam device employing the improved target is shown in FIG. 1. The standard tube envelope 10 contains a cathode 11 and cathode heater 12. The control grid is shown at 13, accelerating grid 14, wall accelerating grid 15, field mesh 16, and decelerating grid 17. All are biased at appropriate potentials known in the art. Alignment coil 18, deflecting coil 19 and focusing coil 20 are standard. The improved target 21 is shown in detail in FIG. 2. The semiconductor substrate 30 includes an array of diflused regions 31 forming p n junctions with the substrate. In the usual mode the substrate is n-type with p-type diffused regions. The reverse configuration is useful when operating in the mesh stabilized mode. The surface of the semiconductor is covered with a dielectric layer 32 except for the windows used to form the diffused regions. The surface portion of the substrate 30 between the diffused regions is provided with a low resistivity layer 33. This layer is provided according to the invention to isolate each diode from others in the array and to improve the target performance as described above.

in greater detail,

An important aspect of the invention is illustrated schematically in FIGS. 3A, 3B and 3C. FIG. 3A shows the conventional target structure without the low resistivity layer. The depletion layer 34 surrounding each diffused region 31 extends into the corresponding region of the adjacent diode. Under adverse conditions, such as a defect causing high junction leakage, inversion of the semiconductor surface will occur, adjacent pregions will be electrically connected and target resolution will be impaired.

In FIG. 3B the surface region of substrate 30 between diodes is provided with a low resistivity layer 33. In this configuration this layer is N'. The depletion region 34 is now confined more closely to the physical p-n junction at and near the surface of the substrate 30. Surface generation is thereby reduced and inversion of this region becomes less likely.

FIG. 3C illustrates an embodiment similar to that of FIG. 38 with reference numerals denoting identical elements except that the N layer in this case extends to the image side of the target. As indicated above this permits the use of higher target voltages without merging under the N layer of the depletion regions of adjacent diodes.

, In a preferred embodiment of the invention the substrate 30 is n-typ'e silicon having a resistivity in the range of l to 100cm. The dielectric layer 32 is SiO The p-diffused region and the N layer have impurity concentrations, obtained by wellknown techniques, in the range of 1.10" to 5.10 atoms/cc. and preferably between and 10" atoms/cc. With higher impurity concentration, breakdown between diodes is apt to occur. Also the diode capacity will be too great and excessive capacitive lag will result. The lower limit is established to give the results illustrated by FIG. 3B.

Although this impurity concentration is obtainable with conventional diffusion techniques greater control and reliability are obtained by implanting the impurities with an ion beam.

For example, approximately l0 /cm of P ions at 300 keV implanted into the silicon substrate will produce a doped region with a projected range of ==4,000 A. and a straggling of =l,000 A. The target can then be processed in the normal manner with an 8,000 A. oxide grown, e.g., in dry oxygen at 1 ,100 C for 40 minutes and annealed in nitrogen for one hour at 400 C.

Alternatively the N layer can be implanted after the growth of the oxide and the formation of the diodes. With an oxide 8,000 A. thick, l0""/cm of P at 600 keV produces the desired N region with the peak impurity concentration at approximately the Si-SiO interface.

The target performance can be further improved by the addition of a semiresistive sea covering the side of the target exposed to the electron beam. The addition of this layer eliminates localized charge accumulation that would otherwise interfere with proper beam landing. Useful materials for this layer are 500 to 10,000 A. of Sb S or 200 to 1,500 A. of gallium arsenide.

Further improvements in target performance can be obtained by depositing conducting islands over the diode regions. For example gold islands of the order of 0.1 to lg. in thickness have been found to increase the diode capacitance thereby increasing the time constant and dynamic range of the target. If the islands are physically larger than the diode areas (e.g., 3,1. separation as compared with normal diode separation of 10 to 1211,) then the beam landing efficiency in terms of the utilization of electron beam current is improved by the ratio of the beam landing areas (one-eighth to more than onehalf. If the islands are square the ratio becomes nearly threefourths.)

Various additional modifications and extensions of this invention will become apparent to those skilled in the art. All such variations and deviations which basically rely on the teachings through which this invention has advanced the art are properly considered Within the spirit and scope of this invention.

What is claimed is:

1. An electron beam storage device comprising in combination: a target structure comprising an n-type silicon wafer having a resistivity in the range of l ohm cm to ohm cm; an array of p-type impurity regions formed into a surface of the wafer, each of said regions forming with the major portion of the wafer a pn junction, an SiO dielectric layer covering the n-type portion of the surface around the p-type regions, means for scanning the array of p-n junctions with the electron beam, and an n-type impurity region formed into the surface of the wafer between the array of p-type impurity regions so as to surround each of the p-n junctions annularly, said region having a resistivity significantly less than the resistivity of the remaining n-type portion of the wafer and an impurity concentration of at least 10 atoms/cc. and extending through the thickness of the wafer.

2. The storage device of claim 1 in which the impurity regions and the dielectric layer are covered with 500 to 10,000 A. of Sb s 3. The storage device of claim 1 in which the impurity regions are covered with 200 to 1,500 A. of gallium arsenide.

4. The storage device of claim 1 further including metal conducting islands covering each impurity region.

5. The storage device of claim 4 in which the metal conductive islands comprise 0.1 to 1.0a of gold.

Claims (5)

1. An electron beam storage device comprising in combination: a target structure comprising an n-type silicon wafer having a resistivity in the range of 1 ohm cm to 100 ohm cm; an array of p-type impurity regions formed into a surface of the wafer, each of said regions forming with the major portion of the wafer a p-n junction, an SiO2 dielectric layer covering the n-type portion of the surface around the p-type regions, means for scanning the array of p-n junctions with the electron beam, and an n-type impurity region formed into the surface of the wafer between the array of p-type impurity regions so as to surround each of the pn junctions annularly, said region having a resistivity significantly less than the resistivity of the remaining n-type portion of the wafer and an impurity concentration of at least 1016 atoms/cc. and extending through the thickness of the wafer.

2. The storage device of claim 1 in which the impurity regions and the dielectric layer are covered with 500 to 10,000 A. of Sb2S3.

3. The storage device of claim 1 in which the impurity regions are covered with 200 to 1,500 A. of gallium arsenide.

4. The storage device of claim 1 further including metal conducting islands covering each impurity region.

5. The storage device of claim 4 in which the metal conductive islands comprise 0.1 to 1.0 Mu of gold.

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