US3668436A - Circuit apparatus for supplying first and second trains of mutually exclusive clock pulses - Google Patents
Circuit apparatus for supplying first and second trains of mutually exclusive clock pulses Download PDFInfo
- Publication number
- US3668436A US3668436A US885210A US3668436DA US3668436A US 3668436 A US3668436 A US 3668436A US 885210 A US885210 A US 885210A US 3668436D A US3668436D A US 3668436DA US 3668436 A US3668436 A US 3668436A
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- Prior art keywords
- power amplifier
- output
- transistor
- resistor
- output terminal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/282—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator astable
- H03K3/2821—Emitters connected to one another by using a capacitor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
- H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping
Definitions
- the clock circuit includes a square wave oscillator having true and complementary output terminals, each driving a different power amplifier. Each oscillator output terminal is connected to its associated power amplifier through a NOR gate. The second terminal of each NOR gate is connected to the output of the opposite power amplifier so that neither power amplifier can begin to form a clock pulse until the clock pulse formed by the other power amplifier has terminated, or in other words, until the output voltage of the other power amplifier has fallen to a defined threshold level.
- This invention relates generally to electronic clock circuits and, more particularly, to a two phase clock circuit for providing trains of essentially non-overlapping first and second clock pulses.
- first phase (01) clock pulses terminate prior to second phase (02) clock pulses beginning and vice versa In many known prior art two phase clock circuits, the cross-over point between a terminating 01 pulse and a beginning 02 pulse occurs at approximately the midpoint of the pulse amplitude transition. That is, assuming that clock pulses 01 and 02 alternately vary between a ground and a 28 volt level, the 01 pulse on its way from 28 volts to ground, will cross the midpoint -14 volts) at substantially the same time as the 02 pulse on its way from ground to 28 volts crosses the 14 volt midpoint.
- two phase clock circuits have been developed with provide trains of substantially non-overlapping first and second clock pulses by delaying the initiation of each pulse by a fixed amount selected for the worst case situation. That is, the first and second trains of clock pulses are respectively developed in response to the true and complementary outputs of a square wave oscillator. A transition in the oscillator output initiates a clock pulse after a fixed delay which must be sufficiently long to assure that the other phase clock pulse has terminated.
- the precise termination time of the clock pulse depends on several factors, such as temperature, load, device parameters, etc., and thus the delay must be selected to be sufficient for a worst case situation. Accordingly, in most situations the selected delay will be greater than is necessary thereby reducing the overall operating speed of the system.
- mutually exclusive two phase clock pulses are developed by inhibiting the initiation of one clock pulse phase until the other phase clock pulse has terminated. That is, an essentially closed loop system is provided which actually uses the termination of the clock pulse of one phase to trigger the initiation of the clock pulse of the other phase. This technique inherently compensates for variations in temperature, load, device parameters, etc.
- a clock circuit including a square wave oscillator having true and complementary output terminals, each driving a different power amplifier.
- Each oscillator output terminal is connected to its associated power amplifier through a gating or coupling means.
- the gating or coupling means is controlled by the output of the opposite power amplifier in a manner such that as long as either power amplifier is providing a clock pulse at an active level, the gating or coupling means to the opposite power amplifier is disabled.
- threshold means in the form of a zener diode are incorporated in the gating circuitry to precisely define the level to which one phase clock pulse must fall prior to initiating formation of the other phase clock pulse.
- FIG. 1A is a block diagram of a typical prior art two phase clock circuit
- FIG. 18 illustrates exemplary wavefonns occurring in the clock circuit of FIG. 1A
- FIG. 2 illustrated non-overlapping clock pulse trains of the type produced by embodiments of the present invention
- FIG. 3 is a block diagram of an embodiment of the present invention.
- FIG. 4 is a detailed schematic diagram of an embodiment of the present invention.
- FIG. 1A of the drawings illustrates a typical prior art two phase clock circuit.
- the clock circuit of FIG. 1A employs a square wave oscillator 10 which provides complementary timing signals A and A on output terminals l2 and 14.
- the timing signals A and A swing between ground and a negative voltage level which will hereinafter be assumed to be 28 volts. Ground will be assumed to constitute and inactive level and 28 volts an active level.
- the oscillator output terminals 12 and 14 are respectively connected to power amplifiers l6 and 18 which respectively provide clock pulse trains 02 and 01 on their output terminals 20 and 22.
- the output terminal 20 is connected to a load 24 which, for example, will comprise a group of logic circuits intended to be responsive to clock phase 0.2.
- power amplifier output terminal 22 will be connected to load 26 which will comprise a group of logic circuits intended to be active during clock phase 0 l Attention is now called to FIG. 1B which illustrates the relationships between the clock pulse trains 01 and 02 and the square wave timing signals A and A provided by oscillator 10. It will be noted that it has been assumed that the power amplifiers 16 and 18 each introduce an inversion.
- timing signal A respectively produce the negative and positive going signal transitions 34 and 36 in the clock pulse train 02.
- negative and positive going transitions 38 and 40 in timing signal A respectively produce the positive and negative going transitions 42 and 44 in clock pulse train 01.
- the clock pulse trains 01 and 02 shown in FIG. 1B cross each other approximately at the midpoint of the clock pulse amplitude. That is, having assumed that the clock pulses swing from approximately ground to 28 volts, it will be apparent that the clock pulses O1 and 02 are each at approximately l4 volts at the same point in time.
- certain two phase logic organizations can not tolerate this degree of overlapping of the clock pulses 01 and 02. In certain two phase logic systems employing metal oxide semi-conductor logic, it is essential that the clock pulses 01 and 02 be substantially mutually exclusive.
- the delay introduced by such delay circuits must be sufficiently long to assure, for a worst case condition, that the first and second phase clock pulses do not overlap. Unfortunately, by selecting the delay for a worst case condition, it will be unnecessarily long for most conditions, thus reducing the overall system operating speed. In accordance with the present invention, no fixed delay is incorporated, but rather the initation of each clock pulse is delayed only as long as is required to permit the other phase clock pulse to terminate.
- a positive going transition 50 of clock pulse 01 is initiated in response to a negative going transition 38 of timing signal A
- the negative going transition 52 of clock pulse 02 is not initiated by the positive going transition 30 of timing signal A which occurs simultaneously with the transition 38 of timing signal A, but instead, the negative going transition 52 of clock pulse 02 is initiated only after clock pulse Ol has returned from 28 volts to ground level.
- the positive going transition 54 of clock pulse 02 initiated in response to the negative going transition 30 of timing signal A essentially reaches the inactive ground level prior to the negative going transition 56 of clock pulse 01 being initiated. in other words, it can be seen that the negative going transitions of both clock pulses O1 and 02 are delayed until the opposite phase clock pulses are substantially terminated.
- the initiation of a negative going transition in the clock pulses of either phase is permitted only when the clock pulse of the other phase returns to a defined threshold value. In the embodiment of H6. 4, the threshold value is defined at about --4 volts.
- a clock pulse 01 is initiated only when the level of clock pulse 02, returning from 28 volts toward ground, reaches 4 volts.
- FIG. 3 illustrates a block diagram of an embodiment in accordance with the present invention.
- the embodiment of FIG. 3 differs from the conventional two phase clock circuit of HG. 1A by the inclusion of coupling circuits or NOR-gates 58 and 60 which respectively couple the oscillator output terminals 12 and 14 to the power amplifiers 16 and 18.
- the output of power amplifier 18 is coupled to the input of NOR-gate 58 and the output of power amplifier 16 is coupled to the input of NOR-gate 60.
- gate 60 will be disabled and thus the initiation of clock pulse 01 will be inhibited.
- NOR-gate 58 will be disabled and the initiation of clock pulse 02 will be inhibited.
- FIG. 4 illustrates a schematic diagram of the clock circuit illustrated in block form in FIG. 3.
- the circuit of FIG. 4 includes a square wave oscillator 62 comprising an emitter coupled multivibrator including first and second transistors Q1 and Q2.
- the collector of transistor 02 is connected through resistor R1 to a source of relatively positive potential, illustrated as ground.
- the emitter of transistor Q2 is connected through resistor R2 to a source of negative potential, illustrated as -28 volts.
- the base of transistor O1 is connected to the collector of transistor Q2 which is coupled through resistor R3 to ground.
- the emitter of transistor 02 is connected through resistor R4 to the negative potential.
- a voltage divider comprised of resistors R5 and R6 is connected between the sources of positive and negative potential with the base of transistor Q2 being connected to the junction between resistors R5 and R6.
- the oscillator 62 is substantially conventional and operates to provide the square wave timing signals A and A (as illustrated in FIG. 18) at the collectors of transistors Q2 and Q1, respectively.
- the collector of transistor O1 is connected to input transistor 03 of power amplifier 64.
- the emitter of transistor O3 is connected to the source of relatively positive potential (ground) and the collector of transistor O3 is connected through resistor R7 and diode CR1 to the source of negative potential.
- Transistor Q3 is connected in a current multiplying arrangement with transistor 04. More particularly, the base of transistor 04 is connected to the collector of transistor Q3.
- the collector of transistor O4 is connected to ground.
- the emitter of transistor Q4 is connected to the output terminal 66 providing clock pulse train 01. Additionally, terminal 66 is connected to the emitter of transistor Q5 whose base is connected to the collectorof transistor Q3.
- the collector of transistor Q5 is connected through resistor R8 to the source of negative potential.
- Transistor Q5 is connected in a current multiplying configuration with transistor Q6 whose collector is connected to the output terminal 66 and whose base is connected to the collector of transistor 05.
- the emitter of transistor Q6 is connected to the source of negative potential.
- transistor O3 is forward biased. This in turn will forward bias transistor Q4 and both will supply load current through output terminal 66 which will thus be connected substantially to ground potential. It will be noted that when transistor O3 is conducting, the base of transistor Q5 will be held high and thus transistor Q5 will be off thus also holding transistor Q6 off. During this time, capacitor C1 connected between the emitter of transistor Q5 and the anode of diode CR1 will charge to approximately 28 volts.
- transistor Q3 When transistor Q3 turns off, transistor Q4 will also turn off. Capacitor C1 will then forward bias transistor Q5 which will turn on to in turn cause transistor O6 to conduct. Thus, transistors Q5 and Q6 will then supply the clock pulse 0l at the negative 28 volt potential.
- Transistor Q1 is off
- the level of clock pulse 02 on terminal 68 is close to ground or at least between approximately 4 volts and ground.
- the base of transistor O3 is connected through zener diode 70 assumed to have a rating of 3.9 volts and resistors R9 to the negative potential source.
- Output terminal 68 of power amplifier 72 is connected through diode CR2 to the junction between zener diode 70 and resistor R9.
- oscillator transistor Q2 similarly drives power amplifier 72 to yield negative 02 clock pulses on terminal 68.
- Circuit apparatus for supplying first and second trains of complementary clock pulses, said apparatus comprising:
- an oscillator circuit having first and second output terminals and including means for alternately providing first polarity signal transitions on said first and second output terminals;
- first and second power amplifiers each having an input terminal and an output terminal and including means providing an output signal at said output terminal at an active level in response to a first polarity signal transition applied to the input terminal thereof;
- a first means coupling said oscillator circuit first output terminal to said first power amplifier input terminal, said first means including a first threshold gate means for maintaining said first power amplifier output signal at said active level subsequent to the termination of a first polarity signal transition on said oscillator circuit first output terminal;
- a second means coupling said oscillator circuit second output terminal to said second power amplifier input terminal, said second means including second threshold gate means for maintaining said second power amplifier output signal at said active level subsequent to the termination of a first polarity signal transition on said oscillator circuit second output terminal;
- first disabling means responsive to said second power amplifier output signal being at said active level for disabling said first threshold gate means
- said first threshold gate means includes a first zener diode connected in series with a first resistor between said first power amplifier input terminal and a source of reference potential; and wherein said second threshold gate means includes a second zener diode connected in series with a second resistor between said second power amplifier input terminal and said source of reference potential.
- first disabling means includes a first diode connected between said second power amplifier output terminal and the junction between said first zener diode and said first resistor; and wherein said second disabling means includes a second diode connected between said first power amplifier output terminal and the junction between said second zener diode and said second resistor.
- Circuit apparatus for supplying first and second trains of complementary clock pulses, said apparatus comprising:
- an oscillator including first and second transistors, each having an output electrode;
- a first resistor having a first end connected to said first transistor output electrode and a second end adapted to be connected to a source of relatively positive potential
- a second resistor having a first end connected to said second transistor output electrode and a second end adapted to be connected to said source of relatively positive potential
- a first power amplifier having an output terminal and including an input transistor having a control electrode and input and output current electrodes
- a second power amplifier having an output terminal and including an input transistor having a control electrode and input and output current electrodes
- first diode means connecting said second power amplifier output terminal to the junction between said first zener diode and said third resistor; and second diode means connecting said first power amplifier output terminal to the junction between said second zener diode and said fourth resistor.
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
Claims (4)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US88521069A | 1969-12-15 | 1969-12-15 |
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US3668436A true US3668436A (en) | 1972-06-06 |
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US885210A Expired - Lifetime US3668436A (en) | 1969-12-15 | 1969-12-15 | Circuit apparatus for supplying first and second trains of mutually exclusive clock pulses |
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Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3761833A (en) * | 1971-09-02 | 1973-09-25 | Int Standard Electric Corp | Amplitude stabilized l.c. oscillator with output circuits for producing semi-sinusoidal clock pulses |
US3824409A (en) * | 1972-06-12 | 1974-07-16 | Massachusetts Inst Technology | Arbiter circuits |
US3961269A (en) * | 1975-05-22 | 1976-06-01 | Teletype Corporation | Multiple phase clock generator |
US3991325A (en) * | 1974-08-16 | 1976-11-09 | U.S. Philips Corporation | Transistor amplifier for generating complementary trapezoidal waveforms |
US3997872A (en) * | 1975-07-14 | 1976-12-14 | Digital Equipment Corporation | Synchronizer circuit |
US4107666A (en) * | 1977-01-10 | 1978-08-15 | The United States Of America As Represented By The Secretary Of The Army | Variable pulse distribution electro-optical system |
JPS53121556A (en) * | 1977-03-31 | 1978-10-24 | Toshiba Corp | 2-phase clock pulse generator circuit |
JPS5466735U (en) * | 1977-10-19 | 1979-05-11 | ||
JPS54129254U (en) * | 1978-02-27 | 1979-09-08 | ||
EP0053014A1 (en) * | 1980-11-20 | 1982-06-02 | Fujitsu Limited | Clock generator circuit |
US4456837A (en) * | 1981-10-15 | 1984-06-26 | Rca Corporation | Circuitry for generating non-overlapping pulse trains |
US4472645A (en) * | 1980-12-22 | 1984-09-18 | British Telecommunications | Clock circuit for generating non-overlapping pulses |
US4529896A (en) * | 1982-03-24 | 1985-07-16 | International Business Machines Corporation | True/complement generator employing feedback circuit means for controlling the switching of the outputs |
EP0262412A1 (en) * | 1986-09-01 | 1988-04-06 | Siemens Aktiengesellschaft | Load-adapted CMOS clock generator |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3259761A (en) * | 1964-02-13 | 1966-07-05 | Motorola Inc | Integrated circuit logic |
US3284645A (en) * | 1964-10-27 | 1966-11-08 | Ibm | Bistable circuit |
US3292100A (en) * | 1966-01-04 | 1966-12-13 | Gen Electric | Pulse generator with multiple phasedisplaced outputs |
US3441751A (en) * | 1966-10-04 | 1969-04-29 | Rca Corp | Two phase clock pulse generator employing delay line having input-output means and characteristic impedance termination means at each end |
US3467839A (en) * | 1966-05-18 | 1969-09-16 | Motorola Inc | J-k flip-flop |
-
1969
- 1969-12-15 US US885210A patent/US3668436A/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3259761A (en) * | 1964-02-13 | 1966-07-05 | Motorola Inc | Integrated circuit logic |
US3284645A (en) * | 1964-10-27 | 1966-11-08 | Ibm | Bistable circuit |
US3292100A (en) * | 1966-01-04 | 1966-12-13 | Gen Electric | Pulse generator with multiple phasedisplaced outputs |
US3467839A (en) * | 1966-05-18 | 1969-09-16 | Motorola Inc | J-k flip-flop |
US3441751A (en) * | 1966-10-04 | 1969-04-29 | Rca Corp | Two phase clock pulse generator employing delay line having input-output means and characteristic impedance termination means at each end |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3761833A (en) * | 1971-09-02 | 1973-09-25 | Int Standard Electric Corp | Amplitude stabilized l.c. oscillator with output circuits for producing semi-sinusoidal clock pulses |
US3824409A (en) * | 1972-06-12 | 1974-07-16 | Massachusetts Inst Technology | Arbiter circuits |
US3991325A (en) * | 1974-08-16 | 1976-11-09 | U.S. Philips Corporation | Transistor amplifier for generating complementary trapezoidal waveforms |
US3961269A (en) * | 1975-05-22 | 1976-06-01 | Teletype Corporation | Multiple phase clock generator |
US3997872A (en) * | 1975-07-14 | 1976-12-14 | Digital Equipment Corporation | Synchronizer circuit |
US4107666A (en) * | 1977-01-10 | 1978-08-15 | The United States Of America As Represented By The Secretary Of The Army | Variable pulse distribution electro-optical system |
JPS53121556A (en) * | 1977-03-31 | 1978-10-24 | Toshiba Corp | 2-phase clock pulse generator circuit |
JPS5466735U (en) * | 1977-10-19 | 1979-05-11 | ||
JPS54129254U (en) * | 1978-02-27 | 1979-09-08 | ||
EP0053014A1 (en) * | 1980-11-20 | 1982-06-02 | Fujitsu Limited | Clock generator circuit |
US4472645A (en) * | 1980-12-22 | 1984-09-18 | British Telecommunications | Clock circuit for generating non-overlapping pulses |
EP0055073B1 (en) * | 1980-12-22 | 1985-07-10 | British Telecommunications | Improvements in or relating to electronic clock generators |
US4456837A (en) * | 1981-10-15 | 1984-06-26 | Rca Corporation | Circuitry for generating non-overlapping pulse trains |
US4529896A (en) * | 1982-03-24 | 1985-07-16 | International Business Machines Corporation | True/complement generator employing feedback circuit means for controlling the switching of the outputs |
EP0262412A1 (en) * | 1986-09-01 | 1988-04-06 | Siemens Aktiengesellschaft | Load-adapted CMOS clock generator |
US4761568A (en) * | 1986-09-01 | 1988-08-02 | Siemens Aktiengesellschaft | Load-adapted clock generator in CMOS circuits |
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Owner name: LITTON BUSINESS SYSTEMS, INC., A NY CORP., CALIFOR Free format text: RE-RECORD OF INSTRUMENT RECORDED AUGUST 15,1977, REEL 3448 FRAMES 860-864 TO CORRRECT THE HABITAT OF ASSIGNEE (NEGATIVE CERTIFICATE ATTACHED;ASSIGNOR:COMPUCORP.;REEL/FRAME:004174/0739 Effective date: 19830914 Owner name: LITTON BUSINESS SYSTEMS, INC., 360 NORTH CRESCENT Free format text: RE-RECORD OF INSTRUMENT RECORDED AUGUST 15,1977, REEL 3448 FRAMES 860-864 TO CORRRECT THE HABITAT OF ASSIGNEE (NEGATIVE CERTIFICATE ATTACHED;ASSIGNOR:COMPUCORP.;REEL/FRAME:004174/0739 Effective date: 19830914 |
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Owner name: MELLON BANK NATIONAL ASSOCIATION ONE MELLON BANK C Free format text: SECURITY INTEREST;ASSIGNOR:MONROE SYSTEMS FOR BUSINESS, INC. A NE CORP;REEL/FRAME:004321/0976 Effective date: 19841016 |
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Owner name: MONROE SYSTEMS FOR BUSINESS, INC. A NE CORP Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:LITTON BUSINESS SYSTEMS, INC. A NY CORP;REEL/FRAME:004423/0130 Effective date: 19841126 |