US3665324A

US3665324A - Trigger controlling method

Info

Publication number: US3665324A
Application number: US45795A
Authority: US
Inventors: Naohisa Nakaya
Original assignee: Iwatsu Electric Co Ltd
Current assignee: Iwatsu Electric Co Ltd
Priority date: 1969-07-10
Filing date: 1970-06-12
Publication date: 1972-05-23
Anticipated expiration: 1989-05-23
Also published as: DE2034397B2; DE2034397C3; DE2034397A1; NL7010276A; GB1318934A; JPS4943224B1

Abstract

An improved trigger controlling method of the present invention uses a memory circuit for storing a signal which is proportional to the differentiated waveform of a sampled observing signal, and the differentiated waveform is controlled by the signal stored in the memory circuit. As a result of this, the improved method of the present invention provides a trigger signal which is obtained automatically and in a stable condition, an output pulse synchronized with an input observing signal for all magnitudes of the input observing signal which is to be applied to a sampling device such as a sampling oscilloscope.

Description

United States Patent 'AMPLITUDE I Nakaya May 23, 1972 [s41 TRIGGER CONTROLLING METHOD 3,490,691 1/1970 Uyetani et a1 ..32s/1s1 x 3,252,099 5/ 1966 Dodd ..328/ 151 X [72] Japan 3,495,097 2/1970 Abramson et al... ....307/240 x [73] Assignee: lwalsu Electric Co, Ltd, Tokyo, Japan 3,369,182 2/1968 Reindl ..328/63 X [22] Filed: June 12, 1970 Primary Examiner-Donald D. Forrer J ,7 Assistant Examiner-R. C. Woodbridge [211 App! No 45 95 Attorney-Robert E. Burns and Emmanuel J. Lobato [30] Foreign Application Priority Data [57] ABSTRACT July 10, 1969 Japan ..44/54079 An improved trigger controlling method of the present invention uses a memory circuit for storing a signal which is propor- [52] US. Cl ..328/63, 307/269, 328/72, tional to h e t a ed aveform of a sampled observing 328/ 151 signal, and the differentiated waveform is controlled by the [51 Int. Cl. ..H03k 5/00 Signal Stored in the memory Circuit AS a result of this, the 58 FieldofSearch ..307/240, 269; 328/63, 72, 139, Proved method of the Present invention Provides a trigger 328/141, 15] signal which is obtained automatically and in a stable condition, an output pulse synchronized with an input observing [56] References Cited signal for all magnitudes of the input observing signal which is to be applied to a sampling device such as a sampling oscil- UNITED STATES PATENTS loscope.

3,465,134 9/1969 James ..328/15l X 8Clailm, 11 Drawing figures TRIGGER 2 SIGNAL TRIGGER 1L gstg I 7 CIRCUIT l R OR 3 I 9 Ix HORIZONTAL RPIIII' 5 I CONTROLLING \6 GENERATOR CR CIRCUIT M 35 iff 7 AUTOMATIC 1 32 CONTROLLING CIRCUIT I e sAI/IPLER T TT TTT P F IER /J /V\\ |O AM LI SIGNAL 4 gigmfi II TO BE OBSERVED SOURCE Patented May 23, 1972 3,665,324

4 Sheets-Sheet 7' IIII'WIWIII" Patented May 23, 1972 3,665,324

4 Sheets-Sheet 4 F/g'. 5B

lYool ,lYool'Q lYzol TRIGGER CONTROLLING METHOD The present invention relates to an improved trigger controlling method and, more particularly to an improved trigger controlling method for acquiring automatically and in a stable condition an output pulse synchronized with an input observing signal for all magnitudes of the input observing signal on a sampling device such as a sampling oscilloscope.

As is well-known, when an external triggering signal synchronized with an observing input signal applied a sampling device is applied to a triggering circuit, the triggering circuit generates a sequence of pulses synchronized with the above-mentioned input signal. The sequence of pulses thus generated which provides constant amplitude and constant width pulses having a frequency lower than a certain given value or the same frequency as the observing input signal is applied to a delay pulse generator. The delay pulse generator generates, by using the above-mentioned sequence of pulses, a high speed sawtooth wave which determines a time-base axis and generates a sequence of delay pulses by comparing the high speed sawtooth wave with a similar signal as a signal scanning the horizontal axis of the cathode-ray tube. The sequence of delay pulses thus obtained is applied to a sampling apparatus which generates a sampling pulse, samples the input observing signal and holds its sampled values for displaying the input signal on the cathode-ray tube via an amplifier. In order to acquire the above-mentioned sequence of pulses synchronized with the input pulse in the trigger circuit, the voltage applied to the trigger circuit or the current passing through the trigger circuit are manually or automatically controlled. However, as is well experienced by persons skilled in the art, the problem is not completely overcome for carrying out the above-mentioned triggering operation in a stable condition for all magnitudes of the input signal. In order to overcome some of the above mentioned drawbacks, the triggering method disclosed in U.S. Patent Application Serial No. 773,61 1, filed November 5, 1968, may be used in the sampling device, but that method does not overcome all of such drawbacks.

A principal object of the present invention is to provide an improved trigger controlling method which can overcome troublesome adjustments of the trigger circuitwhich adjustments are usually necessary with the conventional triggering methods.

Another object of the present invention is to provide an improved trigger controlling method which can carry out the stable triggering operation for a wide range of magnitudes of the input signal.

A further object of the present invention is to provide an improved trigger controlling method which is effectively applicable for various types of sequences of input signals to be converted into output pulses well synchronized with the input I signals.

Further features and advantages of the present invention will be apparent from the ensuing description, reference being made to the accompanying drawings to which, however, the scope of the invention is in no way limited.

FIG.1 is a circuit diagram of an embodiment of a circuit used in the present invention,

FIGS. 2A to 25 is an explanatory diagram for showing a sampled waveform of a sine wave obtained by the sampling device of FIG. 1,

FIG. 3 is an explanatory diagram of the principle adopted in the circuit shown in FIG. 1,

FIG. 4 isanother circuit diagram of another embodiment of a circuit used in the present invention,

FIGS. 5A and 5B is an explanatory diagram for showing a sampled waveform of a sine wave obtained by the sampling device of FIG. 4,

FIG. 6 isan explanatory diagram of the principle adopted in the circuit shown in FIG. 4.

Referring to FIG. 1, the trigger controlling method of the present invention comprises a trigger circuit 1, a delay pulse generator 2, a horizontal scanning signal generator 3, a sampler 4, a cathode-ray tube 5, an automatic trigger controlling circuit 6, a blanking signal source 11 and an automatic amplitude controlling circuit 7. An input signal to be observed 10 is applied to the sampler 4, a differentiated output of the sampler 4 is applied to the trigger circuit 1 via the automatic amplitude controlling circuit 7 and the automatic trigger controlling circuit 6. A trigger signal 9 is also applied to the trigger circuit 1. The output of the trigger circuit 1 is applied to the delay pulse generator 2 and the output of the delay pulse generator 2, that is, the delay pulse is applied to the horizontal scanning signal generator 3 and the sampler 4. An output of the horizontal scanning signal generator 3 is applied to the delay pulse generator 2 and to the horizontal axis of the cathode-ray tube 5. An output of the sampler 4 is applied to the vertical axis of the cathode-ray tube 5. The horizontal scanning signal generator 3 and the automatic trigger controlling circuit 6 are, for example, provided for a staircase wave generator.

The automatic amplitude controlling circuit 7, as illustrated in FIG. 1, provides a memory circuit, and has the differentiated output of the sampler 4 applied to a base of a transistor 12 and to a base of a transistor 33. The transistor 12 is provided with an emitter follower connection, and a collector of the transistor 12 is connected to a positive source potential 35, while the emitter of the transistor 12 is connected to a negative source potential 36 via a resistor 13 and to a ground via a variable resistor 14. A sliding contact point of the resistor 14 is connected via a capacitor 17 to a base of a transistor 18 whose emitter is grounded. A collector of the transistor 18 is connected to a positive source potential 35 via a resistor 16 and to the base of the transistor 18 via a resistor 15. The collector of the transistor 18 is also connected via a diode 19 to a capacitor 20 which is provided as a memory capacitor and which has its other terminal grounded. A memory circuit is composed ofthe diode 19, the capacitor 20, a reset switch 21, a field effect transistor 22 and a resistor 23. A connection point of thediode 19 and the capacitor 20 is connected to a gate of the field effect transistor 22 and to one terminal of the reset switch 21 whose other terminal is grounded. The reset switch can be operated manually, mechanically or electronically. A drain of the field effect transistor 22 is connected to the positive source potential 35, and a source electrode of the field effect transistor 22 is connected to the negative source potential 36 via a resistor 23. The source output of the field effect transistor 22 is connected to a base of a transistor 24 which is provided as a polarity converter. A collector of the transistor 24 is connected to the negative source potential 36 via a resistor 26, and an emitter of the transistor 24 is connected to the positive source potential 35 via a resistor 25. The collector of the transistor 24 is also connected to an emitter of a transistor 29 via a resistor 27, and to a cathode of a diode 31 whose anode is grounded. The transistor 29 is provided for shifting a DC level, and has its collector connected to a positive source potential 35; its emitter connected to the negative source potential 36 via its resistor 28; and a base connected to a slider of a variable resistor 30 whose end terminals are connected, respectively, to the positive source potential 35 and the negative source potential 36. On the other hand, a collector of the transistor 33 is connected to a positive source potential 35 via a resistor 32 and to a connection point of the collector of the transistor 24 and the cathode of the diode 31 via a capacitor 34. An emitter of the transistor 33 is grounded. A blanking signal source 11 which is connected to the base of the transistor 18 is provided for scanning only in a predetermined direction and blanking a signal during a period of scanning in a reversed direction. Usually, a signal of a hold off circuit of a staircase wave generator in the horizontal scanning signal generator 3 is used for a blanking signal of the blanking signal generator 1 1.

Referring to FIGS. 2A to 2B, the explanation of the principle of the circuit shown in FIG. 1 will be given below. When a sinusoidal signal, as shown in FIG. 2A, is sampled by the sampler in a synchronizing condition, the output of the sampler becomes a sinusoidal waveform having a staircase form as shown in FIG. 2B. As a result of this, the amplitude of the differential output becomes small as shown in FIG. 2C. However, when a signal is randomly sampled by the sampler in an unsynchronized condition the output of the sampler 4 becomes a waveform as shown in FIG. 2D. Therefore, the differentiated output of the sampler has a large magnitude of an amplitude as shown in FIG. 2E. For convenience, the detailed explanation of the automatic amplitude controlling circuit 7 will be given later. The differentiated output of the sampler causes a variation of an output of the automatic trigger controlling circuit 6, which latter output controls a variable element such as a tunnel diode included in the trigger circuit. FIG. 3 is an explanatory diagram showing a relation between the difi'erentiated output IYI of the sampler 4 and the output X of the automatic trigger controlling circuit 6. In the synchronized condition, the output X of the automatic trigger controlling circuit is displaced to the synchronized point X therefore, the value of the differentiated output IY I of the sampler 4 becomes its minimum value [Y I. The synchronized condition is maintained in the minimum value I Y I of the differentiated output of the sampler 4. In the unsynchronized condition, the output X of the automatic trigger controlling circuit 6 is displaced from its minimum value point X Therefore, the value of the differentiated output I Y I of the sampler becomes larger than the value of Y I For convenience of explanation, a case having only one minimum value is introduced. A discussion applied to the present case in the following description can well and similarly be applied to another case, wherein more than one minimum value is possessed by the curve. When the amplitude of the observing signal changes, its minimum value IY I varies as shown in FIG. 2C. As shown in FIG. 3, when the amplitude of the observing signal increases, its minimum value IY I becomes I Y, I which is larger than the value I Y I; and when the amplitude of the observing signal decreases, its minimum value I Y I becomes I Y I which is smaller than the value I Y As a result of this, it is difficult to determine the synchronization point, because for example, when the amplitude of the observing signal decreases, the synchronization point is misunderstood before reaching the value X The automatic amplitude controlling circuit 7 is provided for overcoming the above-mentioned drawback.

In the non-synchronized condition, the differentiated output waveform of the sampler 4 has a large amplitude shown in FIG. 2E. This differentiated waveform of the sampler 4 is applied as a signal I Y I to the automatic controlling circuit 6 via the transistor 33 and the capacitor 34, and thereby changes an output X of the automatic trigger controlling circuit 6. On the other hand, the output of the sampler 4 is applied to the transistor 12 provided for the emitter follower and amplified by the transistor 18. In this case, a minimum value of I Y I is proportional to an input signal and accordingly the output of the transistor 18 is proportional to an input signal. The output of the transistor 18 is stored into the capacitor 20 via a diode 19. Field effect transistor 22 is used for maintaining this stored value in the capacitor 20 for a long time. The stored DC signal in the capacitor 20 is applied as an amplitude limiting current 37 to the diode 31 via the transistor 24, thereby always maintaining a value I Y' I applied to the controlling circuit at a constant value, for example, I Y I. When a value of X does not reach the value of X the value of| Y I does not become I Y I so that the synchronizing condition is not obtained, and the automatic amplitude controlling circuit 7 renders the value of X variable. When the synchronizing condition is obtained in accordance with the variation of X, the output I Y of the sampler 4 is as shown in FIG. 2C. Therefore, the signal I Y'I applied to the automatic trigger controlling circuit becomes IY I As a result of this, the automatic trigger circuit 6 ceases its operation and the value of X becomes X,,. In this condition, if the amplitude of the signal increases without changing the current 37, IY'I becomes IY,| at the same time I Y I become IY,I and then the synchronizing condition cannot be obtained in X Under the present circumstances, the signal I Y is also applied to the transistor 12 and a larger value of the signal is stored in the capacitor 20. Accordingly, the signal 37 also becomes a larger current and is applied to the diode 31, thereby controlling the amplitude of I Y, I. As a result of this, I Y I is picked out as I Y I and becomes I Y I in X When the observing signal 10 decreases, Y I becomes I Y, And if the signal 37 does not change, Y I becomes also I Y, Iand then the synchronizing condition cannot be obtained, because the automatic trigger controlling circuit 6 ceases operating without reaching the synchronizing point X At this time, the signal stored in the capacitor 20 is discharged by a switch 21, and newly automatically stores the value proportional to I Y I, the signal 37 applied to the diode 31 decreases and I Y, I is changed to I Y I and applied to the automatic trigger controlled circuit 6. Accordingly, the synchronizing condition is obtained at the synchronizing point X The switching operation of the switch 21 can be carried out manually; or, an electronic or mechanical switch having a predetermined time constant can be used for this purpose.

FIG. 4 shows another embodiment of the present invention. FIG. 4 is similar to FIG. 1 except for the construction of the automatic synchronizing amplitude control circuit 41. Further in FIG. 1, for convenience of explanation, a sample hold cir cuit 42 and an amplifier 43 of FIG. 4 are included in the sampler. Referring to FIG. 4, the difi'erential output of the sampler 4 is connected to a base of a transistor 51 whose collector is connected through a resistor 78 to a positive source potential 76. An emitter of the transistor 51 is connected through a resistor 53 to a negative source potential 77 and through a capacitor 54 to ground. The collector of the transistor 51 is connected through a capacitor 55 to a series circuit composed of a resistor 56 and a diode 57 whose cathode is grounded. A connection point of the capacitor 55 and the series circuit is connected through a capacitor 58 to a cathode of a diode 59 that is provided for an amplitude control diode. On the other hand, an output of the sample hold circuit 42 is connected to a base of an NPN transistor 62 whose collector is connected to a positive source potential 76. An emitter of the transistor 62 is connected through a resistor 63 to a negative potential 77. An emitter follower output of the transistor 62 is connected to a cathode of a diode 64 and an anode of a diode 65. An anode of the diode 64 and a cathode of the diode 65 are respectively connected to a capacitor 66 and a capacitor 67, and to a base of a transistor 69 and a base of a transistor 71. Other terminals of capacitors 66 and 67 are grounded. A resistor 68 is connected between the bases of transistors 69 and 71.

NPN transistors

69, 70 and 71, 72 are provided in a Darlington configuration having a high impedance input circuit, and a field effect transistor can be used instead. Emitters of the

transistors

70 and 72 are connected, respectively, through resistors 73 and 74 to a negative source potential 77. The emitter of the transistor 70 is connected through a resistor 75 to a cathode of the diode 59, and the emitter of the transistor 72 is connected to an anode of the diode 59. A connection point of the anode of the diode 59 and the emitter of the transistor 72 is connected alternatingly through a capacitor 60 to ground. An output of the automatic amplitude control circuit 41 is connected to the automatic trigger controlling circuit via a capacitor 61.

Referring further to FIG. 4, in the non-synchronized condition, a differential output waveform shown in FIG. 2E of the sampler is applied to the diode 59 via the transistor 51. On the other hand, an output signal shown in FIG. 2D of the sample hold circuit 42 is applied through the emitter follower transistor 62 to the cathode of the diode 64 and the anode of the diode 65. The capacitors 66 and 67 are provided as an integrator constituting the storing elements. Output signals stored in the capacitors 66 and 67 are varied respectively with the time constant 1 determined by the resistor 68 and the capacitors 66 and 67. That is, the negative stored level 45 varies toward the positive stored level 46 and the positive stored level 46 varies toward the negative stored level 45 as shown in FIGS. 5A and 5B. The difference between the

level

45 and 46 is maintained at-the zero level in the condition where no observing signal exists. When the output voltage V is a random staircase wave, the difierence between the

levels

45 and 46 becomes irregular and the mean difference voltage becomes smaller than the maximum value of the observing signal. This difference voltage is applied to a diode 59 via

transistors

69, 70 and 71, 72 and a resistor'75. On the other hand, the amplitude of the differential output applied to the diode 59 is controlled bythe above-mentioned difference voltage and is applied to the automatic trigger controlling circuit 6 via a capacitor 61, as Y I or Y I larger than Y I as shown in FIG. 6. The output X of the automatic trigger controlling circuit 6 varies in accordance with the value I Y I. When the value X approaches the synchronization point X the value I Y I attains its minimum value in the value X At the same time, the output signal V becomes a regularly sampled staircase waveform larger than the randomly sampled output signal as shown in FIG. 58. Accordingly, the minimum value of| Y I becomes Y Iin the state of| Y Ior Y oo I near I Y I, then, the synchronizing condition is obtained. The time constant 1' which determines the

voltage differences

45 and 46 is selected in such a manner that the value Y I doesnt exceed the value I Y I in the synchronizing condition even in the minimum voltage difference between the

voltages

45 and 46.

When the observing signal increases, the differential output I Y I increases and the random observing signal V increases. Consequently, the voltage difference between 45 and 46 shown in F IG. 5 also increases and an input of the automatic trigger controlling circuit becomes Y I. When the synchronized condition is obtained, the output signal V increases and I Y I becomesI Y I or a value nearly equal to I Y I.

I When the observing signal decreases, the differential output I Y I decreases and the random observing signal V decreases.

Consequently, the voltage difference between 45 and 46 shown in FIG. also decreases and the differential output applied to the automatic trigger controlling circuit 6 increases and becomes I Y I. When X becomes X and Y I decreases in the synchronizing condition, the output signal V increases and I Y I' becomes its minimum value I Y I or a value nearly equal to l Y I. As a result of this, the response of the automatic trigger controlling circuit 6 ceases and the synchronizing condition is maintained. Referring to FIG. 4, the resistor 56 and the diode 57 are added in such a manner that the differentiating output applied to the diode 59 is a proportional relation with an amplitude of the observing signal.

When no observing signal exists, the value I Y I has a valuel Y I or a value nearly equal to Y On the other hand, when one cycle of the observing signal does not appear on the display surface in the synchronizing condition and the voltage difference between 45 and 46 decreases, the differential output I Y [decreases and the value [Y I becomes IY I or a value nearly equal to I Y I. As mentioned above, by using the voltage difference between 45 and 46 as the amplitude controlling signal of the amplitude control circuit, an automatic synchronizing condition can be obtained independent of the amplitude of the observing signal as well as the frequency of the observing signal. For the above-mentioned explanation, NPN transistors are used. However, PNP transistors can be used with some consideration to the polarity of the potential source. lf necessary, the amplifiers or emitter follower circuits can be effectively used. Further, negative polarity signals are used as the differential outputs of the automatic triggering circuit. However, positive polarity signals can be used by reversing the polarity of the

diodes

57, 59, 64 and 65. The amplifier can be deleted in the case where the differential output I Y I has asufficiently large value.

As mentioned above, by using the automatic trigger controlling circuit of the present invention, the synchronizing condition can be obtained automatically and over a wide range, independent of the variation of the amplitude of the observing signal.

Modifications of the herein disclosed circuits will occur to those skilled in the art and variouscombinations of the circuits will be capable of use together for achieving the desired results of the invention. The scope of the invention is to be interpreted accordingly as defined by the appended claims.

What is claimed is:

1. An improved method for controlling a trigger signal for a sampling device including a sampler circuit for sampling-and holding an input signal, and a trigger circuit for said sampler circuit, wherein the sampler circuit provides an output signal to be displayed, comprising the steps of differentiating the output signal of the sampler circuit to provide a differentiated output signal, producing a DC signal proportional to the differentiated output signal, storing the DC signal, modifying the amplitude of the differentiated output signal in response to variations in amplitude of the DC signal, applying the modified differentiated output signal to the trigger circuit for producing a trigger signal, and applying the trigger signal to the sampler circuit.

2. An improved trigger controlling method as set forth in claim 1, further comprising the step of limiting the modification of the differentiated output signal when said differentiated output signal is below a predetermined minimum signal level.

3. An improved trigger controlling method as set forth in claim 1, further comprising the step of selectively erasing said stored DC signal.

4. An improved method for controlling a trigger signal for a sampling device including a sampler circuit for sampling and holding an input signal, and a trigger circuit for said sampler circuit, wherein the sampler circuit provides an output signal to be displayed, comprising the steps of applying the output signal of the sampler circuit to a capacitive memory circuit, charging the capacitive memory circuit to a voltage level proportional to a maximum amplitude of the sampler circuit output signal, differentiating the output of the sampler circuit to produce a differentiated output signal, modifying the amplitude of the differentiated output signal in response to the voltage level of the memory circuit, discharging the capacitive memory circuit over a predetermined period, applying the modified differentiated output signal to the trigger circuit for producing a trigger signal, and applying the trigger signal to the sampler circuit.

5. An improved trigger controlling method as set forth in claim 4, further comprising the step of limiting the modification of the differentiated output signal when said differentiated output signal is below a predetermined minimum signal level. v

6. An improved trigger controlling method as set forth in claim 3, wherein said step of storing a DC voltage is performed by charging a capacitor,

and wherein said step of erasing said stored DC voltage is performed by shorting said capacitor.

7. An improved trigger controlling system for a sampling apparatus comprising a sampler circuit for sampling and holding an input signal to be observed and for producing an output signal to be displayed, a differential circuit for differentiating the output of said sampler circuit to produce a differentiated output signal, a trigger circuit having an output connected to the sampler circuit, automatic trigger controlling circuit means having an output connected to said trigger circuit for controlling an output signal of said trigger circuit, automatic amplitude controlling circuit means connected between said differential circuit and said automatic trigger controlling circuit, said automatic amplitude controlling circuit means including a memory circuit means for storing a DC signal proportional to said differentiated output signal of said differential circuit, and an amplitude controlling diode means for modifying said differentiated output signal in response to said DC signal, and means connecting said modified differentiated output signal to said trigger controlling circuit means thereby automatically and in a stable manner obtaining a synchronized condition.

8. An improved trigger controlling system for a sampling apparatus comprising sampler circuit means for sampling and holding an input signal and for producing a sampled output signal; amplitude controlling means including a differentiating circuit having an input connected to said sampler circuit means for producing a differentiated signal at an output thereof, capacitive memory circuit means including capacitor means and having an input connected to said sampler circuit means for charging said capacitor means to a voltage level proportional to a maximum amplitude of the sampler circuit means output signal, means for modifying said differentiated signal in response to said charged voltage level of said capacitor means to produce a modified differentiated signal, and discharging means connected to said capacitor means for discharging said charged voltage level over a predetermined time-constant period; a trigger generating circuit having an output connected to said sampler circuit means; and automatic trigger controlling means having an input connected connected to receive said modified difi'erentiated signal, and an output connected to said trigger generating circuit, whereby said sampler circuit means is automatically and stably synchronized.

Claims

1. An improved method for controlling a trigger signal for a sampling device including a sampler circuit for sampling and holding an input signal, and a trigger circuit for said sampler circuit, wherein the sampler circuit provides an output signal to be displayed, comprising the steps of differentiating the output signal of the sampler circuit to provide a differentiated output signal, producing a DC signal proportional to the differentiated output signal, storing the DC signal, modifying the amplitude of the differentiated output signal in response to variations in amplitude of the DC signal, applying the modified differentiated output signal to the trigger circuit for producing a trigger signal, and applying the trigger signal to the sampler circuit.

5. An improved trigger controlling method as set forth in claim 4, further comprising the step of limiting the modification of the differentiated output signal when said differentiated output signal is below a predetermined minimum signal level.

6. An improved trigger controlling method as set forth in claim 3, wherein said step of storing a DC voltage is performed by charging a capacitor, and wherein said step of erasing said stored DC voltage is performed by shorting said capacitor.

8. An improved trigger controlling system for a sampling apparatus comprising sampler circuit means for sampling and holding an input signal and for producing a sampled output signal; amplitude controlling means including a differentiating circuit having an input connected to said sampler circuit means for producing a differentiated signal at an output thereof, capacitive memory circuit means including capacitor means and having an input connected to said sampler circuit means for charging said capacitor means to a voltage level proportional to a maximum amplitude of the sampler circuit means output signal, means for modifying said differentiated signal in response to said charged voltage level of said capacitor means to produce a modified differentiated signal, and discharging means connected to said capacitor means for discharging said charged voltage level over a predetermined time-constant period; a trigger generating circuit having an output connected to said sampler circuit means; and automatic trigger controlling means having an input connected connected to receive said modified differentiated signal, and an output connected to said trigger generating circuit, whereby said sampler circuit means is automatically and stably synchronized.