US3587048A - Status control system - Google Patents

Abstract

N lamps, each having a different coded address, are each coupled to a different one of N flip-flops connected in tandem. The address of a particular lamp is stored in a register. A clock signal controls the binary counter and synchronously the shifting of the state of each flip-flop. A comparator is coupled to the register and the counter producing a ''''0'''' output when the stored address and the count are unequal and a ''''1'''' output when the stored address and count are equal. The latter output occurs when the present state of the flip-flop associated with the addressed lamp appears in the last flip-flop. An electronic switch responds to the ''''0'''' output to connect the flip-flops in a loop and to the ''''1'''' output to inject a coded signal indicative of the status to be assumed by the addressed lamp into the first flipflop and to control the state thereof by the injected coded signal. The shifting of the status of the flip-flops continues during the remaining counts of the counter. At the end of the count, the state induced by the status signal in the first flipflop is present in the flip-flop associated with the addressed lamp and will accordingly control the status of this lamp. Different variations of the above basic system are also disclosed.

Description

United States Patent [72] Inventor Thomas G. Brown, Jr. Ridgewood, NJ.

[21 Appl. No. 865,336

[22) Filed Oct. 10, i969 [45] Patented June 22, 1971 [73] Assignee International Telephone and Telegraph Corporation Nutley, NJ.

[54] STATUS CONTROL SYSTEM H 13,ss7,04s

Primary Examiner-Donald J. Yusko Attorneys-Comell C. Remsen, Jr., Walter J. Baum, Paul W. Hemminger, Percy P. Lantzy, Philip M. Bolton, Isidore Togut and Charles L. Johnson, Jr.

ABSTRACT: N lamps, each having a different coded address, are each coupled to a different one of N flip-flops connected in tandem. The address of a particular lamp is stored in a register. A clock signal controls the binary counter and synchronously the shifting of the state of each flip-flop. A comparator is coupled to the register and the counter producing a 0" output when the stored address and the count are unequal and a 1 output when the stored address and count are equal. The latter output occurs when the present state of the flip-flop associated with the addressed lamp appears in the m Clams 2 Drawing last flipflop. An electronic switch responds to the 0 output U.S. to connect the in a loop and to the 1 output [9 in- 178/3, 340/ 168 ject a coded signal indicative of the status to be assumed by [5|] Int. Cl... .o HOll 5/00, th addressed lam into the first flip-flop and to control the state thereof by the injected coded signal. The shifting of the [50] Fleld of Search 340/147, status f th fli .fl ntinues during the remaining counts 168, 168 s, 163 R; 178/ 3 of the counter. At the end of the count, the state induced by the status signal in the first flip-flop is present in the flip-flop [56] References Cited associated with the addressed lamp and will accordingly con- UNITED STATES PATENTS trol the status of this lamp. Different variations of the above 3,522,587 8/ l 970 Brown, Jr. 340/147 basic system are also disclosed.

Sums n. some/we SWITCH I8 szr/esszr 7 Pu FLOP I g (0050 I [R T s LAMPS i X Aigl-g zn l I N- 5/2 moczssom I g 2 22 9 Ml 1 W nooness i 5 i I REGISTER z i i l i r R T5 2 1 j j 5 1 K I? crcuc I i -r" 7 BIMRY O l i COUNTER r r i RAESL'T I i mma/r Y i /GWA L RIP H0A 7 PROCESSOR 26 27 1 l2 STATUS CONTROL SYSTEM BACKGROUND OF THE INVENTION This invention relates to control systems and more particularly to a system to independently control the status of a plurality of devices, such as lamps, relays and the like.

The following description will be of a status control system as employed in a status display system wherein the status (on or off) of a lamp is controlled to represent the status of an associated communication line. It is to be remembered, however, that this description is only for purposes of explanation, since the status control system could be employed to control the status of a plurality of relays or similar devices rather than lamps.

In a particular status display system there are a large number of indicator lamps to indicate the status or condition of a number of communication lines and the like. The instructions regarding the status change and address of a particular lamp to which this status change is directed is presented to the status display system in a coded form from an external source. Let us assume, for the purposes of explanation, that l2 indicator lamps are present to have their status changed so as to indicate the status of a number of communication lines. Instructions from an external source, such as a message processor at the site of the display system, appears in the form of a code identifying the number or address of the particular lamp to have its status'changed and to tell whether the particular lamp should be turned on or off.

To provide the instructions for 5 I 2 lamps, it is necessary to provide signal conductors to present the coded instructions in parallel form from the message processor, nine of these signal conductors being used to identify the address of a particular lamp and the tenth of these conductors being used to indicate whether to turn the addressed lamp on or off. In a known prior art arrangement selection gates respond to these instructions to decode the instructions and to energize the set or reset conductor leading to the flip-flop associated with the addressed lamp, said associated flip-flop being one of 512 flipflops arranged in parallel between the selection gates and their associated lamp.

The selection gates involve a large amount of equipment. In the most straightforward, or brute force, arrangement of selection gates, there would be a total of 1024 gates, each with 10 inputs, assuming the typical example of 512 lamps mentioned hereinabove. It is also known prior art to cascade gates. For example, the 10 signal conductors could be divided into two groups of five each, each group could be fed into a full I- out-of-32 decoder, and the decoder outputs could be fed to 1024 gates, each with two inputs, one from each of the two decoders, with the interconnections so arranged that each of the I024 gates is uniquely selected by one of the instruction codes. Other cascading arrangements are also known, but in all cases they always use at least 1024 two-input gates plus some additional gating.

SUMMARY OF THE INVENTION An object of the present invention is to provide an improved status control system.

Another object of the present invention is to provide an improved status control system for employment in a status dis play system.

A further object of the present invention is to provide an improved status control system having a substantial reduction in the amount of equipment employed therein.

Still another object of the present invention is to eliminate the selection gates previously employed in status display or control systems and to replace them with a much smaller amount of equipment.

A feature of the present invention is the provision of a system to control the status of a plurality of devices comprising N of the devices to have their status independently controlled, each of the N devices being identified by a different coded address; N bistable means coupled in a tandem arrangement, each of the N means being coupled to a different one of the N devices to control the status thereof in accordance with the state of the associated one of the N means; first means coupled to each of the N means to shift the state of each of the N means through the tandem arrangement thereof; a first source of coded address for a particular one of the N devices; a second source of coded status signal indicating the status that the particular one of the N devices is to assume; and second means coupled to the first and second sources, the first means and the tandem arrangement responsive to the coded address to connect the tandem arrangement in a loop for a first controlled period of time, to disconnect the loop and couple the first of the N means in said tandem arrangement to the second source to inject the status signal into the tandem arrangement after the first controlled period of time, and to reestablish the loop for a second controlled period of time after the injection of the status signal to enable control of the stated the one of the N means associated with the particular one of the N devices in accordance with the status signal and thereby control the status of the particular one of the N devices.

In accordance with the principles of the present invention the particular device addressedhas had its state modified, all

other devices have been restored to their original state existing prior to the start of the operation, and the system in now capable of accepting a new instruction from the processor. Furthermore, until a new instruction is received from the processor, the system will continue to maintain the existing states of all devices.

BRIEF DESCRIPTION OF THE DRAWING The above mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawings, in which:

FIG. I is a block diagram of one prior art arrangement of a status display system as mentioned hereinabove under the heading BACKGROUND OF THE INVENTION; and

FIG. 2 is a block diagram of a status display system incorporating the status control system of the present invention.

DESCRIPTION OF THE PRIOR ART Referring to FIG; I, there is illustrated therein a block diagram of a prior art status control system incorporated in a status display system 11. Employing the above-mentioned example employed, the number of lamps to have their status controlled is equal to 5 I2, in other words N=5 12. In this situation 10 parallel conductors are coupled from processor 12 to provide the coded instructions to system lll. Nine of these lines are employed for the coded address of a particular one of the 512 lamps. The tenth line is to provide coded information as to the status the addressed lamp is to assume.

The IO coded instruction conductors are coupled to selection gates 13 which, as pointed out hereinabove under the heading BACKGROUND OF THE INVENTION, includes 1024 gates, each with 10 inputs, used to decode the coded instructions to energize the set lines 14 or reset lines I5, respectively, coupled in parallel to the output of gates 13. Each of these set and reset lines 14 and 15 are coupled to one of 512 parallel arranged flip-flops 16, each of which have their 1" output coupled to an associated one of the 5 I2 lamps.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 2, there is illustrated therein a block diagram of a status display system incorporating the status control system of the present invention which enables the elimination of the 1024 selection gates and the replacement thereof by a much smaller amount of equipment.

As before, it will be assumed that there are 512 lamps (@512) to have their status controlled. As in the prior art arrangement of FIG. 1, there are associated with each of the lamps one of the flip-flops 17. However, instead of using individual selection gates with each of the flip-flops 17, flip-flops 17 are connected in a tandem arrangement and under certain conditions of electronic switch 18 will be connected in one large loop. The information in the top one of flip-flops 17, flipflop 17 can be shifted to the one below and so on down to the last flip-flop, flip-flop 17,. Information in the last flip-flop of the tandem arrangement, flip-flop 17,, can be shifted via electronic switch 18 directly to the set input of the top flipflop l7 and through NOT 19 to the reset input of flip-flops 17 One embodiment of the electronic switch 18 is illustrated as including INHIBIT gate 20 and AND gate 21 with the operation of switch 18 and, hence, gates 20 and 21 being under control of the output of binary comparator 22,

The coded instructions from a processor similar to processor 12 are stored in set/reset flip-flop 23 and address register 24. The instruction stored in flip-flop 23 indicates the status to be assumed by the addressed lamp and the instructions stored in address register 24 indicate the address for the particular lamp that is to have its status controlled in accordance with the status instructions stored in flip-flop 23. Cyclic binary counter 25 has a range equal to the number oflamps, which in the example employed herein would be a nine bit binary counter with a range ofS l2 states. Busy flip-flop 26 is coupled to the cyclic binary counter 25 and processor 12 and is set when an instruction is received from processor 12 and is reset from its set state when counter 25 reaches the final state of the counting cycle. The result is a set signal from flip-flop 26 having a duration equal to one counting cycle. This set signal is employed as an inhibit signal to processor 12 to prevent a new set of instructions until the system has operated on the first set of instructions and which also is employed by AND gate 27 to provide a clock from clock source 28 to operate counter 25 and also to cause the shifting of the states of flip-flops 17 in the tandem arrangement thereof through switch 18 when properly positioned to connect the tandem arrangement in a loop as described above. Clock 28 is merely a repetitive pulse train obtained either from an internal oscillator, or from an external source if available, but is necessary to synchronize the counting of counter 25 and the shifting of the states offlip-flops 17.

The basic technique for changing one of the lamps is to cycle the tandem arrangement of flip-flops l7 completely one time, i.e., shift 512 times in the example employed herein. During each of these shifts except one, INHIBIT 20 is operative and AND 21 inoperative so as to close the loop. During one particular shift, switch 18 is activated by the output of comparator 22 to inhibit INHIBIT 20 and enable AND 21 so as to transfer the contents of flip-flop 23 into the first flip-flop, flip-flop 17 of the tandem arrangement. The time at which switch 18 is placed in this condition is chosen to coincide with the time at which the information or state of the flip-flop associated with the addressed lamp is being fed from the bottom flip-flop (flip-flop 17,) to switch 18. At each of the l2 individual shifting operations, cyclic counter 25 is advanced by one, with the result that the state of counter 25 always indicates the number or address of the particular lamp whose previous status information is being fed from bottom flip-flop 17,. The state of counter 25 is compared against the content of address register 24 by comparator 22 and the comparator output is a control signal for the electronic switch. When the comparator output signal indicates an inequality in the contents of register 24 and counter 25 there is a 0" condition at the output of comparator 22 to enable INHIBIT and to disable AND 2l. This results in closing the loop. When comparator 22 indicates an equality in the contents of register 24 and counter there is a l output therefrom which inhibits IN- HIBIT 20 and enables AND 21 resulting in disconnecting the loop and thereby enabling transfer of the content of flip-flop 23 to flip-flop 17 On the next shift and count of counter 25, comparator 22 will again indicate an inequality in the contents of register 24 and counter 25, the loop will be reestablished and the shifting will continue for the remaining counts of counter 25. This will result in the status control signal from flip-flop 23 being present in the flip-flop associated with the addressed lamp which then will control the status of this particular lamp to assume the status of the information contained in the status control signal stored in flip-flop 23. This completes one cycle of the operation of the status control system.

The illustrated numbering of the flip-flops 17, with flip-flop 17 being at the top and flip-flop 17 being at the bottom in the tandem arrangement, is useful in showing that the previous status of the addressed lamp will appear in the last flip-flop 17 of the tandem arrangement when an equality is present as indicated by comparator 22. Thus, if lamp number 1 were the addressed lamp, on the first count of counter 25 comparator 22 would recognize an equality and, thus, would cause flipflop 23 to be connected to flip-flop 17,, of switch 18. After this switch 18 reestablishes the loop and counter 25 would then continue counting through 5ll counts until the status from flip-flop 23 for lamp 1 is contained in flip-flop 17,. On the other hand, if the addressed lamp were 512, the present status of flip-flop 17,, would have to be shifted through the complete tandem arrangement before binary comparator 22 would indicate equality at which time switch 18 would open the loop and apply the information from flip-flop 23 to flip-flop 17,, at which time the cycle of operation is completed and lamp 512 would assume the new status indicated by the status signal from flip-flop 23.

It is necessary that lamp change instructions occur relatively infrequently. Whenever a lamp change instruction is not being performed, each lamp will be fed the proper information which pertains to it. However, during the operation of changing the status of one lamp, all lamps are sequentially fed information pertaining to all other lamps, but once the operation is completed each lamp is again fed the information which pertains to it. Typically, the stepping of the tandem arrangement of flip-flops would be done with a clock rate of 1 megahertz. Therefore, with the example employed herein, the time required to complete one operation or cycle is 512 microseconds. This 512 microsecond disturbance in the information fed to each lamp is of no significance, since a lamp cannot respond in that time. The lamp display system can accept new orders no more frequently than every 5l2 microseconds, but this restriction is of no importance in most conceivable applications because of limitations on how often the status information could change and on the ability of a viewer to respond to changes.

There are several variations possible in the basic arrangement of FIG. 2. One is to eliminate comparator 22, change address register 24 to add the capability of counting, and add a gate to sense when the address register has reached a particular state, such as zero when counting in the backward direction, or the maximum possible count when counting in the forward direction. The output of this gate is used in the place of the comparator output. These design choices are of a routine nature. However, it should be noted that for an upward count of register 24 and the gate detecting a maximum count the order of the numbering or addresses of the lamps would have to be as illustrated in FIG. 1 to have the tandem arrangement of FIG. 2 operate properly. However, if the register were caused to count backward and the gate sensed a zero count, then the sequence of numbering of the lamps, the addresses of the lamps, could be as indicated in FIG. 2.

The scheme has application whenever the signals from the tandem arrangement are controlling devices which can tolerate a momentary disturbance during a change operation. As mentioned previously lamps can do this. In most instances, relays also can do so, although if the relays are extremely highspeed types and if there are a very large number of them, a marginal condition might arise. However, this could easily be solved by breaking up the tandem arrangement into several smaller loops, and providing suitable gating to interconnect the appropriate loop to the electronic switch.

The invention cannot be used when the controlled devices cannot tolerate momentary disturbances. However, a variation can be introduced in the system of FIG. 2 for this situation. This variation is to introduce a secondary flip-flop between each flip-flop of the tandem arrangement and the controlled device. The additional flip-flop would hold the information pertaining to the given lamp constant during the time the tandem arrangement is cycling. Once the cycling operation has been completed, information will be transferred from the flip-flops of the tandem arrangement to the secondary flip-flops. In all cases, but one, the secondary flip-flop would be unchanged, just the one associated with addressed controlled device would be changed.

Another variation which is possible is to provide means for clearing all lamps and for setting all lamps, which is useful for initialization and testing. This is readily accomplished by providing means to continuously connect electronic switch 18 to the set/reset flip-flop 23 during the entire cycle time, and means for decoding such an instruction to distinguish it from the customary type. Alternatively, or in addition, means can be provided to use a signal from a manual switch instead of a coded instruction from the processor.

The advantage of the approach of the invention over the prior art is even greater than the direct reduction in the required equipment. Most of the equipment now consists of flipflops cascaded in a serial-shift-register form. This arrangement is widely used for other purposes, and as a result is becoming widely available in efficiently packaged-integrated circuits containing a number of stages per package.

While I have described above the principles of my invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example.

lclaim:

l. A system to control the status of a plurality of devices comprising:

N of said devices to have their status independently controlled, each of said N devices being identified by a different coded address;

N bistable means coupled in a tandem arrangement, each of said N means being coupled to a different one of said N devices to control the status thereof in accordance with the state of the associated one of said N means;

first means coupled to each of said N to shift the state of eachof said N means through said tandem arrangement thereof;

a first source of coded address for a particular one of said N devices;

a second source of coded status signal indicating the status that said particular one of said N devices is to assume; and

second means coupled to said first and second sources, said first means and said tandem arrangement responsive to said coded address to connect said tandem arrangement in a loop for a first controlled period of time, to disconnect said loop and couple the first of said N means in said tandem arrangement to said second source to inject said status signal into said tandem arrangement after said first period of time, and to reestablish said loop for a second controlled period of time after said injection of said status signal to enable control of the state of the one of said N means associated with said particular one of said N devices in accordance with said status signal and thereby control the status of said particular one of said N devices.

2. A system according to claim 1, wherein:

said first period of time is that amount of time necessary to shift the present state of the one of said N means associated with said particular one of said N devices to the last one of said N means in said tandem arrangement; and

said second period of time is that amount of time necessary to shift said status signal from the first one of said N means in said tandem arrangement to said one of said N means associated with said particular one of said N devices.

3. A system according to claim 1, wherein:

each of said N means includes a flip-flop.

4. A system according to claim 1, wherein:

each of said N devices includes a lamp. 5. A system accordlng to claim 1, wherein:

said first means includes a clock source. 6. A system according to claim 1, wherein: said second means includes an electronic switch means to connect said tandem arrangement in said loop during said first and second periods of time and to connect the first of said N means of said tandem arrangement to said second source between said first and second periods of time.

7. A system according to claim 6, wherein: said second means further includes a register coupled to said first source to store said coded address;

a cyclic binary counter coupled to said first means to count in synchronism with the shifting in said tandem arrangement;

a binary comparator coupled to said register and said counter to. produce a control signal having a binary 0 when said address and the count of said counter are unequal which defines said first and second periods of time and a binary l when said address and the count of said counter are equal to define the time of injecting said status signal into the first of said N means of said tandem arrangement; and

means to couple said control signal to said switch means to control the operation thereof.

8. A system according to claim 7, wherein: said first means includes a clock source;

a flip-flop coupled to said counter set at the start of the operation by a signal from said first source and reset at the maximum count thereof;

a coincidence device coupled to said clock source and said flip-flop to provide a .clock signal;

means coupling said clock signal to said counter to control the counting thereof and to each of said N means to control the shifting thereof; and

means coupling the output of said flip-flop to said first and second sources to inhibit output signals therefrom during the counting of said counter.

9. A system according to claim 8, wherein: each of said N means include 10. A system according to claim 9, wherein: said second source includes a set/reset flip-flop.

Claims (10)

1. A system to control the status of a plurality of devices comprising: N of said devices to have their status independently controlled, each of said N devices being identified by a different coded address; N bistable means coupled in a tandem arrangement, each of said N means being coupled to a different one of said N devices to control the status thereof in accordance with the state of the associated one of said N means; first means coupled to each of said N to shift the state of each of said N means through said tandem arrangement thereof; a first source of coded address for a particular one of said N devices; a second source of coded status signal indicating the status that said particular one of said N devices is to assume; and second means coupled to said first and second sources, said first means and said tandem arrangement responsive to said coded address to connect said tandem arrangement in a loop for a first controlled period of time, to disconnect said loop and couple the first of said N means in said tandem arrangement to said second source to inject said status signal into said tandem arrangement after said first period of time, and to reestablish said loop for a second controlled period of time after said injection of said status signal to enable control of the state of the one of said N means associated with said particular one of said N devices in accordance with said status signal and thereby control the status of said particular one of said N devices.

2. A system according to claim 1, wherein: said first period of time is that amount of time necessary to shift the present state of the one of said N means associated with said particular one of said N devices to the last one of said N means in said tandem arrangement; and said second period of time is that amount of time necessary to shift said status signal from the first one of said N means in said tandem arrangement to said one of said N means associated with said particular one of said N devices.

3. A system according to claim 1, wherein: each of said N means includes a flip-flop.

4. A system according to claim 1, wherein: each of said N devices includes a lamp.

5. A system according to claim 1, wherein: said first means includes a clock source.

6. A system according to claim 1, wherein: said second means includes an electronic switch means to connect said tandem arrangement in said loop during said first and second periods of time and to connect the first of said N means of said tandem arrangement to said second source between said first and second periods of time.

7. A system according to claim 6, wherein: said second means further includes a register coupled to said first source to store said coded address; a cyclic binary counter coupled to said first means to count in synchronism with the shifting in said tandem arrangement; a binary comparator coupled to said register and said counter to produce a control signal having a binary ''''0'''' when said address and the count of said counter are unequal which defines said first and second periods of time and a binary ''''1'''' when said address and the count of said counter are equal to define the time of injecting said status signal into the first of said N means of said tandem arrangement; and means to couple said control signal to said switch means to control the operation thereof.

8. A system according to claim 7, wherein: said first means includes a clock source; a flip-flop coupled to said counter set at the start of the operation by a signal from said first source and reset at the maximum count thereof; a coincidence device coupled to said clock source and said flip-flop to provide a clock signal; means coupling said clock signal to said counter to control the counting thereof and to each of said N means to control the shifting thereof; and means coupling the output of said flip-flop to said first and second sources to inhibit output signals therefrom during the counting of said counter.

9. A system according to claim 8, wherein: each of said N means include a flip-flop.

10. A system according to claim 9, wherein: said second source includes a set/reset flip-flop.

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