US3479521A - Current driver organization - Google Patents

Description

Nov. 18, 1969 R. c. SNARE CURRENT DRIVER ORGANIZATION 3 Sheets-Sheet 1 Filed March 25, 1966 FIG. /A

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A L lM/TER L/M/TER CURRENT.

CONTROL SOURCE CURRENT SWITCH so uRcEf' INVENTO/P R C. SNARE Nov. 18, 1969 R. c. SNARE 3,479,521

CURRENT DRIVER ORGANIZATION Filed March 25, 1966 3 SheetsSheet 2 FIG. IB

UPPER r sarcnou A TES //0 42 421 422/, N1 A12 I l I l T 65 3z .40 LEFTXI R/GHTX F sLcr i SELECT- /ON I I /0/v GATE 4 GATE I ,,-50 l V 63/1 BIASED CORE ///0 ACCESS SWITCH MATRIX 45 LOWER Y LSELECf/ON GA r55 x AXIS /9 CURRENT DRIVER Nov. 18, 1969 R. c. SNARE 3,479,521

CURRENT DRIVER ORGANIZATION Filed March 25, 1966 3 Sheets-Sheet 3 VOLTAGE ON THE CONDUCTOR a b c FIG. 2B

VOLTAGE ON THE CONDlCTOR a b c d FIG. 2C I CURRENT THROUGH TH a 1 FIG. 20 W C URRE N T A THROUGH THE WIND/N6 42 (1 b C d United States Patent 3,479,521 CURRENT DRIVER ORGANIZATION Ronald C. Snare, Columbus, Ohio, assignor to Bell Telephone Laboratories, Incorporated, New York, N.Y., a corporation of New York Filed Mar. 25, 1966, Ser. No. 537,499 Int. Cl. H03k 4/00 US. Cl. 307-88 5 Claims ABSTRACT OF THE DISCLOSURE The invention is a circuit arrangement which supplies a trapezoid-shaped current pulse to a selected magnetic core access switch in a memory. The arrangement includes switches that connect a constant direct current source to a parallel combination of the collector-emitter path of a transistor and a selected magnetic access switch. A resistance-capacitance network supplies a monotonically decreasing potential to the base of the transistor for controlling formation of corners of the trapezoid-shaped current pulse without ringing.

This invention relates to electronic circuits and, more specifically, to a circuit configuration for supplying trapezoidal current pulses to an inductive load, e.g., to a selection winding coupled to a magnetic core array.

Coincident current selection of one of a matrix array of biased core access switches to interrogate a particular digital word stored in a memory embodiment is widely employed in the information retrieval art. In a typical such organization, trapezoidal current waveforms are coincidently supplied to orthogonal x and y axis selection conductors to switch flux in an access core at the intersection of the energized windings. A memory word interrogating solenoid is coupled to each core and is responsive to flux being switched in the associated core for having a potential induced therein which translates a corresponding stored information word onto a plurality of digit sensing conductors.

However, the high frequency Wave components manifested by the discontinuity occurring at the termination of the leading edge of the trapezoidal driving current pulse are often coupled to the digit sensing conductors through spurious induction and/or electrostatic conduction paths. Accordingly, these noise signals give rise to an increased error probability in the information digits detected on the digit sensing conductors.

It is therefore an object of the present invention to provide an improved current driver configuration.

More specifically, an object of the present invention is the provision of a trapezoidal type current pulse generating arrangement suitable for driving inductive load elements.

It is another object of the present invention to provide a current driver arrangement for generating a trapezoidal current waveshape which exhibits a regular transition between the leading edge and plateau thereof.

These and other objects of the present invention are realized in a specific illustrative memory interrogating arrangement for energizing a selected one of a plurality of biased core access switches with a trapezoidal current pulse. The organization includes switching circuitry for connecting a constant current source to the parallel combination of a transistor and a selected access switch winding. In addition, a resistance-capacitance impedance net work is employed to connect a potential source to the base of the transistor.

The impedance network gives rise to a monotonically decreasing potential across the inductive access core winding, thereby causing the leading edge of the resulting Patented Nov. 18, 1969 trapezoidal access current to exhibit a gradually increasing, regular characteristic. Since the initial portion of the switch energizing current is free from discontinuities, relatively little noise is injected in the composite memory system during a memory interrogating cycle.

It is thus a feature of the present invention that an inductive load driving organization include a transistor connected in parallel with the load, a potential source characterized by a monotonically decreasing output voltage connected to the transistor base terminal, and a constant current-source connected in series with the shunt transistor-inductive load combination.

It is another feature of the present invention that a current generating arrangement include a transistor, an inductive load connected to the transistor emitter and collector terminals, a constant voltage source, a resistancecapacitance coupling network connecting the voltage source with the transistor base terminal, a constant current source, and switching circuitry for selectively connecting the current source in series with the transistor.

A complete understanding of the present invention and of the above and other features, advantages and variations thereof may be gained from a consideration of the following detailed description of an illustrative embodiment thereof presented hereinbelow in conjunction with the accompanying drawing, in which:

FIGS. 1A and 1B respectively comprise the left and right portions of a schematic diagram illustrating a current driver organization which embodies the principles of the present invention; and

FIGS. 2A through .2D comprise timing diagrams depicting the voltage and current waveshapes characterizing selected circuit components included in the arrangement shown in FIGS. 1A and 1B.

Referring now to FIGS. 1A and 1B, hereinafter referred to composite FIG. 1, there is shown a current driver organization for switching flux in a selected one of a matrix array of biased square loop, ferromagnetic access switch cores 51. Each access core 51 is biased to a first relative hysteresis orientation by a common biasing winding 56 and a current source serially connected thereto. Also coupled to each core 51 is a y axis selection winding 42, and an x axis selection winding 63,. Upper and lower y axis selection gates 40 and 45 are employed to selectively connect one of the y axis selection windings 42 to two y axis energizing conductors 25 and 35. Similarly, right and left x axis selection gates 60 and are functionally adapted to connect a selected x axis winding 63, to two x axis energizing conductors 83 and 84.

In accordance with characteristic coincident current selection operation, y and x axis current drivers 10 and are employed to coincidently supply current pulses to the selected y and x axis windings 42 and 63 via the conductors 25 and 35, and 83 and 84. The magnetic bias generated by the energized biasing winding 56 is overcome, and flux is switched, only in the access core 51 coupled to both of the activated selection windings 42 and 63,, Le, only in the core 51 located at the intersection of these windings.

A solenoid 58 is coupled to each core 51 and is energized when flux is switched in the associated core. The current which flows in an activated solenoid 58,,' may be employed, for example, to interrogate a corresponding information word contained in a twister memory, as shown in A. H. Bobeck Patent 3,069,665, issued Dec. 18, 1962.

The y axis current driver 10, which is illustrative of the drivers 10 and 80, is shown in detail in FIG. 1 and is operative to supply a current waveform of a generally trapezoidal geometry, shown in FIG. 2D, to a selected y axis conductor 42 It is observed that the transition region 100 shown in FIG. 2D between the leading edge and the plateau of the current trapezoid exhibits a regular characteristic free from the sharp discontinuities which give rise to high frequency Fourier wave components. Accordingly, when x and y axis current pulses of the above-considered type are used to select a specific access core, relatively small spurious noise potentials are capacitively and inductively coupled to the memory digit sensing conductors (not shown in the drawing), and hence memory interrogation errors are significantly reduced.

Returning now to FIG. 1, the y axis current driver is shown as including two interconnected volfage limiters 20 and 30. The limiter 20 includes a transistor 24 having the base terminal thereof connected to ground by a capacitor 23. A negative potential source 21, which supplies an output potential of V volts, is connected to the ungrounded terminal of the capacitor 23 through a resistor 22. Similarly, the limiter 30 includes a transistor 34 having a grounded collector terminal and a base terminal connected to ground through a capacitor 33, with a negative voltage source 31 supplying a voltage of V volts to the capacitor 33 via a' resistor 32.

Two current switches 11 and 13, respectively comprising transistors 12 and 14 having the collector terminals thereof grounded, are employed to selectively provide low impedance current by-passes across the limiters 30 and 20. The transistors 12 and 14 are respectively rendered conductive when a control source 15 energizes two output conductors 16 and 17 connected thereto. Similarly, the two limiters included in the x axis current driver 80 are controlled by the source 15 by way of two conductors 18 and 19.

A current source38 supplies a constant current of I amps, in a direction shown in the drawing, to a circuit junction point 29 through an inductor 37, with the emitters of the transistors 14 and 24 and the y axis energizing conductor 35 also being connected to the junction point 29. Finally the emitters of the transistors 12 and 34, the collector of the limiter transistor 24, and the y axis energizing conductor 25 are each connected to a circuit junction point 28.

When the FIG. 1 arrangement resides in its quiescent state, the transistors 12 and 14 are both enabled by the control source 15 and the leads 16 and 17. Accordingly, the current I supplied by the constant current source 38 flows downward through the transistor 14 following the dotted path 100 shown in FIG. 1, with the transistor 14 being in a saturated condition. Since both of the transistors 12 and 14 are energized at this time, relatively low, near ground potentials are supplied by the emitters of these devices to the y axis leads 25 and 35, as shown prior to the time a in FIGS. 2A and 2B. correspondingly, no y axis current is supplied to the selected y axis conductor 42 connected to the y axis energizing leads 25 and by the y selection gates and 45, as depicted for the interval prior to the time a in FIG. 2D. In addition, while the composite FIG. 1 organization resides in its quiescent state, the negative voltage sources 21 and 31 included in the limiters 20 and 30 charge the capacitors 23 and 33 to a quiescent potential of V volts through the associated resistors 22 and 32.

To initiate a y axis energizing trapezoidal pulse, assume that the control source 15 deenergizes the conductor 17 at the time a shown in FIGS. 2B through 2D, thereby rendering the switch 13 transistor 14 nonconductive. The constant current I supplied by the source 38 now attempts to How through a circuit path comprising the still conducting current switch 11, the conductor 25, the selected y axis winding 42,, the conductor 35, and the inductor 37, which circuit path is indicated by a dotted vector 110 in FIG. 1. However, the y axis winding 42, is coupled to a plurality of ferromagnetic access cores 51 and thereby presents a highly inductive impedance to the above-identified series path. Thus, when the current switch 13 is open-circuited by the deenergized conductor 17, the current which flows through the inductor 37 attempts to decrease. Accordingly, the inductor 37 is operative to impress a large negative potential on the node 29 and consequently on the lead 35, as shown in FIG. 2B.

When the negative voltage on the conductor 35 attains the value --V,, the limiter 20 transistor 24 begins to conduct since a potential of V volts is also impressed by the capacitor 23 at this time on the transistor base terminal. Accordingly, the transistor 24 is operative to initially clamp the lead 35 to a potential comprising the algebraic sum of -V volts (the transistor base potential) and a small, negligible potential equal to the transistor 24 base-emitter diode junction voltage drop. This potential of essentially V volts for the conductor 35 is shown at the time a in FIG. 2B.

The potential of the upper y axis energizing conductor 25 following time a remains essentially at zero voltage, as illustrated in FIG. 2A, since the current switch 11 transistor 12 remains conducting. Hence, a net potential of +V volts is supplied by the conductors 25 and 35 across the inductive load comprising the selected y axis winding 42, and the ferromagnetic cores 51, coupled thereto.

and letting L represent the equivalent load inductance, the initial expression for the current i(t) flowing through the selection axis winding 42 after the time a is Hence, as shown in FIG. 2D, the current waveshape impressed in the winding 42 following the time a is initially linear, with a slope of V /L.

However, as time progresses, the conducting transistor 24 is adaptive to draw charge out of the capacitor 23 faster than the source 21 can replace it through the resistor 22. Hence, the transistor 24 base potential, and thereby also the clamping potential applied to the conductor 35, decreases rapidly, as shown in FIG. 2B.

Since @(t) in Equation 2 is therefore a monotonically decreasing function of time, the current i(t) will be less than the linear upper bound given in Equation 3. The particular expression for the leading edge of the trapezoidal current waveform illustrated in FIG. 2D depends upon how close the reactive circuit components comprising the equivalent load inductance L and the capacitance C of the capacitor 23 are to critical damping. In

particular, the current will be of the general form Kfle z( or a sum of these factors, where K K and a are different constants which depend upon the specific circuit parameters.

Independent of the specific quantitative expansion for the leading edge of the driving current Waveform, the operation of the FIG. 1 organization qualitatively proceeds as follows. After the time a when the control source 15 turns off the current switch transistor 14, the full value I of the current supplied by the source 38 flows through the dashed path shown in FIG. 1 comprising the current switch 11, the limiter 20 transistor 24, and the inductor 37. Coincidently therewith, current begins to monotonically build up in the selected y axis winding 42 with this current being deviated from the transistor 24. More specifically, the current in the selected winding 42, follows the dotted path shown in FIG. 1 which includes the switch 11 transistor 12, the conductor 25, the winding 42,, the conductor 35, and the inductor 37. This current transfer process continues in a regular manner, with the current flowing through the selected winding 42, being at all times less than the linear upper bound given by Equation 3. When substantially all the current I flows through the selected winding 42,, i.e., at the time b shown in FIGS. 2B through 2D, the voltage present on the lower y axis energizing conductor 35 given by Equation 1 is small, and conduction through the transistor 24 is extinguished. The plateau current value of I amps then continues to flow through the winding 42,, as shown for the interval between the times b and shown in FIG. 2D. Moreover, the transition between the current waveform regions preceding and following the time b is regular and free from noise generating discontinuities, as shown in FIG. 2D for the region 100.

To terminate the current driving pulse, assume that the control source 15 is operative at a time c shown in FIGS. 2A through 2D to energize the lead 17, hence rendering the current switch 13 transistor 14 conductive, and to then deenergize the conductor 16, thereby open circuiting the transistor 12. The conducting transistor 14 by-passes the current I supplied by the source 38 to ground through the aforementioned dotted path 100 with the transistor 14 residing in a saturated condition, thereby impressing a near ground potential on the conductor 35, as shown in FIG. 2B following the time c.

The energy stored in the inductive load element, which has a current of I amps flowing therethrough at the time 0, attempts to sustain this current and hence impresses a negative potential on the conductor 25. This potential state for the upper y axis energizing conductor 25 is shown in FIG. 2A for the time c. This voltage turns on the limiter 30 transistor 34 which initially clamps the lead 25 to its base potential, i.e., to V volts in accordance with the voltage initially stored in the capacitor 33.

The limiter 30 then functions in a manner analogous to the operation of the limiter 20 described above. In particular, charge is extracted from the capacitor 33 to drive the base of the transistor 34, such that the y axis conductor 25 is clamped to a monotonically decreasing potential following the time c, as shown in FIG. 2A. This diminishing potential impressed across the conducting inductive load element gives rise to a trailing trapezoidal current edge which is always greater than a linear lower bound. While the particular shape of the trailing current edge is dependent upon the specific circuit parameters, a representative curve therefor, shown as a gradual transition to zero current, is depicted following the time c in FIG. 2D.

Hence, the y axis current driver has been shown by the above to supply the current waveform illustrated in FIG. 2D to the selected y axis winding 42,. In a similar manner, the x axis driver 80 coincidentally supplies a like waveform, shown in FIG. 2C, to a selected x axis conductor 63,-. The sum of these currents at or about the time b is sufficient to generate a magnetizing force which switches flux in the selected core 51 and to thereby induce a potential in the selected memory-interrogating solenoid 58, Since each of these currents exhibits a regular characteristic at and about the time b, system access noise problems are minimized.

In addition to alleviating spurious noise difliculties, it is observed that the limiters and 30 perform the salutary function of limiting the absolute potentials appearing in the FIG. 1 arrangement to 1V,[ Volts during circuit switching intervals. From a component rating and cost standpoint, this is desirable in comparison with the large voltage transients which are otherwise produced as currents are switched through inductive loads.

It is to be understood that the above-described arrangement is only illustrative of the application of the principles of the present invention. Numerous other arrangements may be devised by those skilled in the art without departing from the spirit and scope thereof. For example, the current waveforms for the y and x axes, i.e., the current waveforms shown in FIGS. 2C and 2D, may be slightly displaced in time to still further reduce system access noise.

What is claimed is:

1. In combination, a transistor including base, emitter, and collector terminals, an inductive load connected across said transistor emitter and collector terminals and comprising a matrix array of biased ferromagnetic access cores and selection means for coupling a selected subset of said cores to said transistor emitter and collector terminals, a capacitor connected to said transistor base terminal, means for charging said capacitor, a constant current source, switching means for selectively connecting said current source in series with said transistor, said switching means comprises a first additional transistor connected to said current source for selectively providing a by-pass conduction path for the current supplied by said current source, and a control source for selectively enabling said first additional transistor.

2. A combination as in claim 1 wherein said capacitive charging means comprises a constant voltage source, and resistance means connecting said voltage source with said capacitor.

3. A combination as in claim 2 further comprising a second additional transistor including base, emitter and collector terminals, an additional capacitor connected to said second additional transistor base terminal, additional charging means for charging said additional capacitor, and switching means for selectively connecting said second additional transistor emitter collector path in series circuit with said inductive load.

4. In combination, limiter means for selectively supplying a monotonically decreasing output potential, a constant current source connected in series with said limiter means, an inductive load connected in parallel with said limiter means, a current switch connected in parallel with said current source, additional limiter means, an additional current switch connected in parallel with said additional limiter means, and switching means for selectively connecting said additional limiter means in shunt with said inductive load.

5. A combination as in claim 4 wherein each of said limiter means comprises a transistor and means for energizing said transistor with a monotonically decreasing potential.

References Cited UNITED STATES PATENTS 3,284,791 11/ 1966 Voigt et al. 307-237 XR 3,311,900 3/1967 Gauat 340174 3,375,378 3/1968 Vandemore et al. 307237 XR TERRELL W. FEARS, Primary Examiner G. M. HOFFMAN, Assistant Examiner US. Cl. X.R. 307-237, 270

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