US3453500A - Sequential timing circuit - Google Patents

Description

July 1, 1969 R. s. LUNDIN ETAL 53,453,500

SEQUENTIAL TIMING CIRCUIT Filed March 5, 1967 .NaZZern Ware Z flavis United States Patent 3,453,500 SEQUENTIAL TIMING CIRCUIT Robert S. Lundin, Thomaston, and Klaus D. Wallentowitz,

Waterbury, Conn., assignors to General Time Corporation, Stamford, Conn., a corporation of Delaware Filed Mar. 3, 1967, Ser. No. 620,395

Int. Cl. H0111 47/18 US. Cl. 317-137 Claims ABSTRACT OF THE DISCLOSURE Related applications The timer disclosed in the present application utilizes the bridge circuit timer invention disclosed and claimed in Klaus D. Wallentowitz co-pending application, Ser. No. 405,503, filed Oct. 21, 1964, entitled Electronic Timer Circuit. That application is assigned to the same assignee as the present invention and is incorporated herein by reference.

The present invention was made during a program of electronic timer development at applicants assignees Industrial Controls Division Engineering Department and the following United States patent applications resulting from said development exemplify the prior are: The United States patent applications of Robert S. Lundin, Ser. No. 472,844, filed July 19, 1965, entitled Condition Responsive Input Controllers; Ser. No. 479,553, filed Aug. 13, 1965, now Patent No. 3,393,604, entitled Condition Responsive Process Timer; Ser. No. 589,335, filed Oct. 25, 1966, entitled Relay Circuit for Half-Wave Alternating Current Energization and Electronic Timer Employing the Same; Ser. No. 590,707, filed Oct. 31, 1966, entitled Electronic Timer Circuits; and Ser. No. 620,316, filed herewith, entitled Solid State A.C. Relay and Electronic Timer Employing the Same. The United States patent applications of Klaus D. Wallentowitz, Ser. No. 589,336, filed Oct. 25, 1966; Ser. No. 591,016, filed Oct. 31, 1966; Ser. No. 615,527, filed Feb. 13, 1967; and Ser. No. 616,354, filed Feb. 15, 1967; all entitled Electronic Timer Circuit(s); Ser. No. 616,370, filed Feb. 15, 1967, entitled Electronic Timer Circuits Providing Switching at Multiple Intervals; and Ser. No. 620,317, filed herewith, entitled Utility Delay Timer; the United States patent application of Klaus D. Wallentowitz and Robert S. Lundin, Ser. No. 620,543, filed herewith, entitled Electronic Timer Circuit; the United States patent application of George J. Yagusic, entitled Delay on De-energization Electronic Timers, Ser. No. 595,993, filed Nov. 21, 1966; and the United States patent applications of Edward T. Bosman, entitled Electronic Timer Circuits, Ser. No. 595,955, filed Nov. 21, 1966, and Ser. No. 601,780', filed Dec. 14, 1966. All of the aboveidentified applications are assigned to the same assignee as the present application and are incorporated herein by reference.

Background of the invention monitoring successively timed occurrences indicated by the changes in state of a succession of transfer switches.

Such timing circuits are employed, for example, in photocopying machines where the transfer switches monitor the rate at which paper is being fed through the machine. Thus, the transfer switches serve the function of checkpoints. When the machine is operating normally, a switch located at each checkpoint should transfer for a predetermined interval (indicating passage of a sheet past that checkpoint) a predetermined time subsequent to the transfer of the previous switch (indicating arrival of the sheet at the next checkpoint). Delay timers must, therefore, be provided which are initiated by a switch transfer and normally aborted by a succeeding switch transfer. If any timer completes its timing function, it provides a signal indicating either that a longer time has elapsed between successive switch transfers or re-transfer of the first switch than is correct and preventive action may be taken, for example, the machine may be turned off by an output circuit.

It is desirable that fully electronic timers be utilized due to their long life and inherent reliability. However, such timers require direct current for their detector, amplifying and load-controlling stages. Furthermore, unless special means are provided, the timing capacitors of such timers discharge when a timing function is aborted through a detector element and unless special precautions are taken, this may erroneously indicate the completion of a timing function. Thus, according to the prior art, such a sequential timing circuit might employ a. plurality of direct current supplies, one for each timer, and an output relay in each timer to provide the isolation required. Such a plurality of direct current supplies and isolating relays would be quite expensive and would require an excessive amount of power.

The requirement that the timers monitor two intervals requires that logic circuitry be provided in each timer circuit. This could be accomplished with direct current relays, but this would increase the cost of each direct current supply. The use of alternating current relays is desirable, but, according to the prior art, separate switches would have to be provided for the common alternating current and direct current supplies desired for the reasons stated in the preceding paragraph.

Summary of the invention It is, therefore, an object of the present invention to provide a sequential timing circuit.

Another object of the invention is to provide a sequentail timing circuit employing direct current electronic timers.

Still another object of the invention is to provide a sequential timing circuit of the above character having a common direct current supply.

A further object of the invention is to provide a sequential timing circuit of the above character having a positive abort feature.

A still further object of the invention is to provide a sequential timing circuit of the above character employing a single output relay indicating that one of the timers has completed a timing function.

Another object of the invention is to provide a sequential timing circuit of the above character that is inexpensive, rugged, reliable and consumes a minimum of electrical power.

Other objects of the invention will in part be obvious and will in part appear hereinafter.

The invention accordingly comprises the features of construction, combinations of electrical elements, and electrical circuit arrangements which will be exemplified in the electronic timer circuit herein disclosed. The scope of the invention is indicated in the claims.

In general the present invention comprises a plurality of electronic timers ingeniously connected in circuit with a plurality of transfer switches and common AC and DC supplies. Each timer circuit comprises an alternating current relay energized from two adjacent transfer switches in the series thereof. The relay is energized by a transfer of an initial switch and remain energized until transfer of both the initial and a subsequent transfer switch. The timers each comprise a resistor-capacitor bridge timing circuit and a semiconductor detector which is energized when the capacitor becomes fully charged to provide an output signal indicating a malfunction. When the timer is aborted by transfer of the two succeeding transfer switches connected thereto, the capacitor discharges through the detector semiconductor device. However, since the direct current return is through the transfer switches, an output semiconductor cannot be energized thereby and isolates the circuit so that it does not provide a false output signal. All of the output transistors of the succeeding timing circuits are connected to a common relay control circuit.

The drawing For a fuller understanding of the nature and objects of the invention, reference should be had to the following detailed description taken in connection with the accompanying drawing in which the sole figure of the drawing is a schematic electrical circuit diagram of a sequential timing circuit according to the invention.

Specific description Now referring to the drawing, a plurality of transfer switches, S S S have their swingers connected to an AC-DC common bus 10. Each of the switches, except switch S normally connects a preceding one of a plurality of timers, T T T via a conductor, A A A When transferred, each of the switches, except switch S connects bus to the timer associated therewith via conductors B B B,, All of the timers T, (where i indicates the number associated therewith) are identical and comprise a relay KY, connected via conductor B and conductor C, to an AC bus 12. Thus, When the associated transfer switch S, transfers, relay KY energizes, transferring its contacts 14 and, therefore, remains energized until retransfer of switch S and transfer of the next succeeding transfer switch 8 whereupon relay KY, de-energizes and opens holding contacts 14. When power is supplied to the timer T either over conductor B, or conductor A a direct current timing circuit is energized, all of which are commonly connected to DC bus 16 via conductors D Direct current power is supplied to the DC bus 16 by means of filter capacitor C1 and diode CR1. Each direct current operated timer comprises a dropping resistor RA; a reference potential divider formed of resistors RB and RC; a timing capacitor CA; and a variable resistor RD connected in a bridge circuit as shown. The full charging of the capacitor is detected by a detector transtor QA having associated therewith an isolating diode CRA and a junction protecting resistor RE. At the end of a timing interval, transistor QA conducts, causing current to flow through resistors RF and RG, thereby causing output transistor QB to conduct, producing a signal on conductor E connected to the common panic bus 18. This signal causes a silicon-controlled rectifier (SCR) 22 of output circuit 20 to conduct energizing output relay RY.

Since initial energization of relay KY; is caused by transfer of the associated transfer switch 5 if it retransfers and the succeeding transfer switch S transfers, relay KY will de-energize. This will disconnect DC power from the timer circuit T Capacitor CA will discharge through transistor QA, causing transistor QA to assume the conductive state. Transistor QB insures that no signal is supplied on conductor D, because DC power has been removed from transistor QB.

In the output circuit 20, direct current is supplied to SC 22 from AC bus 12 and through diode CR1 and is returned via conductor 24 to AC-DC bus 10. SCR 22 is provided with reverse bias by diode CR2 and resistor R4, as explained in the above-identified application, Ser. No. 591,016. SCR 22 is connected in series with a current limiting resistor R3 and an alarm output relay RY. Diode CR3 connected across relay =RY quickly dissipates the energy stored therein when it is turned off.

A signal on panic bus 18 passes through a common collector resistor R2 and is supplied to the gate 24 of the SCR 22. Resistor R1 and capacitor C2 protect the gate 24 against transients.

The relays KY, are energized with half-wave rectified alternating current in the manner described in the aboveidentified application, Ser. No. 589,335. Thus, they are provided with a half-wave rectifying diode ORC and a self-energizing diode CRD.

Diodes CR-B prevent the possible energization relay KY, for example, through capacitor C1 via conductor D1 through resistors RC, RB and RA. Similarly, diode CRC prevents alternating current from being supplied to resistors RA, RB and RC from alternating current bus 12 through another energized relay coil KY via AC bus 12.

It will be seen that by providing common switching of the alternating current and direct current supplies by means of the switches S, a common direct current supply comprising only filter capacitor C1 and diode CR1 may be provided. Furthermore, capacitor C1 and diode CR1 form the DC supply for output circuit 20.

A sequential timing circuit, according to the present invention, for use in a photocopy machine uses the following components: Resistor R1 is 1 kilohm; resistor R2, 6.8 kilohms; resistor R3, 2 kilohms, rated at five watts; resistor R4, kilohms; resistor RA, 2.7 kilohms; resistor RB, 1.5 kilohms; resistor RC, 1.5 kilohms; resistor RD takes the form of a 500 kilohm potentiometer; resistor RE is 470 kilohms; resistor RP, 10 kilohms; resistor RG, 2.2 kilohms. All resistors are rated at one-half watt unless otherwise noted. Diode CR1 is a type DE300; diodes CR2 and CRA, DESO; and diodes CR3, CRB, CRC, CRD, type DE200; supplied by Semiconductor Products. Transistor QA, type 2N3565 and transistor QB, type 2N4248. Capacitor C1 is a 20 microfarad, rated at 200 volts capacitor; capacitor C2, 1 microfarad; and capacitor CA, 2 microfarads, rated at 25 volts. SCR 22 is a GE type 0106B. Relays KY, and RY may be 117 volt AC relays.

It will thus be seen that the objects set forth above, among those made apparent from the preceding description, are efiiciently attained and, since certain changes may be made in the above construction without departing from the scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawing shall be interpreted as illus trative and not in a limiting sense.

Having described our invention, what we claim as new and desire to secure by Letters Patent is:

1. A sequential timing circuit wherein a plurality of transfer switches are individually transferred during the performance of an associated function comprising:

(A) means connecting the common terminal of each transfer switch to a first alternating current supply terminal;

(B) a plurality of relays (a) each energization terminals thereof connected for energization upon transfer of an associated one of the transfer switches, and

(b) each having holding contacts alternatively connecting its energization terminals for energization until transfer of a succeeding transfer switch;

(C) means connecting said relays to a second alternating current supply terminal;

(D) a plurality of direct current energized timer circuits (a) each connected at one terminal to the energization terminal of one of said relays connected to the transfer switches, and

(b) connected to a common direct current bus;

and

(E) a common direct current supply connected to said direct current bus, connected in parallel with said relays.

2. A sequential timing circuit as defined in claim 1 wherein each of said timer circuits further comprises:

(c) a resistor-capacitor semiconductor detector bridge timing circuit, and

(d) a semiconductor isolation stage connected in circuit with said semiconductor detector.

3. A sequential timing circuit as defined in claim 2, and:

(F) a common output circuit connected to all of said semiconductor isolation stages.

4. A sequential timing circuit as defined in claim 2, wherein there is connected in circuit with each of said relays:

(c) a first diode connected in series with the energization terminals thereof, and

(d) a second diode connected in parallel with the energization terminals thereof.

5. A sequential timing circuit as defined in claim 4 and:

(F) 'a common output circuit connected to all of said semiconductor isolation stages.

6. A sequential timing circuit as defined in claim 5 wherein said output circuit is energized with direct current from said common direct current supply.

7. A sequential timing circuit as defined in claim 1 6 wherein there is connected in circuit with each of said relays:

(c) a first diode connected in series with the energization terminals thereof, and (d) a second diode connected in parallel with the energization terminals thereof. 8. A sequential timing circuit as defined in claim 7 and:

(F? a common output circuit connected to all of said tlmer circuits. 9. A sequential timing circuit as defined in claim 8 wherein said output circuit is energized with direct current from said common direct current supply.

10. A sequential timing circuit as defined in claim 1 wherein each of said timer circuits further comprises:

('c) an isolating diode connected in series therewith and in series with said one terminal of said relay.

References Cited UNITED STATES PATENTS 2,473,916 6/1949 Snyder 192-127 X 3,341,837 9/1967 Washington 340259 3,398,295 8/1968 Fathauer 307141.4

JOHN F. COUCH, Primary Examiner. A. D. PELLINEN, Assistant Examiner.

US. Cl. X.R. 192127; 307-141; 317-142; 340259

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