US3274560A

US3274560A - Message handling system

Info

Publication number: US3274560A
Application number: US223228A
Authority: US
Inventors: Gerry D Granito; Lucius D Smith; Dana R Spencer; Thomas S Stafford
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1962-09-12
Filing date: 1962-09-12
Publication date: 1966-09-20
Anticipated expiration: 1983-09-20

Description

P 1966 e. D. GRANITO ETAL 3,274,560

MESSAGE HANDLING SYSTEM Filed Sept. 12, 1962 DATA WORD DATA ne'elsf ER MEMORY CONTROL R TERilQf 'EQNT Q woRp TA PHAsE MEMORY T12 4 U?) RESET MA m P A a [1 m R 0 HR BF 2 L A$E WE WMW m 1 w n E D A A T iNVENTORS GERRY 0. GRANDTO LUCiUS D. SMlTH DANA R. SPENCER THOMAS s STAFFORD flvo W ATTORNEY United States Patent 3,274,560 MESSAGE HANDLING SYSTEM Gerry D. Granito, Poughkeepsie, N.Y., Lucius D. Smith, Atlanta, Ga., and Dana R. Spencer and Thomas S. Stafford, Wappingers Falls, N.Y., assignors to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Sept. 12, 1962, Ser. No. 223,228 Claims. (Cl. 340-1725) This invention relates in general to communications systems and more particularly to an automatic system for forwarding messages to a plurality of connected terminals in accordance with controlling means which effect an immediate transfer of the message to the outgoing terminal or defer the forwarding of the message until the outlying terminal is free to accept the message.

Increasing use is being made of transmission facilities for transmitting binary data from a plurality of outlying terminals to a central processing unit. A basic problem encountered by these transmission systems is to provide a peripheral unit with the ability to accumulate independent messages being received from the outlying terminals relieving the central processing unit from this burden. The peripheral interchange must also be capable of presenting these accumulated messages to the central processing unit when required by the central unit.

Copending application Serial No. 170,401 now Patent No. 3,229259 entitled Multiple Rate Data System, filed February 1, 1962, describes a peripheral message handling system utilizing control words associated with each of the outlying terminals for the accumulation of serially received bits and characters of messages in assigned blocks of a data word memory. Copending application Serial No. 210,512 now Patent No. 3,202,972 entitled Message Handling System, filed July 17, 1962, describes an addition to the above mentioned system providing control words in the peripheral message handling system for the orderly transfer of messages from the data word memory to the central processing unit in the same order in which the received messages from the terminals have been completed.

An additional requirement of a peripheral message handling system would be to provide an automatic system for accepting messages from the central processing unit for forwarding to a particular terminal. The peripheral system must be able to accept the outgoing messages when the central unit requires, store the characters of the message until the message is complete, and then provide a means for controlling the transfer of the completed message from the data word memory location to the addressed terminal. It is not desirable to require a central processing unit to wait for an outlying terminal to complete a transmission already in progress before ridding itself of an output message. Neither is it desirable for an outlying terminal to be interrupted in the transfer of a message to provide the central processing unit with access to the line for transfer of the outgoing message.

It is therefore a primary object of this invention to provide a message handling system which can forward messages from a central processing unit to an outlying terminal without interruption of either the central processing unit or the outlying terminal.

It is also an object of this invention to provide a message handling system having control means associated with each of the terminals, but independent therefrom, which are capable of effecting immediate transfer of an output message to the terminal when said terminal is not in the process of transferring a message.

It is also an object of this invention to provide a message handling system with control means associated with 3,274,560 Patented Sept. 20, 1966 each of the terminals, but independent therefrom which are capable of effecting immediate transfer of an output message to the terminal if said terminal is not in the process of transferring a message or deferring the transfer of the output message if the addressed terminal is engaged in a message transfer.

Another object of the invention is to provide a message handling system with control means associated with each of a plurality of outlying terminals, but independent therefrom, which can automatically effect the transfer of an output message, once deferred, as soon as the output terminal has completed a message transfer previously in progress.

In accordance with these and other objects of the invention, a message handling system has been provided with a data memory having a plurality of addressable locations. A message being transferred to or from a particular one of the outlying terminals is stored in one of the addressable locations of the memory. Controlling means for indicating the address of a particular one of the addressable memory locations are provided for each of the outlying terminals and the central processing unit. The central processing unit transfer controlling means is utilized for accumulating a complete message in a particular one of the addressable locations of the memory and means are provided for indicating that a completed message is ready for transfer from the particular location to a particular terminal. Status signalling means are provided for indicating when a particular terminal, which is to receive a completed output message, is or is not engaged in a message transfer. In response to the status signal and the completed message indication, means are provided for effecting immediate transfer of the outgoing message to the particular terminal under control of the terminals controlling means. If the particular terminal is in the process of a message transfer, the addressable location of the output message is temporarily stored within the terminals controlling means thereby deferring transfer. As soon as the particular terminal has completed the message transfer previously in progress, transfer of the outgoing message is effected by transferring the address location of the output message from the temporary storage to a primary storage in the terminals controlling means to control transfer between the particular terminal and the designated addressable location.

The foregoing and other objects, features and advantages of the invention will be apparent from the following particular description of the preferred embodiment of the invention as illustrated in the accompanying drawing.

The system shown in the single drawing represents an interchange which forwards input messages from a group of terminal sets to a central computer, and receives output messages that are sent to the terminal sets by the c0rnputer.

Input messages are received from each terminal set over an associated low speed line 1-30. The messages are composed of related characters of information that are based on well known bit configurations such as Start-Check (C)-BA84-21-Stop or Start-l-2-3-4-S-Stop. Each line provides a succession of bits in one of the formats indicated which are shifted over line into a Data Register 101 to form the proper characters. Related bits and characters from each line are stored temporarily in a Data Word Memory 102 until a complete message or message segment is assembled.

Completed input messages or message segments are transferred serial by character from the Data Word Memory 102 through the Data Register 101 over bus 103 to an Input Character Storage (ICS) Register 104, and from there to an Input Shift Register (ISR) 105 for serial by 3 bit transfer to a Modulator (MOD) 106, and transmis sion over line 107 to a central computer, not shown.

Output messages are received serial by bit over line 108, detected by a Demodulator (DEM) 109, shifted into an Output Shift Register (OSR) 110, and transferred to an Output Character Storage (OCS) Register 111. Each output character is subsequently transferred over bus 112, and through the Data Register 101, to the Data Word Memory 102. When a complete output message or message segment has been received, it is then transferred from memory 102, with individual bits being forwarded from Data Register 101 over line 113 to the proper terminal set.

Each line is scanned only once during a particular scan interval, but in the preferred embodiment, successive line scans occur at a much higher rate than the transmission rate of any data line 130. The scan interval is actually composed of a number of stepping intervals 1-30 which correspond to the lines 1-30. Any desired number of lines within a reasonable range could be provided for during this interval.

In addition to the line stepping intervals 1-30, each scan period also includes a step 31 which is used for gating an output character from the Output Character Storage Register 111 to the Data Memory 102, and an additional step which is used either for gating an input character from Data Word Memory 102 to the Input Character Storage Register 104 or to assign a transfer order to a completed message. The functions performed during step 31 are the subject of this invention to be more fully described.

The scanning, sampling and data transfer activities of the system are under control of a Line Control 114 and a Memory Control section 115. The actions of both control sections are governed primarily by the contents of a Control Word Register 116. The operation of the Input Sampling Control 114 is explained in more detail in previously mentioned application Serial No. 170,401 now Patent No. 3,229,259.

Control words are transferred to Register 116 from a Control Word Memory 117. Each line 1-30 has a control word that is located at a particular address in memory 117. Since the lines are scanned in sequence, the respective control words are also preferably arranged in sequence in memory 117. Control word addresses are established by an address counter 118 at coordinate X-Y locations by signals on

lines

119 and 120. When a particular control word is addressed, the corresponding line 130 is also addressed by deriving a line number from the X-Y addresses in Decode block 121. Therefore, as each line is scanned during a scan interval, its corresponding control word will be in Register 116.

Each control word has a configuration like that shown in Control Word Register 116 and the control word bits are used to establish functions as indicated below:

Tag-2 bits Parity Checking and End of Message (EOM) indications.

Phase3 bits Indicates sampling time r and inserted in control WOI'Cl 31.

4 The Data Word Memory 102 is preferably divided into blocks of characters for handling messages or message characters. A suggested memory 102 configuration is as follows:

Total capacity 4000 characters. Number of message blocks 40 blocks of characters each.

During the steps 1-30 of counter 118, lines 1-30 and control words 1-30 are sequentially effective. When any line indicates that service is required, the memory control will assign one of the 40 addressable memory block locations to the line, and insert the block location address in the primary address field of the control word labeled General Bufier Area. Each character of a message is assembled in the assigned block location as defined by a Memory Address in the associated control word. As each character is completed, the next sequential character address is sct into the Memory Address field of the control word. When a message is completed for a line, the General Butter Area address is reset to zero in preparation for another message. In addition, the General Buffer Area address is stored to await assignment of a transfer order in accordance With previously mentioned application Serial No. 210,512 during the scan interval including steps 32-64.

Control words 130 are not only utilized for controlling the transfer into the data Word memory 102 from the associated terminal, but are further utilized to address a message in the data word memory which is to be sent to the associated terminal. In accordance with the present invention, to be more fully discussed, the general buffer area address of an output message will be placed in the General Butler Area field of the control word to provide primary control of access to the data word memory 102 to serially present elements of a character to the associated terminal.

As mentioned previously, steps 1-30 of the counter 118 sequentially obtain control words 130 from the Control Word Memory 117 to control transfer to or from the associated terminal and a designated addressable block location in the data word memory 102. When the counter 118 is stepped to position 31, control word 31 will be placed in the control word register 116. Control word 31 is utilized to control the transfer of characters from the central processing unit through the output character storage 111 and data register 101 to a designated block location in data Word memory 102. The designated addressable location is contained in the General Buffer Area field of control word 31. As before, the particular location in which the character is inserted is dictated not only by the General Buffer Area address but also the Memory Address within the particular addressable location designated. As was the case in assigning general butter areas to input messages from the terminals, a general butler area is assigned to an output message from the central processing unit by the memory control 115.

The first character of each message to be transferred from the central unit through the data word memory 102 to the designated terminal is the terminal address. This terminal address is decoded in the terminal address decoder 200 and stored in a terminal address store 201. When the first character of an output message is received, a general buffer area will be assigned to the message At the same time the general buffer area assigned to this output message is inserted in control word 31, the general buffer area for the output message will be inserted in a Buffer Area for Output storage 202. After each of the scan intervals l30 has been completed and step 31 is reached, control word 31 will be in the control word register 116 controlling the transfer of characters from the output character storage 111, through the data register 101 to the memory address within the general buffer area address indicated. Each time step 31 of the counter 118 is reached, a new character may be inserted in the data word memory 102. An end of message recognizer 203 will be effective, when the end of message character is in the output character storage 111, to set a trigger 204. Trigger 204, BulTer Area for Output storage 202 and the Terminal Address 201 provide recognition and indication of a completed output message for a particular output terminal.

At the completion of steps 32-64 of counter 118, wherein transfer orders are assigned in accordance with application Serial No. 210,512 or wherein a character is presented to the central unit through the input register 105, a new scanning cycle will be commenced. As the scan counter 118 is stepped from 1-30, the lines 1-30 from decoded 121 will be sequentially energized to sample or control an output concerned with the designated line in the line control 114. At the same time, the sequentially energized lines from decoder 121 are presented to a compare circuit 205. When the line associated with the terminal indicated in Terminal Address 201 is effective and its corresponding control word is in register 116, a signal will be generated from the compare circuit 205 to initiate the insertion of the general buffer area location of the output message in the associated control word. The signal generated by trigger 204 indicates that a completed message is ready for a terminal, and the signal from the compare circuit 205 indicates that the terminal having its control Word presently in the register 116 is the terminal to receive the output message.

The next problem is to determine whether or not the control word for the particular terminal is presently being used to control transfer between the terminal and a designated general buffer area location in the data word memory 102. If the terminal designated is in the process of a message transfer, the General Buffer Area field of the control word will contain the address of a buffer area being used in the transfer. An AND circuit 206 is provided for indicating the status of the particular terminal, namely whether or not it is in the process of transferring a message. AND circuit 206 is effective to provide a logical output if there is no general buffer area assigned to that control word. If the terminal is in the process of a transfer there will be a location address in the General Butler Area field of the control word. The output of AND circuit 206 is applied to an AND circuit 207 and through an inverter 209 to an A ND circuit 208.

AND circuit 207 is already partially enabled by the signal from the compare circuit 205 and the trigger 204. Assuming that the terminal which is to receive the output message is not in the process of a transfer, there will be no general buffer area information in the control word and AND circuits 206 will provide the final conditioning signal to AND circuit 207. At this time a gate 210 will be enabled to pass the address of the general buffer area location of the output message from the Butler Area for Output storage 202 to the General Buffer Area field of the control word to provide primary control of the transfer. The next time scan steps 1-30 are encountered, the control word for the terminal slated for an output message will show the general buffer area containing the output message and transfer to the terminal will be immediately commenced.

Each of the control words 1-30 has a secondary address field labeled Buffer Area Waiting. Assuming for the time being that there is no address in the secondary ficld, an AND circuit 211 will provide a logical output. The output of AND circuit 211 is applied as an additional input to AND circuit 208 and as input through inverter 21.3 to an AND circuit 212. Now assuming that the terminal indicated by the terminal address 201 is in the process of a message transfer, the primary field containing the General Buffer Area address will contain information providing no output from AND circuit 206, but AND circuit 211 will provide an output. The absence of an output from AND circuit 206 in the presence of an output from AND circuit 211 will be effective to condition AND circuit 208. These conditions indicate that a message is ready for the particular terminal, but the terminal is at this time in the process of a message transfer. AND circuit 208 will provide an output to condition a gate 214. Since the buffer area address of the output message cannot be inserted in the General Buffer Area field, gate 214 will present the output message buffer area address contained in the storage 202 to the secondary field Butler Area Waiting. This then defers transfer of the output message to the particular terminal. The output of either AND

circuit

207 or 208, is applied to an OR circuit 215 which will provide an output effective to reset the trigger 204, the Buffer Area for Output storage 202 and the Terminal Address 201 in preparation for receiving a new output message from the central unit.

During a later one of the scanning cycles 1-30, the terminal which has an output message waiting will complete the previous transfer. At this time the General Buflier Area field of the control word will have been reset to zero. At this time the AND circuit 206 will provide a logical output indicating that the transfer has been completed. The presence of a location address in the Buffer Area Waiting field will provide no output from AND circuit 211. In this situation AND circuit 212 will be enabled to provide a logical output to a gate 216 to transfer the location address of the output message from the secondary field to the primary field of the control word. The output message which had been deferred will now be transferred out of the addressed location indicated by the General Buffer Area field to the terminal. Energization of either AND circuit 207 or AND circuit 212 will be effective at an OR circuit 217 to place the mode bit of the terminals control word from the binary zero condition to the binary one condition. This provides the necessary indication to control whether information is to be transferred from the line to the data register 101 or vice versa.

It should be noted at this time that each of the control words 1-30 can be controlling a message input from a terminal while deferring an output message. The control word can also be controlling transfer of an output message while deferring another output message.

There has thus been shown a message handling system capable of effectiving immediate transfer of an output message to a terminal or of deferring the transfer of the message entirely under control of a terminal transfer controlling means in the form of the terminals control word. The immediate transfer or deferment is accomplished completely independent from the outlying termiinal or the central processing unit without interruption of either device.

What is claimed is:

1. A message handling system comprising:

a plurality of data lines;

a plurality of utilization devices respectively connected to each said data line;

a data memory. said memory having addressable locations for storing data messages;

control means for placing each said lines in one or the other of two modes for transfer of data to or from an associated utilization device and one of said memory locations as required;

means for recognizing that a completed message is ready for transfer from one of said memory locations to one of said lines;

means, responsive to said control means and said completed message recognition means, for effecting immediate transfer of said message if said line is not presently in one of said modes.

2. A mesage handling system comprising:

a plurality of data lines;

a data memory, said memory having addressable locations for storing data messages;

means, responsive to said control means and said completed message recognition means, for effecting immediate transfer of said message if said line is not presently in one of said modes or for deferring transfer of said message if said line is in one of said modes.

3. A message handling system comprising:

a plurality of data lines;

a plurality of utilization to each said data line;

control means for placing each of said lines in one or the other of two modes for transfer of data to or from an associated utilization device and one of said memory locations as required;

means, responsive to said control means and said completed message recognition means, for effecting immediate transfer of said message if said line is not presently in one of said modes or for deferring transfer of said message if said line is in one of said modes;

and means subsequently activated in said latter case upon completion of the particular mode status of said line, in response to said control means, for effecting transfer of said message from said memory location to said line.

4. A message handling system for controlling the transfer of messages between a central unit and a plurality of terminals comprising:

a data memory, said data memory addressable locations;

means, associated with each of the terminals, for controlling the transfer of a message between one of said addressable locations and the associated terminals; means for controlling the transfer of a message from the central unit to one of said addressable locations;

both said transfer controlling means including means for indicating the address of a particular one of said addressable locations in said data memory containing the message being transferred;

means for indictaing that a completed message is ready for transfer from said data memory to a particular terminal;

status signalling means, responsive to said terminal transfer controlling means, for indicating when the associated terminal is or is not engaged in a message transfer;

and means, responsive to said completed message indication and a signal from said status signalling means indicating the particular terminal is not engated in a message transfer, for transferring said address indication from said central unit transfer controlling means to said terminal transfer controlling means of the particular terminal indicated to effect immediate transfer from said addressed location to the particular terminal.

5. A message handling system for controlling the transfer of messages between a central unit and a plurality of terminals comprising:

a data memory, said data memory having a plurality of addressable locations;

devices respectively connected having a plurality of means, associated with each of the terminals, for controlling the transfer of a message between one of said addressable locations and the associated terminal; means for controlling the transfer of a message from the central unit to one of said addressable locations;

means for indicating that a completed message is ready for transfer from said data memory to a particular terminal;

temporary storage means associated with each of said terminal transfer controlling means;

and means, responsive to said completed message indication and a signal from said status signalling means indicating the particular terminal is engaged in a message transfer, for transferring said address indication from said central unit transfer controlling means to said temporary storage means of said terminal transfer controlling means of the particular terminal indicated to defer transfer from said addresed locations to the particular terminal.

6. A message handling system for controlling the transfer of messages between a central unit and a plurality of terminals comprising:

a data memory, said data memory having a plurality of addressable locations:

means, associated with each of the terminals, for controlling the transfer of a message between one of said addressable locations and the associated terminal; means for controlling the transfer of a message from the central unit to one of said addressable locations;

means, responsive to said completed message indication and a signal from said status signalling means indicating the particular terminal is engaged in a message transfer, for transferring said address indication from said central unit transfer controlling means to said temporary storage means of said terminal transfer controlling means of the particular terminal indicated to defer transfer from said addressed location to the particular terminal;

and means, responsive to said status signalling means indicating the particular terminal is not engaged in a message transfer and the presence of said address indication in said temporary storage means, for transferring the address indication from said temporary storage means to said terminal transfer controlling means address indicating means to effect immediate transfer from said addressed location to the particular terminal.

7. A message handling system in accordance with claim 6 wherein said status signalling means includes:

means, responsive to the presence or absence of a location address in said address indicating means of said terminal transfer controlling means, for indicating when the associated terminal is or is not engaged in a message transfer respectively.

8. A message handling system, comprising:

a plurality of data lines;

a plurality of utilization devices respectively connected to each said data line, each said device operating in a mode during which it supplies data over its associated line or another mode during which it receives data over its associated line;

a data memory, said memory having addressable block locations for storing data messages;

means for storing a plurality of control Words, each of said control words being associated with a particular one of said lines, and each said control word having a primary address field said primary address field identifying one of said block locations containing a message being transferred to or from said associated line;

a control word register;

means for scanning each of said lines in sequence and for concurrently entering its associated control word in said register for controlling transfer in accordance with said primary address field;

means for recognizing and indicating that a completed output message exists in a block location of said data memory for a particular utilization device;

means for providing a status signal indicating the absence of an address in said primary address field;

means, responsive to said status signal and said completed message recognition means, for entering the address of said output message in the primary address field of the control Word associated with said particular utilization device for effecting immediate transfer of said output message.

9. A message handling system, comprising:

a plurality of data lines;

means for storing a plurality of control words, each of said control Words being associated with a particular one of said lines, and each said control word having a primary address field, and a secondary address field, said primary address field identifying one of said block locations containing a message being transferred to or from said associated line;

a control word register;

means responsive to the absence of said status signal and said completed message recognition means, for entering the address of said output message in the secondary address field of the related control word, thereby deferring transfer of said output message.

10. A message handling system, comprising:

a plurality of data lines;

a data memory, said memory having addressable block locations for accumulating data messages;

means for storing a plurality of control words, each of said control words being associated with a particular one of said lines, and each said control word having a primary address field, and a secondary address field, said primary address field identifying one of. said block locations containing a message being transferred to or from said associated line;

a control word register;

means, responsive to the absence of said status signal and said completed message recognition means, for entering the address of said output message in the secondary address field of the related control word, thereby deferring transfer of said output message;

and means, responsive to said status signal, subsequently activated upon completion of either of said modes of said line for transferring the block address stored in said secondary address field to said primary address field of the related control word for effecting transfer of said output message to said utilization device.

References Cited by the Examiner UNITED STATES PATENTS 2,968,027 1/1961 McDonnell et al. 340l72.5 3,029,414 4/1962 Schrimpf 340-4 72,5 3,142,043 7/1964 Schrimpf 340172.5

55 ROBERT C. BAILEY, Primary Examiner.

P. J. HENON, Assistant Examiner.

Claims

1. A MESSAGE HANDLING SYSTEM COMPRISING: A PLURALITY OF DATA LINES; A PLURALITY OF UTILIZATION DEVICES RESPECTIVELY CONNECTED TO EACH SAID DATA LINE; A DATA MEMORY, SAID MEMORY HAVING ADDRESSABLE LOCATIONS FOR STORING DATA MESSAGES; CONTROL MEANS FOR PLACING EACH SAID LINES IN ONE OR THE OTHER OF TWO MODES FOR TRANSFER OF DATA TO OR FROM AN ASSOCIATED UTILIZATION DEVICE AND ONE OF SAID MEMORY LOCATIONS AS REQUIRED; MEANS FOR RECOGNIZING THAT A COMPLETED MESSAGE IS READY FOR TRANSFER FROM ONE OF SAID MEMORY LOCATIONS TO ONE OF SAID LINES; MEANS, RESPONSIVE TO SAID CONTROL MEANS AND SAID COMPLETED MESSAGE RECOGNITION MEANS, FOR EFFECTING IMMEDIATE TRANSFER OF SAID MESSAGE IF SAID LINE IS NOT PRESENTLY IN ONE OF SAID MODES.