US3222644A - Simplified error-control decoder - Google Patents

Simplified error-control decoder Download PDF

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Publication number
US3222644A
US3222644A US212746A US21274662A US3222644A US 3222644 A US3222644 A US 3222644A US 212746 A US212746 A US 212746A US 21274662 A US21274662 A US 21274662A US 3222644 A US3222644 A US 3222644A
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signals
bit
bits
register
code
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US212746A
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Coleman H Burton
Michael E Mitchell
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General Electric Co
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General Electric Co
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Priority claimed from US213733A external-priority patent/US3164804A/en
Priority to FR942668A priority patent/FR1364472A/fr
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/43—Majority logic or threshold decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end

Definitions

  • the invention is directed to error correcting apparatus for digital data processing systems.
  • the apparatus is of the class which operates upon (and generates) code words (or sequences of n digits) which are characterized by consisting of k information ⁇ digits plus n-k redundant digits whereby errors can be corrected by means of the redundant digits.
  • the apparatus will not correct all possiblecombinations of errors, but it can correct up to a given number with certainly and :some additional errors under special circumstances and perform other related functions such as monitoring the number and rate of error corrections.
  • the invention results in great simpliication of apparatus with certain codes.
  • the use of error correction codes is that by transmitting information over a longer time period at the same power, more energy is made available and thus greater signal-to-noise ratio is obtainable.
  • the relations involved can ⁇ be approached with various kinds of analysis and a very large body of complex theory exists.
  • This code is known as the (l5, l) code. It is characterized by consisting of 11:15 binary characters or bits of which k:,7 are ⁇ the information bits and n-kz- S bits are redundant bits which provide an error correcting capability of at least 2 errors in each code word.
  • the combining operation for binary decoding with an odd number of estimators is merely the majority decision operation.
  • Binary decoding with an even number of estimators is accomplished by deciding according to an arbitrary rule in case ⁇ of a tie (and by majority decision otherwise). If a particular estimator is inherently more reliable for the expected kind of error-producing mechanism, it should obviously be used to break ties. (In most cases, the single-digit estimator is more reliable.) In some cases of equal estimator reliability (or credibility), the best arbitrary rule for breaking ties may be pseudorandom choice, or even a truly random choice.
  • FIGURE l is a block diagram of a one ⁇ way digital communication system illustrating binary encoding and decoding
  • FIGURE 2 is a block diagram of an encoder and decoder for a (15, 7) code
  • FIGURE 3 is a schematic diagram of one ⁇ stage of a shift register suitable for use in the FIGURE 2 encoder or decoder;
  • FIGURE 4 is a schematic diagram of a two-input modulo 2 adder for the estimator logic circuits in the FIGURE 2 decoder.
  • FGURES 5A and 5B are ⁇ schematic diagrams of a majority logic circuit for the FIGURE 2 decoder.
  • FIGURE 1 is a block diagram of a representative one-way digitalcommunications system.
  • a data source 2 supplies informationin the form of digital signals such as code words which it is desired to transmit to a remote data utilization device 9.
  • the code word illustrated is a three digit message, a1, a2, a3, shown as 101, which is applied to an encoder in a serial or parallel operation.
  • the output of the encoder is a series of bits (al, a2, a7) in which the last four are redundant bits generated by the encoder. These redundant bits are generated as predetermined logic functions of the information bits so that the bits are logic functions of both redundant and information bits.
  • the code word is then transmitted by transmitter l by sequential bits in accordance with cotnrol pulses from a conventional synch generator 5.
  • the message received by receiver 6 has an error in the third place b3.
  • the complete message has been stored in the decoder 8 under control of synch generator 7 by conventional digital data transmission techniques.
  • the decoder 8 then operates upon the received word, including the erroneous third bit b3, and by sensing the redundant bits (together with the information bits), determines the correct values for b1, b2, b3 which are then applied to the utilization device 9.
  • the apparatus of FIGURE 1 is characterized by the addition of an encoder and a decoder without modification of the ⁇ original system components.
  • the result is that system performance can be vastly improved without redesign of the system.
  • the novel decoder disclosed herein the information is read out of the decoder during k operations following reception of the code word. This is permitted by minimizing the number of the sequential bit decoding operations to the number of information bits in the encoded word.
  • FIGURE 2 is a block diagram illustrating the major components of the invention aranged for encoding and decoding a (15,7) code.
  • the encoder 3 is of a conventional design. Itis comprised of a seven stage shift register 12 which is adapted to receive an information word of seven bits in parallel by suitable gating means. The information word is encoded by simultaneously generating redundant bits and reading out the code wbrd bits during cyclic serial operations. Each clock pulse causes the bit signals in each stage to shift to the right to the next stage. The signals from the last stage are the output bit signals of the encoder 3. During each shift operation, a redundant bit signal is generated by the modulo 2 adder and is entered into the first stage of the shift register l2.
  • the mod 2 adder generates each redundant bit in accordance with the modulo sum of the three bits in the stages where a1, a5 and a7 were originally entered.
  • the mod 2 adder is conveniently a pair of two input mod 2 adders in series in which a1 and a5 are applied to the first and the output of the first and a7 are applied to the second.
  • An appropriate mod l2 adder will be described hereinafter, but it can take any form such as a simplified half adder wherein the sum signal is the output. (The output of each modulo 2 adder in operation is the binary sum casting out all carries.)
  • the redundant bits are serially generated as the code word bits are shifted out of the shift register 12.
  • the decoder 8 in FIGURE 2 includes three major functional units: a 15-stage shift register 16, single-digit cyclic estimator logic circuits 22-25, and a majority logic circuit 30.
  • a mode switch 15 selects either a load mode or a decode mode by switching the serial input of the shift register 16 either to the incoming code word or to a feedback connection for entering decoded bit signals sequentially.
  • the cyclic estimator logic circuits 22-25 are each connected to three stages of the shift register 16 in accordance with an independent logic equation. Each of these cyclic estimator logic circuits are of the same type as the mod 2 adder 13 in encoder 3. Because of the relations of the redundant bits to the information bits, the information bits can be estimated from the code bits in several ways which rely on independent selections of the code word bits.
  • the majority logic circuit 30 since it is arranged to receive the outputs of all cyclic estimator logic circuits, provides an output signal in accordance with the majority ⁇ of the estimators.
  • the majority logic circuit 30 there are four mod 2 estimators and a fth estimate of al is provided for the majority logic circuit 30 directly, by the last stage of the shift register which contains b1. This logic operation is used once for each digit, and will always produce a correct majority logic output if there are two err-ors or less in the received code word because three of the estimates must be correct.
  • the binary digit in the jth stage has the value Rjzbj, where bj is the binary quantized received value of the digit transmitted as aj for jzl, 2, 15.
  • the binary content of the ith stage is RJ-:bJ-H.
  • step-by-step is defined as the correction and feedback to the shift register of a digit which was received in error.
  • each such operation may reduce the Hamming distance between the AWord stored in the register andthe correct word by one unit, which is called a stepf
  • the decoder arrangement of FIGURE 2 is adaptable to various other codes. Examples of such codes are: (21, 1l), (73, 45) and (Zm-L m).
  • the requirements of the codes which are ideally suited for this type of decoder are involved.
  • the practical limitation is the ability to form a set of estimator logic equations which are independent (have no common terms) and are of sufficient number so that the theoretical maximum number of errors can be corrected.
  • the code must be a cyclic, binary group code so that the recursion relationship enables utilization of the same circuitry for successive bits.
  • the radio transmission system illustrated in FIGURE 1 is only representative.
  • the data link transmission systems between the encoder and decoder can incorporate different combinations and permutations of parallel and serial data transmissions, from physical movement f punched cards to intricate systems.
  • the shift registers 12 and 16 can be implemented by a series of standard flip-ops such as shown in FIG- URE 3.
  • Each Hip-flop Rn is a single stage in the shift register and is interconnected with the adjoining stages RM1 and Rn 1.
  • a l bit signal is in the form of a positive voltage and a "0 bit is in the form of a zero voltage level. Therefore, the n-p-n transistors 41 and 42 are interconnected so that when the flip-Hop is set, the right-hand transistor 42 is conducting and the left-hand transistor 41 is olf.
  • the Hip-flop circuit assumes a set or reset state in accordance with the last state of the preceding stage. That is, the output signals of stage RM1 are connected to ⁇ input terminals 43 and 44 so that S :FMI (before the shift) and R11-FMD It is to be understood that in decoders having an even number of estimators, the majority decision would include ⁇ tie-breaking functions'such as selection of the bj value to be decoded.
  • FIGURE 4 A suitable component for the mod 2 adder is shown in FIGURE 4.
  • the illustrated circuit is a ⁇ two-input mod 2 adder in itself and has its output coupled to one of the inputs of an identical two-input mod 2 adder.
  • the n-p-n transistors 51 and 52 operate to produce a positive voltage at the output terminal 57 in accordance with an exclusive or logic function. If either input, A at input terminal 53 or B and E at input terminals 54 and 54', is a l the output atterminal 57 is a positive voltage and if the inputs are both either ls or 0s, the output signal is a zero voltage. This is because the transistor 52 is conducting only if E and A provide positive voltages or if B provides a positive voltage while A provides a zero voltage.
  • FIGURES 5A and 5B illustrate a preferred majority logic circuit.
  • This circuit receives the output of all the estimator logic circuits 22-25 at input terminals 61. Since it combines all of the input signals into an analog signal, it is fundamental that these signals be accurate ⁇ voltages so that a correct comparison is made. Accordingly, clamping circuits 62 are provided to regulate the cornparison voltages.
  • Each clamping circuit includes a Zener diode 63 which produces a voltage reference for a standard transistor clamping circuit. Because of the balanced reference and bias sources, the voltage at one of the clamp- .ing circuit output terminals 64 and 64 is negative or positive and the other is zero.
  • an -output circuit consisting -of three transistors 67, 68 and 69 is provided so that the output signal of the majority logic circuit at terminal 70 assumes either a zero value for a 0 bit or a positive signal value for a l bit of the decoder circuits.
  • the transistors 68 and 69 therefore produce either a fixed positive voltage or a zero voltage depending upon whether transistor 67 is turned on or olf by the majority sum of the estimator signals.
  • the output voltage remains constant regardless of variations in the transistor 67 current.
  • the construction of the decoder can be carried out with other standard components.
  • binary scaler counters can be used as the modulo 2 adders and other shift registers such as magnetic core shift registers can be employed.
  • the control circuit 29 in the FIGURE 2 system provides the normal data processing control functions. These -functions include providing clock pulses to the various components and prtoviding command signals to stop decoding functions after the information bits are decoded and to readout the decoded bits.
  • a decoder comprising:
  • a register adapted to receive the code word signals in such a manner that the bits of the code word signals are entered into positions of the register corresponding to their position in the code word;
  • control circuitry to cyclically shift the bit signals in said register for k bit decoding operations, to initiate a bit decoding operation after each shift
  • a multiple error :correction decoder comprising:
  • control circuitry to cyclically shift the bit signals in said registers lfor k bit decoding operations, to initiate a bit decoding operation after each shift, and to terminate word decoding operations after k bit decoding operations.
  • ROBERT C BAILEY, Primary Examiner.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
US212746A 1962-07-26 1962-07-26 Simplified error-control decoder Expired - Lifetime US3222644A (en)

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Application Number Priority Date Filing Date Title
US212746A US3222644A (en) 1962-07-26 1962-07-26 Simplified error-control decoder
FR942668A FR1364472A (fr) 1962-07-26 1963-07-25 Perfectionnements aux dispositifs de transmission d'informations

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US212746A US3222644A (en) 1962-07-26 1962-07-26 Simplified error-control decoder
US213733A US3164804A (en) 1962-07-31 1962-07-31 Simplified two-stage error-control decoder

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3328759A (en) * 1963-05-13 1967-06-27 Ibm Simplified partial double error correction using single error correcting code
US3404373A (en) * 1965-02-18 1968-10-01 Rca Corp System for automatic correction of burst errors
US3582878A (en) * 1969-01-08 1971-06-01 Ibm Multiple random error correcting system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2552629A (en) * 1950-01-11 1951-05-15 Bell Telephone Labor Inc Error-detecting and correcting system
US2628346A (en) * 1951-11-03 1953-02-10 Monroe Calculating Machine Magnetic tape error control
US2956124A (en) * 1958-05-01 1960-10-11 Bell Telephone Labor Inc Continuous digital error correcting system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2552629A (en) * 1950-01-11 1951-05-15 Bell Telephone Labor Inc Error-detecting and correcting system
US2628346A (en) * 1951-11-03 1953-02-10 Monroe Calculating Machine Magnetic tape error control
US2956124A (en) * 1958-05-01 1960-10-11 Bell Telephone Labor Inc Continuous digital error correcting system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3328759A (en) * 1963-05-13 1967-06-27 Ibm Simplified partial double error correction using single error correcting code
US3404373A (en) * 1965-02-18 1968-10-01 Rca Corp System for automatic correction of burst errors
US3582878A (en) * 1969-01-08 1971-06-01 Ibm Multiple random error correcting system

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