US3094689A - Magnetic core memory circuit - Google Patents

Magnetic core memory circuit Download PDF

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Publication number
US3094689A
US3094689A US37318A US3731860A US3094689A US 3094689 A US3094689 A US 3094689A US 37318 A US37318 A US 37318A US 3731860 A US3731860 A US 3731860A US 3094689 A US3094689 A US 3094689A
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Prior art keywords
windings
transistors
cores
winding
core
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Expired - Lifetime
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US37318A
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English (en)
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Wahlstrom Sven Erik
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Atvidabergs Industrier AB
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Atvidabergs Industrier AB
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
    • G11C11/06014—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit using one such element per bit

Definitions

  • the present invention relates to a magnetic core memory circuit, particularly a magnetic core memory where one or more memory cores are selected and magnetized with the aid of transistor switches.
  • the selection and magnetization of the desired cores in order to write or read information in the core is generally performed by means of electron tube circuits.
  • transistors with their longer life time and lower power consumption are not used more extensively to drive core memories, at least not greater memories where the reading and writ-ing pulses are very fast.
  • the impedance of a drive winding which can pass through several thousand cores is very non-linear and moreover is depending on the number of cores to be switched. If the rise time of the drive pulses is very short and the winding is passing some thousand cores the electromotive force induced in the drive winding may reach some twenty or thirty volts. In order to maintain a constant current in the drive winding and thus a well defined switching time in spite of the nonlinear impedance it is necessary that the drive winding is fed by a constant current source.
  • One possibility for transistorizing a magnetic core memory at least partly is to select the desired winding, for example an X-winding with the aid of transistor switches individual to the diiierent windings and then to feed all the windings of this class (for example the X-windings) of the memory matrix with drive pulses from a constant current source containing electron tubes.
  • the transistor switch of the selected winding is made conducting before the drive pulse appears, and thus the voltage across the switches of the non-selected windings is reduced to electromot-ive force induced in the selected winding.
  • the last mentioned circuit has some drawbacks, particularly in core memories of the kind where the drive pulse is built up of a read pulse having a certain polarity, immediately followed by a write pulse having the opposite polarity.
  • the transistor switches of the nonselected windings then must have such a base bias that the collector-base diode cannot be made conducting when the collector during one half of the drive pulse (for example the positive pulse if the transistor is a pup-transistor) is acting as an emitter.
  • a circuit according to the invention with core memories comprising a "ice plurality of core groups where each group of cores is provided with at least one common winding and a normally closed gate in series with the Winding, said gate being controlled by a first control circuit (for example an address register).
  • a first control circuit for example an address register
  • the invention is characterized therein that all windings and the pertaining gates are connected in parallel between two constant current sources which are normally short circuited to a common point through electronic switches, one of which is arranged to be opened when the cores are to be set into one magnetic state while the other switch is arranged to be opened when the cores are to be set into the opposite state, whereby a constant current is caused to flow in the desired direction from one constant current source through the gate and the common winding of the selected core group.
  • FIG. 1 shows a schematic diagram of a core memory according to the invention and FIGS. 2, 3 and 4 show pulse diagrams.
  • C11, C12 C designate a number of ring shaped memory cores having a rectangular hysteresis loop, said cores being arranged in a matrix array.
  • the cores are provided on one hand with windings X1, X2, Xn each common to all cores of a row and on the other hand with windings Y1, Y2, Yn each common to the cores of a column.
  • the windings are preferably a single wire threaded through the cores.
  • the memory operates according to the coincidence principle i.e. both one X- and one Y-Winding must carry cooperating currents if a core should change the state.
  • Txl, Tx2, Txn and Ty1, Ty2, Tyn designate transistor gates for the X- and Y-windings respectively, said gates being utilized for selecting a certain core in the memory.
  • the transistors are normally cut off but they can be made conducting by applying a suitable voltage to the base, for example from an address register ASx and ASy respectively.
  • All the X-windings X1, X2, Xn are connected in parallel between a read pulse drive circuit and a Write pulse drive circuit.
  • Each drive circuit comprises a constant current source containing a voltage source E2 having a comparatively high negative voltage connected in series with a resistor R having a value which is high compared with the impedance of the X windings and a normally conducting transistor Txr and Txs respectively.
  • the collectors of said transistors are connected to the point P and Q respectively where the resistor R is connected to the parallel connected X windings.
  • the emitters of the transistors Txr and Txy are grounded.
  • the base electrode of the transistor Txr is connected to a readpulse generator LPG while the base of the transistor Txs is connected to a write pulse generator SP6.
  • the waveform of the positive pulses generated by said pulse generators is shown in FIG. 4.
  • a diode D is connected between each point P and Q respectively and a negative voltage source -E1 the voltage of which is somewhat higher than the highest possible voltage which can be induced in the windings.
  • the Y-windings are in the same manner connected between two drive circuits of the same kind as the drive circuits of the Y-windings and thus they are not described in greater detail.
  • the transistors included in the drive circuits of the Y-windings are designated Tyr and Tys, respectively.
  • the read pulse generator LPG is generating a read pulse having the waveform shown in FIG. 4, said pulse being applied to the base of the transistors Txr and Tyr. Said transistors which are of a type having a short rise and decay time, are cut oif causing the short circuit between the points P and ground to be interrupted.
  • a write pulse is generated during the time t5-t6 by the write pulse generator SPG, causing the transistors Txs and Tys to be cut off so that currents having the reverse direction are obtained through the windings Y1 and X2 and set the core into the one-state.
  • the transistors Tx2 and Tyl are again made non-conducting. After a moment a new read and write pulse appears and information can be read out and be written at an arbitrary location in the memory.
  • the windings which have not been selected by the address registers are connected to ground through the drive transistors Txs and Tys respectively.
  • error signals owing to capacitive coupling between the read out winding (not shown) and the unselected windings can be avoided in the read out winding.
  • the transistors Txl-Txn and Tyl-Tyn conduct currents in both directions and they should preferably be bilateral as is indicated in the circuit diagram. As such transistors up to now have been expensive and not readily available it may be necessary to use standard unilateral transistors.
  • the collector electrode is preferably connected to the points P of the drive circuits. Owing to the steeper edges of the read pulses the voltage induced in a selected winding will namely become higher during reading than during writing.
  • the rated back voltages are of the same magnitude it is however suitable to connect the emitter electrodes of the transistors Txl-Txn and Tyl-Tyn to the points P particularly if the current amplification B of the transistor is small in the inverted circuit i.e. when the collector is acting as emitter.
  • the current through the winding is composed of the base current and the current flowing to the point P during the reading phase.
  • the current through the winding is almost equal to the current to the point Q. In this manner the base current which shall be delivered by the address register may be lower than if the collector is connected to the point P.
  • a magnetic core memory circuit comprising a plurality of groups of magnetic cores forming a matrix, each core of which has a rectangular hysteresis loop, each group of cores in said array is connected to at least one common winding, normally closed gate circuit means connected in series with each of said windings for selecting a core, control means connected to said gate means for controlling said gate means, said plurality of windings connected to said cores and said gate circuit means connected thereto are connected in parallel between two constant current sources each of which is normally shortcircuited to a common potential by means of transistor switching means, one transistor means of which is cut oif when setting the cores into one magnetic state while another transistor means is cut off when setting the cores into a reverse state, a constant current flowing from 'one current source to the other through a winding of a core selected by said control means, and non-selected windings being connected to said common potential.
  • control means are provided to open and close the gate of a selected core group only at the times when both switches are conducting.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
US37318A 1959-07-10 1960-06-20 Magnetic core memory circuit Expired - Lifetime US3094689A (en)

Applications Claiming Priority (1)

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SE652259 1959-07-10

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US3094689A true US3094689A (en) 1963-06-18

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US (1) US3094689A (ja)
FR (1) FR1262276A (ja)
GB (1) GB938477A (ja)
NL (1) NL253601A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3143668A (en) * 1962-07-12 1964-08-04 Loy H Bloodworth Power saving switch driver system
US3247494A (en) * 1960-10-14 1966-04-19 Sylvania Electric Prod Memory control systems

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1295019B (de) * 1964-08-06 1969-05-14 Standard Elektrik Lorenz Ag Wortorganisierter Magnetkernspeicher
DE1293845B (de) * 1966-04-29 1969-04-30 Tankbau Weilheim Elektronische Auswahlschaltung in Matrixform
DE1499989B1 (de) * 1966-05-10 1972-03-16 Zentronik Veb K Informationsspeicher und treiberleiterwaehl matrixanordnung

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2917727A (en) * 1957-07-29 1959-12-15 Honeywell Regulator Co Electrical apparatus
US2939119A (en) * 1956-06-30 1960-05-31 Ibm Core storage matrix
US3054988A (en) * 1957-05-22 1962-09-18 Ncr Co Multi-purpose register

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2939119A (en) * 1956-06-30 1960-05-31 Ibm Core storage matrix
US3054988A (en) * 1957-05-22 1962-09-18 Ncr Co Multi-purpose register
US2917727A (en) * 1957-07-29 1959-12-15 Honeywell Regulator Co Electrical apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3247494A (en) * 1960-10-14 1966-04-19 Sylvania Electric Prod Memory control systems
US3143668A (en) * 1962-07-12 1964-08-04 Loy H Bloodworth Power saving switch driver system

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Publication number Publication date
NL253601A (ja)
FR1262276A (fr) 1961-05-26
GB938477A (en) 1963-10-02

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