US2938668A - Serial-parallel binary-decimal adder - Google Patents

Description

May 31, 1960 B. L. HAVENS ET AL 2,938,668

SERIAL-PARALLEL Emmy-DECIMAL ADDER l2 Sheets-Sheet 1 Filed Feb. 20, 1953 m u E wr. ma mw@ n rom N 9-8 .Hhua N WLB :EEG mmm d@ IW lmm m mm n- May 31, 1960 B. L. HAVENS ET AL 2,938,668

SERIAL-PARALLEL Emmy-DECIMAL ADDER l2 Sheets-Sheet 2 Filed Feb. 20, 1953 mmJDa May 31, 1960 B. L. HAVENS ET A1. 2,938,668

SERIAL-PARALLEL BINARY-DECIMAL ADDER Filed Feb. 20. 1953 12 Sheets-Sheet 3 May 31, 1960 B. L. HAvENs ET AL 2,938,668

SERIAL-PARALLEL Emmy-DECIMAL ADDER l2 Sheets-Sheet 4 Filed Feb. 20, 1953 mme INVENTORS BYRON L. HAvENs CHARLES R BORDERS BW 9 ArroRNY l2 Sheets-Sheet 5 ATTORNEY B. L. HAVENS ET AL May 31, 1950 SERIAL-PARALLEL BINARY-DECIMAL ADDER Filed Feb. 20, 1953 May 31, 1960 B. L. HAvENs ETAL A SERIAL-PARALLEL Emmy-DECIMAL ADDER 12 Sheets-Sheet 6 Filed Feb. 20, 1953 BYRdv'ivs CHARLES'R. BORDERS ATTORNEY MHT NNP

Q o m9 May 31, 1960 B. L. HAVENS ET AL 2,938,668

SERIAL-PARALLEL Emmy-DECIMAL ADDER l2 Sheets-Sheet 7 Filed Feb. 20, 1953 TEX May 31, 1960 B. L. HAvENs ET AL 2,938,668

SERIAL-PARALLEL Emmy-DECIMAL ADDER l2 Shecs-Sheet 8 Filed Feb. 20, 1953 mow S R s SNR www Y OA E MS m ELQEUEO WNL M4N IOR RA f YH BC Y B May 31, 1960 5.1.. HAvl-:Ns ET A1. 2,938,658

SERIAL-PARALLEL mmm-DECIMAL ADDER Filed Feb. 20, 1953 l2 Sheets-Sheet 9 +150 VOLTS l N INVENTORS a BYRON L. HAVENS "B CHARLES R. BORDERS FIG. 9a

l2 Sheets-Sheet 10 RNEY B. L. HAVENS ET AL SERIAL-PARALLEL BINARY-DECIMAL ADDER May 31, 1960 Filed Feb. 20. 1953 l2 Sheets-Sheet 11 B. L. HAVENS ET AL SERIAL-PARALLEL BINARYDECMAL ADDER May 31, 1960 Filed Feb. 20, 1953 May 31, 1960 E. L. HAVENS ETAL 2,938,668

SERIL-PARALLEL BINARY-DECIMAL ADDER Filed Feb. 20, 1953 l2 Sheets-Sheet 12 FIG. IO

INVENTORS BYRON L. HAVENS BY CHARLES R. BORDERS N ATTORNEY United States Patent O 2,938,668 'SERIAL-PARALLEL BlNARY-DECMAL ADDER Byron L. Havens, Closter, and Charles R. Borders,

Alpine, NJ., assignors to International Business Machines Corporation, New York, N.Y., a corporation of Newl York I iled Feb. 20, 1953, Ser. No. 338,122 2 Claims. (Cl. 23S-169) This invention relates to digital adders and more particularly to a circuit for adding decimal numbers, column by column, wherein each decimal digit is represented in the pure binary-notation by time coded pulses on a plurality of wires.

ln the binary notation only two digits are employed, i.e. and l. digit 0 and the decimal digit l is represented by binary digit l.. These binary digits are referred to as bits. 'Ihe digital positions Vor orders in a binary number, reading from right to left, correspond in value to 2, 21, 22, 23, 24, etc. or decimal digits 1, 2, 4, 8, 16 etc. respectively. For example, binary number 1001 represents decimal digit 9 which is determinedby the addition of decimal digits 1 and 8 indicated by a binary l in the extreme right and the left binary positions respectively. Hence, by using binary bits or pulses in groups of four wherein a pulse represents .a binary 1 and the absence of a pulse represents a binary 0 any decimal digit from 0 to 9 inclusive may be written in the pure binary-notation.

The system of representing decimal numbers, digit for digit, in the pure binary notation is referred to herein as the `binary-decimal system. The four consecutive binary orders, reading from iight to left, represent the decimal digits 1, 2, 4 and 8 for the units decimal order and are accordingly referred to as .the 1 bit, 2 bit, 4 bit and 8 bit respectively. It follows that the four binary orders of the tens decimal order represent the decimal digits 10, 20, 40 and 80 respectively. Likewise, in subsequent decimal orders, for example, the four respective binary orders of the hundredsA decimal order represent the decimal digits 100, 200, 400 and 800 respectively.

As an example, 459 will be represented in the binarydecimal system by 0100, 0101, 1001. The four binary bits at the right represent the decimal digit 9 of the units order, the next four bits to the left represent the decimal digit 5 of the tens order, and the four bits at the extreme left represent the decimal digit 4 of the hundreds order.

Any decimal number from 0 to 15 inclusive can be represented by a group of four ybinary bits. v However, in the binary-decimal system, only the decimal digits O to 9 inclusive are represented by each group of four binary bits.

The addition of two decimal digits or a decimal column of the decimal numbers to be added may provide atmost a sum of 18 plus a carry. The range of decimal sums is, therefore, 0 to 19 inclusive. As stated, if -this addition is performed in the pure binary notation, and the sum is 16 or more, a carry is provided and in any case if the sum is over 9 (1001), it is not expressed in the binary-decimal system by mere binary addition. It follows that the sum, in the binary-decimal system of two decimal numbers written in the binary-decimal system, may be obtained by adding the two numbers in the pure binary notation and providing circuit means responsive to a sum greater than 9 (1001) which will reduce such sums to the appropriate digit (less than ten) and a decimal carry.

Adders for deriving the sum of decimal numbers expressed in the binary-decimal system by pure binary addi- The decimal digit 0 is represented by binaryV ice tion and then converting that sum to the binary-decimall system are of several types. The adder is a serial type adder if the binary bits representing the decimal digits to be added are received in succession. The adder is a parallel type adder if the binary bits representing the decimal digits to be added are received simultaneously.

A principal object of the invention is to provide a novel binary-decimal adder of the serial-parallel type.

Another object is to provide a novel serial-parallel adder for adding two decimal numbers expressed in the binarydecimal system, each digit of the decimal numbers being expressed in the pure binary notation; and producing ay sum expressed in the binary-decimal notation.

A further object is to provide novel means for converting a binary sum obtained from the addition of numbers represented in the binary-decimal system to a sum expressed in the binary-decimal system.

A still further object is to provide a novel circuit means for receiving a binary sum and converting that sum to a sum expressed in the binary-decimal system without employing electrical addition of pulses. i

vAnother object is to provide a novel binary-decimal type adder wherein the binary sum of two decimal numbers ,to be added is converted to the binary-decimal sum by applying the binary sum to coincidence circuitry.

Other objects of the invention will be pointed out in the following description and claims and illustrated in the accompanying drawings, which disclose, by way of ex-` amples, the principle of the invention and the best mode, which has been contemplated, of applying that principle.

In the drawing: i p Fig. l is a block diagram of one embodiment of the invention,

Fig. 2 is a circuit diagram of a delay circuit suitable for use in the embodiment shown in Fig. 1.

Fig. 2a shows wave forms illustrating the operation of the circuit of Fig. 2,

Fig. 3 is a circuit diagram of an AND circuit typical of the type employed by the invention,

Fig. 4 is a circuit diagram of an OR circuit typical ofv the type employed by the invention,

Fig. 5 is a circuit diagram of a binary adder which may be employed in the embodiment shown in Fig. l,

Fig. 6 is a logical diagram of one embodiment of the rationalizer shown in Fig. 1,

Fig. 6a is a circuit diagram for accomplishingthe functions of the logical diagram of Fig. 6, Y

Fig. 7 is a logical diagram of 'another embodiment of rationalizer shown in Fig. 8, and with Figs. 9, 9a, 9b andV 9c comprises a complete circuit diagram of the binarydecimal adder of the invention.

Briefly, the adder of the invention eiects addition of decimal numbers expressed in the binary-decimal system. In the embodiment shown two decimal numbers are added column bycolumn in time sequence. The binary bits representing each of the .two decimal digits of the same decimal column or order are applied simultaneously to the adder. Each binary bit is applied to a separate input terminal. Four binary adders are provided to eiect binary addition of corresponding or Ilike binary bits, i.e. one adder is provided for the 1 bits, one for the 2 bits, one for the 4 bits, and one for the 8 bits. Each adder has a separate input terminal to receive each of the two bits to be added and a third or carry input terminal. Also, each adder has an output termi- Patented May 31, 1960 nal at which appears the sum of the two binary bits added and a second or carry output terminal. The carry output terminal of each adder, except that for the 8 v bits, is connected to the carry input terminal of the case, it will be'indicated by the presence of carry at the carryoutput terminal of the 8 bit adder, or by the presence ot an output at the 8 bit adder plus an output at the 412i? adder' QI. ai the 2. bit adder- The ratiualzer includes coincidence and pulse transfer circuits responsive to the existence of any of the above conditions to efiect the necessary correction to provide a sum in the binary-decimal Systsru- The output terminal of the 1 bit adder and the output terminals of the rationalizer representing the decimal digits 2, 4, 8 and 10 provide thecgutput in the binary-decimalY system. The 10 output represents the first binary order or l bit of the next decimal order and is therefore referred to as a carry or l bit. carry output terminal or bit is connected through an appropriate delay circuit to the carry input terminal of the 1 bit adder to eiect carry thereto in time coincidence with the addition of the vnext decimal column.L VHence, the delay provided by this delay circuit is equal to the time elapsing between the addition ofsuccessive decimal columns.

Referring more particularly to Fig. l input terminals generally designated as 11 and 12 each comprise four` terminals-designated as 1 bit, .2 bit, 4 bit and 8 bit respectively. The respective binary bits representing one decimal digit f9- be' added are applied to the correspondingly designated terminal of the input terminals 11 and the respective binary bits representing the other decimal* digit to be added are appliedv to the correspondin glyrdesignatedY terminal'of tlie input terminals 12.v All ofthese bits are applied simultaneously. For example, suppose that the decimal'digits 5 and 6 occur. in the same decimal column and are to be added and further that the 5 (0101) is to b e applied to the input terminals f11`and the 6 (0110) is to be applied to the input terminals 12, It follows that pulseswiil b e simultaneously applied' to the 1 bitr and`4 .bit terminals of the input terminals 1,1 au@ 19 the 2, bit and 4- bit terminals ofthe input terminals 12.

The 1 bit terminals ofY both 11 and 12 are connected totheV input terminals 13 and 14. o f the l bit adder 15 having @1u-Output terminal, 15-1 and a carry outputy termina1f'1i61 connected tor the carry input terminal 17 of the 2 bit adder. Similarly, the 2 bit input terminals ae Connected t0 the iup-llt terminals 1,3 and 1.4 0f the 2 bit yadder 1 5- and the carry output terminal 16-2 of the 2v bit adder is connected to the carry input terminal 17 ofthe 4 bit adder. The 4 bit adder is similarly connectedto the 4 bit input terminals and to the carry input terminal 17 of theV 8 bit adder. Each of the binary adders eiects pure binary addition'of the inputs applied toits three input terminals.

The output terminals 1512,` -4 and 15-8 of the 2- bit4 bit: and 8 bit adders respectively and the terminal' 16:-,8of-I the 8 bitY adder supply the inputs to the ratiQnalinerk 19. These inputs activate the various interconnected coincidence circuits so that the output at the terminal 15%1,V of the l bit adder and the output terminal`s .240-t2`v, 21d-4, 22-8 and 23-10 of the rationalizer l? is in the binary-decimal system, the particular output' 'at aux 0.11@ 0f these. terminals representing the dsignated decimal sux thereof. Hence, if the terminal 23-10 is Up it indicates the presence of the decimal digit 10 or the first binary bit of the next decimal order to be added. This carry terminal 23-10 is therefore connected to the input terminal 24 of a delay circuit 25 whose output terminal 26 is connected to the carry input terminal 17 of the 1 bit adder to provide a carry pulse into the next decimal column to be added. This carry pulse or 10 bit is applied to the terminal 17 simultaneously with the application of inputs to the terminals 11 and 12y for the nexty decimal digits or column to be added. i t f y Various circuits used herein or particular points within the circuits are frequently referred to as Up or Down. Up means that the voltage present at the particular point or at the output of the circuit designated is positive with respect to ground. Down means that the voltage present at the particular point or at the output ofthe circuit designated is negative with respect to ground. If the control grid of avacuum tube is referred to as Down, it means that the voltage at that control grid is below the cutol value for the vacuum tube.

Numerous coincidence circuits are employed herein.

. An AND circuit refers to a circuit which is operable to produce a positive voltage at its output terminal only when all of the input terminals thereof have a positive voltage applied rthereto simultaneously. An OR circuit refers to a circuit operable to produce a positive voltage at its output terminal when only one or a plurality of the input terminals thereof has a positive voltage applied thereto.

The invention utilizes numerous dual-type tubes having two tube sections in a single envelope. `Each such section is referred to herein as a tube and designated by a number -followed by the; letter L or R or simply by the letters L and R to indicate the left-hand or righthand tube sectionrespectively, A tube so referred to is similarly designated thereafter if employed with the same, immediate circuitry and for the `same purpose even though' it is` not shown with its corresponding L or R tube.

Referring more particularly to lligs. 2 and 2a, the delay circuit `25 actually used in Fig. l will be described. This circuit is claimed inthe U.S. patentof Byron L. Havens, No. Re. 23,699', granted August 18, 1953. The

curvesV of Fig.v 2a demonstrate the operation Yof the cir-y cuit shown in Fig. 2. In orderto facilitate the description, the time axis (abscissa) is divided into equal time intervals designated T1, T2, T33,r T4 and T 5 respectively.

The length ofl each of these time intervals is dependent upon the particular circuit design and as used herein is equal to the time elapsing betweenthe initiation of the additiony o f one decimall column and the initiation of the addition of the next decimal column to be added. As one example, each time interval maybe of approximately one microsecond duration. Y,

Brielly,-an input pulse ('Fig. 2a) is applied to the input terminal 2,-4,v of the circuit shown in Fig. 2 during one preselected ltime interval and produces an output pulse (Fig, 2a) at the output terminal 26 during the next subsequent time interval, An input pulse may be appliedl to the input terminal 24 during the same time interval, T3 for example, that an output pulse is produced at the output terminal 26. The ybackproduced by an input pulse is used to set up the output pulse and the circuitry is such that there is complete isolation between the output and input pulse during any given time interval.

A clamping pulse (Fig. 2a) is appliedv to the terminal 62 to wipe out or remove the information Vstored afterthat information has; been utilized.

The anode of tube L is connected through inductance- 64 and an anode load resistor 65 in parallel to a +150 volt terminal 66. The inductance 64 is provided to increase the voltage swing in the positive direction at the anode of ,the tubeL (Fig, 2a during T3 andv T4) vfor'a preselected time immediately after'that'tube is rendered non-conductive.

The diode rectiers 67 and 68 connected respectively to input terminal 24 and terminal 69, and the resistor 7i?A The tube R is operated as a cathode follower and is always conductive during operation of the delay circuit.v The cathode load resistor 73 is connected to a 82 volt terminal 74 which is also connected through a resistor 75 and a condenser 76 to the anode of the tube L. The terminal 62 is connected through a resistor 77 and diode rectiiiers 78, 79, and 80, in series, to a -30 volt terminal 81. The juncture 82 is the connection between the rectier 79 and 80 and between the resistor 75 and condenser 76. The juncture 33 joining rectiers 78 and 79 is connected through a parasitic suppressor resistor 84 to the control grid of the tube R and through a condenser 85 to ground.

During the time interval T1, an input pulse is not applied to the input terminal 24 and juncture 71 is therefore Down so that a positive voltage is not applied to the control grid of the tube L. During this time interval the tube L is non-conductive, tube R is conductive, and output terminal 26 is Down. yThe voltage at the anode of tube L is +150 volts and the condenser 76 is charged with 180 volts appearing across it, the left plate is at +150 volts and the right plate is at -30 volts. The juncture 82 cannot he appreciably more negative than the -30 volt terminal 81 because when such is attempted the rectifier 80 conducts and maintains the voltage at juncture 82 to essentially that of the terminal 81. lt is the conduction of rectifier 80 during the time interval T1 that keeps juncture S2 at approximately -30 volts. The resistor 75 tends to prevent the Voltage at juncture 82 from drifting between the application of successive lamping pulses.

p The juncture 83 is also at 30 volts and condenser 85 is charged with -30 volts on its upper plate and its lower plate is at zero volts (ground). Rectifier 79 ccnducts when condenser 85 is being charged and when the clamping pulse (Fig. 2a) applied to the terminal 62 attempts to pull the juncture 83 below -30 volts, the voltage at the terminal 81. Hence, when the clamping pulse is most negative, the voltage at the control grid of the tube R has been pulled Down, and since tube Rl is a cathode follower, the voltage at the output terminal 26 is also pulled Down. Y

This action effects the wiping out of the information stored after that information has been used. In other words, the output pulse produced is brought to an end as shown at the beginning of time intervals T4 and T5 (Fig. 2a). When the clamping pulse thus goes negative the rectifier 78 is rendered conductive.

During the latter portion of time interval T2 the input pulse and synchronous pulse are both positive simultaneously. The juncture 71 is therefore UP and the tube L becomes heavily conductive and the voltage at its anode decreases rapidly (Fig. 2a). The condenser 76 discharges through the tube L. The resulting tendency of juncture 82 to acquire the same voltage increment as the anode of the tube L is arrested by the conduction of rectier 80 and the voltage at this juncture remains -30 volts.

Just at the start of time interval T3 both the input pulse and synchronous pulse go negative and the voltage at the juncture 71 and control grid of tube L accordingly goes Down and tube L is rendered non-conductive. As a result, the voltage at the anode of the tube L increases rapidly and actually exceeds +150 volts because this anode circuit is less than critically damped during the yback time. It is this increased voltage or yback,

which initiates the output pulse. This voltage is transferred through condenser 76 to cause' thevoltage at juncture 82 to go Up (to approximately +5 volts) from -30 volts. The rectifier 79 then conducts to cause the juncture 83 and control grid of tube R is go Up and the upper plate of condenser S5 is charged positive relative to its lower or grounded plate. The voltage at the output terminal 26 connected to the cathode of the tube R follows the control grid thereof and goes Up to initiate the output pulse during the time interval T3.

As the voltage at the anode of the tube L decreases toward +150 volts the voltage at juncture 82 similarly decreases. During the latter portion of time interval T3 the voltage at the juncture 82 is again approximately -30 volts. Both the terminals 24 and 69 again go positive as shown by the second input pulse and synchronousl pulse which occur during the latter part of time interval T3 while the output terminal 26 is still Up.

As a result the tube L again becomes heavily conductive and the voltage at its'anode decreases and the juncture 82 again remains at -30 volts because of the conduction through rectifier S0.

When the clamping pulse goes negative at the start of time interval T4, conduction through rectiiiers 78, 79 and 80 results and juncture 83 as well as juncture 82 is placed at approximately -30 volts. The'control grid of tube R and output terminal 26 therefore go Down and the output pulse, occurring during time interval T3 produced in response to the input pulse applied during time interval T2, is terminated.-

When the juncture 71 goes Down at the start of time interval T4, the tube L becomes non-conductive and its anode Voltage starts to increase rapidly as described hereinbefore.

This increased voltage causes the juncture 82 to go Up, the juncture 83 to go Up and the output terminal 26 to go Up as indicated by the output pulse occurring during time interval T4. The voltage at the `anode of the tube L nally settles, during the time interval T5, at a steady value of +150 volts in accordance with the damping ef fect. If an input pulse Was applied during the time interval T4, the voltage at the anode of tube L would never reach a steady value of +150 volts. Such is indicated byv sumed a voltage value of -30 volts but the juncture 83 is, still Up. When the clamping pulse causes the' terminal:

62 togo negative the rectifers 78, 79 and 80 are rendered conductive and the voltage at the juncture 83 Agoes'Down to terminate the output pulse at the beginning of time interval T5.

It is now clear that the use of yback makes possiblethe production of an output pulse in one preselected time interval in response to an input pulse received during the next prior time interval and that rectifier circuitry and aclamping pulse are employed to effect isolation between input and output circuits simultaneously operable.

It is understood that any suitable delay circuit may be' employed by the invention and that the various voltage values were given merely to facilitate the description and understanding of the circuit operation. Also, the particular values of the circuit components used will Vary in accordance with the particular operation the delay circuit is required to perform.

Fig. 3 shows an AND circuit typical of the type employed by the invention. The resistor R connected between the juncture J and the source of positive voltage B+ tends to pull the juncture J -up to the positive voltage B+. The plates of the diode rectifiers and 96 are connected to juncture J and the cathodes of these rectitiers are connected to the respective input terminals. Hence, the voltage at I can be no higher than the lower ofthe two voltages at the input terminals. The voltage at I 2,9ss,ees f will change only if the increased voltage is present at the more negative ofthe two input terminals. In such case,

the voltage at vI will rise until it reaches this increased voltage value. It is seen, therefore, that when both of the input terminals are Up, I and consequently the output terminal connected thereto is Up. Obviously, additional diodes may be connected between corresponding input terminals andthe juncture J and the juncture will be Up only when all input terminals are Up.

Fig. 4 shows OR circuit using diode rectifiers 97 and 98. The resistor R1 connected between the juncture J1 and a source of negative voltage B- tends to pull down the voltage at J1 to a value equal to that of B-. The cathodes of the diodes are connected to juncture I1 and the plates of these diodes are connected to respective inputterminals. Hence, the voltage at I1 can be no lower than the higher of the voltages at the input terminals.

The voltage at J1 increases in accordance with the more positive voltage at the input terminals. Hence, when either of the input terminals is Up the terminal I and consequently the output terminal connected thereto is Up. Obviously, additional diodes may be connected between corresponding input termnials and the juncture J1 and the juncture will be Up when any one or more of the input terminals is Up. -f Y Referring more particularly to Fig. 5 the novel circuit shown effects addition in true binary fashion. As stated the presence of a pulse at one of the input terminals 13, 14 and 17 indicates the presence of binary l and the absence of a pulse thereat indicates a binary 0. Hence, to eiect addition-'in true binary fashion the output terminal 15-1 must exhibit a binary 0 when no input pulse is applied to the input terminals 13, 14 and 17, a binary l when an input pulse is applied to one input terminal, a binary 0 and a binary 1 carry when pulses are applied to two input terminals,'and a binary 1 and a binary l carryV when .pulses are applied to all three input terminals. These functions are performed by the circuitry shown.

Doderectiiiers 100 and 101 have their cathodes connected to the input terminals 13 and 14 respectivelyand their plates commonly connected at juncture 102 whichis connected through a pull up resistor 103 to the +150 volt line 105. The rectiers 100 and 101 and the resistor 103 comprise an AND circuit 10611. When the input terminals 13 and 14 are Up the juncture 102 is Up. Similarly, the diode rectifiers 107 and.108 are connected between the input terminals 14 and 17 Yand the common juncture 109 is connected through pull up resistor 110'to the +1550 volt line 105. LThe diode rectiers 107 and 108 and 'the pull up resistor 110 comprise an AND circuit designated as 11111.

Thexiiode rectiers v113 and 114 are connected between the input terminals "13 and 17 and their common juncture 115 .is connected through pull up resistor 116 to the +150 volt Vline 105. The rectiers 113 and 114 and pull up resistor 116 comprisean AND circuit 111711. VThe respective junctures 102, 109 `and 115 are connected through the parasitic suppressor resistors 119 to the control grid of -the Ytubes 120, 121 and 122 respectively. The plates of each of these tubes are connected to the +150 volt line 105 and their cathodes are corrmionly connected through a dropping resistor 124 and a load resistor 125 to the -150 volt line 130. The resistor 125 is a common load resistor for each of the cathode fol-- lower tubes 120, 121 and 122 'and the dropping resistor 124 is provided to compensate for the cathode follower bias and thereby keep the cathodes of those tubes at approximately the same voltage as the most positive of their controlgrids. Since the cathodes of the tubes 120, 121 and i122 are commonly connected, the carry output terminal 16-1 is Up when one or more of the grids ofthe tubes '120, 121and v122 are Up. These tubes 120, 121 and 122 therefore comprise a cathode followerV type OR circuit. If any two of thelinput terminals 13, 14 and 17 are Up,A the corresponding AND circuit is renderedeifective to cause the carry output terminal 116-21 to go Up. For example, if the input terminals 13 and 14 go Up, the juncture 102 of AND circuit 106a goes Up, the control grid of the tube -connected thereto goes Up, the cathode of tube 120 goes Up andthe carry loutput terminal 16-1 goes Up. Also, if all three of the input terminals 13, 14 and 17 go UP, the junctures 102, 109 and l115 of AND circuit 10611, 11111 and 11711, respectively, all go Up. The control grids of cathode follower ` tubes 120, 121 and 122 all go Up land carry output terminal 16-1 goes Up. Hence, if Aan input is present at `two or three of the input terminals 13, V14 and 17, a carry output is provided. This complies with the rules of binary addition.

The carry output terminal 16-1 `is also connected through a parasitic suppressor -resistor and grid current limiting resistor 119 to the control grid of inverter tube 131' having Va grounded cathode and its plate rconnected through load resistor 132to the +150 volt line 105. The plate of inverter tube .131 is also connected through a voltage divider comprising resistors 133 and 134 to the +150 volt line 130.V A frequency compensating condenser 135 is connected, in parallel, with the resistor 133 and the juncture of resistors 133 and 134 is connected through a parasitic suppressor 'resistor 119 to the Ycontrol grid of the cathode follower tube 136 having its cathode connected through a load resistor 137 to the -l50 volt line 130 andits plate connected Vto the +150 volt line 105. The control grid of the inverter tube 131 is connected to the carry output terminal 16-1 and is therefore Up when two or three of the input terminals 13, 14 and 17 arerUp. It follows that the Yplate of the inverter tube .131 is Up when one of the input terminals 13, 14 and 17 is Up or when none of those terminals is Up. The' cathode of the cathode follower tube 136 follows its grid and is therefore` Up when one input is present or when rno input is present.

The cathodes of diode rectiers 140, 141 and 142 are connected to the input terminals 13, 14 and 17 respectively and their plates connected to a common juncture 143 which is connected through a pull up resistor 144 to the volt line 105. Rectiers 140, 141 and 142 and pull up resistor 144 comprise an AND circuit 14511. The juncture 143 of AND circuit 145a.is connected through parasitic suppressor resistor119 tothe control grid of the cathode follower tube 147 having its plate connected to the +150 volt line 105.

The diode rectiiiers 148, l149 and 150 have their plates connected to the input terminals 13, 14 and 17 respec-A tively and theircathodes connected to a common juncture" 151 which is connected through a pull down resistor 152 to the 150 volt line 130. The rectiers 148, 149 and' Diode rectifier 158 has its plate connected to the Vplate.

of rectifier 154 and its cathode connected to the cathode of cathode follower 136. Diode rectifiers 154 and 158 and pull up resistor 155 comprise an AND circuit 159:1.

The cathodes of cathode follower tubes 147 and 15.6'

effectively comprise an'OR circuit since they `are commonly connected through a dropping resistor and a.

load resistor 161 to the -150 volt line 130. The juncture at resistors 160 and 161 minal 15-1. Y

The juncture 143 of AND circuit 145a is Up only when all three of the input terminals 13, 14 and 17 are' Up, i.e. only whenthree Ainputs are applied. As a resultv the control grid of cathode followerk tube 147Y goes `Up, and its cathode follows to cause the output terminal is connected to output ter- 15-1 to go Up when three inputs are present. The juncture 151 ofA OR circuit 153 goes Up when one or more of input terminals 13, 14 and 17 go Up. The cathode of cathode follower tube 136 goes Up when one input or no input is present. Hence, the juncture 163 of AND circuit 159a goes Up only when one of the input terminals 13, 14 and 17 is Up. When the juncture 163 of AND circuit 159a goes Up the grid and cathode of cathode follower tube 156 go Up and the output terminal 15-1 goes Up. Hence, output terminal 15-1 goes Up when one or three inputs are applied to the input terminals 13, 14 and 17.

The circuit of Fig. therefore provides an output sum and carry strictly in accordance with the rules of binary addition. Also, as shown hereinbefore, a carry output is provided at terminal 16-1 when two o r three binary ls are added, but not when a single binary 1 is present.

The output and carry terminal designations -1 and 16-1, respectively, indicate that thev binary adder of Fig. 5 corresponds to the l 'bit adder shown in Fig. 1. it is clear that the 2, 4 and 8 bit adders of Fig. 1 are similar, the only difference being in the designation of the output and carry terminals.

The 8 bit adder of Fig. l need not be a complete binary adder as previously described, since it will not be possible to havethree input pulses applied simultaneously. Three such inputs would correspond to a sum of 24 or more,

and 19 is the largest sum possible 'from the addition oftwo numbers in binary-decimal system with a carry from a previous column. For this reason the AND circuit and cathode follower, corresponding to 145a and 147, respectively in Fig. 5, may be omitted in the 8 bit adder of Fig. l.

The logical or block diagram of the rationalizer shown in Fig. 6 will be described in connection with Table I below.

The input terminals 15-2, 15-4, 15-8 and 16-8 correspond to similarly numbered terminals of Fig. 1. The middle column of Table I represents, in the binary notation, the corresponding or oppositely placed decimal number of the left-hand column and the extreme right-hand column designated the corresponding decimal numbers in the binary-decimal system. In the middle column the second binary column from the rightrepresents the input to the terminal 15-2, the third column, the input to the terminal 15-4, the fourth column, the input to the terminal 15-8 and the fifth column, the input to the terminal 16-8. In the right-hand column of Table I, the second binary column from the right indicates the output at the terminal 20-2, the third binary column, the output from the terminal 21-4, the fourth binary column, the output from the terminal 22-8 and the fifth, the output from the terminal 23-10. The output from the terminal 15-1 (Fig. 1) is represented by the right-hand binary v inclusive.

10 columnA or order of the middle-and right-hand columns of Table IL It is evident that the right-hand binary column in the binary-decimal system is identical to that in the pure binary notation, consequently no conversion of the l bit is ever required, regardless of the sum. Thus, the l bit of the sum need not enter the rationalizer.

As stated hereinbefore, the sum derived from the addition of any decimal column must lie between O to l19 This sum is derived by the binary bit adders of Fig. 1 and appears at the output terminals of those adders in the binary notation as shown by the middle column of Table I. The rationalizer converts this sum to thebinary-decimal system as indicated by the righthand column of Table I if such conversion is required, i.e. if the sum is over 9 (1001).

By referring to the middle column of Table I it can be seen by inspection of the second binary column from the right that the terminal 15-2 is Up when the decimal sum is either 2, 3, 6, 7, 10, 11, 14, l5, 18 or 19. From the third binary column it is seen that the input terminal 15-4 is Up when the decimal sum is either 4, 5, 6, 7, 12, 13, 14 or 15. From the fourth binary column it is seen that the terminal y15-8 is Up when the Sum is between 8 to l5 inclusive, and from the fifth column it is seen that the terminal 16-8 is Up when the sum is between 16 to 19 inclusive. Since these terminals must be either Up or Down, they are Down when any sum other than that indicated above is present.

The decimal sums which cause these terminals to be Up are indicated in the figures of the drawing, which figures are enclosed in a rectangle and directed by an arrow toward the lead connected to the terminal to which they apply. The Up conditionof various other points in the circuit are similarly designated.

In Fig. 6 the OR circuit 170, AND circuit 171a and OR circuit 172 are provided to detect sums greater than 9 (1001), All such numbers are indicated by the terminal 16-8 being in the Up condition or the terminal 15-8 being in the Up condition simultaneously with the terminal 15-4 or 15-2 being in the Up condition. If any of these three conditions is present, the lead 173 connected to the output terminal 23-10 is Up and a carry or 10 bit is present. If the terminal 16-8 is Up, the OR circuit connected between the terminal 16-8 and lead 173 functions to cause lead 173 to go Up. OR circuit 172 is connected between terminals 15-2 and 15-4. Hence, its output lead 174 connected to an input of AND circuit 171a is Up if either of those terminals is Up. The other input of AND circuit 171a is connected to terminal 15-8. Hence, if the terminal 15-8 and terminal 15-4 or the terminal 15-8 and the terminal 152`are Up, the output lead 175 of AND circuit 171a is Up. Lead 175 provides one input to the OR circuit 170. Hence, when lead 175 is Up, OR circuit 170 functions to cause lead 173 to go Up. Hence, if a 16 (1,0000), or an 8 (1000) plus a 4 (0100) or a 2 (0010) are present, the terminal 23--10 is Up to provide a carry pulse or a 10 bit.

Lead 173 supplies the input to inverter 177. 'Ihe juncture 178 or output of inverter 177 is therefore Up if the sum is between 0 to 9 inclusive. The juncture 178 and the input terminal 15-2 supply the inputs to OR circuit 179; The juncture 180 or output of OR circuit 179 is therefore Up when either the juncture 178 or the terminal 15-2 is'Up which corresponds to the condition when the sum is either 0 to 9, 10, 1l, 14, 15, 18 or 19. The juncture 180 supplies the input to inverter 181 and its output lead 182 is therefore Up when its input is-Down and vice versa. The lead 182 is therefore Up when the sum is either 12, 13, 16 or 17. The juncture 178 and the terminal 15-2 supply the two inputs to the AND circuit 183:1 and the output lead 184 of AND circuit 183:1 is Up only when both of its inputs are Up `or when the sum is either 2, 3, 6 or 7. Leads 182 and-184 supply the inputs to OR circuit 185. The

11 output of OR circuit 185 is applied to terminal 20-2,

which is Upwhen either of the leads 182 and 184 is Upv or when the sum is either 2, 3, -6, 7, 12, 13, 16 or 17. Iuncture 180 and terminal 15-4 supply the inputs for the OR circuit 187 and the AND circuit 188a. The output lead 189 connected to OR circuit 187 is therefore Up when either juncture 180 or terminal 15-4 is Up or when the sum is either to 15, 18 or 19. Lead 189 supplies the input to inverter '190' whose output lead 191 is Up when its input is Down or when the sum is either 16 or 17. The output lead 192 connected to AND circuit 18811 is Up only when both the input terminal 15-4 and juncture 180 are Up or when the sum is either 4, 5, 6, 7 ,4 14 or v15. Leads 191 and.1 92 supply the inputs to OR circuit 193. The output terminal 21-4 connected tothe output of OR circuit 193 is therefore Up when either one of the leads 191 or 192 is Up or when the sum is either 4, 6, 7, 14, 15, 16 or 17. Input terminal '1S-'8 andA juncture 417 8 supply the inputs to AND circuit195a whose output lead 196 is Up only When the terminal 15-8 and the juncture 178 are VUp or when the sum is 8 or 9. The inputs to AND circuit 197a are supplied by the input terminals l15-2 and 16-8 and its output lead 198 is Up only when both thoseA terminals are Up or when the sum is either l18 or 19.V Leads 196 and 198 supply theinputs for OR circuit 199. The output terminal 22-8 connected to the output lead of OR circuit 199 is there-V fore Up when either of the leads 196 or 19,8 is Up or when the sum is 8, 9, 18 or 19.

The output terminals 15-1 (Fig. 1), 20-2, 21-4, 22-8', and 23-10 supply an output representing the sum in thev vbinary-decimal system ofthe two decimal digits applied in the binary-decimal system to inputs 11 and 12 (Fig. 1) plus the carry, if any, from the previous addition of decimal digits. This is readily seen by reference to the right-hand column of Table I. The right or first binary column thereof appears at terminal 15-1 (Fig. 1) as a result of the normal binary addition elected in the 1 bit adder 15 (Fig. 1). The second binary column from the right shows that a binary l is present when the decimal sum is 2, 3, 6, 7, 12, 13, 16 or 17. Such is in `correspondence with the Up conditionV of terminal 20-2. Similar comparison of the third, fourth, and fth binary columns with the Up condition of terminals 20-4, 22-8 and 2340, respectively, indicates that the output produced at the terminals 151,.202,21-4, 22-8and 23-10 is lin the binary-,decimal system as indicated by the third column of VTable I.

Y,Referring to ,Fig. 6a the circuit diagram `corresponds functionally with'the logical diagram shown in Fig. 6.

The operation ofthe circuit `is more readily under- `sandable when consideredin connection with Fig. `6 and Table I.

The tubes 201L and 201R have their plates connected tothe +150 volt line 105 and their cathodes commonly connected throughload resistor 202 lto the -150 volt line 130. Parasitic suppressor resistors 203 are connected These ,cathode followen to the control grid of each tube. tubes comprise OR circuit 170 vandwhen the terminal 16-8 vis Up, the .output lead 17,3 is Up, denoting the presence of carry. AND circuit 171a comprises diode rectiiers 205 and 2,06 ,and the pull up resistor 207.`

WhentheY lead 175 connected to the juncture of diodesv 205 and 206 is Up, the `output Ylead 173 kis Up, causingl the output terminal 23-10 yto go Up thereby indicatingA the lead V174- connecting'the'juncture of diodes 208 and- 208:1 .to the cathodeof diode 206 ofiAND circuit 171a is Up. 'The cathode of diode 205 is connected to the 12 input terminal 15-8. Hence, the lead v1 75 connected to the juncture of diodes'205 and 206 of AND circuit 171a is Up when an 8 (1000) is present at input terminal I15-8 and a 4 (0100) or a 2 (0010) is present at input terminal 15-'4 or input terminal 15-2, respectively. Since all decimalsums between 10 to 19 inclusive Yare Vrepresented by input terminal 16-8 being in the Up condition, or input terminal 158 being in the Up condition and inputterminal 15-4 or input terminal 15-2 being in the Up condition, it Vis seen that the output terminal 23-10 will be in the yUp condition when the decimal sumV is over 9 (1001). The inverter 177 comprises amplifier tube 211L and cathode follower tube 211R. The cathode of tube j21'1L is connected to ground and its plate is connected through load resistor 212 to the +5150 volt vline and through resistor 213 and frequency compensating condenser 214, in parallel, to the control grid of tube 21'1R. Resistor-215 connected to the grid of tube 211R and the volt line 130 with resistors 213 and 212 comprise a voltage divider. The cathode of cathode follower tubek 211R vis connected through a dropping resistor 2151' kand load resistor 216 to the ,-150 volt line 130. When the control grid of tube 211L is Up its plate is Down, the control grid of cathode -follower tube 211R is Down and the cathode of tube 211R is Down. Hence, when the control grid of the tube 211L is Up, the cathode of tube 211R is Down and vice versa. It, therefore,l follows Vthat the cathode of tube 211R and juncture 178 'are Up when the decimal sum is between 0 to 9 inclusive.

The OR circuit 179 comprises cathode follower tubes 217L and 217R having their plates commonly connected to the +150 Volt line 105 and their cathodes commonly connected through dropping resistor 215r and load resistor- 218 to the -150 volt liner130. The control grid of the tube J217L is connected to the cathode of tube 211R and the control grid of the tube 217R is connected to the input terminal 15e2. The control grids oftubes 217L and 217R and their commonly connected cathodes, are therefore, Up when either the cathoderof tube 211R or the terminal 15-2 is Up. Thev ,inverter` circuit 181 comprising tubes 219L and 219R is similar to inverter circuit 177. However, the cathode circuit of tube 219B` is included as part of OR circuit which also includes tube 220 having its plate connected to the' +150 volt line 105, its `cathode connected to the cathode of tube 219R and its control grid connected to the plate of diode rectifier 221. The output cathode of inverter circuit 181 is Up when the OR circuit 179 is Down andisitherefore Up when the sum is either 12, 13, 16 or 17 This cath ode is connected -to the output terminal 20-2.A ANDHcircuit 183@ comprises diode rectiers 221 and 222 hav-ing their cathodes connected respectively to the cathode of tube 211R and the input terminal 15-2 and the pull up resistor 223 commonly connected to the plates of diode rectiers 221 and 222 and `to the +150 volt line V105. The cathode of tube 211Rand theinput terminal 1 5-2 are. Up only when the sum is either k2, 3, w6 or 7.y .Consex tubes 229L and 229R is-similar to the inverters 177 and 181. The cathode circuit of tube 229R is Vincluded as part of the OR circuit 193 and isconnected to the *cathode of tube '231 having its control grid connected to the platesof diode rectiiiers 232 and 233 and its plateiconnected to the .+1570 -volt Aline 105. The output of OR circuit 187 is Up when thesumis eitherO to 15, 18 or 19. Thev cathode of tube 2-29R and output terminal 21-4 connected thereto` are therefore Up when the sum iseither 1601217v '4 AND circuit 188:1 comprises diode rectiiiers 232'a'ndA 233 having their cathodes connected to the input terminal 15-4 and the output of OR circuit 179 respectively, and pull up resistor 234 connected between the +150 volt line 105 and the juncture of the commonly connected plates of diode rectiers 232 and 233. `The lead 192 connected to the output of AND circuit 188:1 is Up only when the input terminal 154 is Up and the output of OR circuit 179 is Up. The cathodes of tubes 231 and 229R and the output terminal 21-4 are Up when the lead 192 is Up or when the sum is either 4, 5, 6, 7, 14 or 15.

AND circuit 195:1 comprises diode rectiiiers 236 and 237 having their cathodes connected respectively to the cathode of tube 211R and the input terminal 15-8, and pull up resistor 238 connected between the +150 volt line 105 and the juncture of the commonly connected plates of diode rectiiiers 236 and 237. OR circuit 199 is similar to OR circuit 179 and comprises the tubes 2391. and 239R. The control grid of tube 239R is connected to the juncture of the plates of diode rectiers 236 and 237. When the cathode circuit of tube 211R is Up and the input terminal 15-8 is Up, the control grid of tube 239R, cathode circuit of tube 239R and the output terminal 22-8 are Up, i.e. when the sum is either 8 or 9. AND circuit 197a comprises diode rectiers 241 and 242 having their plates connected respectively to the input terminal 16-8 and the input terminal 15-2, and pull up resistor 243 connected between the +150 volt line 105 and the plates of diode rectiiiers 241 and 242. The juncture of the plates of diodes 241 and 242 is also connected to the control grid of tube 239L. Hence, when the input terminals 16-8 and 15-2 are Up, the control grid of tube 239L is Up, and the cathode circuit of tube 239L is Up and the terminal 22-8 connected thereto is also Up, i.e. when thesum is either 18 or 19.

Referring more particularly to Fig. 7 there is shown a logical or block diagram for the rationalizer of Fig. 1. The OR circuit 170, AND circuit 171:1 and OR circuit 172 are as shown in Fig. 6 and provide a l0 bit at the output terminal 23-10 when the decimal sum is between 10-19 inclusive. The inverter 177, AND circuits 195:1 and 197:1, and OR circuit 199 are also as shown in Fig. 6. The output terminal 228 is therefore in the Up condition when the decimal sum is either 8, 9, 18 or 19.

' AND circuit 250:1 receives inputs from the juncture 17 8 and the input terminal 15-4 and provides an output which is Up when the decimal sum is either 4, 5, 6 or 7. Threeinput AND circuit 251:1 receives inputs from the input terminals 15-2, 15-4 and 15-8 and therefore its output is Up when the decimal sum is either 14 or 15. AND circuit 252:1 receives inputs from the lead 173 which is Up when the decimal sum is between 10 to 19 inclusive and from input terminal 15-2. The output of AND circuit 252:z is therefore Up when the decimal sum is either 10, 11, 14, 15, 18 or 19. The output of AND circuit 252:1 provides the input to inverter 253 whose output is Up when the decimal sum is either to 9, 12, 13, 16 or 17. The output of inverter 253 and input terminal `16-8 are connected to supply the inputs to AND circuit 254:1. The output of AND circuit 254a is therefore Up when the decimal sum is either 16 or 17. The outputs of AND circuits 250:1, 251:1, and 254a supply the inputs to OR circuit 255 having its output connected to the output terminal 21-4. Since the output of OR circuit 255 is Up when the output of any one of the AND circuits 250:1 and 251:1 and 254:1 is Up, the output terminal 21-4 is Up when the decimal sum is either 4, 5, 6, 7, 14, 15, 16 or 17.

OR circuit 256 receives its inputs from the lead 173 and `from the input terminal 15.2 and therefore provides an output which is Up when the decimal sum is either 2, 3, 6, 7, to 19 inclusive. The outputs of inverter 253 and OR circuit 256 supply the input to AND circuit 257a having its output connected to the output terminal 14 20-2. Outputterminal 20-2 is therefore Up when the outputs of inverter 253 and OR circuit 256 are Upv orV when the decimal sum is either 2, 3, 6, 7, 12, 13, 16 or 17.

Referring more particularly to Fig. 8 Ithere is shown in logical diagram form another embodiment of the rationalizer shown in Fig. 1. OR circuit 170, AND circuit 171:1, OR circuit 172, inverter 177, AND circuit 195:1, AND circuit 197:1, AND circuit 250:1 and OR circuit *199 correspond to the similarly designated circuits in Fig. 7. Hence, it is seen that the outputs are provided at the output terminals 22-8 and 23-10 in exactly the same manner as explained in connection with Fig. 7.

AND circuit 260:1 receives inputs from the terminals 15-2 and 15-4 and its output is therefore Up when the decimal sum is either 6, 7, 14 or 15. Inverter 261 is connected to the input terminal 15-2 and therefore provides an output which is Up when the decimal sum is either 0, 1, 4, 5, 8, 9, 12, 13, 16 or 17. The output of inverter 261 serves as one of the inputs to the twoinput AND circuit 262a which receives its other input from the input terminal 16-8. The output of AND circuit 262:1 is therefore Up when -the decimal sum is either 16 or 17. The outputs of AND circuits 250:1, 260a and 262:: supply the inputs to the three-input VOR circuit 264 having its output connected to the output terminal 21-4. The output terminal 21-4 is therefore Up when the decimal sum is either 4, 5, 6, 7, 14, 15, 16 or 17. The two-input AND circuit 265:1 receives inputs from the inverter 177 and from the input terminal 15-2. The output of AND circuit 265:1 is therefore Up when the decimal sum is either 2, 3, 6 or 7. The three-input AND circuit 266:1 receives inputs from the inverter 261, input terminal 15-4, and input terminal 15-8. The output of AND circuit 266:1 is therefore Up only when all three of its inputs are Up or when the decimal sum is either 12 or 13. The three-input OR circuit 267 having its output connected to output terminal 20-4 receives its inputs from the AND circuits 262a, 265:1 and 266:1 and provides an output when the outputs of any one or more of those AND circuits is in the Up condition or when the decimal sum is either 2, 3, 6, 7, 12, 13, 16 or 17.

Referring more particularly to Figs. 9, 9a, 9b and 9c, there is shown a complete circuit diagram of the binary adders shown in Fig. l. This diagram is realized when Fig. 9:1 is placed to the left of Fig. 9, Fig. 9b to the left of Fig. 9a and Fig. 9c `to the left of Fig. 9b. t

The binary adder for the 1 bit is shown in Fig. 9. OR' circuit 270 includes diode rectiers 271 and 272having their cathodes commonly connected through a pull down resistor 273 to the volt line 130. OR circuits 274 and 275 are similar to OR circuit 270. Input terminal 13 is commonly connected -fto 'the plates of rectiiers 271 and 272 of OR circuits 270 and 275 respectively. Input terminal 14 is connected to the plates of rectiers 272 and 271 of the OR circuits 270 and 274 respectively and input terminal 17 is connected to the plates of rectiers 272 and 271 of OR circuits 274 and 275 respectively. AND circuit 277:1 comprises the rectifiers 278, 279 and 280 having their plates commonly connected through a pull up resistor 281 and decoupling resistor 282 to the +150 volt line 105. The cathodes of rectiiiers 278, 279 and 280 are connected to the commonly connected cath# odes of the rectiiiers of OR circuits 270, 274 and 275 respectively. It is seen from inspection ol the OR circuits 270, 274 and 275 that all of these commonly connected cathodes are Up when either -two or three of the input terminals 13, 14 and 17 are Up. Hence, when two orl three of inputs 13, 14 and 17 are Up the commonly connected plates of the rectiiers 278, 279 and 280 of AND circuit 277:1 are Up andthe control grid of tube 283 con. nected thereto through parasitic suppressor resistor 284 is Up. The plate of tube 283 is connected to the +150 volt line 105 through resistor 282 and its cathode is connected through dropping resistor 119 and load resistor 285 to the 150 volt line 130. 'i The terminal16-1 lcon-- nected to the juncture of the resistors '119 and 285 is therefore Up when either two or three inputs are applied to the input Iterminals 13, 14 and 17. This juncture is also connected through limiting resis-tor 287 to the control grid of inverter tube 288L having its cathode grounded and Vits plate connected through load resistor 288 and decoupling resistor 282 to the +150 volt line 105. The plate of tube 288L is connected through resistor 289 and frequency compensating capacitor 290, in parallel, and parasitic ysuppressor resistor 284 to the control grid of cathode follower tube 288R. The resistors 289 and 291 connected between the plate of ltube 288L and the -150 Volt line l1'30 ycomprise a voltage divider for biasing the control grid of cathode follower tube ZSSR. The cathode of tube 288Ris connected through load resistor 292 to the -V--150 v olt line 130. The control grid of inverter tube 288L is Up when either two or three inputs are appliedwto :the input terminals 13, 14 and 17. The plate of tube 288L is therefore Up whenV one or no inputs are applied. Accordingly, the control grid and cathode of cathode follower tube 288K is Up when one input orno input is applied to the input terminals 13, 14 and 17 QR circuit 153 is connected to input terminals 13, 14 'and 517 sothat its output connected to the cathode of diode rectifier 1540i AND circuit 159a is Up when either one, two or three inputs are applied :to the input terminals. The cathode of cathode follower tube ZSSR is connected to the cathode of rectifier I158 of AND circuit 159a which is-Up when either one input or no input is applied to the input terminals. The control grid of tube295L connected to the Youtput of AND circuit 159a is therefore Up only when one input is applied to the input terminals. The cathodes of the three d-iode rectiers of AND circuit `145a are each connected -to a different one of the input terminals. The control grid of tube 295K connected to receive the output of AND circuit 145a is therefore Up only when 'three inputs are applied to the input terminals.

' The plates of tubes 295K and 295L are commonly connected through decoupling resistor 282 to the +150 volt line 105 and to ground throughl condenser .297. The cathodes ,of tubes 295R and 29SL are commonly connected through dropping resistor 119 and load resistor 298 to the 150 volt line 130. Since the cathodes of the cathode follower tubes 295R4 and 29SL are commonly connected, it is seen that they collectively serve as a twoinput QR circuit. The control grid of the tube 295R is Up -only when three inputsarepapplied `to the input terminalsand the control grid of the tube 295L'is Up only when one input is applied to the input terminal. The output terminal 15- 1 is therefore Up only when one or threerinputs-are applied to the input terminals 13, 14 and 17.

, Referring to Fig. 9a the tubes 295L, 295R and 288K and the circuitry associated therewith are identical with that shown for the 1 bit adder in Fig. 9. The output terminal 15-2 is therefore Up when one or three inputs are -applied to the input terminals 13, 14 and 17. The tubes 300L, 300R and 301 and the circuitry associated therewithare provided to reestablish the Up and Down voltage levels and are commonly referred to as a carry shaping circuit. The cathodes of tubes 300L and 300R are commonly connected through load resistor 302 to the 150 volt line 130 and each of their anodes are connected through a resistor 303 and peaking inductance 304 toV decoupling resistor 282 connected to the +150 volt line 105. Resistors 306 and 307 connected between the -150 volt line 130 and ground comprise a voltage divider,` The juncture of these resistors is connected through the suppressor resistor 284 to the control grid of'tube 300L. By-pass condenser 308 is connected in parallelwith the resistor 307. The voltage divider causes the control grid of the tube 300L to be held by a fixed bias such Athat the tube is normally plate current con-' ductive; AThe plate of tube 300Lis connected through resistor 309 and capacitor 310v in parallel to the parasitic suppressor resistor 284 connected to the control grid of the tube 301. Resistor 311 connected between resistor 309 and they 150 volt line 130 in conjunction with the resistors 309, 30'3 and 282 comprise a voltage divider which determines the bias applied tothe control grid of the tube 301. The cathode of tube 301 is connected to the carry output terminal 16-2 and through a resistor 312 to the -150 volt line 130.

The control grid yof ther tube 300R is Down when no input or one input is applied tothe terminals 13, 14V

and 17 and its plate Vis therefore Up. When either two or three inputs are applied to the input terminals 13, 14 and 17 the OR circuits 270, 274 and 275 are all operative to cause the AND circuit 277a to become operative thereby causing the voltage at the control grid of tube 300K togo Up. The plate of tube 300R is therefore Down when either two or three inputs are applied to the terminals 13, 14 and 17 and is Up when no input is applied `and when one input is applied. The control grid of tube 2.88K connected thereto through a voltage divider consisting of resistors 289 and 291 and its cathode are also Up when no input is applied or when one input is applied. The` output terminal 152 therefore is Up when either one or three inputs are applied to therinput terminals 13, 14 and 17.

When either two or three inputs are applied to the input terminals 13, 14 and 17, the cathode of tube 300R and the cathode of tube 300L connected thereto go Up.

The voltage 'rise at the cathode of tube 300L isV suf-y cient to cause the voltage at the control grid of tube 300L to be negative with respect to the voltage at the cathode. As a result the tube 300L becomes non-conductive, i.e. no current ilows in its plate circuit. The

plate of tube 300L therefore goes Up when either twoV or three inputs are appliedto the input terminals 13, V14.I

and 17. The control grid and cathode of cathode follower tube 301 accordingly larerUp when either two or three inputs are -applied to the input terminals 13, 14 and 17 and are Down when one input is applied or when no input is applied. When thercontrol Agrid of tube 300K again goes Down, the commonly connected cathodes of tubes 30011` and 300L go Down and the voltage differenceV between the cathode and the ycontrol grid of thertube` Referring to YFig. 9c, the 8 `bit binary adder includes OR circuits k270, v274 and 275v `and AND circuit 277a functioning to place the control grid and the cathode of the tube 315L in the Up condition when either `two or three inputs are applied to the input terminals 13, 14 and 17. The 8 bit binary adderis electrically identical to the l bit adder of Pig. 9, except that the AND circuit a and its associated cathode follower 295R of Fig. 9 are omitted. This omission is permissible because three inputs will neverbe Up in any legitimate addition of two numbers in the binary-decimal system. The cathode of tube 315L is connected through load resistor 316 to the Volt line 130 and through limiting resistor'287 to the control grid of tube 315R having its cathodegrounded and its plate connected through load resistor 317 and decoupling resistor 282 to the +150Vvolt line 105. When the cathode oftube 315L goes Up the control Ygrid of tube 315R connected thereto goes Up and the plate of tube 315R goesDown. Hence, the control grid of the tube 320L is Up forone input and no input. The cathode ofr tubej320L`is connectedthrough aresistor :321 to

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