US2409689A - Electronic computing device - Google Patents

Description

Ogt. 22, 1946. a. A. MORTON EI'AL 2,409,689

ELECTRONIC COIIPUTING DEVICE Filed NOV; 2, 1942 V 2 Sheets-Sheet 2 o a v q a V ZSnventor: r fieoasa-flmok'ron Le/ue E. Fboqg R 1., E my M Patented Oct. 22, 1946 ELECTRONIC COMPUTING DEVICE George A. Morton, Haddon Heights, and Leslie E.

Flory, oaiflyn, N. 1., asaig-nors to Radio Corporation of America, a corporation of Delaware Application November 2, 1942, Serial No. 464,292

8 Claims. 1

This invention relates generally to electronic computers and particularly to electronic apparatus for counting voltage pulses and for adding, subtracting, or multiplying quantities represented by groups oi such pulses.

The basic circuit utilized in adapting the invention herein to the various circuits to be described in the well known "trigger" circuit of the general type described in Theory and Application oi! Vacuum Tubes, by Herbal; J. Reich. In one of its simplest forms, this trigger circuit includes two triodes in which the grid of the first triode is coupled to the anode of the sec-- ond triode through a network comprising a parallel connected resistor and capacitor, and the grid of the second triode is similarly coupled to the anode oi the first triode through a, similar coupling network. The cathodes of both triodes are groimded, either directly, or through suitable cathode resistors. Grid and anode potentials are applied to the respective electrodes through separate resistors. If desired, a gaseous discharge tube may be connected across one of the anode resistors to indicate circuit operation.

In operation, it a negative voltage is applied to the grid of the first triode, the anode current of the triode will be reduced, and theanode potential will become more positive. Due to the connection through the coupling resistor, the grid potential of the second triode will become more positive, causing an increase in the anode current of the secondtriode, with a resultant decrease in the second triode anode potential. This decrease in anode potential will, in turn, cause the grid potential of the first triode to become more negative. This action will continue until the anode current of the first triode is cut off. The first triode will remain cut off, and the second triode will remain conducting, until a positive potential is applied to the grid of the first triode or until a negative potential is applied to the grid of the second triode. In either latter instance, the tube operating conditions will be reversed and the first triode will become conducting and the anode current of the second triode will be cut oil.

One or the features of the instant invention is the utilization of such trigger circuits in cascade arrangement, whereby a predetermined change in the polarization or activization of one triode of the. trigger circuit will generate a, pulse 'to trigger or activate a succeeding trigger circuit in the cascade arrangement. As many trigger circuits as desired may be connected in cascade. The instant invention is an improvement of our copending U. 8. application, Serial No. 464,293, filed November 2, 1942, which describes a cascade trigger circuit arrangement for counting voltage pulses to derive the binary sum, or difference, of successive series of pulses. The instant invention, however, is adapted to counting voltage pulses and indicating the product of two groups of pulses as a binary number.

The binary system of computation is particularly suited to electronic computers since a complete binary term of a binary number may be expressed in terms of the conducting or cut-oft condition of the anode circuit of a conventional vacuum tube. A saving in the number of tubes required for a given number is also possible in a ratio of 3 to 1 over the scale of 10 system. More complete discussions of the binary and similar systems 0! computation may be round in "Elementary Number Theory" by Uspenski and Heaslet, Mathematical Excursions" by H. A.

Merrill, and A Mathematician Explains" by M.

I. Logston.

In order to operate a counter utilizing the binary system, it is necessary to adapt the conventional trigger circuit described heretofore to effect a reversal in polarization or activization by succeeding applied pulses oi! a similar nature. The circuits to be described hereinafter are adapted to this purpose by applying in a symmetrical manner negative operating pulses to the anode circuits of the trigger tubes.

Among the objects of the invention are to provide an improved means for counting voltage pulses. Another object of the invention is to provide improved means for utilizing conventional trigger circuits in a novel cascade arrangement for deriving the product of the numbers of pulses in successive series of voltage pulses. Still another obiect is to provide an improved means for connecting conventional trigger-circuits in cascade arrangement to provide a continuous counter. A further object is to provide improved means for clearing the counter after each operation thereof, for conditioning the circuit for counting succeeding applied pulses. Another ob- Ject is to provide an improved means for deriving the sum of two or more binary numbers which are successively applied to the circuit as groups of potentials. A further object is to provide an improved means for deriving the diil'erence between two binary numbers. Another obiect is to provide an improved means for deriving the binary product of two series of pulses applied to a thermionic tube trigger circuit. Still another object is to provide an improved means for deriving the binary product of the number of pulses in succeeding series of voltage pulses applied to one or more groups of cascaded trigger circuits, wherein the multiplicand is applied as a binary number to an electronic counter and is added to itself a number of times which is equal to the multiplier.

The invention will be described by reference to the accompanying drawings of which Fig. l is a schematic circuit diagram of a binary counter, Fig. 2 is a block circuit diagram of the invention, and Fig. 3 is a schematic circuit diagram of a preferred embodiment of a typical portion of Fig. 2. Similar reference characters indicate similar elements in the drawings.

Referring to the drawings, Figure 1 comprises a trigger circuit of the type described heretofore. The grid al of a first triode I is connected to the anode p2 of a second triode 2 through a network comprising the parallel connected resistor rI and capacitor cI. The anode pl of the first triode I is connected to the grid 02 of the second triode 2 through a second network comprising the parallel connected resistor 12 and capacitor c2. The cathodes of the first and second triodes I, 2 are grounded through suitable resistors. A source of negative bias potentialis connected to the grid III of the first tube I through a grid resistor r3, and to the grid 02 of the second triode 2 through a second grid resistor 14. Anode potential is applied to the anode pl of the first tube I through an anode coupling resistor 1'8, and to the anode p2 of the second tube 2 through a second anode coupling resistor rQ; A gaseous indicator tube 3. which may be a conventional neon tube, is connected across the second anode resistor 16 to indicate when the current exceeds a predetermined value, which depends upo the. anode current flowing in the second tube 2. A choking resistor H is connected in series with the positive anode power supply lead to the common terminals of the anode resistors r! and r8. Negative input control pulses 4 are applied'to the input terminals B. 5, which are connected between ground and through an input coupling capacitor c3, to .i

the common terminal of the anode resistors 15 and r6.

In operation, if it is assumed that the first tube I initially is drawing anode current, the second tube 2 will be biased ed. A negative pulse 4, ap-' plied to the input terminals 5, will appear on the anode p2 of the tube 2 and on the grid gl of the first tube I which will in turn reduce the anode current in the first tube I. This, in turn, will make the potential on the anode pl of the first tube I more positive, and degenerate simultaneously any of the original negative pulse applied at pl. A positive pulse will be applied to the grid 2 of the tube 2 causing the tube 2 to become conducting. This efiect will increase and continue, because of the difference in the potential charges on the capacitors cl and 02, until the first tube I is cut oil, and the second tube 2 becomes completely conducting. A subsequent negative pulse applied to the input terminals 5 will cause the stable conditions of the trigger tubes I, 2 to be reversed since the circuit is compietely symmetrical.

The indicator tube 3 will be illuminated when the second tube 2 is conducting, since only under this condition is there an appreciable voltage drop across the anode coupling resistor r6. If it is assumed that the conducting condition of the first tube pl represents 'zero, and the conducting condition of the second tube 2 represents the result is a binary counter in which zero is indicated on the indicator tube 3 when the tube is extinguished, and 1 is indicated when the tube is illuminated. The second pulse applied to the input terminals 5 will cut oil the second trigger tube 2 and cause the first tube I to again become conducting. In order to indicate that two pulses have occurred instead of none, it is essential that a carryover system, corresponding to the carryover in arithmetic, be employed which will provide a second indication representative of the second term of the binary total.

It will be seen that the circuit of Fig. 1 employs two identical trigger circuits I and II connected in a novel cascade arrangement whereby two terms of a binary number may be indicated. As illustrated, the circuit comprises two trigger circuits of the general type described heretofore, but it should be understood that as many such circuits as required for the multiplicand may be connected in cascade arrangement in a similar manner. The first and second trigger tubes I and 2, and the first indicator tube 3 correspond to the first term of the binary number. The third and fourth trigger tubes II and I2 and the second indicator tube I3 correspond to the second term of the binary number. The connection I8 from the anode M2 is provided for coupling to succeeding trigger circuits of similar types. The grid of a transfer tube 8 is connected to the anode p2 of the second trigger tube 2 through a second coupling capacitor 05. The anode of the transfer tube 8 is connected to the common terminal of the anode resistors H 5, rl 6 and H 1 of the second trigger circuit comprising the tubes II and I2. The grids of the 'second and fourth trigger tubes 2 and I2 are connected respectively through suitable choking resistors rIII and to a fixed contact of a reset switch sI. The movable contact of the reset switch sI is connected to a suitable negative terminal of a potential source 9 to provide cut-oil grid bias for the tubes 2 and I2 when the switch is closed. The positive terminal of the bias potential source is grounded.

In operation, if the reset switch sI is open, the first trigger tube I is assumed to be conducting and the second trigger tube 2 to be cut oil, the first negative pulse applied to the input terminals 5 will reverse the stable conditions of the trig er tubes causing the second tube 2 to become conducting and illuminating the first indicator tube 3. The second pulse applied to the input terminals 5 will again reverse the stable conditions of the tubes I and 2 and the indicator tube 3 will be extinguished. When the second trigger tube 2 becomes non-conducting upon the application of the second input pulse to the input terminals 5, the potential upon the anode p2 thereof becomes more positive which, in turn, applies a positive pulse to the grid of the second transfer tube 8, which is biased normally to anode current cut oil condition. Due to normal phase inversion in the transfer tube 8, a negative pulse will be derived from the anode thereof and applied to the second trigger circuit comprising the third and fourth tubes II and I2, causing the stable condition of the second trigger circuit II to be reversed. It will therefore be understood that the first pulse applied to the circuit will cause the first indicator tube 3 to be illuminated. The second pulse applied to the circuit will cause the first indicator tube 3 to be extinguished, and cause the second indicator tube I3 to be illuminated. A third pulse applied to the circuit Will cause the first indicator tube 3 to be illuminated in addition to the second indicator tube l3.

Figure 2 comprises a block diagram of an electronic multiplying system wherein a multiplicand is set up as a binary number on a series of cascaded trigger circuits 1, II, III, IV, and V of the general type described heretofore. The binary multiplicand is then transferred to a second binary counter, including a second series of cascaded trigger circuits XI, 2H1, XIII, XIV, XV, and XVI, upon which the binary product is derived. The circuits to be described hereinafter accomplish both the direct transfer of the muitiplicand to the product counter and the carryover operation required as each element product counter changes from one to zero in the binary system. Each of the trigger circuits 1, II, III, IV, V of the multiplicand counter is connected to a corresponding transfer amplifier 30, 3|, 32, 33, 34, respectively, in such a manner that when the counter trigger circuit is in the binary zero condition, the amplifier tube is inoperative, and

when the counter is in the binary 1 condition, the corresponding amplifier is biased to the anode current cutoff condition. Negative pulses 4 are applied to the multiplicand binary counter to establish the multiplicand as a binary quantity.

Pulses l4, the number of which correspond to the value of the multiplier, are derived from a multiplier pulse source I4 and applied to the terminal 6, which is connected to the respective grid circuits of the transfer amplifiers 3|, 32, 33 and 34. The pulses l4 may be derived in any known manner, such as a telephone dial or other sequential contactor which is connected to interrupt a source of potential. The multiplier pulses l4 will therefore be transmitted by only the transfer amplifiers which are connected to the corresponding multiplicand trigger circuits which are in the binary 1 condition. The pulses transmitted by the-respective transfer amplifiers are next applied to separate differentiating circuits 40, 4|, 42 43 and 44, respectively, from which are derived a positive pulse 45 and a negative pulse 46, separated by the width of the multiplier pulses l4. These pulses are next applied directly to the product binary counter comprising the trigger circuits XI, XII, XIII, XIV, and XV, respectively. The positive pulse 45 is utilized to accomplish the carryover operation between successive product counter trigger circuits whenever it is applied to one of the trigger circuits which is in the binary 1 condition. The negative pulse 46 is utilized to trigger the corresponding product binary trigger circuit to the next binary number.

Both negative and positive pulses 46 and 45, re-

spectively, are applied to the input of a second group of transfer amplifiers 50, 5|, 52, 53, and 54, respectively, which are connected to the corresponding product trigger circuits. The second transfer amplifiers are so connected that they are inoper \tive when the corresponding product trigger circuit is in the binary zero condition, and are just cut off when the corresponding trigger circuit is in the binary 1 condition. The outputs of the second transfer amplifiers are connected by the leads n to trigger the next succeeding trigger circuits of the product counter. It

will therefore be seen that if the first product trigger circuit XI is in the binary 1 condition, the transfer amplifier 50 will be just cutoff. The positive pulse 45 applied to the input of the transfer amplifier will, therefore, provide a negative pulse in the lead n to the second product trigger circuit XII. The negative pulse 46, which immediately follows the positive pulse 45, will then trigger the first product trigger circuit XI to the binary zero condition by means of the directly transmitted pulse over the connection k.

A condition may arise, for example, where successive carryover pulses are applied to successive circuits in which no positive or negative pulses 45, 46 exist due to the fact that the corresponding term in the multiplicand is binary zero, and the corresponding product trigger circuit is initially also in the binary zero condition. The first pulse on the line 11., connecting, for example, the transfer amplifier 5|! to the trigger circuit XII of the product counter will change the trigger circuit XII from the binary zero to the binary 1 condition, which will activate the corresponding transfer amplifier 5|. A succeeding, or a coinciding, carryover pulse on the line n is applied to a transformer TI to apply a second positive pulse to the transfer amplifier 5| over the line m. The coincidence of the positive pulse throughthe transformer TI and the control voltage from the second trigger circuit XII will therefore make the second transfer amplifier 5| conducting, and provide a negative pulse in its anode circuit which will be applied to trigger the next succeeding product trigger circuit XIII. Likewise, the coincidence of a pulse on the line n with a pulse on the line from the corresponding differentiating circuit, will provide a, carryover pulse to the next succeeding product trigger circuit, even .though the transfer amplifier is initially inactive.

As many trigger circuits as desired may be utilized in the multiplicand counter. As explained heretofore in Figure l, the successive trigger circuits are connected together by transfer amplifiers 8, I8, 28 and 38, respectively, for accomplishing the carryover operation incident to setting up the multiplicand. The number of trigger circuits required in the product counter will be one more than the sum of the number of binary terms in the multiplicand and multiplier, respectively. Indicator lamps L may be connected in the anode circuits of the individual trigger circuits of the product counter in the same manner as described heretofore in Figure 1 for the individual trigger circuits of the multiplicand counter. Likewise, the anode circuits of the product counter may be connected to apply the binary product directly to other utilization circuits. The product trigger circuits, with their associated carryovertransfer amplifiers and coupling circuits, comprise a product accumulator.

Figure 3 indicates the apparatus required for two binary terms in the multiplicand. The multiplicand counter comprises the trigger circuits I and II and the carryover transfer tube 8. The multiplicand is applied to the counter through one'or both of the input terminals 5, 5', depending upon the nature of the multiplicand source. For example, if the multiplicand is in the form of a plurality of pulses corresponding in number to the numerical value thereof, the pulses are all applied to the input terminal 5, and accumulated on the counter as a binary number. If the multiplicand is already in the form of a plurality of separate voltages corresponding in magnitude and arrangement with the binary value thereof, the separate voltages are applied to the separate corresponding input terminals 5, 5', etc. to transfer the binary multiplicand directly to the corresponding multiplicand counter elements. The product counter comprises the trigger circuits XI, XII which have a different type of carryover transfer tube II, the circuit of which will be described hereinafter. A second product carryover transfer tube II is shown for the application of carryover pulses to the next succeeding product trigger circuit, not shown.

The grid of the transfer tube 3| is connected larly connected" through a second differentiating circuit comprising the capacitor I and the resistor I! to the cathode of a diode rectifier II. The anode of the diode rectifier tube I is connected through a coupling capacitor III to the common terminal of the anode circults-of the tubes of the product trigger circuit XI. A control potential is derived from the cathode of the first trigger tube 2| of the'pr'oduct trigger circuit XI, and applied to the control electrode of the carryover transfer tube I through voltage dividers l1 and I4, whereby the normally high negative bias applied to the grid of the tube I is reduced to approximately cut-off when the product trigger circuit Xi. is in the binary 1 condition.

The second multiplicand trig er circuit 11 is similarly connected through a transfer tube II to a carryover transfer tube i and a diode 0 I and then to the second product trigger circuit XII. In order to accomplish the carryover operation in the product counter, a connection is made, through the coupling capacitor 12, between the second cathode of the second diode rectifier ti, and the anode of the first carryover transfer tube ll. The primary winding of the transformer TI is connected in series with the anode circuit of the first carryover transfer tube Ill. The secondary winding of the transformer TI is connected in any suitable manner to apply a positive pulse to the control electrode of the second carryover transfer tube Ii when coincidental carryover pulses occur. The functions of the diodes are to prevent reaction on preceding trigger circuits due to pulses in subsequent binary term trigger circuits.

All counters may be cleared after each multiplying operation is completed by applying a high negative bias simultaneously to all binary 1 tubes in the manner which is described in referring to Fig. 1.

The circuit may also be utilized for deriving directly the sum of two binary numbers. The first number is applied as a group of potentials representative of a binary number to the multiplicand counter. A single multiplying pulse is then applied to transfer the number to the product or final counter. The multiplicand counter is then cleared. The second number is then applied to the multiplicand counter, and a second multiplying pulse is applied to transfer it to the final counter. The two numbers are then added directly in the final counter. If the multiplicand counter is again cleared, the process may be repeated, and the sum of any desired number of binary numbers obtained. By modifying the carryover circuit in accordance with thedisclosure in the copending application, referred to heretofore, the difference of two binary 8 numbers may also be obtained in a similar manner.

Thus the invention described comprises an electronic multiplying device in which the multiplicand is applied to a cascaded binary counter and transferred to a second or product binary counter, in which the first binary indications are multiplied a number of times corresponding to the value of the multiplier. Provision has been made in both counters to accomplish binary carryover operations where required, and to segregate the carryover operation from the direct application of the multiplicand 'to the product counter. I

We claim as our invention:

1. A binary multiplying device including a plurality of cascaded trigger circuits, means for polarizing said trigger circuits to represent a binary multiplicand, a source of pulses the number of which is representative of a multiplier, a plurality of blocking amplifiers, means responsive to predetermined polarization of said trigger circuits for unblocking predetermined ones of said amplifiers, means for applying said pulses to all of said amplifiers, means for differentiating the pulses derived from said unblocked amplifiers, a plurality of cascaded second trigger circuits, a plurality of transfer blocking amplifiers, means responsive to the polarization of each of said second trigger circuits for unblocking selectively a different one of said transfer amplifiers, means for applying said differentiated pulses to vary the polarization of said second trigger circuits to transfer said multiplicand thereto for each of said multiplier pulses, and means for applying said differentiated pulses to trigger said second trigger circuits in response to said selective unblocking of said transfer amplifiers for providing carryover binary numbers.

2. A binary multiplying device for two quantitles including a first binary counter circuit having a plurality of trigger circuits, means for applying one of said quantities to said counter as a multiplicand, a second binary counter circuit having a plurality of trigger circuits, a plurality of blocking amplifiers, means interposing one of said amplifiers between corresponding trigger circuits of said first and said second counters, means including said first counter for unblocking said amplifiers for transferring said multiplicand to said second counter, means for applying pulses to said transferring means for repeating said transfer a number of times corresponding to said other quantity as a multiplier, and means for deriving from said second counter voltages characteristic of the binary sum of said repeated multiplicands.

3. A binary muitiplylnz device for two quantities including a first binary counter circuit having a plurality of trigger circuits, means for applying one of said quantities to said counter as a multiplicand, a second binary counter circuit having a plurality of trigger circuits, a plurality of blocking amplifiers, means interposing one of said amplifiers between corresponding trigger circuits of said first and said second counters, means including said first counter for unblocking said amplifiers for transferring said multiplicand to said second counter, means for applying pulses to said transferring means for repeating said transfer a number of times corresponding to said other quantity as a multiplier, a plurality of transfer amplifiers, means interposing one of said transfer amplifiers between successive trigger circuits of said second counter and between said second counter and said blocking amplifiers, means including said transfer amplifiers responsive to predetermined polarization of each of said trigger circuits of said second counter for changing the polarization of succeeding trigger circuits of said second counter, and means for deriving from said second counter voltages characteristic of the binary sum of said repeated multiplicands.

4. An electronic computer including a group of electronic tubes connected in pairs to form trigger circuits, means for applying to said circuits different polarizing potentials corresponding to a number, a second group of electronic tubes connected in pairs to form trigger circuits, means connecting said first and said second groups for deriving output potentials in response to said applied potentials, and means for applying pulses to said connecting means for deriving additional output potentials a number of times corresponding to a second number to derive on said second group voltages characteristic of the product of said first and second numbers.

5. An electronic computer including a group of electronic tubes, means for applying to said tubes potentials corresponding to a number to vary the current conditions in said tubes, a second group of electronic tubes, means connecting said first and said second groups for deriving output currents in response to said applied potentials, a number of times corresponding to a second numher to derive on said second group the product of said'numbers in terms of the current conditions in said tubes of said second group.

6. The combination of first and second groups of electron discharge units, means for establishing in said first group potentials representative of one number, means for applying pulses representative of another number, means for trans- 10 mitting said potentials once for each of said pulses, means for differentiating said transmitted potentials to derive positive and negative half cycles from each of said potentials, and means for transmitting said negative half cycles to said second group.

7. The combination of first and second groups of electron discharge units, means for establishing in said first group potentials representative of one number, means for applying pulses representative of another number, means for transmitting said potentials once for each of said pulses, means for differentiating said transmitted potentials to derive positive and negative half cycles from each of said potentials, means for transmitting said negative half cycles to said second group, and means for transmitting potentials dependent on said positive half cycles to said second group when the unitsv of said second group are in a predetermined condition.

8; The combination of first and second groups of electron discharge units, means for establishing in said first group potentials representative oi one number, means for applying pulses representative of another number, means for transmitting said potentials once for each of said pulses, means for differentiating said transmitted potentials to derive positive and negative half cycles from each of said potentials, means for transmitting said negative half cycles to said second group, and amplifying means controlled by the units of said second group so as to transmit potentials dependent on said positive half cycles to the units of said second group when the units of said second group are in a predetermined condition.

GEO. A. MORTON. LESLIE. E. FLOR-Y.

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