US20220352166A1 - Tie off device - Google Patents
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- US20220352166A1 US20220352166A1 US17/863,175 US202217863175A US2022352166A1 US 20220352166 A1 US20220352166 A1 US 20220352166A1 US 202217863175 A US202217863175 A US 202217863175A US 2022352166 A1 US2022352166 A1 US 2022352166A1
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- gate
- transistor
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- tie
- power rail
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- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11809—Microarchitecture
- H01L2027/11829—Isolation techniques
- H01L2027/11831—FET isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Definitions
- FIG. 9 is a block diagram illustrating another example semiconductor device in accordance with some embodiments.
- Multi-threshold voltage IC devices are sometimes used to optimize delay or power in various circuits and devices.
- a multi-threshold voltage IC device may include several different devices, each having a different threshold voltage (i.e., operating voltage).
- the multi-threshold voltage IC device may include two or more of a low threshold voltage (LVT) device, a standard threshold voltage (SVT) device and a high threshold voltage (HVT) device.
- LVT low threshold voltage
- SVT standard threshold voltage
- HVT high threshold voltage
- FIG. 2 is a block diagram illustrating an example interconnect metal layer structure 20 in accordance with some embodiments.
- the metal layer structure 20 includes a plurality of conductive layers M (e.g., M 1 , M 2 , M 3 , etc.). In the embodiment shown, the metal layer structure 20 illustrates only two layers (e.g., M 2 and M 3 ). Metal layer structures having different numbers of layers, e.g., from 1 to N layers, are within the scope of the disclosed embodiments.
- each metal bar MB has a width Wbar.
- all widths Wbar are of the same dimension, but the disclosed embodiments are not limited to such a configuration.
- the widths Wbar may be of different dimensions (e.g., one width Wbar may be shorter/larger than another one).
- Two adjacent metal bars MB are spaced or separated by a distance, e.g., distance D.
- the active area 110 is fabricated to have different VT characteristics by using channel and/or halo implantation optimization.
- a HVT device may be achieved by heavily implanting the device channel/halo pockets including ion implantation and a thermal anneal.
- FIG. 8 illustrates another example where the poly gate of the tie-off transistor connects to the power rail through one or more metal connectors.
- the device 104 shown in FIG. 8 includes the second (VSS) power rail 114 and has NMOS transistors.
- the active area or fin 111 extends in the X-axis direction, and the poly gates 120 contact the active area 111 and extend in the Y-axis direction.
- the plurality of poly gates 120 again includes five poly gates labeled 120 a - 120 e.
- the first NMOS transistor 131 in the first VT region 140 is formed by the first active area 111 and the first poly gate 120 a
- the second NMOS transistor 133 in the second VT region 142 is formed by the active area 111 and the second poly gate 120 b .
- the first NMOS transistor 131 has the first VT
- the second NMOS transistor 133 has the second VT different than the first VT as described above.
- FIG. 10 illustrates a device 106 that includes the first and second fins 110 , 111 that define the PMOS region 150 and the NMOS region 152 .
- the device 106 includes the first and second power rails 112 , 114 , which are the VDD and VSS power rails, respectively, in the illustrated example.
- the active areas or fins 110 and 111 extend in the X-axis direction.
- the plurality of poly gates 120 contact the active area 111 and extend in the Y-axis direction such that the poly gates 120 extend generally perpendicular to the active areas 110 , 111 .
- the device 106 has five poly gates 120 a - 120 e and is thus also a five CPP structure.
- the conductive via 126 connects the VDD rail 112 to the poly gate 120 a of the first NMOS transistor 131 . Therefore, the first NMOS transistor 131 is always on.
- the metal line 162 is connected to the VSS rail 114 by a conductive via 129
- the poly gate 120 b of the second NMOS transistor 133 is connected to the metal line 164 through the M 0 metal layer 160 .
- the second poly gate 120 b includes the cut poly 154 .
- the VSS voltage leaks to the drain side of the NMOS transistor 131 from its source.
- the “leaked” VSS voltage is so referred to as a “soft VSS” connection, which ties off the NMOS transistor 133 .
- the processes are realized as functions of a program stored in a non-transitory computer readable recording medium.
- a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like.
- the design house (or design team) 320 generates an IC design layout diagram 322 .
- the IC design layout diagram 322 includes various geometrical patterns, or IC layout diagrams designed for an IC device 360 , e.g., an IC device including one or more of the disclosed IC structures 100 - 106 , discussed above.
- the geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device 360 to be fabricated.
- the various layers combine to form various IC features.
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Abstract
An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.
Description
- This application is a division of U.S. patent application Ser. No. 16/879,166, filed May 20, 2020, which claims the benefit of U.S. Provisional Application No. 62/863,387, filed on Jun. 19, 2019, which are both incorporated by reference in their entirety.
- Vertical semiconductor devices, such as fin-based metal-oxide-semiconductor field-effect transistors (FinFET), are three-dimensional structures on the surface of a semiconductor substrate. Fins extend upwards from the body of the substrate, and may be formed by depositing fin material on the substrate, etching non-fin areas of the substrate, or a combination thereof. The channel of the FET is formed in this vertical fin, and a gate is provided over (e.g., wrapping) the fin. Wrapping the gate around the fin increases the contact area between the channel region and the gate and allows the gate to control the channel from both sides. As integrated circuit devices get smaller, spacing or “pitch” between devices may result in electromagnetic interference among adjacent devices.
- Adjacent devices, such as FinFETs, may be electrically isolated, where an adjacent transistor may be used as an isolation device. Such an isolation device may be referred to as a “tie-off” device in which the active area of the tie-off device is set to an off state. A gate of an isolation device (a “tie-off gate”) may be biased to place the isolation device in an OFF state and provide isolation for an adjacent active device.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. In addition, the drawings are illustrative as examples of embodiments of the invention and are not intended to be limiting.
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FIG. 1 is a block diagram illustrating an example of a semiconductor device in accordance with some embodiments. -
FIG. 2 is a block diagram illustrating example metal layers of the semiconductor device shown inFIG. 1 in accordance with some embodiments. -
FIG. 3 is a block diagram illustrating an example FinFET device in accordance with some embodiments. -
FIG. 4 is a block diagram illustrating an example semiconductor device in accordance with some embodiments. -
FIG. 5 is a block diagram illustrating another example semiconductor device in accordance with some embodiments. -
FIG. 6 is a block diagram illustrating a further example semiconductor device in accordance with some embodiments. -
FIG. 7 is a block diagram illustrating yet another example semiconductor device in accordance with some embodiments. -
FIG. 8 is a block diagram illustrating a further example semiconductor device in accordance with some embodiments. -
FIG. 9 is a block diagram illustrating another example semiconductor device in accordance with some embodiments. -
FIG. 10 is a block diagram illustrating another example semiconductor device in accordance with some embodiments. -
FIG. 11 is a flow diagram illustrating an example of a method in accordance with some embodiments. -
FIG. 12 is a block diagram illustrating aspects of an example of a of an electronic design automation (EDA) system in accordance with some embodiments. -
FIG. 13 is a block diagram illustrating aspects of an example of an IC manufacturing system and manufacturing flow in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Multi-threshold voltage IC devices are sometimes used to optimize delay or power in various circuits and devices. A multi-threshold voltage IC device may include several different devices, each having a different threshold voltage (i.e., operating voltage). For example, the multi-threshold voltage IC device may include two or more of a low threshold voltage (LVT) device, a standard threshold voltage (SVT) device and a high threshold voltage (HVT) device.
- Adjacent devices, including adjacent multi-threshold IC devices such as multi-threshold FinFETs, may be electrically isolated using one or more isolation devices. Such an isolation device may be referred to as a “tie-off” device. In some examples, a transistor is configured as an isolation device, where the active area of the tie-off device is set to an off state. A gate of an isolation device (a “tie-off gate”) may be biased to place the isolation device in an off state and provide isolation for an adjacent active device. For instance, a tie-off device may be situated at a threshold voltage (VT) boundary between devices.
- In accordance with some disclosed embodiments, a poly gate for a tie-off transistor is positioned at VT boundary of mixed VT structure. The transistor may be tied off by a conductive via connecting the poly gate to a power rail maintain the device in an off state. Positioning the poly gate at the VT boundary and directly connecting the poly gate to the power rail by the via may save device area.
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FIG. 1 is a block diagram illustrating a cross-section of anexample semiconductor structure 10 in accordance with some embodiments. Thestructure 10 is shown in the X-axis and Z-axis directions inFIG. 1 , while the Y-axis direction is orthogonal to the plane of the cross-section illustrated inFIG. 1 . Thestructure 10 includes abase layer 12 and aninterconnect layer 14. - Generally, the
base layer 12 includes a semiconductor substrate that, in turn, includes polysilicon regions (also termed “poly” throughout this disclosure), diffusion regions, semiconductor wells (e.g., N-wells, P-wells, deep N-wells, deep P-wells), etc., wherein semiconductor devices (e.g., transistors, diodes, etc.) are formed. Theinterconnect layer 14 includes N (e.g., an integer number of) conductive layers (e.g., metal layers M1 to MN) used for interconnecting devices within layers in interconnect layer 120 and for forming electrical connections to external devices, etc. Theinterconnect layer 14 generally includes vias, inter-level dielectric materials, passivation layers, bonding pads, packaging resources, etc. Each metal (e.g., conductive) layer M in theinterconnect layer 14 is commonly called metal one, metal two, metal three (M1, M2, M3, etc) layers, etc. Between the various metal layers M are dielectric materials (e.g., high-K, low-K material, etc.) 16 used to insulate the metal layers M. Thebase layer 12 andinterconnect layer 14 are often called a front-end structure and a backend structure, respectively, because they are the respective “front end of line” (FEOL) and “back end of line” (BEOL) in the semiconductor fabrication process. -
FIG. 2 is a block diagram illustrating an example interconnectmetal layer structure 20 in accordance with some embodiments. Themetal layer structure 20 includes a plurality of conductive layers M (e.g., M1, M2, M3, etc.). In the embodiment shown, themetal layer structure 20 illustrates only two layers (e.g., M2 and M3). Metal layer structures having different numbers of layers, e.g., from 1 to N layers, are within the scope of the disclosed embodiments. - In the embodiment shown in
FIG. 2 , each metal layer M includes a plurality of metal bars MB, for example, metal bars MB21, MB22, and MB23 in layer M2 and metal bars MB31, MB32, MB33 in layer M3. In some embodiments, the shape of the metal bars is cylindrical or some other shape, and can be any cross-sectional shape. In the embodiment shown, each of the metal bars MB in a layer M are substantially parallel to one another. In the embodiment shown, each metal layer M2 and M3 includes three metal bars MB, however, configurations having different numbers of metal bars MB per metal layer M are within the scope of the disclosed embodiments. In some embodiments, a first set of metal bars MB (e.g., metal bars MB in metal layers M1, M3, M5, etc.) run in a first direction (e.g., X-axis direction) while a second set of metal bars MB (e.g., in metal layers M2, M4, M6, etc.) run in a second direction (e.g., Y-axis direction) wherein the X-axis direction is perpendicular to the Y-axis direction. Different configurations wherein all bars MB run in one direction, e.g., X-axis direction, Y-axis direction, or any other convenient direction, or a combination of directions, including non-perpendicular directions, are within the scope of the disclosed embodiments. In the embodiment shown inFIG. 2 , each metal bar MB has a width Wbar. In some embodiments, all widths Wbar are of the same dimension, but the disclosed embodiments are not limited to such a configuration. Depending on design choices, the widths Wbar may be of different dimensions (e.g., one width Wbar may be shorter/larger than another one). Two adjacent metal bars MB are spaced or separated by a distance, e.g., distance D. In some embodiments, distances D are selected to meet the minimum requirements of spacing between two metal bars MB to form capacitance between those two bars. In some embodiments, all distances D in themetal layer structure 20 are of the same dimension, but the disclosed embodiments are not limited to such a configuration. That is, distances D may be of different dimensions (e.g., one distance D may be shorter/longer than another one). The thickness of a metal bar MB in a layer M is proportional to the layer M thickness, which can be process technology dependent, and different groups of layers M can have different thicknesses. For example, a first group of metal layers M (e.g., Mx) can have a first thickness, a second group of metal layer M (e.g., My) can have a second thickness, and a third group of metal layers (e.g., Mz) can have a third thickness, etc, wherein the first, the second, and the third thickness are different. In the embodiment shown, themetal layer structure 20 has a width W and a length L. -
FIG. 3 is a block diagram illustrating a cross-section of anexample semiconductor structure 30 in accordance with some embodiments. The embodiment shown includes a FEOL layer including semiconductor structures and a BEOL layer including interconnect metal layer structures. - In the embodiment shown, the FEOL layer includes a
FinFET transistor 32. TheFinFET transistor 32 includes asemiconductor substrate 34, afin 36, anisolation region 38, a polysilicon structure, e.g.poly 40, the conductive contacts S and D connected to the fin, and the conductive contact G connected to thepoly 40. In the embodiment shown, the conduction path for current is the fin 36 (the fin can also be referred to as an active area or region). The poly 40 functions as a gate allowing current flow in the fin from the S (e.g. source) contact to the D (e.g. drain) contact. In general, such a gate structure includes one or more conductive segments including one or more conductive materials such as the poly noted above. Other gate materials could include one or more metals, doped polysilicon, and/or other conductive materials. The conductive segments are thus configured to control a voltage provided to an underlying dielectric layer. In various embodiments, the gate dielectric layer includes, for example, one or more of silicon dioxide and/or a high-k dielectric material, e.g., a dielectric material having a k value higher than 3.8 or 7.0. In some embodiments, a high-k dielectric material includes aluminum oxide, hafnium oxide, lanthanum oxide, or another suitable material. For example, for a voltage potential between the S and D contacts, current can flow in the fin from S to D depending on a voltage applied to thepoly 40. If a voltage less than a threshold voltage (VT) is applied to thepoly 40, then appreciable current cannot flow in the fin from the S to the D contacts, and thetransistor 32 is “off.” If a voltage greater than or equal to the VT is applied to thepoly 40, appreciable current flows from S to D via the fin and thetransistor 32 is “on.” In some embodiments, the S, D, and G contacts form connections between multiple fins and polys in the FEOL layer, thereby connecting the sources, drains, and gates of one or more transistors. In some embodiments, the sources, drains, and gates of thetransistor 32 are connected to an interconnect metal layer structure in the BEOL layer. For example, the gate of thetransistor 32 may be connected to other structures by one or more of the metal bars in one of the layers of the interconnect metal structure in the BEOL layer, and the S/D contacts of thetransistor 32 may be similarly be connected to other structures using other ones of the metal bars in one or more of the metal layers in the BEOL layer. In some embodiments, the BEOL layer serves to connect thetransistor 32 to peripheral circuits. In the embodiment shown, the D, and G contacts connect to the metal bars in the BEOL layer using vias. For example, Vial forms a connection between the D contact to a metal bar in the first metal layer M1 above the FEOL layer. In the embodiment shown, a separate Vial connects the G contact to a conductive landing pad in the M1 layer, and Via2 connects the conductive landing pad to a metal bar in the M2 layer. -
FIG. 4 illustrates an example of anintegrated circuit device 100 in accordance with disclosed aspects. In general, thedevice 100 may include FinFET structures such as those shown inFIGS. 1-3 . Thedevice 100 shown inFIG. 4 includes afirst power rail 112, such as a VDD or VSS power rail. In the example ofFIG. 4 , thepower rail 112 is the VDD rail. A firstactive area 110 extends in the X-axis direction. In some examples, theactive area 110 include a fin such as thefin 36 shown inFIG. 3 . A plurality of poly gates 120 contact theactive area 110 and extend in the Y-axis direction. In other words, the poly gates 120 extend generally perpendicular to theactive area 110. In the example illustrated inFIG. 4 , the plurality of poly gates 120 includes five poly gates labeled 120 a-120 e. - A
first transistor 130 is formed by the firstactive area 110 and a first one of thepoly gates 120 a, and asecond transistor 132 is formed by the firstactive area 110 and a second one of thepoly gates 120 b. In the illustrated example, thefirst transistor 130 has a first VT, and thesecond transistor 132 has a second VT different than the first VT. Thedevice 100 thus includes a continuousactive area 110 that defines two different VT levels. In the illustrated embodiment, theactive area 110 includes afirst VT region 140 and asecond VT region 142. For example, the first and second VTs could be any of a standard VT (SVT), low VT (LVT), ultra low VT (uLVT), high VT (HVT), etc. Thus, for example, thefirst transistor 130 may have a standard VT (SVT) and thesecond transistor 132 may have a low VT (LVT). - Multiple VT devices may achieve a better power efficiency in some IC devices. In some examples, the
active area 110 is fabricated to have different VT characteristics by using channel and/or halo implantation optimization. For example, a HVT device may be achieved by heavily implanting the device channel/halo pockets including ion implantation and a thermal anneal. - A tie-
off transistor 134 is positioned between thefirst transistor 130 and thesecond transistor 134. The tie-off transistor 134 is formed by the firstactive area 110 and a third one of thepoly gates 120 c. Thethird poly gate 120 c of the tie-off transistor 134 is connected to thepower rail 112 maintain the tie-off transistor in an off state. The tie-off transistor 134 is configured to electrically isolate thefirst transistor 130 having the first VT from thesecond transistor 132 having the second TV. In the example illustrated inFIG. 1 , the first andsecond transistors off transistor 134 are PMOS transistors. The PMOS tie-off transistor 134 has itspoly gate 120 c connected to theVDD power rail 112 by a conductive via 122 to keep the tie-off transistor 134 off to electrically isolate thefirst transistor 130 from thesecond transistor 132. - In some examples, the tie-
off transistor 134 may be situated at the boundary of the first andsecond VT regions poly gate 120 c that connects the tie-off transistor 134 to theVDD rail 112 extends along the Y-axis direction directly over the VT boundary. Connecting the tie-off transistor to thepower rail 112 using thepoly gate 120 c saves area as compared to using a metal line for the tie-off device. - In the example of
FIG. 4 , thepoly gates fin 110 in a FinFET. Such poly segments are sometimes also referred to as a poly-on-OD-edge (PODE). The PODE helps to achieve better device performance and better poly profile control. - In some embodiments, the PODE structures are formed on the edge of the
device 100, and are used to protect the ends of thefin 110 during processing. That is, the PODE polysilicon structures are not electrically connected as gates for the transistors but are instead “dummy” structures, having no function in the circuit. The PODE structures cover and protect the ends of thefin 110, providing additional reliability during processing. - In general, the number of poly gates 120 in contact with the
fin 110 can be considered to be the “pitch,” often termed the “contacted poly pitch” or CPP, of the IC device along one dimension. The CPP may be at least partially determinative of the density of the IC device. By positioning thepoly gate 120 c of the tie-off transistor 134 directly over the VT region boundary, thepoly gate 120 c is “shared” by both the first andsecond VT regions second VT regions -
FIG. 5 illustrates another example integratedcircuit device 101 in accordance with disclosed aspects. Thedevice 101 shown inFIG. 5 is similar to thedevice 100 ofFIG. 4 , though thedevice 101 includes asecond power rail 114, which is the VSS power rail in the illustrated example, and rather than including PMOS transistors as in thedevice 100 ofFIG. 4 ,FIG. 5 discloses NMOS transistors. As with thedevice 100 disclosed above, thedevice 101 includes an active area orfin 111 that extends in the X-axis direction. The plurality of poly gates 120 contact theactive area 111 and extend in the Y-axis direction such that the poly gates 120 extend generally perpendicular to theactive area 111. The plurality of poly gates 120 illustrated inFIG. 5 are again labeled 120 a-120 e. In other words, thedevice 101 is also a five CPP structure. - A
first NMOS transistor 131 having the first VT is formed by theactive area 111 and thefirst poly gate 120 a, and asecond NMOS transistor 133 having the second VT is formed by theactive area 111 and thesecond poly gate 120 b. Thedevice 101 thus includes the continuousactive area 111 with thefirst VT region 140 and thesecond VT region 142. As noted above, the first and second VTs could be any of a standard VT (SVT), low VT (LVT), ultra low VT (uLVT), high VT (HVT), etc. - A tie-
off transistor 135 is positioned between thefirst NMOS transistor 131 and thesecond NMOS transistor 133. The tie-off transistor 135 is formed by theactive area 111 and thethird poly gate 120 c. In the example illustrated inFIG. 5 , the tie-off transistor 135 is an NMOS transistor with thepoly gate 120 c connected to theVSS power rail 114 by a conductive via 123 to keep the tie-off transistor 135 off to electrically isolate thefirst NMOS transistor 131 from thesecond NMOS transistor 133. The tie-off transistor 135 is situated at the boundary of the first andsecond VT regions -
FIG. 6 illustrates an embodiment of anintegrated circuit device 102 that includes both PMOS and NMOS transistors with tie-off transistors having poly gates coupled to the VDD and VSS power rails. As such, thedevice 102 includes the first andsecond fins PMOS region 150 andNMOS region 152. Thedevice 102 includes the first and second power rails 112,114, which are the VDD and VSS power rails, respectively, in the illustrated example. The active areas orfins active area 111 and extend in the Y-axis direction such that the poly gates 120 extend generally perpendicular to theactive areas device 102 has five poly gates 120 a-120 e and is thus also a five CPP structure. - The
PMOS region 150 includes thefirst PMOS transistor 130 formed by the firstactive area 110 and thefirst poly gate 120 a, and thesecond PMOS transistor 132 formed by the firstactive area 110 and thepoly gate 120 b. Thefirst NMOS transistor 131 is formed by theactive area 111 and thefirst poly gate 120 a, and thesecond NMOS transistor 133 is formed by theactive area 111 and thesecond poly gate 120 b. Thedevice 102 includes the continuousactive areas first VT region 140 and thesecond VT region 142. Accordingly, thefirst PMOS transistor 130 and thefirst NMOS transistor 131 have the first VT, while thesecond PMOS transistor 134 and thesecond NMOS transistor 135 have the second VT. As noted above, the first and second VTs could be any of a standard VT (SVT), low VT (LVT), ultra low VT (uLVT), high VT (HVT), etc. - The tie-
off transistors active areas third poly gate 120 c, and are positioned at the border of the first andsecond VT regions off transistor 134 is positioned between the first andsecond PMOS transistors off transistor 135 is positioned between the first andsecond NMOS transistors - In the example illustrated in
FIG. 6 , the tie-off transistor 134 is a PMOS transistor and the tie-off transistor 135 is an NMOS transistor. Thepoly gate 120 c connected to the VDD power rail by the conductive via 122 and to theVSS power rail 114 by the conductive via 123. The poly gate 120 is patterned or cut at aseparation 154 such that the upper portion of thepoly gate 120 c connects the PMOS tie-off transistor 134 to theVDD rail 112, but does not connect the gate of the PMOS tie-off transistor 134 to the VSS terminal. The lower portion of thepoly gate 120 c connects the NMOS tie-off transistor 135 to theVSS rail 114, but does not connect the gate of the NMOS tie-off transistor 135 to the VDD terminal. In other words, thepoly gate 120 c does not directly connect or short the VDD rail to the VSS rail. In this manner, both tie-off transistors second PMOS transistors second NMOS transistors - In the devices 100-102 shown in
FIGS. 4-6 , thepoly gates 120 c for each of the tie-off transistors conductive vias conductive vias poly gate 120 c to the respective power rails.FIG. 7 illustrates an example integratedcircuit device 103 in accordance with further embodiments, where the poly gate of the tie-off transistor connects to the power rail through one or more metal connectors. Thedevice 103 shown inFIG. 7 includes the first (VDD)power rail 112 and has PMOS transistors. The first active area orfin 110 extends in the X-axis direction, and the poly gates 120 contact theactive area 110 and extend in the Y-axis direction. In the example illustrated inFIG. 7 , the plurality of poly gates 120 again includes five poly gates labeled 120 a-120 e. - The
first PMOS transistor 130 in thefirst VT region 140 is formed by the firstactive area 110 and thefirst poly gate 120 a, and thesecond PMOS transistor 132 in thesecond VT region 142 is formed by the firstactive area 110 and thesecond poly gate 120 b. Thus, thefirst transistor 130 has the first VT, and thesecond transistor 132 has the second VT different than the first VT as described above. - The PMOS tie-
off transistor 134 is positioned between thefirst PMOS transistor 130 and thesecond PMOS transistor 132. The tie-off transistor 134 is formed by the firstactive area 110 and thepoly gate 120 c. Thepoly gate 120 c of the tie-off transistor 134 is connected to thepower rail 112 to maintain the tie-off transistor in an off state. More specifically, in the example shown inFIG. 7 a conductive via 124 connects thepoly gate 120 c to a metal conductor or metal bar in one of the metal layers 160 such as the MO metal layer. In the illustrated example, theM0 metal layer 160 extends in the X-axis direction. Themetal layer 160 is connected to a metal strip 162 (such as a metal deposit over the active area 110) by a conductive via 125, and themetal strip 162 connects to theVDD rail 112 by another conductive via 126. In the illustrated example, themetal strip 162 extends in the Y-axis direction. Thus, thepoly gate 120 c is connected to theVDD rail 112 by theM0 metal layer 160 and themetal strip 162 to maintain the tie-off transistor 134 in an off state for isolating thePMOS transistors -
FIG. 8 illustrates another example where the poly gate of the tie-off transistor connects to the power rail through one or more metal connectors. Thedevice 104 shown inFIG. 8 includes the second (VSS)power rail 114 and has NMOS transistors. The active area orfin 111 extends in the X-axis direction, and the poly gates 120 contact theactive area 111 and extend in the Y-axis direction. In the example illustrated inFIG. 8 , the plurality of poly gates 120 again includes five poly gates labeled 120 a-120 e. - The
first NMOS transistor 131 in thefirst VT region 140 is formed by the firstactive area 111 and thefirst poly gate 120 a, and thesecond NMOS transistor 133 in thesecond VT region 142 is formed by theactive area 111 and thesecond poly gate 120 b. Thus, thefirst NMOS transistor 131 has the first VT, and thesecond NMOS transistor 133 has the second VT different than the first VT as described above. - The NMOS tie-
off transistor 135 is positioned between thefirst NMOS transistor 131 and thesecond NMOS transistor 133. The tie-off transistor 135 is formed by theactive area 111 and thepoly gate 120 c, which is connected to theVSS power rail 114 to maintain the NMOS tie-off transistor 135 in an off state. More specifically, in the example shown inFIG. 8 a conductive via 124 connects thepoly gate 120 c to theM0 metal layer 160. Themetal layer 160 is connected to a metal strip 162 (such as a metal deposit over the active area 110) by a conductive via 125, and themetal strip 162 connects to theVSS rail 114 by a conductive via 127. Thus, thepoly gate 120 c is connected to theVSS rail 114 by theM0 metal layer 160 and themetal strip 162 to maintain the NMOS tie-off transistor 135 in an off state for isolating theNMOS transistors -
FIGS. 9 and 10 illustrate example devices that use a “soft” connection of tie-off transistors to the appropriate power rails. For instance,FIG. 9 illustrates adevice 105 that includes the first andsecond fins PMOS region 150 and theNMOS region 152. Thedevice 105 includes the first and second power rails 112,114, which are the VDD and VSS power rails, respectively, in the illustrated example. The active areas orfins active area 111 and extend in the Y-axis direction such that the poly gates 120 extend generally perpendicular to theactive areas device 105 has five poly gates 120 a-120 e and is thus also a five CPP structure. - The
PMOS region 150 includes thefirst PMOS transistor 130 formed by the firstactive area 110 and thefirst poly gate 120 a, and thesecond PMOS transistor 132 formed by the firstactive area 110 and thepoly gate 120 b. Thefirst NMOS transistor 131 is formed by theactive area 111 and thefirst poly gate 120 a, and thesecond NMOS transistor 133 is formed by theactive area 111 and thesecond poly gate 120 b. Thedevice 105 includes the continuousactive areas first VT region 140 and thesecond VT region 142. Accordingly, thefirst PMOS transistor 130 and thefirst NMOS transistor 131 have the first VT, while thesecond PMOS transistor 134 and thesecond NMOS transistor 135 have the second VT. As noted above, the first and second VTs could be any of a standard VT (SVT), low VT (LVT), ultra low VT (uLVT), high VT (HVT), etc. - In the embodiment of
FIG. 9 , the conductive via 127 connects theVSS rail 114 to thepoly gate 120 a of thefirst PMOS transistor 130. Therefore, thefirst PMOS transistor 130 is always on. Howevermetal line 162 MD is connected to VDD by a conductive via 128, and thepoly gate 120 b of thesecond PMOS transistor 132 is connected to themetal line 164 through theM0 metal layer 160. Thesecond poly gate 132 includes thecut poly 154. As such, the VDD voltage leaks to the drain side of thePMOS transistor 130 from its source. The “leaked” VDD voltage is so referred to as a “soft” VDD connection, which ties off thePMOS transistor 132. - Similarly,
FIG. 10 illustrates adevice 106 that includes the first andsecond fins PMOS region 150 and theNMOS region 152. Thedevice 106 includes the first and second power rails 112,114, which are the VDD and VSS power rails, respectively, in the illustrated example. The active areas orfins active area 111 and extend in the Y-axis direction such that the poly gates 120 extend generally perpendicular to theactive areas device 106 has five poly gates 120 a-120 e and is thus also a five CPP structure. - The
PMOS region 150 includes thefirst PMOS transistor 130 formed by the firstactive area 110 and thefirst poly gate 120 a, and thesecond PMOS transistor 132 formed by the firstactive area 110 and thepoly gate 120 b. Thefirst NMOS transistor 131 is formed by theactive area 111 and thefirst poly gate 120 a, and thesecond NMOS transistor 133 is formed by theactive area 111 and thesecond poly gate 120 b. Thedevice 106 includes the continuousactive areas first VT region 140 and thesecond VT region 142. Accordingly, thefirst PMOS transistor 130 and thefirst NMOS transistor 131 have the first VT, while thesecond PMOS transistor 134 and thesecond NMOS transistor 135 have the second VT. As noted above, the first and second VTs could be any of a standard VT (SVT), low VT (LVT), ultra low VT (uLVT), high VT (HVT), etc. - In the embodiment of
FIG. 10 , the conductive via 126 connects theVDD rail 112 to thepoly gate 120 a of thefirst NMOS transistor 131. Therefore, thefirst NMOS transistor 131 is always on. Themetal line 162 is connected to theVSS rail 114 by a conductive via 129, and thepoly gate 120 b of thesecond NMOS transistor 133 is connected to themetal line 164 through theM0 metal layer 160. Thesecond poly gate 120 b includes thecut poly 154. As such, the VSS voltage leaks to the drain side of theNMOS transistor 131 from its source. The “leaked” VSS voltage is so referred to as a “soft VSS” connection, which ties off theNMOS transistor 133. -
FIG. 11 illustrates a method in accordance with disclosed embodiments. The illustratedmethod 200 provides a tie-off device. More particularly, the method includes forming a first active area on a substrate atstep 210. The first active area, such as thefin 110, has afirst VT region 140 and asecond VT region 142. Atstep 212, afirst gate 120 a is formed that contacts thefirst VT region 140 of the first active area to form a first transistor having a first VT. In some examples, the first transistor may be a PMOS transistor such as thePMOS transistor 130, or an NMOS transistor such as theNMOS transistor 131 shown inFIGS. 4-10 . Asecond gate 120 b is formed atstep 214 that contacts thesecond VT region 142 of the firstactive area 110 to form a second transistor having a second VT that is different than the first VT. In some examples, the second transistor may be a PMOS transistor such as thePMOS transistor 132, or an NMOS transistor such as theNMOS transistor 133 shown inFIGS. 4-10 . Athird gate 120 c is formed atstep 216 to contact the firstactive area 110 between thefirst gate 120 a and thesecond gate 120 b to form a tie-off transistor positioned between the first transistor and the second transistor. In some examples, the tie-off transistor may be a PMOS transistor such as the PMOS tie-off transistor 134, or an NMOS tie-off transistor such as the NMOS tie-off transistor 135 shown inFIGS. 4-10 . Atstep 218, thethird gate 120 c is connected to a power rail, such as the VDD or VSS power rails, to maintain the tie-off transistor 134 in an off state and thus electrically isolating the first transistor from the second transistor. - In some embodiments, some or all of the
method 200 is executed by a processor of a computer. In some embodiments, some or all of themethod 200 is executed by aprocessor 302 of anEDA system 300, discussed below with respect toFIG. 12 . - Some or all of the operations of the
method 200 are capable of being performed as part of a design procedure performed in a design house, such as the design house 320 discussed below with respect toFIG. 13 . -
FIG. 12 is a block diagram of an electronic design automation (EDA) system 700, in accordance with some embodiments. In some embodiments, theEDA system 300 includes an automated place and route (APR) system. In some embodiments, theEDA system 300 is a general purpose computing device including aprocessor 302 and a non-transitory, computer-readable storage medium 304. The computer-readable storage medium 304, may be encoded with, for example, stores,computer program code 306, i.e., a set of executable instructions. Execution ofinstructions 306 by theprocessor 302 represents (at least in part) an EDA tool which implements a portion or all of, e.g., themethod 200 described above with respect toFIG. 11 (hereinafter, the noted processes and/or methods). Further,fabrication tools 303 may be included for layout and physical implementation of IC devices in accordance with methods disclosed herein such as themethod 200 ofFIG. 11 . - The
processor 302 is electrically coupled to the computer-readable storage medium 304 via abus 308. Theprocessor 302 is also electrically coupled to an I/O interface 310 by thebus 308. Anetwork interface 312 is also electrically connected to theprocessor 302 via thebus 308. Thenetwork interface 312 is connected to anetwork 314, so that theprocessor 302 and the computer-readable storage medium 304 are capable of connecting to external elements via thenetwork 314. Theprocessor 302 is configured to execute thecomputer program code 306 encoded in the computer-readable storage medium 304 in order to cause thesystem 300 to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, theprocessor 302 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. - In one or more embodiments, the computer-
readable storage medium 304 is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, the computer-readable storage medium 304 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 304 includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). - In one or more embodiments, the computer-
readable storage medium 304 storescomputer program code 306 configured to cause thesystem 300 to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, the computer-readable storage medium 304 also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, the computer-readable storage medium 304 stores alibrary 307 of standard cells including the various IC devices disclosed herein. - The
EDA system 300 includes an I/O interface 310. The I/O interface 310 is coupled to external circuitry. In one or more embodiments, the I/O interface 310 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to theprocessor 302. - The
EDA system 300 also includes anetwork interface 312 coupled to theprocessor 302. Thenetwork interface 312 allows thesystem 300 to communicate with thenetwork 314, to which one or more other computer systems are connected. Thenetwork interface 312 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two ormore systems 300. - The
system 300 is configured to receive information through an I/O interface 310. The information received through the I/O interface 310 includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing byprocessor 302. The information is transferred to theprocessor 302 via thebus 308. TheEDA system 300 is configured to receive information related to a UI through the I/O interface 310. The information is stored in the computer-readable medium 304 as a user interface (UI) 342. - In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by the
EDA system 300. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. - In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like.
- As noted above, embodiments of the
EDA system 300 may includefabrication tools 303 for implementing the processes and/or methods stored in thestorage medium 304. For instance, a synthesis ay be performed on a design in which the behavior and/or functions desired from the design are transformed to a functionally equivalent logic gate-level circuit description by matching the design to standard cells selected from thestandard cell library 307. The synthesis results in a functionally equivalent logic gate-level circuit description, such as a gate-level netlist. Based on the gate-level netlist, a photolithographic mask may be generated that is used to fabricate the integrated circuit by thefabrication tools 303. Further aspects of device fabrication are disclosed in conjunction withFIG. 13 , which is a block diagram ofIC manufacturing system 301, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using themanufacturing system 301. - In
FIG. 13 , theIC manufacturing system 301 includes entities, such as a design house 320, amask house 330, and an IC manufacturer/fabricator (“fab”) 350, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing anIC device 360, such as the devices 100-106 disclosed herein. The entities in thesystem 301 are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of the design house 320,mask house 330, andIC fab 350 is owned by a single larger company. In some embodiments, two or more of design house 320,mask house 330, andIC fab 350 coexist in a common facility and use common resources. - The design house (or design team) 320 generates an IC design layout diagram 322. The IC design layout diagram 322 includes various geometrical patterns, or IC layout diagrams designed for an
IC device 360, e.g., an IC device including one or more of the disclosed IC structures 100-106, discussed above. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components ofIC device 360 to be fabricated. The various layers combine to form various IC features. For example, a portion of the IC design layout diagram 322 includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design house 320 implements a design procedure to form a IC design layout diagram 322. The design procedure includes one or more of logic design, physical design or place and route. The IC design layout diagram 322 is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram 322 can be expressed in a GDSII file format or DFII file format. - The
mask house 330 includes adata preparation 332 and amask fabrication 344. Themask house 330 uses the IC design layout diagram 322 to manufacture one ormore masks 345 to be used for fabricating the various layers of theIC device 360 according to the IC design layout diagram 322. Themask house 330 performsmask data preparation 332, where the IC design layout diagram 322 is translated into a representative data file (“RDF”). Themask data preparation 332 provides the RDF to themask fabrication 344. Themask fabrication 344 includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle) 345 or asemiconductor wafer 353. The design layout diagram 322 is manipulated by themask data preparation 332 to comply with particular characteristics of the mask writer and/or requirements of theIC fab 350. InFIG. 13 , themask data preparation 332 and themask fabrication 344 are illustrated as separate elements. In some embodiments, themask data preparation 332 and themask fabrication 344 can be collectively referred to as a mask data preparation. - In some embodiments, the
mask data preparation 332 includes an optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. The OPC adjusts the IC design layout diagram 322. In some embodiments, themask data preparation 332 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. - In some embodiments, the
mask data preparation 332 includes a mask rule checker (MRC) that checks the IC design layout diagram 322 that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram 322 to compensate for limitations during themask fabrication 344, which may undo part of the modifications performed by OPC in order to meet mask creation rules. - In some embodiments, the
mask data preparation 332 includes lithography process checking (LPC) that simulates processing that will be implemented by theIC fab 350 to fabricate theIC device 360. LPC simulates this processing based on the IC design layout diagram 322 to create a simulated manufactured device, such as theIC device 360. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine the IC design layout diagram 322. - It should be understood that the above description of
mask data preparation 332 has been simplified for the purposes of clarity. In some embodiments,data preparation 332 includes additional features such as a logic operation (LOP) to modify the IC design layout diagram 322 according to manufacturing rules. Additionally, the processes applied to the IC design layout diagram 322 duringdata preparation 332 may be executed in a variety of different orders. - After the
mask data preparation 332 and during themask fabrication 344, amask 345 or a group ofmasks 345 are fabricated based on the modified IC design layout diagram 322. In some embodiments, themask fabrication 344 includes performing one or more lithographic exposures based on the IC design layout diagram 322. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle) 345 based on the modified IC design layout diagram 322. Themask 345 can be formed in various technologies. In some embodiments, themask 345 is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of themask 345 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, themask 345 is formed using a phase shift technology. In a phase shift mask (PSM) version of themask 345, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by themask fabrication 344 is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in thesemiconductor wafer 353, in an etching process to form various etching regions in thesemiconductor wafer 353, and/or in other suitable processes. - The
IC fab 350 includeswafer fabrication 352. TheIC fab 350 is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, theIC Fab 350 is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (FEOL fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (BEOL fabrication), and a third manufacturing facility may provide other services for the foundry business. - The
IC fab 350 uses mask(s) 345 fabricated by themask house 330 to fabricate theIC device 360. Thus, theIC fab 350 at least indirectly uses the IC design layout diagram 322 to fabricate theIC device 360. In some embodiments, thesemiconductor wafer 353 is fabricated by theIC fab 350 using mask(s) 345 to form theIC device 360. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on the IC design layout diagram 322. TheSemiconductor wafer 353 includes a silicon substrate or other proper substrate having material layers formed thereon. Thesemiconductor wafer 353 further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). - Thus, disclosed embodiments include an integrated circuit device that includes a first power rail and a first active area extending in a first direction. A plurality of gates contact the first active area and extend in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first VT. A second transistor includes the first active area and a second one of the gates, and the second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor. The tie-off transistor includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.
- In accordance with other disclosed embodiments, a semiconductor device includes a first power rail and a second power rail. A first PMOS transistor includes a first fin extending in a first direction and a first gate. The first PMOS transistor has a first VT, and the first gate extends in a second direction perpendicular to the first direction. A second PMOS transistor includes the first fin and a second gate that extends in the second direction. The second PMOS transistor has a second VT different than the first VT. The second gate is connected to the first power rail. A second fin extends in the first direction. A first NMOS transistor includes the second fin and the first gate. The first NMOS transistor has the first VT. A second NMOS transistor includes the second fin and the second gate. The second NMOS transistor has the second VT. The second gate is connected to the second power rail.
- In accordance with still further embodiments, a method includes forming a first active area on a substrate, where the first active area has a first VT region and a second VT region. A first gate is formed that contacts the first VT region of the first active area to form a first transistor having a first VT. A second gate is formed to contact the second VT region of the first active area to form a second transistor having a second VT that is different than the first VT. A third gate is formed to contact the first active area between the first gate and the second gate to form a tie-off transistor positioned between the first transistor and the second transistor. The third gate is connected to a power rail to maintain the tie-off transistor in an off state.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. A semiconductor device, comprising:
a first power rail;
a second power rail;
a first fin extending in a first direction;
a first PMOS transistor including the first fin and a first gate, the first PMOS transistor having a first threshold voltage (VT), the first gate extending in a second direction perpendicular to the first direction;
a second PMOS transistor including the first fin and a second gate extending in the second direction, the second PMOS transistor having a second VT different than the first VT, and wherein the second gate is connected to the first power rail;
a second fin extending in the first direction;
a first NMOS transistor including the second fin and the first gate, the first NMOS transistor having the first VT;
a second NMOS transistor including the second fin and the second gate, the second NMOS transistor having the second VT, and wherein the second gate is connected to the second power rail.
2. The integrated circuit device of claim 1 , wherein the first gate is connected to the second power rail, and wherein the second gate is connected to the first power rail through the first PMOS transistor.
3. The integrated circuit device of claim 1 , wherein the first gate is connected to the first power rail, and wherein the second gate is connected to the second power rail through the first NMOS transistor.
4. The integrated circuit device of claim 2 , wherein the second gate is connected to the first PMOS transistor through a metal layer extending in the first direction and a metal strip extending in the second direction.
5. The integrated circuit device of claim 1 , further comprising:
a third PMOS transistor including the first fin and a third gate, the third PMOS transistor having the second VT, wherein the second PMOS transistor is between the first and third PMOS transistors;
a third NMOS transistor including the first fin and the third gate, the third NMOS transistor having the second VT, wherein the second NMOS transistor is between the first and third NMOS transistors.
6. The integrated circuit device of claim 1 , wherein the first, second and third gates comprise respective first, second and third poly gates, and wherein the second poly gate includes a cut poly between the first and second fins, and wherein the second poly gate is directly connected to the first power rail.
7. A method, comprising:
forming a first active area on a substrate, the first active area including a first threshold voltage (VT) region and a second VT region;
forming a first gate contacting the first VT region of the first active area to form a first transistor having a first VT;
forming a second gate contacting the second VT region of the first active area to form a second transistor having a second VT different than the first VT;
forming a third gate contacting the first active area between the first gate and the second gate to form a tie-off transistor positioned between the first transistor and the second transistor; and
connecting the third gate to a power rail to maintain the tie-off transistor in an off state.
8. The method of claim 7 , wherein the tie-off transistor is a PMOS transistor and wherein connecting the third gate to the power rail to maintain the tie-off transistor in the off state includes connecting the third gate to a VDD power rail.
9. The method of claim 8 , wherein connecting the third gate to the VDD power rail includes providing a conductive via extending between the third gate and the VDD power rail.
10. The method of claim 8 , wherein the first and second transistors and the tie-off transistor are PMOS transistors, the method further comprising:
forming a second active area on the substrate, the second active area including the first VT region and the second VT region;
forming the first gate to further contact second active area to form a first NMOS transistor having the first VT;
forming the second gate to further contact the second active area to form a second NMOS transistor having the second VT;
forming the third gate to further contact the second active area to form an NMOS tie-off transistor positioned between the first NMOS transistor and the second NMOS transistor; and
connecting the third gate to a second power rail to maintain the NMOS tie-off transistor in an off state.
11. An integrated circuit device, comprising:
a first active area on a substrate, the first active area including a first threshold voltage (VT) region and a second VT region;
a first gate contacting the first VT region of the first active area to form a first transistor having a first VT;
a second gate contacting the second VT region of the first active area to form a second transistor having a second VT different than the first VT;
a third gate contacting the first active area at a boundary of the first VT region and the second VT region between the first gate and the second gate to form a tie-off transistor positioned between the first transistor and the second transistor; and
wherein the third gate is connected to a power rail to maintain the tie-off transistor in an off state.
12. The integrated circuit device of claim 11 , wherein the tie-off transistor is a PMOS transistor and wherein the third gate is connected to a VDD power rail.
13. The integrated circuit device of claim 12 , further comprising a conductive via extending between the third gate and the VDD power rail.
14. The integrated circuit device of claim 12 , wherein the first and second transistors and the tie-off transistor are PMOS transistors, the device further comprising:
a second active area on the substrate, the second active area including the first VT region and the second VT region;
the first gate further contacting the second active area to form a first NMOS transistor having the first VT;
the second gate further contacting the second active area to form a second NMOS transistor having the second VT;
the third gate further contacting the second active area at the boundary of the first VT region and the second VT region between the first gate and the second gate to form an NMOS tie-off transistor positioned between the first NMOS transistor and the second NMOS transistor; and
wherein the third gate is connected to a second power rail to maintain the NMOS tie-off transistor in an off state.
15. The integrated circuit device of claim 11 , wherein the first active area includes a fin.
16. The integrated circuit device of claim 14 , wherein the first and second active areas include respective first and second fins.
17. The integrated circuit device of claim 11 , wherein the first, second and third gates include respective first, second and third poly gates.
18. The integrated circuit device of claim 17 , wherein the third poly gate is connected to a VSS power rail by a conductive via.
19. The integrated circuit device of claim 17 , wherein the third poly gate is connected to a VSS power rail by a metal layer and a conductive via.
20. The integrated circuit device of claim 17 , wherein the third poly gate includes a cut poly between the first and second active areas.
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US201962863387P | 2019-06-19 | 2019-06-19 | |
US16/879,166 US11862637B2 (en) | 2019-06-19 | 2020-05-20 | Tie off device |
US17/863,175 US20220352166A1 (en) | 2019-06-19 | 2022-07-12 | Tie off device |
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