US20220037319A1 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
- Publication number
- US20220037319A1 US20220037319A1 US17/210,751 US202117210751A US2022037319A1 US 20220037319 A1 US20220037319 A1 US 20220037319A1 US 202117210751 A US202117210751 A US 202117210751A US 2022037319 A1 US2022037319 A1 US 2022037319A1
- Authority
- US
- United States
- Prior art keywords
- isolation insulating
- insulating layer
- layer
- active
- sacrificial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 238000000034 method Methods 0.000 title claims description 37
- 238000002955 isolation Methods 0.000 claims abstract description 201
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 9
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 392
- 125000006850 spacer group Chemical group 0.000 description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 24
- 239000011229 interlayer Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 239000012535 impurity Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 229910010041 TiAlC Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910034327 TiC Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 description 1
- XWCMFHPRATWWFO-UHFFFAOYSA-N [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] Chemical compound [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] XWCMFHPRATWWFO-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 239000004964 aerogel Substances 0.000 description 1
- MIQVEZFSDIJTMW-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O-2].[Al+3].[Hf+4] MIQVEZFSDIJTMW-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- JQJCSZOEVBFDKO-UHFFFAOYSA-N lead zinc Chemical compound [Zn].[Pb] JQJCSZOEVBFDKO-UHFFFAOYSA-N 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- QLOAVXSYZAJECW-UHFFFAOYSA-N methane;molecular fluorine Chemical compound C.FF QLOAVXSYZAJECW-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 125000000962 organic group Chemical group 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- KJXBRHIPHIVJCS-UHFFFAOYSA-N oxo(oxoalumanyloxy)lanthanum Chemical compound O=[Al]O[La]=O KJXBRHIPHIVJCS-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02603—Nanowires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
Definitions
- the present disclosure relates to a semiconductor device and a method for fabricating the same.
- a multi-gate transistor As one of scaling techniques for increasing the density of integrated circuit devices, a multi-gate transistor has been proposed, in which a fin-shaped or a nanowire-shaped silicon body is formed on a substrate, and a gate is formed on the surface of the silicon body. Since the multi-gate transistor uses a three-dimensional (3D) channel, scaling of the multi-gate transistor can be easily achieved. Further, current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, a short channel effect (SCE) in which the potential of a channel region is affected by a drain voltage can be effectively suppressed.
- SCE short channel effect
- Embodiments may be realized by providing a semiconductor device including a substrate having a first region and a second region separated from each other, a laminate structure in which at least one sacrificial layer and at least one active layer are alternately stacked on the substrate, a first isolation insulating layer disposed on the laminate structure on the first region, a second isolation insulating layer disposed on the laminate structure on the second region and having substantially the same thickness as the first isolation insulating layer, a first upper active pattern spaced apart from the first isolation insulating layer, a first gate electrode surrounding at least a part of the first upper active pattern, a second upper active pattern spaced apart from the second isolation insulating layer, and a second gate electrode surrounding at least a part of the second upper active pattern, wherein a top surface of the first isolation insulating layer and a top surface of the second isolation insulating layer are disposed at different heights.
- Embodiments may also be realized by providing a semiconductor device including a substrate having a first region and a second region different from each other, a first isolation insulating layer disposed on the first region, a first active pattern disposed on the first isolation insulating layer, a first gate electrode surrounding at least a part of the first active pattern, a second isolation insulating layer disposed on the second region, a second active pattern disposed on the second isolation insulating layer, and a second gate electrode surrounding at least a part of the second active pattern, wherein the first isolation insulating layer and the second isolation insulating layer include different materials.
- Embodiments may still be realized by providing a method for fabricating a semiconductor device including forming a laminate structure in which sacrificial layers and active layers are alternately stacked on a substrate including a first region and a second region separated from each other, etching the laminate structure on the first region to form a first stacked structure protruding from a first sacrificial layer among the sacrificial layers, removing the first sacrificial layer and forming a first isolation insulating layer in a space from which the first sacrificial layer has been removed, etching the laminate structure on the second region to form a second stacked structure protruding from a second sacrificial layer among the sacrificial layers, removing the second sacrificial layer and forming a second isolation insulating layer in a space from which the second sacrificial layer has been removed, removing the sacrificial layer included in the first stacked structure and the second stacked structure, and forming a gate electrode in
- FIG. 1 is a schematic plan view of a semiconductor device according to some embodiments.
- FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1 ;
- FIG. 3 is a cross-sectional view taken along line B-B′ of FIG. 1 ;
- FIG. 4 is a cross-sectional view taken along line A-A′ of FIG. 1 , according to some embodiments;
- FIG. 5 is a cross-sectional view taken along line B-B′ of FIG. 1 , according to some embodiments;
- FIG. 6 is a cross-sectional view taken along line A-A′ of FIG. 1 , according to some embodiments;
- FIG. 7 is a cross-sectional view taken along line B-B′ of FIG. 1 , according to some embodiments.
- FIG. 8 is a schematic plan view of a semiconductor device according to some other embodiments.
- FIG. 9 is a cross-sectional view taken along lines C-C′ and D-D′ of FIG. 8 ;
- FIGS. 10A and 10B are graphs showing electron mobility and hole mobility with respect to vertical stress applied to a channel, respectively;
- FIG. 11 is a schematic plan view illustrating a semiconductor device according to some other embodiments.
- FIG. 12 is a cross-sectional view taken along lines E-E′, F-F′, G-G′, and H-H′ of FIG. 11 ;
- FIG. 13 is a cross-sectional view taken along lines E-E′, F-F′, G-G′, and H-H′ of FIG. 11 , according to some embodiments;
- FIGS. 14 to 32 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments.
- FIGS. 33 to 36 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments.
- FIGS. 37 to 40 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments.
- FIGS. 41 and 42 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments.
- FIG. 1 is a schematic plan view illustrating a semiconductor device according to some embodiments.
- FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1 .
- FIG. 3 is a cross-sectional view taken along line B-B′ of FIG. 1 .
- a semiconductor device may include a substrate 100 , a first isolation insulating layer 110 , first active patterns 122 and 123 , a first gate dielectric layer 130 , a first gate electrode 140 , a first gate spacer 150 , a first source/drain region 160 , and an interlayer insulating layer 190 .
- the substrate 100 may be a bulk silicon substrate.
- the first isolation insulating layer 110 may be disposed on the substrate 100 .
- the first isolation insulating layer 110 may include, e.g., at least one of silicon oxide, silicon oxynitride, silicon nitride or a combination thereof, but the present disclosure is not limited thereto.
- the first active patterns 122 and 123 may be disposed on the first isolation insulating layer 110 .
- the first active patterns 122 and 123 may include a first lower active pattern 122 disposed on the first isolation insulating layer 110 , and a first upper active pattern 123 disposed on the first lower active pattern 122
- the first active patterns 122 and 123 may extend, e.g., in a first direction X 1 .
- the first lower active pattern 122 may be in, e.g., direct, contact with the first isolation insulating layer 110 .
- the first lower active pattern 122 may be an active pattern disposed at a lowermost portion among the first active patterns 122 and 123 penetrating the first gate electrode 140 .
- the first upper active pattern 123 may be disposed on the first lower active pattern 122 .
- the first upper active pattern 123 may include a plurality of sub-active patterns 124 , 126 , and 128 sequentially disposed in a thickness direction of the substrate 100 , e.g., in a third direction Z 1 .
- the first sub-active pattern 124 may be disposed on the first lower active pattern 122
- the second sub-active pattern 126 may be disposed on the first sub-active pattern 124
- the third sub-active pattern 128 may be disposed on the second sub-active pattern 126 .
- the first sub-active pattern 124 , the second sub-active pattern 126 , and the third sub-active pattern 128 may overlap each other in the third direction Z 1 .
- the first upper active pattern 123 may be spaced apart from the first lower active pattern 122 in the third direction Z 1 .
- the first sub-active pattern 124 , the second sub-active pattern 126 , and the third sub-active pattern 128 may be spaced apart from each other in the third direction Z 1 .
- the first sub-active pattern 124 may be spaced apart from the first lower active pattern 122
- the second sub-active pattern 126 may be spaced apart from the first sub-active pattern 124
- the third sub-active pattern 128 may be spaced apart from the second sub-active pattern 126 .
- the first active patterns 122 and 123 may contain silicon (Si) that is an elemental semiconductor material.
- Each of the first active patterns 122 and 123 may be used as a channel region of a transistor including the first gate electrode 140 .
- three sub-active patterns of the first upper active pattern 123 are illustrated in FIG. 2 and FIG. 3 for simplicity of description, the present disclosure is not limited thereto.
- the semiconductor device according to some embodiments may include two or less sub-active patterns or four or more sub-active patterns.
- the first gate electrode 140 may be disposed on the first isolation insulating layer 110 .
- the first gate electrode 140 may intersect the first active patterns 122 and 123 .
- the first gate electrode 140 may be parallel to the top surface of the substrate 100 and may be elongated in the second direction Y 1 .
- the first active patterns 122 and 123 may penetrate the first gate electrode 140 while extending in the first direction X 1 . Accordingly, the first gate electrode 140 may be formed to surround the first upper active pattern 123 . Further, the first gate electrode 140 may be formed to surround, e.g., portions of, the first lower active pattern 122 that are not in contact with the first isolation insulating layer 110 .
- the first gate electrode 140 may include a conductive material.
- the first gate electrode 140 may include at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al or a combination thereof, but is not limited thereto.
- the first gate electrode 140 may be formed, e.g., by a replacement process, but is not limited thereto.
- the first gate electrode 140 that is a single layer is illustrated, this is merely an example, and the first gate electrode 140 may be formed by stacking a plurality of conductive materials.
- the first gate electrode 140 may include a work function adjusting layer to adjust the work function and a filling conductive layer to fill a space formed by the work function adjusting layer.
- the work function adjusting layer may include at least one of, e.g., TiN, TaN, TiC, TaC, TiAlC or a combination thereof.
- the filling conductive layer may include, e.g., W or Al.
- the first gate dielectric layer 130 may be interposed between the first gate electrode 140 and each of first active patterns 122 and 123 .
- the first gate dielectric layer 130 may be formed to surround the first upper active pattern 123 .
- the first gate dielectric layer 130 may be formed to surround portions of the first lower active pattern 122 that are not in contact with the first isolation insulating layer 110 , e.g., the first gate dielectric layer 130 may not separate between a bottom of the first lower active pattern 122 and the first isolation insulating layer 110 .
- the first gate dielectric layer 130 may extend along the top surface of the first isolation insulating layer 110 .
- the first gate dielectric layer 130 may include, e.g., at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a higher dielectric constant than silicon oxide.
- the high-k material may include, e.g., at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and a combination thereof, but is not limited thereto.
- An interface layer may be formed between each of the first active patterns 122 and 123 and the first gate dielectric layer 130 .
- the interface layer may be formed to surround the first upper active pattern 123 and to surround portions of the first lower active pattern 122 that are not in contact with the first isolation insulating layer 110 , and may extend along the top surface of the first isolation insulating layer 110 .
- the present disclosure is not limited thereto.
- the first source/drain region 160 may be formed on the first isolation insulating layer 110 . Further, the first source/drain region 160 may be disposed on the side surface of the first gate electrode 140 . For example, the first source/drain region 160 may be disposed on both, e.g., opposite, side surfaces of the first gate electrode 140 .
- the first source/drain region 160 may be spaced, e.g., separated, apart from the first gate electrode 140 by the first gate spacer 150 to be described later. Further, the first source/drain region 160 may be, e.g., directly, connected to the first active patterns 122 and 123 . For example, the first active patterns 122 and 123 may be connected to the first source/drain region 160 while penetrating the first gate spacer 150 . The first source/drain region 160 may be used as a source/drain region of a transistor including the first gate electrode 140 .
- the first source/drain region 160 may include an epitaxial layer formed on the substrate 100 .
- the first source/drain region 160 may be formed by an epitaxial growth method.
- the first source/drain region 160 that is a single layer is illustrated, this is merely an example and the first source/drain region 160 may be formed by stacking a plurality of epitaxial layers.
- the first source/drain region 160 may include a plurality of epitaxial layers having different impurity concentrations, which are sequentially stacked on the isolation insulating layer 110 .
- the first source/drain region 160 may be a raised source/drain region including a top surface protruding more upward than the top surface of the substrate 100 .
- the first source/drain region 160 may protrude more upward than the topmost surface of the first upper active pattern 123 penetrating the first gate electrode 140 .
- the top surface of the first source/drain region 160 may protrude more upward than the top surface of the third sub-active pattern 128 .
- the first source/drain region 160 may include n-type impurities or impurities for preventing the diffusion of n-type impurities.
- the first source/drain region 160 may contain at least one of P, Sb, As, or a combination thereof
- the first source/drain region 160 may include a tensile stress material.
- the first active patterns 122 and 123 are made of silicon (Si)
- the first source/drain region 160 may include a material, e.g., SiC, having a smaller lattice constant than silicon (Si).
- the tensile stress material may apply tensile stress to the first active patterns 122 and 123 to improve the mobility of carriers in the channel region.
- the first source/drain region 160 may include p-type impurities or impurities for preventing the diffusion of p-type impurities.
- the first source/drain region 160 may include at least one of B, C, In, Ga, Al or a combination thereof
- the semiconductor device according to some embodiments is a
- the first source/drain region 160 may include a compressive stress material.
- the first source/drain region 160 may include a material having a larger lattice constant than silicon (Si).
- the first source/drain region 160 may include SiGe.
- the compressive stress material may apply compressive stress to the first active patterns 122 and 123 to improve the mobility of carriers in the channel region.
- the first gate spacer 150 may be disposed on the isolation insulating layer 110 .
- the first gate spacer 150 may extend along the side surface of the first gate electrode 140 .
- the first gate spacer 150 may electrically insulate the first gate electrode 140 from the first source/drain region 160 .
- the first active patterns 122 and 123 may penetrate the first gate spacer 150 while extending in the first direction X 1 .
- the first gate spacer 150 may be disposed at the ends of the first active patterns 122 and 123 . Accordingly, the first gate space 150 may be formed to surround the ends of the first active patterns 122 and 123 .
- the first gate spacer 150 may include first inner spacers 151 and a first outer spacer 152 .
- the first inner spacers 151 may be disposed between the lower active pattern 122 and the first sub-active pattern 124 , between the first sub-active pattern 124 and the second sub-active pattern 126 , and between the second sub-active pattern 126 and the third sub-upper active pattern 128 .
- the first inner spacers 151 may be disposed at positions vertically overlapping the first active patterns 122 and 123 .
- the first outer spacer 152 may be disposed on the third sub-active pattern 128 disposed at an uppermost portion among the first active patterns 122 and 123 , e.g., the third sub-active pattern 128 may be between the first outer spacer 152 and a topmost of the first inner spacers 151 .
- the first inner spacer 151 may include, e.g., at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxynitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC) or a combination thereof.
- the first outer spacer 152 may include, e.g., at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN) or a combination thereof.
- the first inner spacer 151 and the first outer spacer 152 may contain different materials, or may contain the same material.
- the first lower active pattern 122 and the first sub-active pattern 124 may be spaced apart from each other by a first distance D 1 , e.g., along the direction Z 1
- the first sub-active pattern 124 and the second sub-active pattern 126 may be spaced apart from each other by the first distance D 1 , e.g., along the direction Z 1
- the second sub-active pattern 126 and the third sub-active pattern 128 may be spaced apart from each other by the first distance D 1 , e.g., along the direction Z 1
- a thickness T 1 of the first isolation insulating layer 110 e.g., along the direction Z 1 , may be substantially the same as the distance D 1 between the first lower active pattern 122 and the first sub-active pattern 124 .
- the interlayer insulating layer 190 may be disposed on the first isolation insulating layer 110 and the first source/drain region 160 .
- the interlayer insulating layer 190 may surround the sidewall of the first gate spacer 150 .
- the interlayer insulating layer 190 may be formed to fill the space on the side surface of the first gate electrode 140 .
- the interlayer insulating layer 190 may include, e.g., at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.
- the low-k dielectric material may include, for example, at least one of flowable oxide (FOX), Tonen Silazene (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetra ethyl ortho silicate (PETEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO), Xerogel, Aerogel, amorphous fluorinated carbon, organo silicate glass (OSG), parylene, bis-benzocyclobutene (BCB), SiLK, polyimide, a porous polymeric material, or a combination thereof, but is not limited thereto.
- FOX flowable oxide
- TOSZ Tonen Sil
- fins are formed on the substrate. Accordingly, since a punch through may occur, a punch through stopper may be formed on the fins to reduce or prevent the punch through. While the punch through stopper may reduce the punch through, the fins may have higher threshold voltages than those of the active patterns due to the punch through stopper, thereby deteriorating performance of the semiconductor device.
- the semiconductor device does not include a silicon-on-insulator (SOI) substrate
- the lower portions of the active patterns may be insulated from the substrate 100 by the first isolation insulating layer 110 .
- the active patterns are formed on the first isolation insulating layer 110 , and fins are not included. Accordingly, the first isolation insulating layer 110 may apply stress to the active pattern, which makes it possible to reduce or prevent punch through.
- the performance of the semiconductor device can be improved or enhanced.
- FIGS. 4 and 5 are cross-sectional views illustrating a semiconductor device according to some other embodiments.
- FIG. 4 is a cross-sectional view taken along line A-A′ of FIG. 1 .
- FIG. 5 is a cross-sectional view taken along line B-B′ of FIG. 1 .
- descriptions of features described previously with reference to FIGS. 2 and 3 will be omitted or described only briefly.
- a semiconductor device may include the first active pattern 123 .
- the first active pattern 123 may include the first to third sub-active patterns 124 , 126 , and 128 spaced apart from the first isolation insulating layer 110 .
- the first sub-active pattern 124 may be spaced apart from the first isolation insulating layer 110
- the second sub-active pattern 126 may be spaced apart from the first sub-active pattern 124
- the third sub-active pattern 128 may be spaced apart from the second sub-active pattern 126 .
- the first sub-active pattern 124 may be a first active pattern on the first isolation insulating layer 110 , i.e., without the first lower active pattern 122 of FIGS. 2 and 3 .
- the first active pattern 123 may contain silicon germanium (SiGe).
- the first to third sub-active patterns 124 , 126 and 128 may have the same thickness TA 1 , e.g., along the direction Z 1 .
- the thickness T 1 of the first isolation insulating layer 110 may be substantially the same as the thickness TA 1 of each of the first to third sub-active patterns 123 , 126 , and 128 .
- FIGS. 6 and 7 are cross-sectional views illustrating a semiconductor device according to some other embodiments.
- FIG. 6 is a cross-sectional view taken along line A-A′ of FIG. 1 .
- FIG. 7 is a cross-sectional view taken along line B-B′ of FIG. 1 .
- descriptions of features described previously with reference to FIGS. 2 and 3 will be omitted or described only briefly.
- the first active pattern 122 may contain silicon (Si).
- the first active patterns 122 and 123 may include the first lower active pattern 122 disposed on the first isolation insulating layer 110 , and the first upper active pattern 123 spaced apart from the first lower active pattern 122 .
- the first active pattern 122 contains silicon germanium (SiGe)
- the first lower active pattern 122 may be omitted unlike the drawing.
- a thickness T 1 ′ of the first isolation insulating layer 110 may be greater than the thickness TA 1 of each of the first active patterns 122 and 123 and the distance D 1 between the first active patterns 122 and 123 .
- FIG. 8 is a schematic plan view illustrating a semiconductor device according to some other embodiments.
- FIG. 9 is a cross-sectional view taken along lines C-C′ and D-D′ of FIG. 8 .
- FIGS. 10A and 10B are graphs showing electron mobility and hole mobility with respect to vertical stress applied to a channel, respectively. For simplicity of description, descriptions of features described previously with reference to FIGS. 2 and 3 will be omitted or described only briefly.
- the substrate 100 may include a first region I and a second region II different from each other.
- the first region I and the second region II of the substrate 100 may be adjacent to each other or may be spaced apart from each other.
- the first region I and the second region II of the substrate 100 may be, e.g., horizontally separated regions.
- Different types of transistors may be formed in the first region I and the second region II of the substrate 100 .
- a PMOS transistor may be formed in the second region II of the substrate 100 .
- a first isolation insulating layer 110 may be disposed on the first region I of the substrate 100 .
- First active patterns 122 and 123 may be disposed on the first isolation insulating layer 110 .
- the first lower active pattern 122 may be in contact with the first isolation insulating layer 110
- the first upper active pattern 123 may be spaced apart from the first isolation insulating layer 110 .
- the first gate electrode 140 may be disposed on the first isolation insulating layer 110 .
- the first gate electrode 140 may be formed to surround the first active patterns 122 and 123 .
- the first gate dielectric layer 130 may be interposed between the first active patterns 122 and 123 and the first gate electrode 140 .
- a second isolation insulating layer 210 may be disposed on the second region II of the substrate 100 .
- Second active patterns 222 and 223 may be disposed on the second isolation insulating layer 210 .
- the second lower active pattern 222 may be in, e.g., direct, contact with the second isolation insulating layer 210
- the second upper active pattern 223 may be spaced apart from the second isolation insulating layer 210 .
- a second gate electrode 240 may be disposed on the second isolation insulating layer 210 .
- the second gate electrode 240 may be formed to surround the second active patterns 222 and 223 .
- a second gate dielectric layer 230 may be interposed between the second active patterns 222 and 223 and the second gate electrode 240 .
- a second gate spacer 250 may be disposed on the second isolation insulating layer 210 .
- the second gate spacer 250 may extend along the side surface of the second gate electrode 240 .
- the second gate spacer 250 may electrically insulate the second gate electrode 240 from a second source/drain region 260 .
- a thickness T 1 _ 1 of the first isolation insulating layer 110 may be substantially the same as a thickness T 1 _ 2 of the second isolation insulating layer 210 .
- the first isolation insulating layer 110 and the second isolation insulating layer 210 may contain different materials. Accordingly, the stress applied to the first active patterns 122 and 123 by the first isolation insulating layer 110 and the stress applied to the second active patterns 222 and 223 by the second isolation insulating layer 210 may have different directions.
- the first isolation insulating layer 110 may apply compressive vertical stress (a) to the first lower active pattern 122 .
- the first isolation insulating layer 110 may apply the stress from the first isolation insulating layer 110 toward the first lower active pattern 122 .
- the second isolation insulating layer 210 may apply tensile vertical stress (b) to the second lower active pattern 222 .
- the second isolation insulating layer 210 may apply the stress from the second lower active pattern 222 toward the second isolation insulating layer 210 .
- FIG. 10A is a graph showing the electron mobility with respect to vertical stress applied to a channel containing silicon.
- FIG. 10B is a graph showing the hole mobility with respect to vertical stress applied to silicon.
- Vertical stress having a negative value means compressive stress
- vertical stress having a positive value means tensile stress.
- the electron mobility increases as the compressive vertical stress is applied to the channel, e.g., electron mobility ratio increases as the compressive vertical stress (negative values on the graph) increases.
- the hole mobility increases as the tensile vertical stress is applied to the channel, e.g., the hole mobility ratio increases as the tensile vertical stress (positive values on the graph) increases.
- an NMOS transistor is formed in the first region I and the first isolation insulating layer 110 applies the compressive vertical stress (a) to the first active patterns 122 and 123 , so that the electron mobility in the first active patterns 122 and 123 may be increased.
- a PMOS transistor is formed in the second region II and the second isolation insulating layer 210 applies the tensile vertical stress (b) to the second active patterns 222 and 223 , so that the hole mobility in the second active patterns 222 and 223 may be increased.
- the semiconductor device may apply stress to the first active patterns 122 and 123 and the second active patterns 222 and 223 in the vertical direction (e.g., third directions Z 1 and Z 2 ) as well as in the horizontal direction (e.g., first directions X 1 and X 2 ).
- the stress it is possible to apply the stress to the first active patterns 122 and 123 in the horizontal direction (e.g., the first direction X 1 ) depending on the material contained in the first source/drain region 160 , and also possible to apply the stress to the first active patterns 122 and 123 in the vertical direction (e.g., the third direction Z 1 ) depending on the material contained in the first isolation insulating layer 110 .
- the semiconductor device according to some other embodiments can apply stress to the active patterns more effectively compared to a semiconductor device formed on an SOI substrate and including active patterns. Therefore, the performance of the semiconductor device according to embodiments may be improved or enhanced.
- FIG. 11 is a schematic plan view illustrating a semiconductor device according to some other embodiments.
- FIG. 12 is a cross-sectional view taken along lines E-E′, F-F′, G-G′, and H-H′ of FIG. 11 .
- the substrate 100 may include the first region I, the second region II, and a third region III, and a fourth region IV different from each other.
- the first region I, the second region II, the third region III and the fourth region IV may be, e.g., horizontally separate regions.
- the substrate 100 includes four regions for simplicity of description, the present disclosure is not limited thereto.
- the semiconductor device according to some embodiments may include five or more regions.
- One or more sacrificial layers 201 , 301 , 303 , 401 , 403 , and 405 , and one or more active layers 202 , 302 , 304 , 402 , 404 , and 406 may be alternately stacked on the substrate 100 .
- One or more sacrificial layers 201 , 301 , 303 , 401 , 403 , and 405 , and one or more active layers 202 , 302 , 304 , 402 , 404 , and 406 may be stacked in third directions Z 1 , Z 2 , Z 3 , and Z 4 .
- the third directions Z 1 , Z 2 , Z 3 , and Z 4 may be the thickness direction of the substrate 100 and may be the same direction, e.g., but reflecting different respective regions on the substrate 100 .
- the first sacrificial layers 201 , 301 , and 401 , the first active layers 202 , 302 , and 402 , the second sacrificial layers 303 and 403 , the second active layers 304 and 404 , the third sacrificial layer 405 , and the third active layer 406 may be sequentially stacked on the substrate 100 .
- the sacrificial layers 201 , 301 , 303 , 401 , and 403 in the respective regions I, II, III, and VI may be the sacrificial layers on the same level.
- the first sacrificial layer 201 in the second region II, the first sacrificial layer 301 in the third region III, and the first sacrificial layer 401 in the fourth region VI may be the sacrificial layers on the same level.
- the second sacrificial layer 303 in the third region III and the second sacrificial layer 403 in the fourth region VI may be the sacrificial layers on the same level.
- the active layers 202 , 302 , 304 , 402 , and 404 in the respective regions I, II, III, and VI may be the active layers on the same level.
- the first active layer 202 in the second region II, the first active layer 302 in the third region III, and the first active layer 402 in the fourth region VI may be the active layers on the same level.
- the second active layer 304 in the third region III and the second active layer 404 in the fourth region VI may be the active layers on the same level.
- the layers on the same level may mean the layers formed by the same manufacturing process.
- the sacrificial layers 201 , 301 , 303 , 401 , 403 , and 405 , and the active layers 202 , 302 , 304 , 402 , 404 , and 406 may have a stair shape.
- the first sacrificial layer 201 and the first active layer 202 may be formed in the second region II.
- the second sacrificial layer 303 and the second active layer 304 may be further formed in addition to the layers formed in the second region II.
- the third sacrificial layer 403 and the third active layer 404 may be further formed in addition to the layers formed in the third region III.
- the sacrificial layers 201 , 301 , 303 , 401 , 403 , and 405 , and the active layers 202 , 302 , 304 , 402 , 404 , and 406 may contain different materials.
- the sacrificial layers 201 , 301 , 303 , 401 , 403 , and 405 may contain silicon
- the active layers 202 , 302 , 304 , 402 , 404 , and 406 may contain silicon germanium.
- the first to fourth regions I, II, III, and VI may include first to fourth isolation insulating layers 110 , 210 , 310 , and 410 , respectively.
- the first to fourth isolation insulating layers 110 , 210 , 310 , and 410 may be arranged at different positions.
- the first to fourth isolation insulating layers 110 , 210 , 310 , and 410 may be arranged at different positions in the third directions Z 1 , Z 2 , Z 3 , and Z 4 .
- the third directions Z 1 , Z 2 , Z 3 and Z 4 may be the same direction.
- the first to fourth isolation insulating layers 110 , 210 , 310 , and 410 may not overlap in the horizontal direction (e.g., second directions Y 1 , Y 2 , Y 3 , and Y 4 ).
- the second directions Y 1 , Y 2 , Y 3 , and Y 4 may be the same direction, e.g., but reflecting different respective regions on the substrate 100 .
- the second isolation insulating layer 210 may be disposed above the first isolation insulating layer 110
- the third isolation insulating layer 310 may be disposed above the second isolation insulating layer 210
- the fourth isolation insulating layer 410 may be disposed above the third isolation insulating layer 310 .
- the top surface of the first isolation insulating layer 110 , the top surface of the second isolation insulating layer 210 , the top surface of the third isolation insulating layer 310 , and the top surface of the fourth isolation insulating layer 410 may be arranged at different heights.
- the number of the sacrificial layers 201 , 301 , 303 , 401 , 403 , and 405 , and the number of the active layers 202 , 302 , 304 , 402 , 404 , and 406 arranged under the respective first to fourth isolation insulating layers 110 , 210 , 310 , and 410 may vary.
- n sacrificial layers n being a natural number
- n active layers may be disposed.
- m sacrificial layers (m being a natural number) and m active layers may be disposed. In this case, n and m may be different from each other.
- the number of sacrificial layers disposed under the first isolation insulating layer 110 and the number of active layers disposed under the first isolation insulating layer 110 may be the same, but the number of sacrificial layers and the number of active layers disposed under the first isolation insulating layer 110 may be different from the number of sacrificial layers and the number of active layers disposed under the second isolation insulating layer 210 .
- the first sacrificial layer 201 and the first active layer 202 may be sequentially stacked under the second isolation insulating layer 210 .
- the first sacrificial layer 301 , the first active layer 302 , the second sacrificial layer 303 , and the second active layer 304 may be sequentially stacked under the third isolation insulating layer 310 .
- the first sacrificial layer 401 , the first active layer 402 , the second sacrificial layer 403 , the second active layer 404 , the third sacrificial layer 405 , and the third active layer 406 may be sequentially stacked under the fourth isolation insulating layer 410 .
- the first isolation insulating layer 110 may be formed in the space from which the sacrificial layer in the first region I on the same level as the first sacrificial layer 201 in the second region II has been removed. Therefore, the thickness T 1 of the first isolation insulating layer 110 may be substantially the same as a thickness TS 21 of the first sacrificial layer 201 in the second region II.
- the second isolation insulating layer 210 may be formed in the space from which the sacrificial layer in the second region II on the same level as the second sacrificial layer 303 in the third region III has been removed. Therefore, a thickness T 2 of the second isolation insulating layer 210 may be substantially the same as a thickness TS 31 of the second sacrificial layer 303 in the third region III.
- the third isolation insulating layer 310 may be formed in the space from which the sacrificial layer in the third region III on the same level as the third sacrificial layer 405 in the fourth region VI has been removed. Therefore, a thickness T 3 of the third isolation insulating layer 310 may be substantially the same as a thickness TS 41 of the third sacrificial layer 405 in the fourth region VI.
- the fourth isolation insulating layer 410 may have a thickness T 4 .
- the first lower active pattern 122 may be formed by patterning the active layer in the first region I on the same level as the first active layer 202 in the second region II. Therefore, the first lower active pattern 122 may be formed on the same level as the first active layer 202 in the second region II.
- the thickness TA 1 of the first lower active pattern 122 is substantially the same as a thickness TS 22 of the first active layer 202 in the second region II.
- the second lower active pattern 222 may be formed by patterning the active layer in the second region II on the same level as the second active layer 304 in the third region III. Therefore, the second lower active pattern 222 may be formed on the same level as the second active layer 304 in the third region III.
- the thickness TA 2 of the second lower active pattern 222 may be substantially the same as a thickness TS 32 of the second active layer 304 in the third region III.
- the third lower active pattern 322 may be formed by patterning the active layer in the third region III on the same level as the third active layer 406 in the fourth region VI. Therefore, the third lower active pattern 322 may be formed on the same level as the third active layer 406 in the fourth region VI.
- the thickness TA 3 of the third lower active pattern 322 may be substantially the same as a thickness TS 42 of the third active layer 406 in the fourth region VI.
- the first gate electrode 140 may surround the first active patterns 122 and 123
- the second gate electrode 240 may surround the second active patterns 222 and 223
- the third gate electrode 340 may surround the third active patterns 322 and 333
- the fourth gate electrode 440 may surround a fourth active pattern 422 .
- the fourth active pattern 422 may have a thickness TA 4 .
- the number of the first active patterns 122 and 123 arranged on the first region I, the number of the second active patterns 222 and 223 arranged on the second region II, the number of the third active patterns 322 and 323 arranged on the third region III, and the number of the fourth active pattern 422 arranged on the fourth region VI may be different from each other.
- the area of the first active patterns 122 and 123 surrounded by the first gate electrode 140 , the area of the second active patterns 222 and 223 surrounded by the second gate electrode 240 , the area of the third active patterns 322 and 323 surrounded by the third gate electrode 340 , and the area of the fourth active pattern 422 surrounded by the fourth gate electrode 440 may be different from each other.
- the driving performance of the elements formed in the first to fourth regions I, II, III, and VI of the semiconductor device may be different.
- the number of the first active patterns 122 and 123 arranged on the first region I is four for simplicity of description, the present disclosure is not limited thereto.
- five or more first active patterns 122 and 123 may be arranged on the first region I.
- the number of the active patterns arranged on the second to fourth regions II, III, and VI may also be increased.
- the driving performance of the semiconductor device may vary depending on the contact area between the gate electrode and the active patterns. At this time, the size of the semiconductor device may be increased to increase the contact area between the gate electrode and the active patterns.
- the contact area between the gate electrode and the active pattern may be increased or decreased by adjusting the position where the active patterns are formed. In other words, the contact area between the gate electrode and the active patterns may be increased without increasing the area of the semiconductor device.
- FIG. 13 is a cross-sectional view taken along lines E-E′, F-F′, G-G′, and H-H′ of FIG. 11 .
- E-E′, F-F′, G-G′, and H-H′ of FIG. 11 are cross-sectional views taken along lines E-E′, F-F′, G-G′, and H-H′ of FIG. 11 .
- descriptions of features described previously with reference to FIGS. 11 and 12 will be omitted or described only briefly.
- the first to fourth isolation insulating layers 110 , 210 , 310 , and 410 may be arranged at different positions in, e.g., the third directions Z 1 , Z 2 , Z 3 , and Z 4 .
- the third directions Z 1 , Z 2 , Z 3 , and Z 4 may be the same direction.
- the first to fourth isolation insulating layers 110 , 210 , 310 , and 410 may at least partially overlap each other in the horizontal direction (e.g., the second directions Y 1 , Y 2 , Y 3 , and Y 4 ).
- the second directions Y 1 , Y 2 , Y 3 , and Y 4 may be the same direction.
- at least a part of the second isolation insulating layer 210 may overlap the first isolation insulating layer 110
- at least a part of the third isolation insulating layer 310 may overlap the second isolation insulating layer 210
- at least a part of the fourth isolation insulating layer 410 may overlap the third isolation insulating layer 310 .
- the first isolation insulating layer 110 may be formed in the space from which the sacrificial layer and the active layer on the same level as the first sacrificial layer 201 in the second region II, the first active layer 202 in the second region II, and the second sacrificial layer 303 in the third region III have been removed. Therefore, the thickness T 1 ′ of the first isolation insulating layer 110 may be greater than the thickness TS 21 of the first sacrificial layer 201 in the second region II and the thickness TS 22 of the first active layer 202 in the second region II.
- the thickness T 1 ′ of the first isolation insulating layer 110 may be substantially the same as the sum of the thickness TS 21 of the first sacrificial layer 201 in the second region II, the thickness TS 22 of the first active layer 202 in the second region II, and the thickness TS 31 of the second sacrificial layer 303 in the third region III.
- the second isolation insulating layer 210 may be formed in the space from which the sacrificial layer and the active layer on the same level as the second sacrificial layer 303 in the third region III, the second active layer 304 in the third region III, and the third sacrificial layer 405 in the fourth region VI have been removed. Therefore, the thickness T 2 ′ of the second isolation insulating layer 210 may be greater than the thickness TS 31 of the second sacrificial layer 303 in the third region III, and the thickness TS 32 of the second active layer 304 in the third region III.
- the thickness T 2 ′ of the second isolation insulating layer 210 may be substantially the same as the sum of the thickness TS 31 of the second sacrificial layer 303 in the third region III, the thickness TS 32 of the second active layer 304 in the third region III, and the thickness TS 41 of the third sacrificial layer 405 in the fourth region VI.
- the thickness T 3 ′ of the third isolation insulating layer 310 may be greater than the thickness TS 41 of the third sacrificial layer 405 in the fourth region VI and the thickness TS 42 of the third active layer 406 in the fourth region VI.
- the fourth isolation insulating layer 410 may have a thickness T 4 ′.
- FIGS. 14 to 32 are views illustrating, e.g., sequential, stages in a method for fabricating a semiconductor device according to some embodiments.
- FIGS. 15, 17, 19, 21, 23, 25, 27, 29, and 31 are cross-sectional views taken along line A-A′ of FIG. 14 .
- FIGS. 16, 18, 20, 22, 24, 26, 30, and 32 are cross-sectional views taken along line B-B′ of FIG. 14 .
- a laminate structure ST 1 in which sacrificial layers 1001 , 1002 , 1003 , and 1004 and active layers 1011 , 1012 , 1013 , and 1014 are alternately stacked may be formed on the substrate 100 .
- the active layers 1011 , 1012 , 1013 , and 1014 may contain a material having an etching selectivity with respect to the sacrificial layers 1001 , 1002 , 1003 , and 1004 .
- the sacrificial layers 1001 , 1002 , 1003 , and 1004 and the active layers 1011 , 1012 , 1013 , and 1014 may be formed by, e.g., an epitaxial growth method.
- the sacrificial layers 1001 , 1002 , 1003 , and 1004 may contain silicon germanium
- the active layers 1011 , 1012 , 1013 , and 1014 may contain silicon.
- the present disclosure is not limited thereto.
- the active layer 1014 is disposed at the uppermost portion of the laminate structure ST 1 for simplicity of description, the present disclosure is not limited thereto.
- a sacrificial layer may be disposed at the uppermost portion of the laminate structure ST 1 .
- the buffer layer 1500 may contain, e.g., silicon oxide.
- a first mask pattern 1600 may be formed on the buffer layer 1500 .
- the first mask pattern 1600 may be elongated in the first direction X 1 .
- an etching process may be performed using the first mask pattern 1600 as an etching mask.
- the laminate structure ST 1 may be etched to form a stacked structure S 1 .
- the etching process may be performed from the top surface to the laminate structure ST 1 to at least a part of the first sacrificial layer 1001 disposed at the lowermost portion.
- at least a part of the top surface of the first sacrificial layer 1001 may be exposed by the etching process. For example, as illustrated in FIG.
- a first portion of the first sacrificial layer 1001 may be at the bottom of the stacked structure S 1 to overlap the bottoms of the layers of the stacked structure S 1 , while a second portion of the first sacrificial layer 1001 may be adjacent to the first portion but not overlapping the bottom of stacked structure S 1 , e.g., a thickness of the second portion of the first sacrificial layer 1001 may be less than a thickness of the first portion of the first sacrificial layer 1001 relative to the substrate 100 .
- the first to fourth active layers 1011 , 1012 , 1013 , and 1014 may be etched to form first to fourth active patterns 122 , 124 , 126 , and 128 extending in the first direction X 1 .
- the stacked structure S 1 protruding from the first sacrificial layer 1001 in the third direction Z 1 may be formed.
- the stacked structure S 1 may include a part of the first sacrificial layer 1001 , and the first to fourth sacrificial layers 1001 , 1002 , 1003 , and 1004 , and the first to fourth active patterns 122 , 124 , 126 , and 128 .
- a liner layer 1700 may be formed.
- the liner layer 1700 may be formed to be conformal on the top surface and the side surface of the first mask pattern 1600 , the side surface of the stacked structure S 1 , and the exposed top surface of the first sacrificial layer 1001 .
- a part of the liner layer 1700 formed on the top surface of the first sacrificial layer 1001 exposed by the stacked structure S 1 may be removed by isotropic etching, e.g., a part of the liner layer 1700 may be removed from the second portion of the first sacrificial layer 1001 that does not overlap the bottom of the stacked structure S 1 .
- the liner layer 1700 may surround the top surface and the side surface of the first mask pattern 1600 and the side surface of the stacked structure S 1 .
- the liner layer 1700 may contain, e.g., the same material as the material contained in the first mask pattern 1600 .
- the liner layer 1700 may include, e.g., silicon nitride, but is not limited thereto.
- the first sacrificial layer 1001 exposed by the liner layer 1700 may be removed.
- the first sacrificial layer 1001 may be completely removed through the second portion of the first sacrificial layer 1001 that is exposed by the liner layer 1700 , e.g., including the first portion of the first sacrificial layer 1001 between the substrate 100 and the active pattern 122 .
- a pre-isolation insulating layer 110 P may be formed on the substrate 100 .
- the pre-isolation insulating layer 110 P may be formed on the substrate 100 and along the sides and bottom of the stacked structure, e.g., including in the space between the substrate 100 and the active pattern 122 . Accordingly, the space from which the first sacrificial layer 1001 has been removed can be filled with the pre-isolation insulating layer 110 P.
- an etching process may be performed using, as an etching mask, the liner layer 1700 disposed on the top surface of the first mask pattern 1600 . Accordingly, the side surfaces of the active patterns 122 , 124 , 126 , and 128 and the side surfaces of the sacrificial layers 1002 , 1003 , and 1004 may be exposed.
- the isolation insulating layer 110 may be formed in the space from which the first sacrificial layer 1001 has been removed. That is, a portion of the pre-isolation insulating layer 110 P between the substrate 100 and the active pattern 122 may become the isolation insulating layer 110 .
- the liner layer 1700 , the first mask pattern 1600 , and the buffer layer 1500 may be removed. Then, a dummy gate electrode 140 P extending in the second direction Y 1 may be formed on the fourth active pattern 128 .
- the dummy gate electrode 140 P may be formed using a second mask pattern 1800 as an etching mask.
- a dummy gate dielectric layer or a protective layer may be further formed between the dummy gate electrode 140 P and the fourth active pattern 128 .
- a pre-gate spacer 150 P may be formed on the sidewall of the dummy gate electrode 140 P.
- the first source/drain region 160 may be formed on both sides of the dummy gate electrode 140 P.
- the sacrificial layers 1002 , 1003 , and 1004 and the active patterns 122 , 124 , 126 , and 128 may be partially removed to form the first source/drain region 160 .
- the sacrificial layers 1002 , 1003 , and 1004 and the active patterns 122 , 124 , 126 , and 128 are partially removed, at least a part of the sacrificial layers 1002 , 1003 , and 1004 overlapping the pre-gate spacer 150 P may be further removed.
- the first inner spacers 151 may be formed at the positions where the sacrificial layers 1002 , 1003 , and 1004 are further removed.
- the first source/drain region 160 may be formed on both sides of the dummy gate electrode 140 P.
- an interlayer insulating layer 180 covering the first source/drain region 160 may be formed on the isolation insulating layer 110 .
- the dummy gate electrode 140 P may be exposed by the interlayer insulating layer 180 .
- the second mask pattern 1800 may be removed during the formation of the interlayer insulating layer 180 . Further, the first outer spacer 152 may be formed on the first inner spacer 151 during the formation of the interlayer insulating layer 180 . Accordingly, the gate spacer 150 including the inner spacers 151 and the outer spacer 152 may be formed.
- the dummy gate electrode 140 P and the sacrificial layers 1002 , 1003 , and 1004 may be removed. Accordingly, a trench 140 T elongated in the second direction Y 1 may be formed. Further, the first active patterns 122 , 124 , 126 , and 128 may be exposed.
- the first lower active pattern 122 may be formed on the isolation insulating layer 110 .
- the first sub-active pattern 124 may be spaced apart from the first lower active pattern 122
- the second sub-active pattern 126 may be spaced apart from the first sub-active pattern 124
- the third sub-active pattern 128 may be spaced apart from the second sub-active pattern 126 .
- the first gate dielectric layer 130 and the first gate electrode 140 may be formed in the trench 140 T.
- the first gate electrode 140 that is a single layer is illustrated for simplicity of description, the technical spirit of the present disclosure is not limited thereto.
- the first gate electrode 140 may be a multiple layer.
- the first gate electrode 140 may include a work function adjusting layer to adjust the work function and a filling conductive layer to fill a space formed by the work function adjusting layer.
- the semiconductor device according to some embodiments uses a bulk silicon substrate, rather than an SOI substrate, so that it is possible to form the semiconductor device including the first isolation insulating layer 110 on the substrate 100 .
- FIGS. 33 to 36 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments.
- FIGS. 33 and 35 are cross-sectional views taken along line A-A′ of FIG. 14 .
- FIGS. 34 and 36 are cross-sectional views taken along line B-B′ of FIG. 14 .
- FIG. 33 is a view subsequent to FIG. 27 and FIG. 34 is a view subsequent to FIG. 28 .
- the first source/drain region 160 may be formed on both sides of the dummy gate electrode 140 P.
- the sacrificial layers 1002 , 1003 , and 1004 and the active patterns 122 , 124 , 126 , and 128 may be partially removed to form the first source/drain region 160 .
- the sacrificial layers 1002 , 1003 , and 1004 and the active patterns 122 , 124 , 126 , and 128 are partially removed, at least a part of the sacrificial layers 1002 , 1003 , and 1004 overlapping the pre-gate spacer 150 P may be further removed.
- the first inner spacers 151 may be formed at the positions where the active pattern 122 , 124 , 126 , and 128 are further removed.
- the first source/drain region 160 may be formed on both sides of the dummy gate electrode 140 P.
- the interlayer insulating layer 180 covering the first source/drain region 160 may be formed on the isolation insulating layer 110 .
- the dummy gate electrode 140 P may be exposed by the interlayer insulating layer 180 .
- the second mask pattern 1800 may be removed during the formation of the interlayer insulating layer 180 . Further, the first outer spacer 152 may be formed on the first inner spacer 151 during the formation of the interlayer insulating layer 180 . Accordingly, the gate spacer 150 including the inner spacers 151 and the outer spacer 152 may be formed. Further, the outer spacer 152 may be formed on the inner spacer 151 .
- the dummy gate electrode 140 P and the active patterns 122 , 124 , 126 , and 128 may be removed. Accordingly, the trench 140 T elongated in the second direction Y 1 may be formed. Further, the sacrificial layers 1002 , 1003 , and 1004 may be exposed. The second to fourth sacrificial layers 1002 , 1003 , and 1004 may be spaced apart from each other. In other words, the second to fourth sacrificial layers 1002 , 1003 , and 1004 may be used as active patterns.
- the second to fourth sacrificial layers 1002 , 1003 , and 1004 may correspond to the first active patterns 124 , 126 , and 128 of FIGS. 4 and 5 .
- the first gate dielectric layer 130 and the first gate electrode 140 may be formed in the trench 140 T.
- FIGS. 37 to 40 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments.
- FIGS. 37 to 40 are cross-sectional views taken along line B-B′ of FIG. 14 .
- FIG. 37 is a view subsequent to FIG. 16 .
- an etching process may be performed using the first mask pattern 1600 as an etching mask.
- the etching process may be performed from the top surface of the laminate structure to at least a part of the first active layer 1011 disposed at the lowermost portion.
- the second to fourth active layers 1012 , 1013 , and 1014 may be etched to form the second to fourth active patterns 124 , 126 , and 128 extending in the first direction X 1 .
- a stacked structure protruding from the first active pattern 122 in the third direction Z 1 may be formed.
- the stacked structure may be formed on the first sacrificial layer 1001 , and may include the first to fourth active patterns 122 , 124 , 126 , and 128 and the second to fourth sacrificial layers 1002 , 1003 , and 1004 .
- the position of the stopper of the etching process may be set in consideration of an etching material and/or an etching time. Accordingly, a sacrificial layer or an active layer at a desired position may be set as the stopper of the etching process, and the top surface thereof may be exposed. Therefore, the number of active patterns included in the semiconductor device may be adjusted.
- a liner layer 1700 may be formed.
- the liner layer 1700 may be formed to be conformal to the top surface and the side surface of the first mask pattern 1600 , the side surface of the stacked structure, and the exposed top surface of the first active pattern 122 . Then, a part of the liner layer 1700 formed on the top surface of the first active pattern 122 exposed by the stacked structure may be removed by isotropic etching. Accordingly, the liner layer 1700 may surround the top surface and the side surface of the first mask pattern 1600 , and the side surface of the stacked structure.
- the first active pattern 122 exposed by the liner layer 1700 may be removed.
- the first sacrificial layer 1001 and the second sacrificial layer 1002 exposed by the removal of the first active pattern 122 may be removed. Then, the first isolation insulating layer 110 may be formed in the space from which the first sacrificial layer 1001 , the first active pattern 122 , and the second sacrificial layer 1002 have been removed.
- the first gate dielectric layer 130 and the first gate electrode 140 may be formed.
- the first active pattern 122 , the first sacrificial layer 1001 , and the second sacrificial layer 1002 may be removed to form the first isolation insulating layer 110 .
- FIGS. 41 and 42 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments.
- FIGS. 41 and 42 are cross-sectional views taken along lines C-C′ and D-D′ of FIG. 8 .
- FIG. 37 is a view subsequent to FIG. 22 .
- a first liner layer 1700 may be formed on the first region I, and a second liner layer 2700 may be formed on the second region II.
- the sacrificial layer on the first region I and the sacrificial layer on the second region II may be removed.
- a third mask pattern may be formed on the first region I.
- a second pre-isolation insulating layer 210 P may be formed on the second region II exposed by the third mask pattern. Accordingly, the space from which the sacrificial layer has been removed on the second region II can be filled.
- an etching process may be performed using, as an etching mask, the second liner layer 2700 disposed on the top surface of the second mask pattern 2600 in the second region II. Accordingly, the side surfaces of the second active patterns 222 , 224 , 226 , and 228 and the side surfaces of the second sacrificial layers 2002 , 2003 , and 2004 may be exposed. Further, the second isolation insulating layer 210 may be formed.
- a fourth mask pattern may be formed on the second region II, and the third mask pattern on the first region I may be removed.
- a first pre-isolation insulating layer may be formed on the second region II exposed by the fourth mask pattern. Accordingly, the space from which the sacrificial layer has been removed on the first region I can be filled.
- an etching process may be performed using, as an etching mask, the first liner layer 1700 disposed on the top surface of the first mask pattern 1600 in the first region I. Accordingly, the side surfaces of the first active patterns 122 , 124 , 126 , and 128 and the side surfaces of the first sacrificial layers 1002 , 1003 , and 1004 may be exposed. Further, the first isolation insulating layer 210 may be formed.
- the first region I may include the first isolation insulating layer 110 and the first gate electrode 140 formed on the first isolation insulating layer 110
- the second region II may include the second isolation insulating layer 210 containing a material different from the material contained in the first isolation insulating layer 110 and the second gate electrode 240 formed on the second isolation insulating layer 210 .
- aspects of the present disclosure provide a semiconductor device with improved product reliability. Aspects of the present disclosure also provide a method for fabricating a semiconductor device with improved product reliability.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
- Korean Patent Application No. 10-2020-0095308, filed on Jul. 30, 2020, in the Korean Intellectual Property Office, and entitled: “Semiconductor Device and Method for Fabricating the Same,” is incorporated by reference herein in its entirety.
- The present disclosure relates to a semiconductor device and a method for fabricating the same.
- As one of scaling techniques for increasing the density of integrated circuit devices, a multi-gate transistor has been proposed, in which a fin-shaped or a nanowire-shaped silicon body is formed on a substrate, and a gate is formed on the surface of the silicon body. Since the multi-gate transistor uses a three-dimensional (3D) channel, scaling of the multi-gate transistor can be easily achieved. Further, current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, a short channel effect (SCE) in which the potential of a channel region is affected by a drain voltage can be effectively suppressed.
- Embodiments may be realized by providing a semiconductor device including a substrate having a first region and a second region separated from each other, a laminate structure in which at least one sacrificial layer and at least one active layer are alternately stacked on the substrate, a first isolation insulating layer disposed on the laminate structure on the first region, a second isolation insulating layer disposed on the laminate structure on the second region and having substantially the same thickness as the first isolation insulating layer, a first upper active pattern spaced apart from the first isolation insulating layer, a first gate electrode surrounding at least a part of the first upper active pattern, a second upper active pattern spaced apart from the second isolation insulating layer, and a second gate electrode surrounding at least a part of the second upper active pattern, wherein a top surface of the first isolation insulating layer and a top surface of the second isolation insulating layer are disposed at different heights.
- Embodiments may also be realized by providing a semiconductor device including a substrate having a first region and a second region different from each other, a first isolation insulating layer disposed on the first region, a first active pattern disposed on the first isolation insulating layer, a first gate electrode surrounding at least a part of the first active pattern, a second isolation insulating layer disposed on the second region, a second active pattern disposed on the second isolation insulating layer, and a second gate electrode surrounding at least a part of the second active pattern, wherein the first isolation insulating layer and the second isolation insulating layer include different materials.
- Embodiments may still be realized by providing a method for fabricating a semiconductor device including forming a laminate structure in which sacrificial layers and active layers are alternately stacked on a substrate including a first region and a second region separated from each other, etching the laminate structure on the first region to form a first stacked structure protruding from a first sacrificial layer among the sacrificial layers, removing the first sacrificial layer and forming a first isolation insulating layer in a space from which the first sacrificial layer has been removed, etching the laminate structure on the second region to form a second stacked structure protruding from a second sacrificial layer among the sacrificial layers, removing the second sacrificial layer and forming a second isolation insulating layer in a space from which the second sacrificial layer has been removed, removing the sacrificial layer included in the first stacked structure and the second stacked structure, and forming a gate electrode in a space from which the sacrificial layer has been removed to form a gate structure, wherein the first isolation insulating layer and the second isolation insulating layer are formed at different heights.
- Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
-
FIG. 1 is a schematic plan view of a semiconductor device according to some embodiments; -
FIG. 2 is a cross-sectional view taken along line A-A′ ofFIG. 1 ; -
FIG. 3 is a cross-sectional view taken along line B-B′ ofFIG. 1 ; -
FIG. 4 is a cross-sectional view taken along line A-A′ ofFIG. 1 , according to some embodiments; -
FIG. 5 is a cross-sectional view taken along line B-B′ ofFIG. 1 , according to some embodiments; -
FIG. 6 is a cross-sectional view taken along line A-A′ ofFIG. 1 , according to some embodiments; -
FIG. 7 is a cross-sectional view taken along line B-B′ ofFIG. 1 , according to some embodiments; -
FIG. 8 is a schematic plan view of a semiconductor device according to some other embodiments; -
FIG. 9 is a cross-sectional view taken along lines C-C′ and D-D′ ofFIG. 8 ; -
FIGS. 10A and 10B are graphs showing electron mobility and hole mobility with respect to vertical stress applied to a channel, respectively; -
FIG. 11 is a schematic plan view illustrating a semiconductor device according to some other embodiments; -
FIG. 12 is a cross-sectional view taken along lines E-E′, F-F′, G-G′, and H-H′ ofFIG. 11 ; -
FIG. 13 is a cross-sectional view taken along lines E-E′, F-F′, G-G′, and H-H′ ofFIG. 11 , according to some embodiments; -
FIGS. 14 to 32 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments; -
FIGS. 33 to 36 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments; -
FIGS. 37 to 40 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments; and -
FIGS. 41 and 42 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments. -
FIG. 1 is a schematic plan view illustrating a semiconductor device according to some embodiments.FIG. 2 is a cross-sectional view taken along line A-A′ ofFIG. 1 .FIG. 3 is a cross-sectional view taken along line B-B′ ofFIG. 1 . - Referring to
FIGS. 1 to 3 , a semiconductor device according to some embodiments may include asubstrate 100, a firstisolation insulating layer 110, firstactive patterns gate dielectric layer 130, afirst gate electrode 140, afirst gate spacer 150, a first source/drain region 160, and an interlayer insulatinglayer 190. In some embodiments, thesubstrate 100 may be a bulk silicon substrate. - The first
isolation insulating layer 110 may be disposed on thesubstrate 100. The firstisolation insulating layer 110 may include, e.g., at least one of silicon oxide, silicon oxynitride, silicon nitride or a combination thereof, but the present disclosure is not limited thereto. - The first
active patterns isolation insulating layer 110. The firstactive patterns active pattern 122 disposed on the firstisolation insulating layer 110, and a first upperactive pattern 123 disposed on the first loweractive pattern 122 The firstactive patterns - The first lower
active pattern 122 may be in, e.g., direct, contact with the firstisolation insulating layer 110. The first loweractive pattern 122 may be an active pattern disposed at a lowermost portion among the firstactive patterns first gate electrode 140. - The first upper
active pattern 123 may be disposed on the first loweractive pattern 122. The first upperactive pattern 123 may include a plurality ofsub-active patterns substrate 100, e.g., in a third direction Z1. For example, the firstsub-active pattern 124 may be disposed on the first loweractive pattern 122, and the secondsub-active pattern 126 may be disposed on the firstsub-active pattern 124, and the thirdsub-active pattern 128 may be disposed on the secondsub-active pattern 126. The firstsub-active pattern 124, the secondsub-active pattern 126, and the thirdsub-active pattern 128 may overlap each other in the third direction Z1. - The first upper
active pattern 123 may be spaced apart from the first loweractive pattern 122 in the third direction Z1. The firstsub-active pattern 124, the secondsub-active pattern 126, and the thirdsub-active pattern 128 may be spaced apart from each other in the third direction Z1. For example, the firstsub-active pattern 124 may be spaced apart from the first loweractive pattern 122, the secondsub-active pattern 126 may be spaced apart from the firstsub-active pattern 124, and the thirdsub-active pattern 128 may be spaced apart from the secondsub-active pattern 126. - In some embodiments, the first
active patterns - Each of the first
active patterns first gate electrode 140. Although three sub-active patterns of the first upperactive pattern 123 are illustrated inFIG. 2 andFIG. 3 for simplicity of description, the present disclosure is not limited thereto. For example, the semiconductor device according to some embodiments may include two or less sub-active patterns or four or more sub-active patterns. - The
first gate electrode 140 may be disposed on the firstisolation insulating layer 110. Thefirst gate electrode 140 may intersect the firstactive patterns first gate electrode 140 may be parallel to the top surface of thesubstrate 100 and may be elongated in the second direction Y1. - The first
active patterns first gate electrode 140 while extending in the first direction X1. Accordingly, thefirst gate electrode 140 may be formed to surround the first upperactive pattern 123. Further, thefirst gate electrode 140 may be formed to surround, e.g., portions of, the first loweractive pattern 122 that are not in contact with the firstisolation insulating layer 110. - The
first gate electrode 140 may include a conductive material. For example, thefirst gate electrode 140 may include at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al or a combination thereof, but is not limited thereto. Thefirst gate electrode 140 may be formed, e.g., by a replacement process, but is not limited thereto. - Although the
first gate electrode 140 that is a single layer is illustrated, this is merely an example, and thefirst gate electrode 140 may be formed by stacking a plurality of conductive materials. For example, thefirst gate electrode 140 may include a work function adjusting layer to adjust the work function and a filling conductive layer to fill a space formed by the work function adjusting layer. The work function adjusting layer may include at least one of, e.g., TiN, TaN, TiC, TaC, TiAlC or a combination thereof. The filling conductive layer may include, e.g., W or Al. - The first
gate dielectric layer 130 may be interposed between thefirst gate electrode 140 and each of firstactive patterns gate dielectric layer 130 may be formed to surround the first upperactive pattern 123. The firstgate dielectric layer 130 may be formed to surround portions of the first loweractive pattern 122 that are not in contact with the firstisolation insulating layer 110, e.g., the firstgate dielectric layer 130 may not separate between a bottom of the first loweractive pattern 122 and the firstisolation insulating layer 110. The firstgate dielectric layer 130 may extend along the top surface of the firstisolation insulating layer 110. - The first
gate dielectric layer 130 may include, e.g., at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, e.g., at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and a combination thereof, but is not limited thereto. - An interface layer may be formed between each of the first
active patterns gate dielectric layer 130. The interface layer may be formed to surround the first upperactive pattern 123 and to surround portions of the first loweractive pattern 122 that are not in contact with the firstisolation insulating layer 110, and may extend along the top surface of the firstisolation insulating layer 110. However, the present disclosure is not limited thereto. - The first source/
drain region 160 may be formed on the firstisolation insulating layer 110. Further, the first source/drain region 160 may be disposed on the side surface of thefirst gate electrode 140. For example, the first source/drain region 160 may be disposed on both, e.g., opposite, side surfaces of thefirst gate electrode 140. - The first source/
drain region 160 may be spaced, e.g., separated, apart from thefirst gate electrode 140 by thefirst gate spacer 150 to be described later. Further, the first source/drain region 160 may be, e.g., directly, connected to the firstactive patterns active patterns drain region 160 while penetrating thefirst gate spacer 150. The first source/drain region 160 may be used as a source/drain region of a transistor including thefirst gate electrode 140. - The first source/
drain region 160 may include an epitaxial layer formed on thesubstrate 100. For example, the first source/drain region 160 may be formed by an epitaxial growth method. Although the first source/drain region 160 that is a single layer is illustrated, this is merely an example and the first source/drain region 160 may be formed by stacking a plurality of epitaxial layers. For example, the first source/drain region 160 may include a plurality of epitaxial layers having different impurity concentrations, which are sequentially stacked on theisolation insulating layer 110. - In some embodiments, the first source/
drain region 160 may be a raised source/drain region including a top surface protruding more upward than the top surface of thesubstrate 100. The first source/drain region 160 may protrude more upward than the topmost surface of the first upperactive pattern 123 penetrating thefirst gate electrode 140. For example, the top surface of the first source/drain region 160 may protrude more upward than the top surface of the thirdsub-active pattern 128. - In the case where the semiconductor device according to some embodiments is an NMOS transistor, the first source/
drain region 160 may include n-type impurities or impurities for preventing the diffusion of n-type impurities. For example, the first source/drain region 160 may contain at least one of P, Sb, As, or a combination thereof - In addition, when the semiconductor device according to some embodiments is an NMOS transistor, the first source/
drain region 160 may include a tensile stress material. For example, when the firstactive patterns drain region 160 may include a material, e.g., SiC, having a smaller lattice constant than silicon (Si). The tensile stress material may apply tensile stress to the firstactive patterns - Alternatively, when the semiconductor device according to some embodiments is a PMOS transistor, the first source/
drain region 160 may include p-type impurities or impurities for preventing the diffusion of p-type impurities. For example, the first source/drain region 160 may include at least one of B, C, In, Ga, Al or a combination thereof - In addition, when the semiconductor device according to some embodiments is a
- PMOS transistor, the first source/
drain region 160 may include a compressive stress material. For example, when the firstactive patterns drain region 160 may include a material having a larger lattice constant than silicon (Si). For example, the first source/drain region 160 may include SiGe. The compressive stress material may apply compressive stress to the firstactive patterns - The
first gate spacer 150 may be disposed on theisolation insulating layer 110. Thefirst gate spacer 150 may extend along the side surface of thefirst gate electrode 140. Thefirst gate spacer 150 may electrically insulate thefirst gate electrode 140 from the first source/drain region 160. - The first
active patterns first gate spacer 150 while extending in the first direction X1. Thefirst gate spacer 150 may be disposed at the ends of the firstactive patterns first gate space 150 may be formed to surround the ends of the firstactive patterns - The
first gate spacer 150 may include firstinner spacers 151 and a firstouter spacer 152. The firstinner spacers 151 may be disposed between the loweractive pattern 122 and the firstsub-active pattern 124, between the firstsub-active pattern 124 and the secondsub-active pattern 126, and between the secondsub-active pattern 126 and the third sub-upperactive pattern 128. - The first
inner spacers 151 may be disposed at positions vertically overlapping the firstactive patterns outer spacer 152 may be disposed on the thirdsub-active pattern 128 disposed at an uppermost portion among the firstactive patterns sub-active pattern 128 may be between the firstouter spacer 152 and a topmost of the firstinner spacers 151. - The first
inner spacer 151 may include, e.g., at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxynitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC) or a combination thereof. The firstouter spacer 152 may include, e.g., at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN) or a combination thereof. The firstinner spacer 151 and the firstouter spacer 152 may contain different materials, or may contain the same material. - In some embodiments, the first lower
active pattern 122 and the firstsub-active pattern 124 may be spaced apart from each other by a first distance D1, e.g., along the direction Z1, the firstsub-active pattern 124 and the secondsub-active pattern 126 may be spaced apart from each other by the first distance D1, e.g., along the direction Z1, and the secondsub-active pattern 126 and the thirdsub-active pattern 128 may be spaced apart from each other by the first distance D1, e.g., along the direction Z1. A thickness T1 of the firstisolation insulating layer 110, e.g., along the direction Z1, may be substantially the same as the distance D1 between the first loweractive pattern 122 and the firstsub-active pattern 124. - The interlayer insulating
layer 190 may be disposed on the firstisolation insulating layer 110 and the first source/drain region 160. The interlayer insulatinglayer 190 may surround the sidewall of thefirst gate spacer 150. The interlayer insulatinglayer 190 may be formed to fill the space on the side surface of thefirst gate electrode 140. - The interlayer insulating
layer 190 may include, e.g., at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. The low-k dielectric material may include, for example, at least one of flowable oxide (FOX), Tonen Silazene (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetra ethyl ortho silicate (PETEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO), Xerogel, Aerogel, amorphous fluorinated carbon, organo silicate glass (OSG), parylene, bis-benzocyclobutene (BCB), SiLK, polyimide, a porous polymeric material, or a combination thereof, but is not limited thereto. - During fabrication of a semiconductor device including an active pattern directly on a bulk silicon substrate, e.g., without an insulator therebetween, fins are formed on the substrate. Accordingly, since a punch through may occur, a punch through stopper may be formed on the fins to reduce or prevent the punch through. While the punch through stopper may reduce the punch through, the fins may have higher threshold voltages than those of the active patterns due to the punch through stopper, thereby deteriorating performance of the semiconductor device.
- In contrast, while the semiconductor device according to some embodiments does not include a silicon-on-insulator (SOI) substrate, the lower portions of the active patterns may be insulated from the
substrate 100 by the firstisolation insulating layer 110. Further, the active patterns are formed on the firstisolation insulating layer 110, and fins are not included. Accordingly, the firstisolation insulating layer 110 may apply stress to the active pattern, which makes it possible to reduce or prevent punch through. In addition, the performance of the semiconductor device can be improved or enhanced. -
FIGS. 4 and 5 are cross-sectional views illustrating a semiconductor device according to some other embodiments.FIG. 4 is a cross-sectional view taken along line A-A′ ofFIG. 1 .FIG. 5 is a cross-sectional view taken along line B-B′ ofFIG. 1 . For simplicity of description, descriptions of features described previously with reference toFIGS. 2 and 3 will be omitted or described only briefly. - Referring to
FIGS. 4 and 5 , a semiconductor device according to some other embodiments may include the firstactive pattern 123. - The first
active pattern 123 may include the first to thirdsub-active patterns isolation insulating layer 110. For example, the firstsub-active pattern 124 may be spaced apart from the firstisolation insulating layer 110, the secondsub-active pattern 126 may be spaced apart from the firstsub-active pattern 124, and the thirdsub-active pattern 128 may be spaced apart from the secondsub-active pattern 126. In other words, the firstsub-active pattern 124 may be a first active pattern on the firstisolation insulating layer 110, i.e., without the first loweractive pattern 122 ofFIGS. 2 and 3 . In some embodiments, the firstactive pattern 123 may contain silicon germanium (SiGe). - In some embodiments, the first to third
sub-active patterns isolation insulating layer 110 may be substantially the same as the thickness TA1 of each of the first to thirdsub-active patterns -
FIGS. 6 and 7 are cross-sectional views illustrating a semiconductor device according to some other embodiments.FIG. 6 is a cross-sectional view taken along line A-A′ ofFIG. 1 .FIG. 7 is a cross-sectional view taken along line B-B′ ofFIG. 1 . For simplicity of description, descriptions of features described previously with reference toFIGS. 2 and 3 will be omitted or described only briefly. - Referring to
FIGS. 6 and 7 , in the semiconductor device according to some other embodiments, the firstactive pattern 122 may contain silicon (Si). The firstactive patterns active pattern 122 disposed on the firstisolation insulating layer 110, and the first upperactive pattern 123 spaced apart from the first loweractive pattern 122. For example, when the firstactive pattern 122 contains silicon germanium (SiGe), the first loweractive pattern 122 may be omitted unlike the drawing. - A thickness T1′ of the first
isolation insulating layer 110, e.g., along the direction Z1, may be greater than the thickness TA1 of each of the firstactive patterns active patterns -
FIG. 8 is a schematic plan view illustrating a semiconductor device according to some other embodiments.FIG. 9 is a cross-sectional view taken along lines C-C′ and D-D′ ofFIG. 8 .FIGS. 10A and 10B are graphs showing electron mobility and hole mobility with respect to vertical stress applied to a channel, respectively. For simplicity of description, descriptions of features described previously with reference toFIGS. 2 and 3 will be omitted or described only briefly. - Referring to
FIGS. 8 to 10B , in the semiconductor device according to some other embodiments, thesubstrate 100 may include a first region I and a second region II different from each other. The first region I and the second region II of thesubstrate 100 may be adjacent to each other or may be spaced apart from each other. The first region I and the second region II of thesubstrate 100 may be, e.g., horizontally separated regions. - Different types of transistors may be formed in the first region I and the second region II of the
substrate 100. In some embodiments, when an NMOS transistor is formed in the first region I of thesubstrate 100, a PMOS transistor may be formed in the second region II of thesubstrate 100. - A first
isolation insulating layer 110 may be disposed on the first region I of thesubstrate 100. Firstactive patterns isolation insulating layer 110. The first loweractive pattern 122 may be in contact with the firstisolation insulating layer 110, and the first upperactive pattern 123 may be spaced apart from the firstisolation insulating layer 110. - The
first gate electrode 140 may be disposed on the firstisolation insulating layer 110. Thefirst gate electrode 140 may be formed to surround the firstactive patterns gate dielectric layer 130 may be interposed between the firstactive patterns first gate electrode 140. - A second
isolation insulating layer 210 may be disposed on the second region II of thesubstrate 100. Secondactive patterns isolation insulating layer 210. The second loweractive pattern 222 may be in, e.g., direct, contact with the secondisolation insulating layer 210, and the second upperactive pattern 223 may be spaced apart from the secondisolation insulating layer 210. - A
second gate electrode 240 may be disposed on the secondisolation insulating layer 210. Thesecond gate electrode 240 may be formed to surround the secondactive patterns gate dielectric layer 230 may be interposed between the secondactive patterns second gate electrode 240. - A
second gate spacer 250 may be disposed on the secondisolation insulating layer 210. Thesecond gate spacer 250 may extend along the side surface of thesecond gate electrode 240. Thesecond gate spacer 250 may electrically insulate thesecond gate electrode 240 from a second source/drain region 260. - In some embodiments, a thickness T1_1 of the first
isolation insulating layer 110 may be substantially the same as a thickness T1_2 of the secondisolation insulating layer 210. The firstisolation insulating layer 110 and the secondisolation insulating layer 210 may contain different materials. Accordingly, the stress applied to the firstactive patterns isolation insulating layer 110 and the stress applied to the secondactive patterns isolation insulating layer 210 may have different directions. - In detail, the first
isolation insulating layer 110 may apply compressive vertical stress (a) to the first loweractive pattern 122. In other words, the firstisolation insulating layer 110 may apply the stress from the firstisolation insulating layer 110 toward the first loweractive pattern 122. - The second
isolation insulating layer 210 may apply tensile vertical stress (b) to the second loweractive pattern 222. In other words, the secondisolation insulating layer 210 may apply the stress from the second loweractive pattern 222 toward the secondisolation insulating layer 210. -
FIG. 10A is a graph showing the electron mobility with respect to vertical stress applied to a channel containing silicon.FIG. 10B is a graph showing the hole mobility with respect to vertical stress applied to silicon. Vertical stress having a negative value means compressive stress, and vertical stress having a positive value means tensile stress. - Referring to
FIG. 10A , the electron mobility increases as the compressive vertical stress is applied to the channel, e.g., electron mobility ratio increases as the compressive vertical stress (negative values on the graph) increases. Referring toFIG. 10B , the hole mobility increases as the tensile vertical stress is applied to the channel, e.g., the hole mobility ratio increases as the tensile vertical stress (positive values on the graph) increases. - Therefore, in the semiconductor device according to some embodiments, an NMOS transistor is formed in the first region I and the first
isolation insulating layer 110 applies the compressive vertical stress (a) to the firstactive patterns active patterns isolation insulating layer 210 applies the tensile vertical stress (b) to the secondactive patterns active patterns - Accordingly, the semiconductor device may apply stress to the first
active patterns active patterns active patterns drain region 160, and also possible to apply the stress to the firstactive patterns isolation insulating layer 110. In addition, it is possible to apply the stress to the secondactive patterns drain region 260, and also possible to apply the stress to the secondactive patterns isolation insulating layer 210. Accordingly, the semiconductor device according to some other embodiments can apply stress to the active patterns more effectively compared to a semiconductor device formed on an SOI substrate and including active patterns. Therefore, the performance of the semiconductor device according to embodiments may be improved or enhanced. -
FIG. 11 is a schematic plan view illustrating a semiconductor device according to some other embodiments.FIG. 12 is a cross-sectional view taken along lines E-E′, F-F′, G-G′, and H-H′ ofFIG. 11 . For simplicity of description, descriptions of features described previously with reference toFIGS. 2 and 3 will be omitted or described only briefly. - Referring to
FIGS. 11 and 12 , in the semiconductor device according to some other embodiments, thesubstrate 100 may include the first region I, the second region II, and a third region III, and a fourth region IV different from each other. The first region I, the second region II, the third region III and the fourth region IV may be, e.g., horizontally separate regions. Although it is illustrated inFIGS. 11 and 12 that thesubstrate 100 includes four regions for simplicity of description, the present disclosure is not limited thereto. For example, the semiconductor device according to some embodiments may include five or more regions. - One or more
sacrificial layers active layers substrate 100. One or moresacrificial layers active layers substrate 100 and may be the same direction, e.g., but reflecting different respective regions on thesubstrate 100. For example, the firstsacrificial layers active layers sacrificial layers active layers sacrificial layer 405, and the thirdactive layer 406 may be sequentially stacked on thesubstrate 100. - The
sacrificial layers sacrificial layer 201 in the second region II, the firstsacrificial layer 301 in the third region III, and the firstsacrificial layer 401 in the fourth region VI may be the sacrificial layers on the same level. The secondsacrificial layer 303 in the third region III and the secondsacrificial layer 403 in the fourth region VI may be the sacrificial layers on the same level. - The
active layers active layer 202 in the second region II, the firstactive layer 302 in the third region III, and the firstactive layer 402 in the fourth region VI may be the active layers on the same level. The secondactive layer 304 in the third region III and the secondactive layer 404 in the fourth region VI may be the active layers on the same level. Here, the layers on the same level may mean the layers formed by the same manufacturing process. - In detail, the
sacrificial layers active layers sacrificial layer 201 and the firstactive layer 202 may be formed in the second region II. In the third region III, the secondsacrificial layer 303 and the secondactive layer 304 may be further formed in addition to the layers formed in the second region II. In the fourth region VI, the thirdsacrificial layer 403 and the thirdactive layer 404 may be further formed in addition to the layers formed in the third region III. - The
sacrificial layers active layers sacrificial layers active layers - The first to fourth regions I, II, III, and VI may include first to fourth
isolation insulating layers isolation insulating layers isolation insulating layers - The first to fourth
isolation insulating layers substrate 100. For example, the secondisolation insulating layer 210 may be disposed above the firstisolation insulating layer 110, the thirdisolation insulating layer 310 may be disposed above the secondisolation insulating layer 210, and the fourthisolation insulating layer 410 may be disposed above the thirdisolation insulating layer 310. In other words, the top surface of the firstisolation insulating layer 110, the top surface of the secondisolation insulating layer 210, the top surface of the thirdisolation insulating layer 310, and the top surface of the fourthisolation insulating layer 410 may be arranged at different heights. - The number of the
sacrificial layers active layers isolation insulating layers isolation insulating layer 110, n sacrificial layers (n being a natural number) and n active layers may be disposed. Under the secondisolation insulating layer 210, m sacrificial layers (m being a natural number) and m active layers may be disposed. In this case, n and m may be different from each other. In other words, the number of sacrificial layers disposed under the firstisolation insulating layer 110 and the number of active layers disposed under the firstisolation insulating layer 110 may be the same, but the number of sacrificial layers and the number of active layers disposed under the firstisolation insulating layer 110 may be different from the number of sacrificial layers and the number of active layers disposed under the secondisolation insulating layer 210. - For example, the first
sacrificial layer 201 and the firstactive layer 202 may be sequentially stacked under the secondisolation insulating layer 210. The firstsacrificial layer 301, the firstactive layer 302, the secondsacrificial layer 303, and the secondactive layer 304 may be sequentially stacked under the thirdisolation insulating layer 310. The firstsacrificial layer 401, the firstactive layer 402, the secondsacrificial layer 403, the secondactive layer 404, the thirdsacrificial layer 405, and the thirdactive layer 406 may be sequentially stacked under the fourthisolation insulating layer 410. - The first
isolation insulating layer 110 may be formed in the space from which the sacrificial layer in the first region I on the same level as the firstsacrificial layer 201 in the second region II has been removed. Therefore, the thickness T1 of the firstisolation insulating layer 110 may be substantially the same as a thickness TS21 of the firstsacrificial layer 201 in the second region II. - The second
isolation insulating layer 210 may be formed in the space from which the sacrificial layer in the second region II on the same level as the secondsacrificial layer 303 in the third region III has been removed. Therefore, a thickness T2 of the secondisolation insulating layer 210 may be substantially the same as a thickness TS31 of the secondsacrificial layer 303 in the third region III. - The third
isolation insulating layer 310 may be formed in the space from which the sacrificial layer in the third region III on the same level as the thirdsacrificial layer 405 in the fourth region VI has been removed. Therefore, a thickness T3 of the thirdisolation insulating layer 310 may be substantially the same as a thickness TS41 of the thirdsacrificial layer 405 in the fourth region VI. The fourthisolation insulating layer 410 may have a thickness T4. - The first lower
active pattern 122 may be formed by patterning the active layer in the first region I on the same level as the firstactive layer 202 in the second region II. Therefore, the first loweractive pattern 122 may be formed on the same level as the firstactive layer 202 in the second region II. The thickness TA1 of the first loweractive pattern 122 is substantially the same as a thickness TS22 of the firstactive layer 202 in the second region II. - The second lower
active pattern 222 may be formed by patterning the active layer in the second region II on the same level as the secondactive layer 304 in the third region III. Therefore, the second loweractive pattern 222 may be formed on the same level as the secondactive layer 304 in the third region III. The thickness TA2 of the second loweractive pattern 222 may be substantially the same as a thickness TS32 of the secondactive layer 304 in the third region III. - The third lower
active pattern 322 may be formed by patterning the active layer in the third region III on the same level as the thirdactive layer 406 in the fourth region VI. Therefore, the third loweractive pattern 322 may be formed on the same level as the thirdactive layer 406 in the fourth region VI. The thickness TA3 of the third loweractive pattern 322 may be substantially the same as a thickness TS42 of the thirdactive layer 406 in the fourth region VI. - Meanwhile, the
first gate electrode 140 may surround the firstactive patterns second gate electrode 240 may surround the secondactive patterns third gate electrode 340 may surround the thirdactive patterns 322 and 333, and thefourth gate electrode 440 may surround a fourthactive pattern 422. The fourthactive pattern 422 may have a thickness TA4. - The number of the first
active patterns active patterns active patterns active pattern 422 arranged on the fourth region VI may be different from each other. In other words, the area of the firstactive patterns first gate electrode 140, the area of the secondactive patterns second gate electrode 240, the area of the thirdactive patterns third gate electrode 340, and the area of the fourthactive pattern 422 surrounded by thefourth gate electrode 440 may be different from each other. Accordingly, the driving performance of the elements formed in the first to fourth regions I, II, III, and VI of the semiconductor device according to some embodiments may be different. Although it is illustrated inFIGS. 11 and 12 that the number of the firstactive patterns active patterns - The driving performance of the semiconductor device may vary depending on the contact area between the gate electrode and the active patterns. At this time, the size of the semiconductor device may be increased to increase the contact area between the gate electrode and the active patterns.
- However, in the semiconductor device according to some embodiments, the contact area between the gate electrode and the active pattern may be increased or decreased by adjusting the position where the active patterns are formed. In other words, the contact area between the gate electrode and the active patterns may be increased without increasing the area of the semiconductor device.
-
FIG. 13 is a cross-sectional view taken along lines E-E′, F-F′, G-G′, and H-H′ ofFIG. 11 . For simplicity of description, descriptions of features described previously with reference toFIGS. 11 and 12 will be omitted or described only briefly. - Referring to
FIGS. 11 and 13 , in the semiconductor device according to some other embodiments, the first to fourthisolation insulating layers - The first to fourth
isolation insulating layers isolation insulating layer 210 may overlap the firstisolation insulating layer 110, at least a part of the thirdisolation insulating layer 310 may overlap the secondisolation insulating layer 210, and at least a part of the fourthisolation insulating layer 410 may overlap the thirdisolation insulating layer 310. - The first
isolation insulating layer 110 may be formed in the space from which the sacrificial layer and the active layer on the same level as the firstsacrificial layer 201 in the second region II, the firstactive layer 202 in the second region II, and the secondsacrificial layer 303 in the third region III have been removed. Therefore, the thickness T1′ of the firstisolation insulating layer 110 may be greater than the thickness TS21 of the firstsacrificial layer 201 in the second region II and the thickness TS22 of the firstactive layer 202 in the second region II. Further, the thickness T1′ of the firstisolation insulating layer 110 may be substantially the same as the sum of the thickness TS21 of the firstsacrificial layer 201 in the second region II, the thickness TS22 of the firstactive layer 202 in the second region II, and the thickness TS31 of the secondsacrificial layer 303 in the third region III. - The second
isolation insulating layer 210 may be formed in the space from which the sacrificial layer and the active layer on the same level as the secondsacrificial layer 303 in the third region III, the secondactive layer 304 in the third region III, and the thirdsacrificial layer 405 in the fourth region VI have been removed. Therefore, the thickness T2′ of the secondisolation insulating layer 210 may be greater than the thickness TS31 of the secondsacrificial layer 303 in the third region III, and the thickness TS32 of the secondactive layer 304 in the third region III. Further, the thickness T2′ of the secondisolation insulating layer 210 may be substantially the same as the sum of the thickness TS31 of the secondsacrificial layer 303 in the third region III, the thickness TS32 of the secondactive layer 304 in the third region III, and the thickness TS41 of the thirdsacrificial layer 405 in the fourth region VI. - The thickness T3′ of the third
isolation insulating layer 310 may be greater than the thickness TS41 of the thirdsacrificial layer 405 in the fourth region VI and the thickness TS42 of the thirdactive layer 406 in the fourth region VI. The fourthisolation insulating layer 410 may have a thickness T4′. -
FIGS. 14 to 32 are views illustrating, e.g., sequential, stages in a method for fabricating a semiconductor device according to some embodiments. For reference,FIGS. 15, 17, 19, 21, 23, 25, 27, 29, and 31 are cross-sectional views taken along line A-A′ ofFIG. 14 .FIGS. 16, 18, 20, 22, 24, 26, 30, and 32 are cross-sectional views taken along line B-B′ ofFIG. 14 . - Referring to
FIGS. 14 to 16 , a laminate structure ST1 in whichsacrificial layers active layers substrate 100. - The
active layers sacrificial layers sacrificial layers active layers sacrificial layers active layers - Although the four
active layers sacrificial layers FIGS. 14 to 16 for simplicity of description, the present disclosure is not limited thereto. Further, although it is illustrated that theactive layer 1014 is disposed at the uppermost portion of the laminate structure ST1 for simplicity of description, the present disclosure is not limited thereto. For example, a sacrificial layer may be disposed at the uppermost portion of the laminate structure ST1. - Then, a
buffer layer 1500 may be formed on the laminate structure ST1. Thebuffer layer 1500 may contain, e.g., silicon oxide. - Then, a
first mask pattern 1600 may be formed on thebuffer layer 1500. Thefirst mask pattern 1600 may be elongated in the first direction X1. - Referring to
FIGS. 17 and 18 , an etching process may be performed using thefirst mask pattern 1600 as an etching mask. The laminate structure ST1 may be etched to form a stacked structure S1. - At this time, the etching process may be performed from the top surface to the laminate structure ST1 to at least a part of the first
sacrificial layer 1001 disposed at the lowermost portion. In other words, at least a part of the top surface of the firstsacrificial layer 1001 may be exposed by the etching process. For example, as illustrated inFIG. 18 , a first portion of the firstsacrificial layer 1001 may be at the bottom of the stacked structure S1 to overlap the bottoms of the layers of the stacked structure S1, while a second portion of the firstsacrificial layer 1001 may be adjacent to the first portion but not overlapping the bottom of stacked structure S1, e.g., a thickness of the second portion of the firstsacrificial layer 1001 may be less than a thickness of the first portion of the firstsacrificial layer 1001 relative to thesubstrate 100. Further, the first to fourthactive layers active patterns - Accordingly, the stacked structure S1 protruding from the first
sacrificial layer 1001 in the third direction Z1 may be formed. The stacked structure S1 may include a part of the firstsacrificial layer 1001, and the first to fourthsacrificial layers active patterns - Referring to
FIGS. 19 and 20 , aliner layer 1700 may be formed. Theliner layer 1700 may be formed to be conformal on the top surface and the side surface of thefirst mask pattern 1600, the side surface of the stacked structure S1, and the exposed top surface of the firstsacrificial layer 1001. Then, a part of theliner layer 1700 formed on the top surface of the firstsacrificial layer 1001 exposed by the stacked structure S1 may be removed by isotropic etching, e.g., a part of theliner layer 1700 may be removed from the second portion of the firstsacrificial layer 1001 that does not overlap the bottom of the stacked structure S1. Accordingly, theliner layer 1700 may surround the top surface and the side surface of thefirst mask pattern 1600 and the side surface of the stacked structure S1. - The
liner layer 1700 may contain, e.g., the same material as the material contained in thefirst mask pattern 1600. Theliner layer 1700 may include, e.g., silicon nitride, but is not limited thereto. - Referring to
FIGS. 21 and 22 , the firstsacrificial layer 1001 exposed by theliner layer 1700 may be removed. For example, as illustrated inFIG. 21 , the firstsacrificial layer 1001 may be completely removed through the second portion of the firstsacrificial layer 1001 that is exposed by theliner layer 1700, e.g., including the first portion of the firstsacrificial layer 1001 between thesubstrate 100 and theactive pattern 122. - Referring to
FIGS. 23 and 24 , a pre-isolationinsulating layer 110P may be formed on thesubstrate 100. For example, as illustrated inFIG. 24 , the pre-isolation insulatinglayer 110P may be formed on thesubstrate 100 and along the sides and bottom of the stacked structure, e.g., including in the space between thesubstrate 100 and theactive pattern 122. Accordingly, the space from which the firstsacrificial layer 1001 has been removed can be filled with the pre-isolation insulatinglayer 110P. - Referring to
FIGS. 25 and 26 , an etching process may be performed using, as an etching mask, theliner layer 1700 disposed on the top surface of thefirst mask pattern 1600. Accordingly, the side surfaces of theactive patterns sacrificial layers - Further, the
isolation insulating layer 110 may be formed in the space from which the firstsacrificial layer 1001 has been removed. That is, a portion of the pre-isolation insulatinglayer 110P between thesubstrate 100 and theactive pattern 122 may become theisolation insulating layer 110. - Referring to
FIGS. 27 and 28 , theliner layer 1700, thefirst mask pattern 1600, and thebuffer layer 1500 may be removed. Then, adummy gate electrode 140P extending in the second direction Y1 may be formed on the fourthactive pattern 128. - The
dummy gate electrode 140P may be formed using asecond mask pattern 1800 as an etching mask. A dummy gate dielectric layer or a protective layer may be further formed between thedummy gate electrode 140P and the fourthactive pattern 128. In addition, a pre-gate spacer 150P may be formed on the sidewall of thedummy gate electrode 140P. - Referring to
FIGS. 29 and 30 , the first source/drain region 160 may be formed on both sides of thedummy gate electrode 140P. In some embodiments, thesacrificial layers active patterns drain region 160. - After the
sacrificial layers active patterns sacrificial layers inner spacers 151 may be formed at the positions where thesacrificial layers drain region 160 may be formed on both sides of thedummy gate electrode 140P. - Then, an
interlayer insulating layer 180 covering the first source/drain region 160 may be formed on theisolation insulating layer 110. Thedummy gate electrode 140P may be exposed by theinterlayer insulating layer 180. - The
second mask pattern 1800 may be removed during the formation of the interlayer insulatinglayer 180. Further, the firstouter spacer 152 may be formed on the firstinner spacer 151 during the formation of the interlayer insulatinglayer 180. Accordingly, thegate spacer 150 including theinner spacers 151 and theouter spacer 152 may be formed. - Referring to
FIGS. 31 and 32 , thedummy gate electrode 140P and thesacrificial layers trench 140T elongated in the second direction Y1 may be formed. Further, the firstactive patterns - The first lower
active pattern 122 may be formed on theisolation insulating layer 110. The firstsub-active pattern 124 may be spaced apart from the first loweractive pattern 122, the secondsub-active pattern 126 may be spaced apart from the firstsub-active pattern 124, and the thirdsub-active pattern 128 may be spaced apart from the secondsub-active pattern 126. - Next, referring to
FIGS. 2 and 3 , the firstgate dielectric layer 130 and thefirst gate electrode 140 may be formed in thetrench 140T. Although thefirst gate electrode 140 that is a single layer is illustrated for simplicity of description, the technical spirit of the present disclosure is not limited thereto. For example, thefirst gate electrode 140 may be a multiple layer. For example, thefirst gate electrode 140 may include a work function adjusting layer to adjust the work function and a filling conductive layer to fill a space formed by the work function adjusting layer. In other words, the semiconductor device according to some embodiments uses a bulk silicon substrate, rather than an SOI substrate, so that it is possible to form the semiconductor device including the firstisolation insulating layer 110 on thesubstrate 100. -
FIGS. 33 to 36 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments. For reference,FIGS. 33 and 35 are cross-sectional views taken along line A-A′ ofFIG. 14 .FIGS. 34 and 36 are cross-sectional views taken along line B-B′ ofFIG. 14 .FIG. 33 is a view subsequent toFIG. 27 andFIG. 34 is a view subsequent toFIG. 28 . - Referring to
FIGS. 33 and 34 , the first source/drain region 160 may be formed on both sides of thedummy gate electrode 140P. In some embodiments, thesacrificial layers active patterns drain region 160. - After the
sacrificial layers active patterns sacrificial layers inner spacers 151 may be formed at the positions where theactive pattern drain region 160 may be formed on both sides of thedummy gate electrode 140P. - Then, the
interlayer insulating layer 180 covering the first source/drain region 160 may be formed on theisolation insulating layer 110. Thedummy gate electrode 140P may be exposed by theinterlayer insulating layer 180. - The
second mask pattern 1800 may be removed during the formation of the interlayer insulatinglayer 180. Further, the firstouter spacer 152 may be formed on the firstinner spacer 151 during the formation of the interlayer insulatinglayer 180. Accordingly, thegate spacer 150 including theinner spacers 151 and theouter spacer 152 may be formed. Further, theouter spacer 152 may be formed on theinner spacer 151. - Referring to
FIGS. 35 and 36 , thedummy gate electrode 140P and theactive patterns trench 140T elongated in the second direction Y1 may be formed. Further, thesacrificial layers sacrificial layers sacrificial layers - Next, referring to
FIGS. 4 and 5 , the second to fourthsacrificial layers active patterns FIGS. 4 and 5 . The firstgate dielectric layer 130 and thefirst gate electrode 140 may be formed in thetrench 140T. -
FIGS. 37 to 40 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments. For reference,FIGS. 37 to 40 are cross-sectional views taken along line B-B′ ofFIG. 14 .FIG. 37 is a view subsequent toFIG. 16 . - Referring to
FIG. 37 , an etching process may be performed using thefirst mask pattern 1600 as an etching mask. At this time, the etching process may be performed from the top surface of the laminate structure to at least a part of the firstactive layer 1011 disposed at the lowermost portion. In other words, at least a part of the top surface of the firstactive layer 1011 may be exposed by the etching process. Further, the second to fourthactive layers active patterns - Accordingly, a stacked structure protruding from the first
active pattern 122 in the third direction Z1 may be formed. The stacked structure may be formed on the firstsacrificial layer 1001, and may include the first to fourthactive patterns sacrificial layers - In other words, in the method for fabricating a semiconductor device according to some other embodiments, the position of the stopper of the etching process may be set in consideration of an etching material and/or an etching time. Accordingly, a sacrificial layer or an active layer at a desired position may be set as the stopper of the etching process, and the top surface thereof may be exposed. Therefore, the number of active patterns included in the semiconductor device may be adjusted.
- Referring to
FIG. 38 , aliner layer 1700 may be formed. Theliner layer 1700 may be formed to be conformal to the top surface and the side surface of thefirst mask pattern 1600, the side surface of the stacked structure, and the exposed top surface of the firstactive pattern 122. Then, a part of theliner layer 1700 formed on the top surface of the firstactive pattern 122 exposed by the stacked structure may be removed by isotropic etching. Accordingly, theliner layer 1700 may surround the top surface and the side surface of thefirst mask pattern 1600, and the side surface of the stacked structure. - Referring to
FIG. 39 , the firstactive pattern 122 exposed by theliner layer 1700 may be removed. - Referring to
FIG. 40 , the firstsacrificial layer 1001 and the secondsacrificial layer 1002 exposed by the removal of the firstactive pattern 122 may be removed. Then, the firstisolation insulating layer 110 may be formed in the space from which the firstsacrificial layer 1001, the firstactive pattern 122, and the secondsacrificial layer 1002 have been removed. - Next, referring to
FIGS. 23 to 31 andFIGS. 6 to 7 , the firstgate dielectric layer 130 and thefirst gate electrode 140 may be formed. - In the method for fabricating a semiconductor device according to some other embodiments, the first
active pattern 122, the firstsacrificial layer 1001, and the secondsacrificial layer 1002 may be removed to form the firstisolation insulating layer 110. -
FIGS. 41 and 42 are views illustrating stages in a method for fabricating a semiconductor device according to some embodiments. For reference,FIGS. 41 and 42 are cross-sectional views taken along lines C-C′ and D-D′ ofFIG. 8 .FIG. 37 is a view subsequent toFIG. 22 . - Referring to
FIG. 41 , afirst liner layer 1700 may be formed on the first region I, and asecond liner layer 2700 may be formed on the second region II. The sacrificial layer on the first region I and the sacrificial layer on the second region II may be removed. - Then, a third mask pattern may be formed on the first region I. A second pre-isolation insulating
layer 210P may be formed on the second region II exposed by the third mask pattern. Accordingly, the space from which the sacrificial layer has been removed on the second region II can be filled. - Referring to
FIG. 42 , an etching process may be performed using, as an etching mask, thesecond liner layer 2700 disposed on the top surface of thesecond mask pattern 2600 in the second region II. Accordingly, the side surfaces of the secondactive patterns sacrificial layers isolation insulating layer 210 may be formed. - Then, a fourth mask pattern may be formed on the second region II, and the third mask pattern on the first region I may be removed. A first pre-isolation insulating layer may be formed on the second region II exposed by the fourth mask pattern. Accordingly, the space from which the sacrificial layer has been removed on the first region I can be filled.
- Then, an etching process may be performed using, as an etching mask, the
first liner layer 1700 disposed on the top surface of thefirst mask pattern 1600 in the first region I. Accordingly, the side surfaces of the firstactive patterns sacrificial layers isolation insulating layer 210 may be formed. - Next, referring to
FIGS. 27 to 31 andFIGS. 8 and 9 , the first region I may include the firstisolation insulating layer 110 and thefirst gate electrode 140 formed on the firstisolation insulating layer 110, and the second region II may include the secondisolation insulating layer 210 containing a material different from the material contained in the firstisolation insulating layer 110 and thesecond gate electrode 240 formed on the secondisolation insulating layer 210. - By way of summation and review, aspects of the present disclosure provide a semiconductor device with improved product reliability. Aspects of the present disclosure also provide a method for fabricating a semiconductor device with improved product reliability.
- Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020200095308A KR20220015154A (en) | 2020-07-30 | 2020-07-30 | Semiconductor device and method for fabricating the same |
KR10-2020-0095308 | 2020-07-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
US20220037319A1 true US20220037319A1 (en) | 2022-02-03 |
Family
ID=80004637
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/210,751 Pending US20220037319A1 (en) | 2020-07-30 | 2021-03-24 | Semiconductor device and method for fabricating the same |
Country Status (3)
Country | Link |
---|---|
US (1) | US20220037319A1 (en) |
KR (1) | KR20220015154A (en) |
CN (1) | CN114068718A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210313442A1 (en) * | 2020-04-07 | 2021-10-07 | Samsung Electronics Co., Ltd. | Semiconductor devices including gate spacer |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9583583B2 (en) * | 2012-10-10 | 2017-02-28 | Samsung Electronics Co., Ltd. | Semiconductor device with nanowires in different regions at different heights |
US20180053690A1 (en) * | 2016-08-17 | 2018-02-22 | Samsung Electronics Co., Ltd. | Horizontal nanosheet fets and method of manufacturing the same |
US10593673B2 (en) * | 2018-05-15 | 2020-03-17 | International Business Machines Corporation | Nanosheet with single epitaxial stack forming off-set dual material channels for gate-all-around CMOS |
US20200373300A1 (en) * | 2019-05-23 | 2020-11-26 | International Business Machines Corporation | Multi-threshold voltage gate-all-around transistors |
-
2020
- 2020-07-30 KR KR1020200095308A patent/KR20220015154A/en active Search and Examination
-
2021
- 2021-03-24 US US17/210,751 patent/US20220037319A1/en active Pending
- 2021-07-29 CN CN202110862128.9A patent/CN114068718A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9583583B2 (en) * | 2012-10-10 | 2017-02-28 | Samsung Electronics Co., Ltd. | Semiconductor device with nanowires in different regions at different heights |
US20180053690A1 (en) * | 2016-08-17 | 2018-02-22 | Samsung Electronics Co., Ltd. | Horizontal nanosheet fets and method of manufacturing the same |
US10593673B2 (en) * | 2018-05-15 | 2020-03-17 | International Business Machines Corporation | Nanosheet with single epitaxial stack forming off-set dual material channels for gate-all-around CMOS |
US20200373300A1 (en) * | 2019-05-23 | 2020-11-26 | International Business Machines Corporation | Multi-threshold voltage gate-all-around transistors |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210313442A1 (en) * | 2020-04-07 | 2021-10-07 | Samsung Electronics Co., Ltd. | Semiconductor devices including gate spacer |
US11810964B2 (en) * | 2020-04-07 | 2023-11-07 | Samsung Electronics Co., Ltd. | Semiconductor devices including gate spacer |
Also Published As
Publication number | Publication date |
---|---|
CN114068718A (en) | 2022-02-18 |
KR20220015154A (en) | 2022-02-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10243040B1 (en) | Semiconductor device | |
US11640973B2 (en) | Semiconductor device and method for fabricating the same | |
US11967595B2 (en) | Semiconductor devices with nanowires and methods for fabricating the same | |
US11195833B2 (en) | Semiconductor device and method for fabricating the same | |
US11133383B2 (en) | Semiconductor device and method for fabricating the same | |
US10559687B2 (en) | Semiconductor device | |
KR20170139781A (en) | Method for fabricating semiconductor device | |
US10586852B2 (en) | Semiconductor device | |
KR20190111308A (en) | Semiconductor device including self-aligned contact, and method for fabricating the same | |
US11784186B2 (en) | Semiconductor device and method for fabricating the same | |
US11195917B2 (en) | Semiconductor device | |
US11063036B2 (en) | Semiconductor device and method for fabricating the same | |
US20220037319A1 (en) | Semiconductor device and method for fabricating the same | |
KR20170038384A (en) | Semiconductor device | |
US20230031546A1 (en) | Semiconductor device and method of fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, MUN HYEON;KIM, SUNG MIN;HA, DAE WON;SIGNING DATES FROM 20210227 TO 20210305;REEL/FRAME:055899/0879 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: ADVISORY ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |