US20220005735A1 - Self-limiting liners for increasing contact trench volume in n-type and p-type transistors - Google Patents
Self-limiting liners for increasing contact trench volume in n-type and p-type transistors Download PDFInfo
- Publication number
- US20220005735A1 US20220005735A1 US17/475,595 US202117475595A US2022005735A1 US 20220005735 A1 US20220005735 A1 US 20220005735A1 US 202117475595 A US202117475595 A US 202117475595A US 2022005735 A1 US2022005735 A1 US 2022005735A1
- Authority
- US
- United States
- Prior art keywords
- type
- region
- layer
- contact
- devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 claims abstract description 140
- 230000001681 protective effect Effects 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 148
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 29
- 239000004020 conductor Substances 0.000 claims description 18
- 238000006243 chemical reaction Methods 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 2
- 229910052760 oxygen Inorganic materials 0.000 claims 2
- 239000001301 oxygen Substances 0.000 claims 2
- 239000011241 protective layer Substances 0.000 claims 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 56
- 238000000034 method Methods 0.000 description 53
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 50
- 238000004519 manufacturing process Methods 0.000 description 44
- 230000008569 process Effects 0.000 description 41
- 125000006850 spacer group Chemical group 0.000 description 28
- 239000000377 silicon dioxide Substances 0.000 description 23
- 229910052681 coesite Inorganic materials 0.000 description 22
- 229910052906 cristobalite Inorganic materials 0.000 description 22
- 229910052682 stishovite Inorganic materials 0.000 description 22
- 229910052905 tridymite Inorganic materials 0.000 description 22
- 230000015572 biosynthetic process Effects 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 238000000151 deposition Methods 0.000 description 10
- 238000000407 epitaxy Methods 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000011049 filling Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 239000001307 helium Substances 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 229910052754 neon Inorganic materials 0.000 description 3
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000009833 condensation Methods 0.000 description 2
- 230000005494 condensation Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- XWCMFHPRATWWFO-UHFFFAOYSA-N [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] Chemical compound [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] XWCMFHPRATWWFO-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000010405 anode material Substances 0.000 description 1
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 description 1
- 239000010406 cathode material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229940119177 germanium dioxide Drugs 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- -1 hafnium nitride Chemical class 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- JQJCSZOEVBFDKO-UHFFFAOYSA-N lead zinc Chemical compound [Zn].[Pb] JQJCSZOEVBFDKO-UHFFFAOYSA-N 0.000 description 1
- 239000012705 liquid precursor Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000002135 nanosheet Substances 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- KJXBRHIPHIVJCS-UHFFFAOYSA-N oxo(oxoalumanyloxy)lanthanum Chemical compound O=[Al]O[La]=O KJXBRHIPHIVJCS-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- UVGLBOPDEUYYCS-UHFFFAOYSA-N silicon zirconium Chemical compound [Si].[Zr] UVGLBOPDEUYYCS-UHFFFAOYSA-N 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02603—Nanowires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- the present invention relates in general to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to fabrication methods and resulting structures for self-limiting liners configured and arranged to increase the contact trench volume in n-type and p-type transistors.
- MOSFETs such as fin-type field effect transistors (FinFETs)
- FinFETs fin-type field effect transistors
- MOSFETs employ semiconductor fins and a gate structure wrapped over the sidewalls and top of a central portion of the fin.
- the central portion of the fin functions as the channel, and the portions of the fin that are not under the gate function as the source and the drain.
- Raised source/drain (S/D) regions can be epitaxially grown over the S/D portions of the fin to increase the S/D volume and provide a larger surface for interfacing with S/D conductive contacts.
- Embodiments of the invention are directed to a method of forming a protective liner of a semiconductor device.
- a non-limiting example of the method includes forming a source or a drain (S/D) region, forming a first layer of protective material over a top surface of the S/D region, and forming a second layer of protective material over the first layer of protective material, wherein the second layer of protective material includes an oxide of a first type of material.
- An anneal is applied to the first layer and the second layer to drive the first type of material into the first layer, drive a second type of material from the first layer into the second layer, and convert at least a portion of the second layer of protective material to an oxide of the second type of material, wherein the oxide of the second type of material is the protective liner.
- Embodiments of the invention are directed to a method of forming protective liners of semiconductor devices formed on a substrate.
- a non-limiting example of the method includes, in an n-type region of the substrate, performing fabrication operations that include forming an n-type source or a drain (S/D) region, forming a first layer of protective material over a top surface of the n-type S/D region, and forming a second layer of protective material over the first layer of protective material, wherein the second layer of protective material includes an oxide of a first type of material.
- An anneal is applied to the first layer and the second layer to drive the first type of material into the first layer, drive a second type of material from the first layer into the second layer, and convert at least a first portion of the second layer of protective material to a first oxide of the second type of material, wherein the first oxide of the second type of material includes a protective liner of the n-type S/D region.
- the method further includes, in a p-type region of the substrate, performing fabrication operations that include forming a p-type S/D region and forming the second layer of protective material over a top surface of the p-type S/D region, wherein the second layer of protective material includes the oxide of the first type of material.
- An anneal is applied to the first layer and the p-type S/D region to drive the first type of material into the p-type S/D region, drive the second type of material from the p-type S/D region into the second layer, and convert at least a second portion of the second layer of protective material to a second oxide of the second type of material, wherein the second oxide of the second type of material is a protective liner of the p-type S/D region.
- Embodiments of the invention are directed to a set of semiconductor devices formed on a substrate.
- a non-limiting example of the devices includes an n-type region having a first n-type S/D region, a second n-type S/D region, and a first layer of protective material over a top surface of the second n-type S/D region, wherein the first layer of protective material includes a first type of material and a second type of material.
- a second layer of protective material is formed over the first layer of protective material, wherein the second layer of protective material includes an oxide of the second type of material.
- the non-limiting example of the devices includes a p-type region having a first p-type S/D region, a second p-type S/D region, and the second layer of protective material over a top surface of the second p-type S/D region, wherein the second p-type S/D region second layer of protective material includes the first type of material and the second type of material, and wherein the second layer of protective material includes the oxide of the second type of material.
- FIG. 1 depicts a three-dimensional view of a known FinFET device architecture
- FIGS. 2A-13 depict cross-sectional views of a section of a substrate/wafer after various fabrication operations to form n-type MOSFETs and p-type MOSFETs thereon according to embodiments of the invention, in which:
- FIG. 2A depicts a cross-sectional view of the nFET region and the pFET region of the substrate/wafer showing the results of initial fabrication operations according to embodiments of the invention
- FIG. 2B depicts a cross-sectional view showing the dimensions of the high aspect ratio source/drain (S/D) contact trench of the nFET region shown in FIG. 2A ;
- FIG. 3 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention
- FIG. 4 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention
- FIG. 5 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention
- FIG. 6 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention
- FIG. 7 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention
- FIG. 8 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention
- FIG. 9 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention.
- FIG. 10 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention
- FIG. 11 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention
- FIG. 12 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention
- FIG. 13 depicts a cross-sectional view of the nFET region and the pFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention.
- FIG. 14 depicts a diagram illustrating the selective formation of a silicon dioxide layer from an anneal-driven reaction between germanium dioxide and silicon germanium according to embodiments of the invention.
- a typical wafer fabrication process applies a series of complex steps to a semiconductor wafer to define conductors, transistors, resistors, and other electronic components on the semiconductor wafer.
- Transistors are formed in a variety of configurations.
- FinFETs are non-planar transistor architectures that employ semiconductor fins and a gate structure wrapped around the fin sidewalls.
- FIG. 1 a three-dimensional view of a known FinFET 100 is shown in FIG. 1 .
- the basic electrical layout and mode of operation of FinFET 100 do not differ significantly from a traditional FET.
- FinFET 100 includes a semiconductor substrate 102 , shallow trench isolation (STI) layers 104 , a fin 106 and a gate 114 , configured and arranged as shown.
- Fin 106 includes a source region 108 , a drain region 110 and a channel region 112 , wherein gate 114 extends over the top and sides of channel region 112 .
- a single fin 106 is shown in FIG. 1 .
- FinFET devices can be fabricated having multiple fins formed on STI 104 and substrate 102 .
- Substrate 102 can be silicon
- STI 104 can be an oxide (e.g., silicon oxide)
- the fin 106 can be silicon that has been enriched to a desired concentration level of germanium.
- the gate 114 controls the source to drain current flow (labeled ELECTRICITY FLOW in FIG. 1 ).
- source 108 , drain 110 and channel 112 of the FinFET 100 are formed from the fin 106 , which is built as a three-dimensional bar on top of the semiconductor substrate 102 .
- the fin 106 extends through the STI layer 104 and serves as the body of the device.
- the gate electrode 114 is then wrapped over the top and sides of a central portion of the fin 106 .
- the central portion of the fin functions as the channel 112 .
- the source and drain regions 108 , 110 are the portions of the fin 106 on either side of the channel 112 that are not under the gate electrode 114 .
- raised source/drain (S/D) regions can be epitaxially grown over the S/D portions 108 , 110 of the fin 106 to increase the S/D volume and provide a larger surface for interfacing S/D conductive contacts (not shown in FIG. 1 ) with the raised S/D region.
- the S/D contacts are formed on either side of the gate structure 114 , which includes a conductive gate material (e.g., tungsten (W), aluminum (Al), and the like), which is bound at its lower portion by a dielectric liner (not shown).
- the FET can be a FinFET, a planar FET, a nanowire FET, a nanosheet FET, a vertical FET (VFET), etc.
- Transistors and interconnects are the two main structures of an IC.
- the transistors typically reside on or near the bottom level/layer of the IC structure.
- Several levels are above the transistor level including, for example, one or more interconnect levels (i.e., signal wiring) that transmit signals and power throughout the IC.
- the transistors are communicatively coupled to the closest interconnect level by conductive contacts.
- An IC can have, for example, millions of transistors, billions of contacts, and 10-15 interconnect levels/layer.
- Contact resistance is an important performance parameter for transistors. Contact resistance can be generally defined as the contribution to the transistor's total resistance that can be attributed to the contacts, and more specifically, to the interfaces between the contacts and the conductive terminals of the transistor (e.g., the S/D regions). Contact resistance can be contrasted with the transistor's intrinsic resistance, which is an inherent property based on specific transistor features (e.g., dimensions, materials, and the like). Many factors impact contact resistance, including for example, the contact's size/shape, the area of the contact-to-S/D interface, the contact material, and whether the transistor is n-type or p-type. Because unwanted contact resistance slows transistors down, it is, in general, desirable to reduce contact resistance, or maintain it within a predetermined range such that the transistor can achieve its performance targets.
- S/D contacts can be fabricated by forming a S/D contact trench over the surface of the S/D region where the S/D contact will interface.
- the S/D contact trench can be defined by the top surface of the S/D region and the gate sidewalls that extend above and on opposite sides of the S/D region.
- the S/D contact trench is filled with a protective material. For example, a silicon nitride liner can be deposited over the trench sidewalls, and the remaining volume of the S/D contact trench is filled with silicon oxide.
- a mask is used to open the contact trench, thereby removing the silicon oxide (e.g., by directional etch such as reactive ion etch (RIE)) from the contact trench as the silicon nitride liner protects S/D during oxide RIE process.
- a second RIE process is then performed to remove silicon nitride liner from the top of the S/D.
- a conductive material is then deposition on top of the exposed S/D to form contact. Note that in such a prior art process flow, the silicon nitride liner remains on trench sidewalls, thus shrinking the contact trench volume/size that is available for the metal contact. The smaller the contact trench, the higher the contact resistance.
- embodiments of the invention do not need the silicon nitride liner, thus effectively increasing the contact trench volume/size and reducing the contact resistance in comparison with known approaches.
- FIG. 2B The dimensions of a high aspect-ratio S/D contact trench are illustrated by a S/D contact trench 222 B shown in FIG. 2B .
- the structures surrounding the S/D contact trench 222 B are shown in FIG. 2A , and the details of the structures shown in FIGS. 2A and 2B are described in greater detail subsequently herein.
- FIG. 2B is referenced here for purposes of introducing the space constraints that result from reducing the transistor foot print by forming increasingly higher aspect-ratio S/D contacts.
- the S/D contact trench 222 B is defined by a top surface of a doped-silicon (Si) S/D region 220 B and inner sidewalls of gate spacers 234 B and 234 C.
- Si doped-silicon
- the dimensions of the S/D contact trench 220 B are defined by a height dimension (H), a width dimension (W), and a Z dimension (shown by the X/Y/Z diagram).
- the portion of the S/D contact trench 222 B that is allocated to the liners is defined by the height dimension H, the width dimensions A, and the Z dimension. Accordingly, after forming the necessary liners, the remaining space in the S/D contract trench 222 B for forming a S/D contact (e.g., S/D contact 1302 A shown in FIG. 13 ) is defined by the height dimension H, the width dimension B, and the Z dimension.
- H can be about 100 nm
- W can be about 15 nm
- the etch stop liner can be about 5 nm. In this example, only about 5 nm of width is left for forming both the uniform etch stop layer and the S/D contact.
- the reduced space in the S/D contact trench 222 B for forming the S/D contact puts additional pressure on known semiconductor device fabrication processes and results in the formation of taller and narrower high aspect-ratio S/D contacts.
- the SD contact's contact resistance is driven continuously higher. If the S/D contact resistance falls in a certain range, device performance will be degraded.
- Removing the etch stop liners from trench sidewalls to enlarge the contact trench size requires an isotropic etch process that would undesirably create undercutting of etch stop liner in other areas and consequently create yield problem.
- embodiments of the invention address the above-described shortcomings of the prior art by providing fabrication methods and resulting structures for self-limiting liners configured and arranged to increase the portion of the contact trench volume that is available for forming the contact therein. With more of the contact trench's volume available for the contact, a larger contact can be formed, which decreases contact resistance and facilitates the use of different types of conductive contact material in the n-type and p-type transistors on the wafer.
- the n-type transistor conductive contact material can be selected based at least in part on its ability to reduce contact resistance in an n-type transistor environment (e.g., where the S/D region is doped to perform as an-type S/D region).
- the p-type transistor conductive contact material can be selected based at least in part on its ability to reduce contact resistance in a p-type transistor environment (e.g., where the S/D region is doped to perform as a p-type S/D region). Accordingly, aspects of the invention facilitate controlling or tuning n-type transistor contact resistance independently from p-type transistor contact resistance.
- the self-limiting liner is an etch stop liner that is fabricated in a novel manner that limits the formation of the etch stop liner to the region or surface where the etch stop liner is needed. Because the etch stop liner is not on portions of the contact trench where protection is not needed (e.g., along the trench sidewalls), more lateral space in the contact trench can be allocated to the contact, which allows for the formation of a wider contact, thereby improving contact resistance and facilitating the use of different types of conductive contact material in the n-type and p-type transistors on the wafer.
- aspects of the invention can be applied to planar or non-planar MOSFET architectures (e.g., FinFETs, VFETs, etc.).
- aspects of the invention can be applied to an n-type FinFET architecture having a S/D region formed from a doped first type of semiconductor material (e.g., Si).
- a S/D contact trench of the FinFET is the space over the S/D region in which the S/D contact will be formed.
- the S/D contact trench can be defined by the top surface of the S/D region and the gate sidewalls that extend above and on opposite sides of the S/D region top surface.
- a protective material e.g., aSi
- the protective material must be removed from the S/D contact trench prior to forming the S/D contact.
- an etch stop layer can be formed in accordance with aspects of the invention over the top surface of the S/D region in order to protect the S/D region from damage when the protective material is removed to open up the S/D contact trench.
- the etch stop layer can be formed according to aspects of the invention as a self-limiting liner that is fabricated in a manner that limits the formation of the etch stop liner to the top surface of the S/D region where the etch stop liner is needed.
- the etch stop liner formed in accordance with aspects of the invention is not formed along the gate sidewalls, more lateral space in the S/D contact trench can be allocated to the S/D contact, which allows for the formation of a wider S/D contact, thereby improving contact resistance and facilitating the use of different types of conductive contact material in the n-type and p-type transistors on the wafer.
- the etch stop liner is formed in the S/D contact trench prior to depositing the protective material.
- the etch stop liner according to aspects of the invention is self-limiting in that it is formed according to a process that leverages a controlled chemical reaction.
- the novel etch stop fabrication process can include forming a layer of material over a top surface of the doped S/D region.
- the doped S/D region is formed from a doped first type of semiconductor material (e.g., Si), and the deposited layer of material is formed from a combination of the first type of semiconductor material (e.g., Si) and a second type of semiconductor material (e.g., germanium (Ge)).
- the layer of SiGe material can be deposited or formed using an epitaxial growth process. Using an epitaxially growth process, the layer of SiGe material can be grown from the top surface of the doped Si S/D region, which substantially confines the layer of SiGe material top surface of the doped Si S/D region where the etch stop protection will be needed. In some embodiments of the invention, the layer of SiGe material is grown during a S/D epitaxy process (i.e., after S/D epitaxy, continue the epitaxy process to grow SiGe layer). Therefore, no additional process is needed.
- Another layer that includes an oxide of the second type of semiconductor material is deposited within the S/D contact trench, and more specifically over the SiGe layer and along sidewalls of the gate spacers that extend above and on opposite sides of the S/D region.
- GeO 2 can be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition technique.
- the controlled chemical reaction according to aspects of the invention is facilitated by applying at least one anneal operation to the GeO 2 layer and the SiGe layer, wherein the at least one anneal operation is sufficient to result in the portion of the GeO 2 layer that is over the SiGe layer interacting with the SiGe layer to begin converting that portion of the GeO 2 layer to SiO 2 .
- the at least one anneal operation includes a first anneal at a first predetermined temperature (e.g., about 700 Celsius) in an inert gas environment (e.g., nitrogen, argon, helium, neon, hydrogen).
- a second anneal at a second predetermined temperature/environment can be applied, wherein the second predetermined temperature is less than the first predetermined temperature, and wherein the environment is also an inert gas (e.g., nitrogen, argon, helium, neon, hydrogen).
- an inert gas e.g., nitrogen, argon, helium, neon, hydrogen.
- FIG. 14 depicts a diagram illustrating an example of the above-described selective formation of a SiO 2 layer from an anneal-driven reaction between GeO 2 and SiGe.
- the pre-anneal structure is a GeO 2 layer 1402 over a SiGe 20% layer 1404 , which is over a Si layer 1412 .
- the notation “SiGe20%” indicates that the SiGe material contains 20% Ge and 80% Si.
- the post-anneal structure is a SiO 2 layer 1406 over a SiGe40% layer 1408 , which is over a SiGe 20% layer 1410 .
- the SiGe 20% layer 1410 is over the Si layer 1412 .
- the anneal reaction proceeds according to Equation 1 shown in FIG. 14 .
- the GeO 2 layer 1402 will react with the SiGe 20% layer 1404 , thus leading to a condensation of Ge and converting the GeO 2 layer 1402 to SiO 2 , thereby forming the SiO 2 layer 1406 .
- As the reaction proceeds more Si in the SiGe20% layer 1404 is oxidized to SiO 2 , and the surface of the SiGe20% layer 1404 is continuously enriched with additional Ge.
- the additional Ge flowing into the SiGe20% layer 1404 leads to a condensation of Ge that spreads inward from the surface interface between the layers 1402 , 1404 .
- the Ge concentration in the SiGe layer 1408 continues to increase until the desired ratios are reached.
- the self-limiting etch stop layer formation process can be well-controlled, as the reaction of GeO 2 with the SiGe only occurs during the anneal, which can, in some embodiments be a spike anneal at a temperature from about 500-700 degrees Celsius.
- the selective SiO 2 formation in this manner is self-limited and will continue until either all of the GeO 2 is consumed or the SiGe surface becomes sufficiently enriched with germanium that the Equation 1 reaction cannot proceed.
- the reaction will stop when available Si atoms are not enough at the SiGe surface. Consequently, the severity of the self-limiting etch stop layer formation process can be tuned by adjusting the thickness of the GeO 2 layer that has been deposited on the SiGe layer, or by adjusting the anneal temperature/duration.
- the gate spacers that define a portion of the S/D contact trench are formed from a material (e.g., SiN) that does not react with GeO 2 . Accordingly, the annealing method of the present invention is highly selective to SiGe, and, after the necessary reactions shown in Equation 1 have completed, the unreacted GeO 2 in the can be easily removed by exposing it to a water containing wash because GeO 2 is water soluble.
- a material e.g., SiN
- FIG. 2A depicts a semiconductor structure 200 after initial fabrication stages according to embodiments of the invention.
- Known fabrication operations have been used to form the semiconductor structure 200 shown in FIG. 2A .
- a variety of fabrication operations are suitable for fabricating the semiconductor structure 200 to the stage shown in FIG. 2A . Because the fabrication operations are well-known, they have been omitted in the interest of brevity.
- the structure 200 will be, after completion of the fabrication processes, a group of in-series n-type MOSFETs (e.g., n-type MOSFET 240 ) formed in an nFET region 204 of a Si wafer/substrate 202 , along with a group of in-series p-type MOSFETs (e.g., p-type MOSFET 340 ) formed in a pFET region 304 of the Si wafer/substrate 202 .
- a group of in-series n-type MOSFETs e.g., n-type MOSFET 240
- a group of in-series p-type MOSFETs e.g., p-type MOSFET 340
- the n-type MOSFET 240 and the p-type MOSFET 340 are FinFET architectures having doped Si raised S/D regions 220 A, 220 B, 320 A, 320 B.
- embodiments of the invention are not limited to a particular type of MOSFET device or IC architecture. Rather, embodiments of the invention are capable of being implemented in conjunction with any type of planar or non-planar transistor device or IC architecture, now known or later developed, for which there is a need to form a conductive contact to a S/D of the transistor device.
- the n-type MOSFET 240 includes a Si channel region 210 B (which can be lightly doped or undoped), doped-Si S/D regions 220 A, 220 B, a gate 230 B, a hardmask 232 B, and gate spacers 234 B, configured and arranged as shown.
- a Si channel 210 A which can be slightly doped or lightly doped
- a gate 230 A which can be slightly doped or lightly doped
- a hardmask 232 A a hardmask 232 A
- gate spacers 234 A configured and arranged as shown.
- the n-type MOSFET 240 shares the S/D region 220 A with a first in-series n-type MOSFET that is in series with the n-type MOSFET 240 and is formed from a Si channel 210 A, a gate 230 A, a hardmask 232 A, gate spacers 234 A, and another doped-Si S/D region (not shown) adjacent to and communicatively coupled with the channel region 210 A.
- a Si channel 210 C which can be lightly doped
- a gate 230 C a hardmask 232 C
- gate spacers 234 C configured and arranged as shown.
- the n-type MOSFET 240 shares the S/D region 220 B with a second in-series n-type MOSFET that is in series with the n-type MOSFET 240 and is formed from a Si channel 210 C (which can be lightly doped), a gate 230 C, a hardmask 232 C, gate spacers 234 C, and another doped Si S/D region (not shown) adjacent to and communicatively coupled with the channel region 210 C.
- a first S/D contact trench 222 A is defined by a top surface of the S/D region 220 A and sidewalls of the gate spacers 234 A, 234 B.
- a second S/D contact trench 222 B is defined by a top surface of the S/D region 220 B and sidewalls of the gate spacers 234 B, 234 C.
- the p-type MOSFET 340 includes a Si channel region 310 B (which can be lightly doped), doped-SiGe S/D regions 320 A, 320 B, a gate 330 B, a hardmask 332 B, and gate spacers 334 B, configured and arranged as shown.
- a Si channel 310 A which can be slightly doped
- a gate 330 A which can be slightly doped
- a hardmask 332 A a hardmask 332 A
- gate spacers 334 A configured and arranged as shown.
- the p-type MOSFET 340 shares the S/D region 320 A with a first in-series p-type MOSFET that is in series with the p-type MOSFET 340 and is formed from a Si channel 310 A (which can be lightly doped or undoped), a gate 330 A, a hardmask 332 A, gate spacers 334 A, and another doped SiGe S/D region (not shown) adjacent to and communicatively coupled with the channel region 310 A.
- a Si channel 310 C (which can be lightly doped), a gate 330 C, a hardmask 332 C, and gate spacers 334 C, configured and arranged as shown.
- a Si channel 310 C which can be lightly doped
- a gate 330 C a gate 330 C
- a hardmask 332 C a hardmask 332 C
- gate spacers 334 C configured and arranged as shown.
- the p-type MOSFET 340 shares the S/D region 320 B with a second in-series p-type MOSFET that is in series with the p-type MOSFET 340 and is formed from a Si channel 310 C, a gate 330 C, a hardmask 332 C, gate spacers 334 C, and another doped SiGe S/D region (not shown) adjacent to and communicatively coupled with the channel region 310 C.
- a first high aspect-ratio S/D contact trench 322 A is defined by a top surface of the S/D region 320 A and sidewalls of the gate spacers 334 A, 334 B.
- a second high aspect-ratio S/D contact trench 322 B is defined by a top surface of the S/D region 320 B and sidewalls of the gate spacers 334 B, 334 C.
- the n-type MOSFET 240 and the p-type MOSFET 340 can have the same channel material (e.g., Si). Alternatively, the n-type MOSFET 240 and the p-type MOSFET 340 can have different channel material (e.g., n-type MOSFET 240 has Si channels, and p-type MOSFET 340 has SiGe channels).
- the gates 230 A, 230 B, 230 C, 330 A, 330 B, 330 C can be dummy gates, for example, including a dummy gate oxide and a dummy gate placeholder such as amorphous silicon or polycrystalline silicon. Dummy gates can be replaced with final gate structures such as a high-k gate dielectric and a metal gate. Alternatively, the gates 230 A, 230 B, 230 C, 330 A, 330 B, 330 C can be final gate structures that include a high-k gate dielectric and a metal gate or any other suitable gate materials.
- gate dielectrics can include any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, high-k materials, or any combination of these materials.
- high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
- the high-k can further include dopants such as lanthanum, aluminum, magnesium.
- the gate conductor can include any suitable conducting material.
- the conductive material can further include dopants that are incorporated during or after deposition.
- the gate can further include a workfunction setting layer between the gate dielectric and gate conductor.
- the workfunction setting layer can be a workfunction metal (WFM).
- WFM can be any suitable material.
- a conductive material or a combination of multiple conductive materials can serve as both gate conductor and WFM.
- the gate conductor and WFM can be formed by any suitable process or any suitable combination of multiple processes.
- the gate spacer can include any suitable dielectric materials.
- FIG. 2B illustrates the space constraints that result from reducing transistor foot print by forming the S/D contact trenches 222 A, 222 B, 322 A, 322 B (shown in FIG. 2A ) to have increasingly higher aspect-ratios.
- the dimensions depicted in FIG. 2B for the S/D contact trench 222 B apply equally to the S/D contact trenches 222 A, 322 A, 322 B.
- the S/D contact trench 222 B is defined by a top surface of the S/D region 220 B and inner sidewalls of gate spacers 234 B and 234 C.
- the dimensions of the S/D contact trench 220 B are defined by a height dimension (H), a width dimension (W), and a Z dimension (shown by the X/Y/Z diagram).
- the portion of the S/D contact trench 222 B that is allocated to the required liner i.e., the contact liner 1202 shown in FIG. 12
- the height dimension H is defined by the height dimension H, the width dimensions A, and the Z dimension.
- the remaining space in the S/D contract trench 222 B for forming the S/D contact 1302 A is defined by the height dimension H, the width dimension B, and the Z dimension.
- H can be about 100 nm
- W can be about 15 nm
- the contact liner 1202 (shown in FIG. 12 ) can be about 5 nm.
- the available volume of the S/D contact trench 222 B is increased because, in accordance with aspects of the invention, none of the volume of the S/D contact trench 222 B is allocated to an etch stop liner.
- the increase in available space in the S/D contact trench 222 B enables the formation of relatively wider high aspect-ratio S/D contacts.
- a novel self-limiting liner is utilized to increase the portion of the S/D contact trench volume that is available for forming the contact therein. With more of the S/D contact trench's volume available for the contact, a larger contact can be formed, which decreases contact resistance and facilitates the use of different types of conductive contact material in the n-type and p-type transistors on the wafer.
- the n-type transistor conductive contact material e.g., S/D contact 1302 A shown in FIG. 13
- the p-type transistor conductive contact material e.g., S/D contact 1302 B shown in FIG.
- aspects of the invention and specifically the increase in available S/D contact trench volume, facilitate controlling or tuning n-type transistor contact resistance independently from p-type transistor contact resistance.
- the self-limiting liner is an etch stop liner (e.g., SiO2 layer 502 and SiGe layer 224 A′ shown in FIG. 5 ), which is fabricated in a novel manner that limits the formation of the etch stop liner to the region or surface (e.g., the top surfaces of the S/D regions 220 A, 220 B) where the etch stop liner is needed. Because the etch stop liner is not on portions of the contact trench where protection is not needed (e.g., along sidewalls of the gate spacers 234 B, 234 C), more lateral space in the S/D contact trench 222 B can be allocated to the S/D contact (e.g., S/D contact 1302 A shown in FIG. 13 ), which allows for the formation of a wider S/D contact, thereby improving (i.e., reducing) contact resistance and facilitating the use of different types of conductive contact material in the n-type and p-type transistors on the wafer.
- etch stop liner e
- FIGS. 3-12 depict the result of various fabrication operations applied to the semiconductor structure 200 for forming self-limiting etch stop liners (e.g., SiO2 layer 502 and SiGe layer 224 A′ shown in FIG. 5 ) in the S/D contact trenches 222 A, 222 B in accordance with aspects of the invention.
- FIGS. 3-12 describe fabrication operations applied to the nFET region 204 of the substrate 202 .
- substantially the same fabrication operations can be applied to the semiconductor structure 200 for forming self-limiting etch stop liners (e.g., SiO2 layer 502 A′ shown in FIG. 13 ) in the S/D contact trenches 322 A, 322 B of the pFET region 304 of the substrate 202 .
- the S/D regions 320 A, 320 B of the n-type MOSFET 340 are formed from SiGe, depositing SiGe layers corresponding to the SiGe layers 224 A, 224 B can, optionally, be omitted.
- the SiGe layers 224 A, 224 B can formed using an epitaxial growth process.
- Materials can be epitaxially grown from gaseous or liquid precursors using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable process.
- VPE vapor-phase epitaxy
- MBE molecular-beam epitaxy
- LPE liquid-phase epitaxy
- the SiGe layers 224 A and 224 B are formed during the source/drain epitaxy process (i.e., SiGe layers on top of n-type MOSFET are grown after growing the n-type source/drain, and SiGe layers on top of p-type MOSFET are grown after growing the p-type source/drain).
- the SiGe layers can be grown by a dedicated epitaxy process, i.e., SiGe layers are grown on top of both n-type source/drain and p-type source/drain after the formation of both n-type source/drain and p-type source/drain.
- the SiGe 224 A and 224 B layers can be doped or undoped.
- known fabrication processes e.g., an atomic layer deposition (ALD)
- ALD atomic layer deposition
- the GeO 2 layer 402 is conformally deposited over the semiconductor structure 200 to cover the SiGe layers 224 A, 224 B and sidewalls of the gate spacers 234 A, 234 B, 234 C of the S/D contact trenches 222 A, 222 B.
- a non-limiting example range for the GeO 2 thickness is 2-6 nm.
- At least one anneal operation has been applied to the GeO 2 layer 402 (shown in FIG. 4 ) and the SiGe layers 224 A, 224 B (shown in FIG. 4 ) to enable a reaction that forms SiO 2 layers 502 and SiGe layers 224 A′, 224 B that each have a different Ge concentration than the SiGe layers 224 A, 224 B, respectively.
- the at least one anneal operation is sufficient to result in the GeO 2 layer 402 and the SiGe layers 224 A, 224 B interacting (or reacting) to convert the portions of the GeO 2 layer 402 that are over the SiGe layers 224 A, 224 B to the SiO 2 layers 502 .
- the at least one anneal operation is sufficient to result in Ge diffusing from the original GeO 2 layer 402 into the SiGe layers 224 A, 224 B to increase the Ge concentrations thereof and form the of the SiGe layers 224 A′, 224 B′.
- the at least one anneal operation includes a first anneal at a first predetermined temperature (e.g., a spike anneal at about 700 degrees Celsius) in a nitrogen ambient.
- the at least one anneal operation can further include a second anneal at a second predetermined temperature (e.g., about 450 degrees Celsius) in a nitrogen ambient, wherein the second predetermined temperature is less than the first predetermined temperature. Additional details of the above-described reaction are depicted in FIG. 14 and were previously described in this detailed description. Any inert environment (e.g., nitrogen, argon, helium, neon) can be used in the anneal.
- a first predetermined temperature e.g., a spike anneal at about 700 degrees
- the unreacted portions of the GeO 2 layer 402 have been removed by exposing the unreacted portions of the GeO 2 layer 402 to a water containing wash because GeO 2 is water soluble.
- materials are used that do not substantially react with GeO 2 in the manner depicted by Equation 1 of FIG. 14 .
- the hardmasks 232 A, 232 B, 232 C and the gate spacers 234 A, 234 B, 234 C can be formed from a nitride (e.g., SiN).
- a protective material e.g., amorphous Si (aSi)
- the protective material 602 A is overfilled in the S/D contract trenches 222 A, 222 B then polished back (e.g., using chemical mechanical polishing (CMP)) to the level shown in FIG. 6 .
- CMP chemical mechanical polishing
- the purpose of aSi is to serve as a sacrificial filling material filling any gaps between gates.
- the SiO 2 is needed on top of the S/D epitaxy so that later the aSi can be removed without also attacking the S/D epitaxy. It is noted that the S/D epitaxy and aSi are all semiconductor materials so they have poor etch selectivity between each other. Subsequently, the aSi is removed in contact region and replaced with conducting contact materials. The aSi in non-contact trench region is then removed and replaced with a dielectric material or dielectric material(s).
- the advantage of having aSi as the sacrificial material is that it can be removed very selective to SiO 2 . Therefore, even a thin SiO 2 layer, e.g., 3 nm, is sufficient to serve as an etch stop layer to protect the S/D epitaxy when removing aSi from the contact trench.
- the blocking mask 802 can be any suitable masking material, including but not limited to, photoresist, photoresist in conjunction with an organic planarization layer (OPL), or any suitable hardmask material.
- OPLs are used to fill pre-existing features, and to planarize the substrate to allow for larger patterning process windows.
- the SiO2 layer 502 functions as an etch-stop layer that prevents the RIE that was used to remove the aSi 602 A from also removing portions of the S/D region 220 A, particularly where both the aSi 602 A and the doped-Si S/D region 220 A are formed from Si.
- SiO 2 also protects doped SiGe S/D in p-type MOSFET region.
- the blocking mask 802 (shown in FIG. 8 ) has been removed, and known semiconductor fabrication operations have been used to form a protective interlayer dielectric (ILD) region 902 in the S/D contact trench 222 a (shown in FIG. 8 ).
- the ILD region (or dummy contact) 902 can be formed by depositing any suitable dielectric material or materials. For example, an oxide material such as spin-on-glass or flowable oxide can be used to fill the trenches. Planarization processes (e.g., using CMP) can be used to bring the ILD region 902 to the level of the gate spacers 234 A, 234 B and the hardmasks 232 A, 232 B.
- the ILD 902 can further include a dielectric liner (e.g., silicon nitride) in the dummy contact sidewalls before filling the rest of the dummy contact trench with flowable oxide.
- the ILD region (or dummy contact) 902 is deposited in the S/D contact trench 222 A because the series coupling of multiple instances of the n-type MOSFET 240 , which was previously described herein, means that a conductive contact does not need to be made to every S/D region. In other cases, the ILD region 902 serves as the isolation between adjacent devices.
- each S/D contact trench that has been filled with a S/D conductive contact is adjacent a S/D contact trench that has been filled with a nonconductive material such as ILD 902 .
- the Si channel 210 A (which can be slightly doped)
- the gate 230 A the gate 230 A
- the hardmask 232 A the gate spacers 234 A, configured and arranged as shown.
- the n-type MOSFET 240 shares the S/D region 220 A with a first in-series n-type MOSFET that is in series with the n-type MOSFET 240 and is formed from the Si channel 210 A (which can be lightly doped), the gate 230 A, the hardmask 232 A, gate spacers 234 A, and another doped-Si S/D region (not shown) adjacent to and communicatively coupled with the channel region 210 A.
- the Si channel 210 C which can be lightly doped
- the gate 230 C the hardmask 232 C
- gate spacers 234 C configured and arranged as shown.
- the n-type MOSFET 240 shares the S/D region 220 B with a second in-series n-type MOSFET that is in series with the n-type MOSFET 240 and is formed from the Si channel 210 C (which can be lightly doped), the gate 230 C, the hardmask 232 C, gate spacers 234 C, and another doped Si S/D region (not shown) adjacent to and communicatively coupled with the channel region 210 C.
- a conductive S/D contact will be formed over the S/D region of the in-series n-type MOSFET that is to the left of the n-type MOSFET 240 .
- a conductive S/D contact 1302 A (shown in FIG. 13 ) will be deposited in the S/D contact trench 222 B (shown in FIG. 10 )
- an ILD region similar to ILD region 902 will be formed over the S/D region of the in-series n-type MOSFET that is to the right of the n-type MOSFET 240 .
- known semiconductor fabrication processes have been used to remove the aSi 602 B (shown in FIG. 9 ), thereby reopening the S/D contact trench 222 B.
- the known fabrication processes include a RIE process, a wet etch process such as ammonia etch, a silicon plasma etch, or a silicon dry etch.
- the etch can be isotropic or anisotropic.
- etch is isotropic so all remaining aSi in the contact trenches can be removed.
- the SiO 2 layer 502 functions as an etch-stop layer that prevents the RIE that was used to remove the aSi 602 B from also removing portions of the S/D region 220 B.
- a pre-clean operation can be applied to the inner surfaces of the S/D contact trench 222 B prior to depositing the contact liner 1202 (shown in FIG. 12 ), and the pre-clean operation can be configured and arranged to also remove the SiO 2 layer 502 and the SiGe layer 224 B′ from over the S/D region 220 B in the S/D contact trench 222 B.
- a wet etch such as diluted hydrofluoric acid can be used to serve dual purposes: simultaneously removing SiO 2 and serving as pre-clean step before depositing conducting material on top of the S/D.
- the contact liner 1202 is configured and arranged to minimize contact resistance.
- the liner 1202 can be titanium (Ti).
- the liner 1202 can also be nickel platinum (NiPt).
- the “bulk” contact (or fill material) 1302 can include conducting metal(s), which can be the same for both the n-type S/D and the p-type S/D.
- the metal contact fill 1302 can be tungsten (W), aluminum (Al), copper (Cu), or cobalt (Co), and can further include a barrier layer (not shown).
- the barrier layer can be titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), niobium nitride (NbN), tungsten nitride (WN), or combinations thereof, where the barrier layer can prevent diffusion and/or alloying of the metal contact fill material with the top source drain material, and/or anode/cathode material.
- the barrier layer can be conformally deposited in the trench(es) by ALD, CVD, MOCVD, PECVD, or combinations thereof.
- the metal fill 1302 can be formed by ALD, CVD, and/or PVD to form the electrical contacts.
- FIG. 13 depicts the semiconductor structure 200 showing the results of the above-described fabrication processes applied to both the nFET region 204 and the pFET region 304 . Additionally, in FIG. 13 , known semiconductor fabrication processes have been used to form the S/D contacts 1302 A, 1302 B.
- the S/D contact 1302 A can be formed from any suitable conducting material. Examples of suitable materials for the S/D contact 1302 A include titanium (Ti).
- the S/D contact 1302 B can be formed from any suitable conducting material. Examples of suitable materials for the S/D contact 1302 B include NiPt (nickel platinum).
- the S/D contacts 1302 A, 1302 B can further include dopants that are incorporated during or after deposition.
- different conductive materials can be deposited on n-type S/D and p-type S/D to minimize the contact resistance of n-type and p-type S/D, respectively.
- the different conductive materials can be two different conductive liners (e.g., Ti for n-type S/D and NiPt for p-type S/D) with the remaining contact trenches filled with a common conductive material (e.g., tungsten or cobalt).
- the entire n-type S/D contact trench can be filled with Ti, and the entire p-type S/D contact trench can be filled with NiPt.
- the entire n-type S/D contact trench can be filled with Ti, and the entire p-type S/D contact trench can be filled with NiPt liner plus tungsten or cobalt filling the rest of the p-type contact trench.
- the gates 230 A, 230 B, 230 C, 330 A, 330 B, 330 C can be a dummy gate, and a replacement-metal-gate (RMG) fabrication process will be used to replace the dummy gates 230 A, 230 B, 230 C, 330 A, 330 B, 330 C with a metal gate structure.
- RMG replacement-metal-gate
- the dummy gates 230 , 240 can be removed using a so-called poly open CMP (POC) process in which the dummy gates 230 A, 230 B, 230 C, 330 A, 330 B, 330 C can be removed by an etching process, e.g., RIE or chemical oxide removal (COR), to form trenches between the gate spacers 234 A, 234 B, 234 C, 334 A, 334 B, 334 C.
- the metal gate structure can include a metal liner, e.g., a work-function metal, and a gate metal deposited on a high-k dielectric material.
- the metal liner can be, for example, TiN or TaN, and the gate metal can be aluminum or tungsten.
- Known process flows for the metal gate formation involves multiple annealing operations, including, for example, a high-k post-deposition anneal (PDA) and a high temperature anneal applied to the high-k dielectric to improve reliability.
- PDA high-k post-deposition anneal
- high temperature anneal applied to the high-k dielectric to improve reliability.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
- The present invention relates in general to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to fabrication methods and resulting structures for self-limiting liners configured and arranged to increase the contact trench volume in n-type and p-type transistors.
- Some non-planar metal oxide semiconductor field effect transistors (MOSFETs), such as fin-type field effect transistors (FinFETs), employ semiconductor fins and a gate structure wrapped over the sidewalls and top of a central portion of the fin. The central portion of the fin functions as the channel, and the portions of the fin that are not under the gate function as the source and the drain. Raised source/drain (S/D) regions can be epitaxially grown over the S/D portions of the fin to increase the S/D volume and provide a larger surface for interfacing with S/D conductive contacts.
- Embodiments of the invention are directed to a method of forming a protective liner of a semiconductor device. A non-limiting example of the method includes forming a source or a drain (S/D) region, forming a first layer of protective material over a top surface of the S/D region, and forming a second layer of protective material over the first layer of protective material, wherein the second layer of protective material includes an oxide of a first type of material. An anneal is applied to the first layer and the second layer to drive the first type of material into the first layer, drive a second type of material from the first layer into the second layer, and convert at least a portion of the second layer of protective material to an oxide of the second type of material, wherein the oxide of the second type of material is the protective liner.
- Embodiments of the invention are directed to a method of forming protective liners of semiconductor devices formed on a substrate. A non-limiting example of the method includes, in an n-type region of the substrate, performing fabrication operations that include forming an n-type source or a drain (S/D) region, forming a first layer of protective material over a top surface of the n-type S/D region, and forming a second layer of protective material over the first layer of protective material, wherein the second layer of protective material includes an oxide of a first type of material. An anneal is applied to the first layer and the second layer to drive the first type of material into the first layer, drive a second type of material from the first layer into the second layer, and convert at least a first portion of the second layer of protective material to a first oxide of the second type of material, wherein the first oxide of the second type of material includes a protective liner of the n-type S/D region. The method further includes, in a p-type region of the substrate, performing fabrication operations that include forming a p-type S/D region and forming the second layer of protective material over a top surface of the p-type S/D region, wherein the second layer of protective material includes the oxide of the first type of material. An anneal is applied to the first layer and the p-type S/D region to drive the first type of material into the p-type S/D region, drive the second type of material from the p-type S/D region into the second layer, and convert at least a second portion of the second layer of protective material to a second oxide of the second type of material, wherein the second oxide of the second type of material is a protective liner of the p-type S/D region.
- Embodiments of the invention are directed to a set of semiconductor devices formed on a substrate. A non-limiting example of the devices includes an n-type region having a first n-type S/D region, a second n-type S/D region, and a first layer of protective material over a top surface of the second n-type S/D region, wherein the first layer of protective material includes a first type of material and a second type of material. A second layer of protective material is formed over the first layer of protective material, wherein the second layer of protective material includes an oxide of the second type of material. The non-limiting example of the devices includes a p-type region having a first p-type S/D region, a second p-type S/D region, and the second layer of protective material over a top surface of the second p-type S/D region, wherein the second p-type S/D region second layer of protective material includes the first type of material and the second type of material, and wherein the second layer of protective material includes the oxide of the second type of material.
- Additional features and advantages are realized through techniques described herein. Other embodiments and aspects are described in detail herein. For a better understanding, refer to the description and to the drawings.
- The subject matter which is regarded as embodiments is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
-
FIG. 1 depicts a three-dimensional view of a known FinFET device architecture; -
FIGS. 2A-13 depict cross-sectional views of a section of a substrate/wafer after various fabrication operations to form n-type MOSFETs and p-type MOSFETs thereon according to embodiments of the invention, in which: -
FIG. 2A depicts a cross-sectional view of the nFET region and the pFET region of the substrate/wafer showing the results of initial fabrication operations according to embodiments of the invention; -
FIG. 2B depicts a cross-sectional view showing the dimensions of the high aspect ratio source/drain (S/D) contact trench of the nFET region shown inFIG. 2A ; -
FIG. 3 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention; -
FIG. 4 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention; -
FIG. 5 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention; -
FIG. 6 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention; -
FIG. 7 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention; -
FIG. 8 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention; -
FIG. 9 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention; -
FIG. 10 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention; -
FIG. 11 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention; -
FIG. 12 depicts a cross-sectional view of the nFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention; -
FIG. 13 depicts a cross-sectional view of the nFET region and the pFET region of the substrate/wafer showing the results of fabrication operations according to embodiments of the invention; and -
FIG. 14 depicts a diagram illustrating the selective formation of a silicon dioxide layer from an anneal-driven reaction between germanium dioxide and silicon germanium according to embodiments of the invention. - Although this specification includes a detailed description of an exemplary FinFET non-planar MOSFET device architecture, implementation of the teachings recited herein are not limited to a particular type of MOSFET device or integrated circuit (IC) architecture. Rather, embodiments of the present invention are capable of being implemented in conjunction with any other type of planar or non-planar transistor device or IC architecture, now known or later developed, for which there is a need to form a conductive contact to a source or drain (S/D) of the transistor device.
- For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.
- Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, a typical wafer fabrication process applies a series of complex steps to a semiconductor wafer to define conductors, transistors, resistors, and other electronic components on the semiconductor wafer. Transistors are formed in a variety of configurations. For example, FinFETs are non-planar transistor architectures that employ semiconductor fins and a gate structure wrapped around the fin sidewalls. To illustrate the non-planar architecture of FinFETs, a three-dimensional view of a known FinFET 100 is shown in
FIG. 1 . The basic electrical layout and mode of operation of FinFET 100 do not differ significantly from a traditional FET. FinFET 100 includes asemiconductor substrate 102, shallow trench isolation (STI)layers 104, afin 106 and agate 114, configured and arranged as shown. Fin 106 includes asource region 108, adrain region 110 and achannel region 112, whereingate 114 extends over the top and sides ofchannel region 112. For ease of illustration, asingle fin 106 is shown inFIG. 1 . In practice, FinFET devices can be fabricated having multiple fins formed on STI 104 andsubstrate 102.Substrate 102 can be silicon, STI 104 can be an oxide (e.g., silicon oxide), and thefin 106 can be silicon that has been enriched to a desired concentration level of germanium. Thegate 114 controls the source to drain current flow (labeled ELECTRICITY FLOW inFIG. 1 ). - In contrast to planar MOSFETs,
source 108,drain 110 andchannel 112 of the FinFET 100 are formed from thefin 106, which is built as a three-dimensional bar on top of thesemiconductor substrate 102. Thefin 106 extends through theSTI layer 104 and serves as the body of the device. Thegate electrode 114 is then wrapped over the top and sides of a central portion of thefin 106. The central portion of the fin functions as thechannel 112. The source and drainregions fin 106 on either side of thechannel 112 that are not under thegate electrode 114. - In some FinFET architectures, raised source/drain (S/D) regions (not shown in
FIG. 1 ) can be epitaxially grown over the S/D portions fin 106 to increase the S/D volume and provide a larger surface for interfacing S/D conductive contacts (not shown inFIG. 1 ) with the raised S/D region. The S/D contacts are formed on either side of thegate structure 114, which includes a conductive gate material (e.g., tungsten (W), aluminum (Al), and the like), which is bound at its lower portion by a dielectric liner (not shown). The FET can be a FinFET, a planar FET, a nanowire FET, a nanosheet FET, a vertical FET (VFET), etc. - Transistors and interconnects are the two main structures of an IC. The transistors typically reside on or near the bottom level/layer of the IC structure. Several levels are above the transistor level including, for example, one or more interconnect levels (i.e., signal wiring) that transmit signals and power throughout the IC. The transistors are communicatively coupled to the closest interconnect level by conductive contacts. An IC can have, for example, millions of transistors, billions of contacts, and 10-15 interconnect levels/layer.
- Contact resistance is an important performance parameter for transistors. Contact resistance can be generally defined as the contribution to the transistor's total resistance that can be attributed to the contacts, and more specifically, to the interfaces between the contacts and the conductive terminals of the transistor (e.g., the S/D regions). Contact resistance can be contrasted with the transistor's intrinsic resistance, which is an inherent property based on specific transistor features (e.g., dimensions, materials, and the like). Many factors impact contact resistance, including for example, the contact's size/shape, the area of the contact-to-S/D interface, the contact material, and whether the transistor is n-type or p-type. Because unwanted contact resistance slows transistors down, it is, in general, desirable to reduce contact resistance, or maintain it within a predetermined range such that the transistor can achieve its performance targets.
- In known MOSFET architectures (e.g., FinFETs, VFETs, etc.), S/D contacts can be fabricated by forming a S/D contact trench over the surface of the S/D region where the S/D contact will interface. For example, in a FinFET architecture, the S/D contact trench can be defined by the top surface of the S/D region and the gate sidewalls that extend above and on opposite sides of the S/D region. During typical fabrication operations that occur prior to contact formation, the S/D contact trench is filled with a protective material. For example, a silicon nitride liner can be deposited over the trench sidewalls, and the remaining volume of the S/D contact trench is filled with silicon oxide. To form the S/D contact, a mask is used to open the contact trench, thereby removing the silicon oxide (e.g., by directional etch such as reactive ion etch (RIE)) from the contact trench as the silicon nitride liner protects S/D during oxide RIE process. A second RIE process is then performed to remove silicon nitride liner from the top of the S/D. A conductive material is then deposition on top of the exposed S/D to form contact. Note that in such a prior art process flow, the silicon nitride liner remains on trench sidewalls, thus shrinking the contact trench volume/size that is available for the metal contact. The smaller the contact trench, the higher the contact resistance. In contrast, and as explained in greater detail subsequently herein, embodiments of the invention do not need the silicon nitride liner, thus effectively increasing the contact trench volume/size and reducing the contact resistance in comparison with known approaches.
- The dimensions of a high aspect-ratio S/D contact trench are illustrated by a S/
D contact trench 222B shown inFIG. 2B . The structures surrounding the S/D contact trench 222B are shown inFIG. 2A , and the details of the structures shown inFIGS. 2A and 2B are described in greater detail subsequently herein.FIG. 2B is referenced here for purposes of introducing the space constraints that result from reducing the transistor foot print by forming increasingly higher aspect-ratio S/D contacts. As shown inFIG. 2B , the S/D contact trench 222B is defined by a top surface of a doped-silicon (Si) S/D region 220B and inner sidewalls ofgate spacers D contact trench 220B are defined by a height dimension (H), a width dimension (W), and a Z dimension (shown by the X/Y/Z diagram). The portion of the S/D contact trench 222B that is allocated to the liners (e.g., the uniform etch stop layer) is defined by the height dimension H, the width dimensions A, and the Z dimension. Accordingly, after forming the necessary liners, the remaining space in the S/D contract trench 222B for forming a S/D contact (e.g., S/D contact 1302A shown inFIG. 13 ) is defined by the height dimension H, the width dimension B, and the Z dimension. - As MOSFET dimensions continue to decrease, the dimensions allocated to the S/D contact trench decrease as well. More specifically, to reduce MOSFET footprints, higher aspect-ratio MOSFET features are utilized. For example, referring still to the S/
D contact trench 222B inFIG. 2B , in a typical FinFET MOSFET architecture, H can be about 100 nm, W can be about 15 nm, and the etch stop liner can be about 5 nm. In this example, only about 5 nm of width is left for forming both the uniform etch stop layer and the S/D contact. The reduced space in the S/D contact trench 222B for forming the S/D contact puts additional pressure on known semiconductor device fabrication processes and results in the formation of taller and narrower high aspect-ratio S/D contacts. As S/D contacts become taller and narrower, the SD contact's contact resistance is driven continuously higher. If the S/D contact resistance falls in a certain range, device performance will be degraded. Removing the etch stop liners from trench sidewalls to enlarge the contact trench size requires an isotropic etch process that would undesirably create undercutting of etch stop liner in other areas and consequently create yield problem. - Turning now to an overview of aspects of the invention, embodiments of the invention address the above-described shortcomings of the prior art by providing fabrication methods and resulting structures for self-limiting liners configured and arranged to increase the portion of the contact trench volume that is available for forming the contact therein. With more of the contact trench's volume available for the contact, a larger contact can be formed, which decreases contact resistance and facilitates the use of different types of conductive contact material in the n-type and p-type transistors on the wafer. The n-type transistor conductive contact material can be selected based at least in part on its ability to reduce contact resistance in an n-type transistor environment (e.g., where the S/D region is doped to perform as an-type S/D region). The p-type transistor conductive contact material can be selected based at least in part on its ability to reduce contact resistance in a p-type transistor environment (e.g., where the S/D region is doped to perform as a p-type S/D region). Accordingly, aspects of the invention facilitate controlling or tuning n-type transistor contact resistance independently from p-type transistor contact resistance.
- In embodiments of the invention, the self-limiting liner is an etch stop liner that is fabricated in a novel manner that limits the formation of the etch stop liner to the region or surface where the etch stop liner is needed. Because the etch stop liner is not on portions of the contact trench where protection is not needed (e.g., along the trench sidewalls), more lateral space in the contact trench can be allocated to the contact, which allows for the formation of a wider contact, thereby improving contact resistance and facilitating the use of different types of conductive contact material in the n-type and p-type transistors on the wafer.
- Aspects of the invention can be applied to planar or non-planar MOSFET architectures (e.g., FinFETs, VFETs, etc.). For example, aspects of the invention can be applied to an n-type FinFET architecture having a S/D region formed from a doped first type of semiconductor material (e.g., Si). A S/D contact trench of the FinFET is the space over the S/D region in which the S/D contact will be formed. Thus, the S/D contact trench can be defined by the top surface of the S/D region and the gate sidewalls that extend above and on opposite sides of the S/D region top surface. During the operations for fabricating the FinFET, a protective material (e.g., aSi) can be formed in the S/D contact trench prior to forming the actual S/D contact therein. The protective material must be removed from the S/D contact trench prior to forming the S/D contact. Accordingly, an etch stop layer can be formed in accordance with aspects of the invention over the top surface of the S/D region in order to protect the S/D region from damage when the protective material is removed to open up the S/D contact trench. The etch stop layer can be formed according to aspects of the invention as a self-limiting liner that is fabricated in a manner that limits the formation of the etch stop liner to the top surface of the S/D region where the etch stop liner is needed. Because the etch stop liner formed in accordance with aspects of the invention is not formed along the gate sidewalls, more lateral space in the S/D contact trench can be allocated to the S/D contact, which allows for the formation of a wider S/D contact, thereby improving contact resistance and facilitating the use of different types of conductive contact material in the n-type and p-type transistors on the wafer.
- In embodiments of the invention, the etch stop liner is formed in the S/D contact trench prior to depositing the protective material. The etch stop liner according to aspects of the invention is self-limiting in that it is formed according to a process that leverages a controlled chemical reaction. The novel etch stop fabrication process can include forming a layer of material over a top surface of the doped S/D region. The doped S/D region is formed from a doped first type of semiconductor material (e.g., Si), and the deposited layer of material is formed from a combination of the first type of semiconductor material (e.g., Si) and a second type of semiconductor material (e.g., germanium (Ge)). In embodiments of the invention, the layer of SiGe material can be deposited or formed using an epitaxial growth process. Using an epitaxially growth process, the layer of SiGe material can be grown from the top surface of the doped Si S/D region, which substantially confines the layer of SiGe material top surface of the doped Si S/D region where the etch stop protection will be needed. In some embodiments of the invention, the layer of SiGe material is grown during a S/D epitaxy process (i.e., after S/D epitaxy, continue the epitaxy process to grow SiGe layer). Therefore, no additional process is needed. Another layer that includes an oxide of the second type of semiconductor material (e.g., a layer of GeO2) is deposited within the S/D contact trench, and more specifically over the SiGe layer and along sidewalls of the gate spacers that extend above and on opposite sides of the S/D region. GeO2 can be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition technique.
- The controlled chemical reaction according to aspects of the invention is facilitated by applying at least one anneal operation to the GeO2 layer and the SiGe layer, wherein the at least one anneal operation is sufficient to result in the portion of the GeO2 layer that is over the SiGe layer interacting with the SiGe layer to begin converting that portion of the GeO2 layer to SiO2. In some embodiments of the invention, the at least one anneal operation includes a first anneal at a first predetermined temperature (e.g., about 700 Celsius) in an inert gas environment (e.g., nitrogen, argon, helium, neon, hydrogen). In embodiments of the invention, a second anneal at a second predetermined temperature/environment can be applied, wherein the second predetermined temperature is less than the first predetermined temperature, and wherein the environment is also an inert gas (e.g., nitrogen, argon, helium, neon, hydrogen).
-
FIG. 14 depicts a diagram illustrating an example of the above-described selective formation of a SiO2 layer from an anneal-driven reaction between GeO2 and SiGe. As shown inFIG. 14 , the pre-anneal structure is a GeO2 layer 1402 over a SiGe 20% layer 1404, which is over aSi layer 1412. The notation “SiGe20%” indicates that the SiGe material contains 20% Ge and 80% Si. The post-anneal structure is a SiO2 layer 1406 over aSiGe40% layer 1408, which is over a SiGe 20% layer 1410. The SiGe 20% layer 1410 is over theSi layer 1412. - The anneal reaction proceeds according to
Equation 1 shown inFIG. 14 . The GeO2 layer 1402 will react with the SiGe 20% layer 1404, thus leading to a condensation of Ge and converting the GeO2 layer 1402 to SiO2, thereby forming the SiO2 layer 1406. As the reaction proceeds, more Si in theSiGe20% layer 1404 is oxidized to SiO2, and the surface of theSiGe20% layer 1404 is continuously enriched with additional Ge. The additional Ge flowing into theSiGe20% layer 1404 leads to a condensation of Ge that spreads inward from the surface interface between thelayers SiGe layer 1408 continues to increase until the desired ratios are reached. - In embodiments of the invention, the self-limiting etch stop layer formation process can be well-controlled, as the reaction of GeO2 with the SiGe only occurs during the anneal, which can, in some embodiments be a spike anneal at a temperature from about 500-700 degrees Celsius. The selective SiO2 formation in this manner is self-limited and will continue until either all of the GeO2 is consumed or the SiGe surface becomes sufficiently enriched with germanium that the
Equation 1 reaction cannot proceed. For example, if a relatively thick GeO2 layer is used, the reaction will stop when available Si atoms are not enough at the SiGe surface. Consequently, the severity of the self-limiting etch stop layer formation process can be tuned by adjusting the thickness of the GeO2 layer that has been deposited on the SiGe layer, or by adjusting the anneal temperature/duration. - The gate spacers that define a portion of the S/D contact trench are formed from a material (e.g., SiN) that does not react with GeO2. Accordingly, the annealing method of the present invention is highly selective to SiGe, and, after the necessary reactions shown in
Equation 1 have completed, the unreacted GeO2 in the can be easily removed by exposing it to a water containing wash because GeO2 is water soluble. - Turning now to a more detailed description of aspects of the present invention,
FIG. 2A depicts asemiconductor structure 200 after initial fabrication stages according to embodiments of the invention. Known fabrication operations have been used to form thesemiconductor structure 200 shown inFIG. 2A . A variety of fabrication operations are suitable for fabricating thesemiconductor structure 200 to the stage shown inFIG. 2A . Because the fabrication operations are well-known, they have been omitted in the interest of brevity. In embodiments of the invention, thestructure 200 will be, after completion of the fabrication processes, a group of in-series n-type MOSFETs (e.g., n-type MOSFET 240) formed in annFET region 204 of a Si wafer/substrate 202, along with a group of in-series p-type MOSFETs (e.g., p-type MOSFET 340) formed in apFET region 304 of the Si wafer/substrate 202. In the example depicted inFIG. 2A , the n-type MOSFET 240 and the p-type MOSFET 340 are FinFET architectures having doped Si raised S/D regions - In the
nFET region 204 of thesubstrate 202, the n-type MOSFET 240 includes aSi channel region 210B (which can be lightly doped or undoped), doped-Si S/D regions gate 230B, ahardmask 232B, andgate spacers 234B, configured and arranged as shown. To the left of the n-type MOSFET 240 are aSi channel 210A (which can be slightly doped or lightly doped), agate 230A, ahardmask 232A, andgate spacers 234A, configured and arranged as shown. In the embodiment of the invention depicted inFIG. 2A , the n-type MOSFET 240 shares the S/D region 220A with a first in-series n-type MOSFET that is in series with the n-type MOSFET 240 and is formed from aSi channel 210A, agate 230A, ahardmask 232A,gate spacers 234A, and another doped-Si S/D region (not shown) adjacent to and communicatively coupled with thechannel region 210A. To the right of the n-type MOSFET 240 are aSi channel 210C (which can be lightly doped), agate 230C, ahardmask 232C, andgate spacers 234C, configured and arranged as shown. In the embodiment of the invention depicted inFIG. 2A , the n-type MOSFET 240 shares the S/D region 220B with a second in-series n-type MOSFET that is in series with the n-type MOSFET 240 and is formed from aSi channel 210C (which can be lightly doped), agate 230C, ahardmask 232C,gate spacers 234C, and another doped Si S/D region (not shown) adjacent to and communicatively coupled with thechannel region 210C. A first S/D contact trench 222A is defined by a top surface of the S/D region 220A and sidewalls of thegate spacers D contact trench 222B is defined by a top surface of the S/D region 220B and sidewalls of thegate spacers - Similarly, in the
pFET region 304 of thesubstrate 202, the p-type MOSFET 340 includes aSi channel region 310B (which can be lightly doped), doped-SiGe S/D regions gate 330B, ahardmask 332B, andgate spacers 334B, configured and arranged as shown. To the left of the p-type MOSFET 340 are aSi channel 310A (which can be slightly doped), agate 330A, ahardmask 332A, andgate spacers 334A, configured and arranged as shown. In the embodiment of the invention depicted inFIG. 2A , the p-type MOSFET 340 shares the S/D region 320A with a first in-series p-type MOSFET that is in series with the p-type MOSFET 340 and is formed from aSi channel 310A (which can be lightly doped or undoped), agate 330A, ahardmask 332A,gate spacers 334A, and another doped SiGe S/D region (not shown) adjacent to and communicatively coupled with thechannel region 310A. To the right of the p-type MOSFET 340 are a Si channel 310C (which can be lightly doped), agate 330C, ahardmask 332C, andgate spacers 334C, configured and arranged as shown. In the embodiment of the invention depicted inFIG. 2A , the p-type MOSFET 340 shares the S/D region 320B with a second in-series p-type MOSFET that is in series with the p-type MOSFET 340 and is formed from a Si channel 310C, agate 330C, ahardmask 332C,gate spacers 334C, and another doped SiGe S/D region (not shown) adjacent to and communicatively coupled with the channel region 310C. A first high aspect-ratio S/D contact trench 322A is defined by a top surface of the S/D region 320A and sidewalls of thegate spacers D contact trench 322B is defined by a top surface of the S/D region 320B and sidewalls of thegate spacers type MOSFET 240 and the p-type MOSFET 340 can have the same channel material (e.g., Si). Alternatively, the n-type MOSFET 240 and the p-type MOSFET 340 can have different channel material (e.g., n-type MOSFET 240 has Si channels, and p-type MOSFET 340 has SiGe channels). - The
gates gates - In general, gate dielectrics can include any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, high-k materials, or any combination of these materials. Examples of high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k can further include dopants such as lanthanum, aluminum, magnesium.
- In general, the gate conductor can include any suitable conducting material. The conductive material can further include dopants that are incorporated during or after deposition. In some embodiments, the gate can further include a workfunction setting layer between the gate dielectric and gate conductor. The workfunction setting layer can be a workfunction metal (WFM). WFM can be any suitable material. In some embodiments of the invention, a conductive material or a combination of multiple conductive materials can serve as both gate conductor and WFM. The gate conductor and WFM can be formed by any suitable process or any suitable combination of multiple processes. In general, the gate spacer can include any suitable dielectric materials.
-
FIG. 2B illustrates the space constraints that result from reducing transistor foot print by forming the S/D contact trenches FIG. 2A ) to have increasingly higher aspect-ratios. The dimensions depicted inFIG. 2B for the S/D contact trench 222B apply equally to the S/D contact trenches FIG. 2B , the S/D contact trench 222B is defined by a top surface of the S/D region 220B and inner sidewalls ofgate spacers D contact trench 220B are defined by a height dimension (H), a width dimension (W), and a Z dimension (shown by the X/Y/Z diagram). The portion of the S/D contact trench 222B that is allocated to the required liner (i.e., thecontact liner 1202 shown inFIG. 12 ) is defined by the height dimension H, the width dimensions A, and the Z dimension. In accordance with aspects of the invention, after forming a contact liner 1202 (shown inFIG. 12 ), the remaining space in the S/D contract trench 222B for forming the S/D contact 1302A (shown inFIG. 13 ) is defined by the height dimension H, the width dimension B, and the Z dimension. - Referring still to the S/
D contact trench 222B inFIG. 2B , in a typical FinFET MOSFET architecture, H can be about 100 nm, W can be about 15 nm, and the contact liner 1202 (shown inFIG. 12 ) can be about 5 nm. In this example, about 5 nm of width is left for forming the S/D contact 1302A, and the available volume of the S/D contact trench 222B is increased because, in accordance with aspects of the invention, none of the volume of the S/D contact trench 222B is allocated to an etch stop liner. The increase in available space in the S/D contact trench 222B enables the formation of relatively wider high aspect-ratio S/D contacts. In embodiments of the invention, a novel self-limiting liner is utilized to increase the portion of the S/D contact trench volume that is available for forming the contact therein. With more of the S/D contact trench's volume available for the contact, a larger contact can be formed, which decreases contact resistance and facilitates the use of different types of conductive contact material in the n-type and p-type transistors on the wafer. The n-type transistor conductive contact material (e.g., S/D contact 1302A shown inFIG. 13 ) can be selected based at least in part on its ability to reduce contact resistance in an n-type transistor environment. The p-type transistor conductive contact material (e.g., S/D contact 1302B shown inFIG. 13 ) can be selected based at least in part on its ability to reduce contact resistance in a p-type transistor environment. Accordingly, aspects of the invention, and specifically the increase in available S/D contact trench volume, facilitate controlling or tuning n-type transistor contact resistance independently from p-type transistor contact resistance. - In embodiments of the invention, the self-limiting liner is an etch stop liner (e.g.,
SiO2 layer 502 andSiGe layer 224A′ shown inFIG. 5 ), which is fabricated in a novel manner that limits the formation of the etch stop liner to the region or surface (e.g., the top surfaces of the S/D regions gate spacers D contact trench 222B can be allocated to the S/D contact (e.g., S/D contact 1302A shown inFIG. 13 ), which allows for the formation of a wider S/D contact, thereby improving (i.e., reducing) contact resistance and facilitating the use of different types of conductive contact material in the n-type and p-type transistors on the wafer. -
FIGS. 3-12 depict the result of various fabrication operations applied to thesemiconductor structure 200 for forming self-limiting etch stop liners (e.g.,SiO2 layer 502 andSiGe layer 224A′ shown inFIG. 5 ) in the S/D contact trenches FIGS. 3-12 describe fabrication operations applied to thenFET region 204 of thesubstrate 202. However, substantially the same fabrication operations can be applied to thesemiconductor structure 200 for forming self-limiting etch stop liners (e.g.,SiO2 layer 502A′ shown inFIG. 13 ) in the S/D contact trenches pFET region 304 of thesubstrate 202. Because the S/D regions type MOSFET 340 are formed from SiGe, depositing SiGe layers corresponding to the SiGe layers 224A, 224B can, optionally, be omitted. - In
FIG. 3 , known fabrication operations have been used to form SiGe layers 224A, 224B over top surfaces of the doped-Si S/D regions SiGe - In
FIG. 4 , known fabrication processes (e.g., an atomic layer deposition (ALD)) have been used to conformally deposit alayer 402 formed from a material that includes an oxide of Ge (e.g., GeO2). The GeO2 layer 402 is conformally deposited over thesemiconductor structure 200 to cover the SiGe layers 224A, 224B and sidewalls of thegate spacers D contact trenches - In
FIG. 5 , at least one anneal operation has been applied to the GeO2 layer 402 (shown inFIG. 4 ) and the SiGe layers 224A, 224B (shown inFIG. 4 ) to enable a reaction that forms SiO2 layers 502 andSiGe layers 224A′, 224B that each have a different Ge concentration than the SiGe layers 224A, 224B, respectively. The at least one anneal operation is sufficient to result in the GeO2 layer 402 and the SiGe layers 224A, 224B interacting (or reacting) to convert the portions of the GeO2 layer 402 that are over the SiGe layers 224A, 224B to the SiO2 layers 502. Concurrently, the at least one anneal operation is sufficient to result in Ge diffusing from the original GeO2 layer 402 into the SiGe layers 224A, 224B to increase the Ge concentrations thereof and form the of the SiGe layers 224A′, 224B′. In some embodiments of the invention, the at least one anneal operation includes a first anneal at a first predetermined temperature (e.g., a spike anneal at about 700 degrees Celsius) in a nitrogen ambient. In embodiments of the invention, the at least one anneal operation can further include a second anneal at a second predetermined temperature (e.g., about 450 degrees Celsius) in a nitrogen ambient, wherein the second predetermined temperature is less than the first predetermined temperature. Additional details of the above-described reaction are depicted inFIG. 14 and were previously described in this detailed description. Any inert environment (e.g., nitrogen, argon, helium, neon) can be used in the anneal. - As also shown in
FIG. 5 , subsequent to the above-described anneal(s), the unreacted portions of the GeO2 layer 402 (shown inFIG. 4 ) have been removed by exposing the unreacted portions of the GeO2 layer 402 to a water containing wash because GeO2 is water soluble. In areas other than where it is desired to form the SiO2 layer 502, materials are used that do not substantially react with GeO2 in the manner depicted byEquation 1 ofFIG. 14 . For example, thehardmasks gate spacers - In
FIG. 6 , known fabrication operations have been used to deposit a protective material (e.g., amorphous Si (aSi)) 602A, 602B in the S/D contract trenches FIG. 5 ). In embodiments of the invention, theprotective material 602A is overfilled in the S/D contract trenches FIG. 6 . The purpose of aSi is to serve as a sacrificial filling material filling any gaps between gates. The SiO2 is needed on top of the S/D epitaxy so that later the aSi can be removed without also attacking the S/D epitaxy. It is noted that the S/D epitaxy and aSi are all semiconductor materials so they have poor etch selectivity between each other. Subsequently, the aSi is removed in contact region and replaced with conducting contact materials. The aSi in non-contact trench region is then removed and replaced with a dielectric material or dielectric material(s). The advantage of having aSi as the sacrificial material is that it can be removed very selective to SiO2. Therefore, even a thin SiO2 layer, e.g., 3 nm, is sufficient to serve as an etch stop layer to protect the S/D epitaxy when removing aSi from the contact trench. - In
FIG. 7 , known semiconductor fabrication processes have been used to deposit a blockingmask 802 over theaSi 602B. In embodiments of the invention, the blockingmask 802 can be any suitable masking material, including but not limited to, photoresist, photoresist in conjunction with an organic planarization layer (OPL), or any suitable hardmask material. In general, OPLs are used to fill pre-existing features, and to planarize the substrate to allow for larger patterning process windows. - In
FIG. 8 , known semiconductor fabrication processes (e.g., a reactive ion etch (RIE)) have been used to remove theaSi 602A (shown inFIG. 7 ), thereby reopening the S/D contact trench 222A. In accordance with aspects of the invention, theSiO2 layer 502 functions as an etch-stop layer that prevents the RIE that was used to remove theaSi 602A from also removing portions of the S/D region 220A, particularly where both theaSi 602A and the doped-Si S/D region 220A are formed from Si. SiO2 also protects doped SiGe S/D in p-type MOSFET region. - In
FIG. 9 , the blocking mask 802 (shown inFIG. 8 ) has been removed, and known semiconductor fabrication operations have been used to form a protective interlayer dielectric (ILD)region 902 in the S/D contact trench 222 a (shown inFIG. 8 ). The ILD region (or dummy contact) 902 can be formed by depositing any suitable dielectric material or materials. For example, an oxide material such as spin-on-glass or flowable oxide can be used to fill the trenches. Planarization processes (e.g., using CMP) can be used to bring theILD region 902 to the level of thegate spacers hardmasks ILD 902 can further include a dielectric liner (e.g., silicon nitride) in the dummy contact sidewalls before filling the rest of the dummy contact trench with flowable oxide. The ILD region (or dummy contact) 902 is deposited in the S/D contact trench 222A because the series coupling of multiple instances of the n-type MOSFET 240, which was previously described herein, means that a conductive contact does not need to be made to every S/D region. In other cases, theILD region 902 serves as the isolation between adjacent devices. In accordance with embodiments of the invention, each S/D contact trench that has been filled with a S/D conductive contact is adjacent a S/D contact trench that has been filled with a nonconductive material such asILD 902. - More specifically, with respect to the series coupling of multiple instances of the n-
type MOSFET 240, as previously described herein, to the left of the n-type MOSFET 240 are theSi channel 210A (which can be slightly doped), thegate 230A, thehardmask 232A, andgate spacers 234A, configured and arranged as shown. In the embodiment of the invention depicted inFIG. 9 , the n-type MOSFET 240 shares the S/D region 220A with a first in-series n-type MOSFET that is in series with the n-type MOSFET 240 and is formed from theSi channel 210A (which can be lightly doped), thegate 230A, thehardmask 232A,gate spacers 234A, and another doped-Si S/D region (not shown) adjacent to and communicatively coupled with thechannel region 210A. To the right of the n-type MOSFET 240 are theSi channel 210C (which can be lightly doped), thegate 230C, thehardmask 232C, andgate spacers 234C, configured and arranged as shown. In the embodiment of the invention depicted inFIG. 9 , the n-type MOSFET 240 shares the S/D region 220B with a second in-series n-type MOSFET that is in series with the n-type MOSFET 240 and is formed from theSi channel 210C (which can be lightly doped), thegate 230C, thehardmask 232C,gate spacers 234C, and another doped Si S/D region (not shown) adjacent to and communicatively coupled with thechannel region 210C. Because theILD region 902 has been deposited in the S/D contact trench 222A, a conductive S/D contact will be formed over the S/D region of the in-series n-type MOSFET that is to the left of the n-type MOSFET 240. Because a conductive S/D contact 1302A (shown inFIG. 13 ) will be deposited in the S/D contact trench 222B (shown inFIG. 10 ), an ILD region similar toILD region 902 will be formed over the S/D region of the in-series n-type MOSFET that is to the right of the n-type MOSFET 240. - In
FIG. 10 , known semiconductor fabrication processes have been used to remove theaSi 602B (shown inFIG. 9 ), thereby reopening the S/D contact trench 222B. In embodiments of the invention, the known fabrication processes include a RIE process, a wet etch process such as ammonia etch, a silicon plasma etch, or a silicon dry etch. In embodiments of the invention, the etch can be isotropic or anisotropic. In embodiments of the invention, etch is isotropic so all remaining aSi in the contact trenches can be removed. In accordance with aspects of the invention, the SiO2 layer 502 functions as an etch-stop layer that prevents the RIE that was used to remove theaSi 602B from also removing portions of the S/D region 220B. - In
FIG. 11 , known semiconductor fabrication processes have been used to remove the SiO2 layer 502 and theSiGe layer 224B′ from over the S/D region 220B in the S/D contact trench 222B. In accordance with aspects of the invention, a pre-clean operation can be applied to the inner surfaces of the S/D contact trench 222B prior to depositing the contact liner 1202 (shown inFIG. 12 ), and the pre-clean operation can be configured and arranged to also remove the SiO2 layer 502 and theSiGe layer 224B′ from over the S/D region 220B in the S/D contact trench 222B. In some embodiment of the invention, a wet etch such as diluted hydrofluoric acid can be used to serve dual purposes: simultaneously removing SiO2 and serving as pre-clean step before depositing conducting material on top of the S/D. - In
FIG. 12 , known semiconductor fabrication processes have been used to form thecontact liner 1202, which is configured and arranged to minimize contact resistance. For an n-type S/D, theliner 1202 can be titanium (Ti). For an n-type S/D, theliner 1202 can also be nickel platinum (NiPt). The “bulk” contact (or fill material) 1302 can include conducting metal(s), which can be the same for both the n-type S/D and the p-type S/D. The metal contact fill 1302 can be tungsten (W), aluminum (Al), copper (Cu), or cobalt (Co), and can further include a barrier layer (not shown). The barrier layer can be titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), niobium nitride (NbN), tungsten nitride (WN), or combinations thereof, where the barrier layer can prevent diffusion and/or alloying of the metal contact fill material with the top source drain material, and/or anode/cathode material. In embodiments of the invention, the barrier layer can be conformally deposited in the trench(es) by ALD, CVD, MOCVD, PECVD, or combinations thereof. In embodiments of the invention, the metal fill 1302 can be formed by ALD, CVD, and/or PVD to form the electrical contacts. -
FIG. 13 depicts thesemiconductor structure 200 showing the results of the above-described fabrication processes applied to both thenFET region 204 and thepFET region 304. Additionally, inFIG. 13 , known semiconductor fabrication processes have been used to form the S/D contacts D contact 1302A can be formed from any suitable conducting material. Examples of suitable materials for the S/D contact 1302A include titanium (Ti). In embodiments of the invention, the S/D contact 1302B can be formed from any suitable conducting material. Examples of suitable materials for the S/D contact 1302B include NiPt (nickel platinum). The S/D contacts - In embodiments of the invention, different conductive materials can be deposited on n-type S/D and p-type S/D to minimize the contact resistance of n-type and p-type S/D, respectively. Three approaches can be used to achieve this goal. First, the different conductive materials can be two different conductive liners (e.g., Ti for n-type S/D and NiPt for p-type S/D) with the remaining contact trenches filled with a common conductive material (e.g., tungsten or cobalt). Second, the entire n-type S/D contact trench can be filled with Ti, and the entire p-type S/D contact trench can be filled with NiPt. Third, the entire n-type S/D contact trench can be filled with Ti, and the entire p-type S/D contact trench can be filled with NiPt liner plus tungsten or cobalt filling the rest of the p-type contact trench.
- In the embodiments of the invention, the
gates dummy gates dummy gates 230, 240 can be removed using a so-called poly open CMP (POC) process in which thedummy gates gate spacers - The terms “about,” “substantially,” “approximately,” “slightly less than,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value.
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/475,595 US20220005735A1 (en) | 2018-06-07 | 2021-09-15 | Self-limiting liners for increasing contact trench volume in n-type and p-type transistors |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/002,559 US10665511B2 (en) | 2018-06-07 | 2018-06-07 | Self-limiting liners for increasing contact trench volume in N-type and P-type transistors |
US16/564,666 US11183430B2 (en) | 2018-06-07 | 2019-09-09 | Self-limiting liners for increasing contact trench volume in n-type and p-type transistors |
US17/475,595 US20220005735A1 (en) | 2018-06-07 | 2021-09-15 | Self-limiting liners for increasing contact trench volume in n-type and p-type transistors |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/564,666 Continuation US11183430B2 (en) | 2018-06-07 | 2019-09-09 | Self-limiting liners for increasing contact trench volume in n-type and p-type transistors |
Publications (1)
Publication Number | Publication Date |
---|---|
US20220005735A1 true US20220005735A1 (en) | 2022-01-06 |
Family
ID=68764224
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/002,559 Active US10665511B2 (en) | 2018-06-07 | 2018-06-07 | Self-limiting liners for increasing contact trench volume in N-type and P-type transistors |
US16/564,666 Active US11183430B2 (en) | 2018-06-07 | 2019-09-09 | Self-limiting liners for increasing contact trench volume in n-type and p-type transistors |
US17/475,595 Pending US20220005735A1 (en) | 2018-06-07 | 2021-09-15 | Self-limiting liners for increasing contact trench volume in n-type and p-type transistors |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/002,559 Active US10665511B2 (en) | 2018-06-07 | 2018-06-07 | Self-limiting liners for increasing contact trench volume in N-type and P-type transistors |
US16/564,666 Active US11183430B2 (en) | 2018-06-07 | 2019-09-09 | Self-limiting liners for increasing contact trench volume in n-type and p-type transistors |
Country Status (1)
Country | Link |
---|---|
US (3) | US10665511B2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10665511B2 (en) * | 2018-06-07 | 2020-05-26 | International Business Machines Corporation | Self-limiting liners for increasing contact trench volume in N-type and P-type transistors |
US11205709B2 (en) * | 2018-06-25 | 2021-12-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect filling in patterned layer |
US10985272B2 (en) * | 2018-11-05 | 2021-04-20 | Samsung Electronics Co., Ltd. | Integrated circuit devices including vertical field-effect transistors |
FR3088481A1 (en) * | 2018-11-14 | 2020-05-15 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD FOR MANUFACTURING A FIELD-JUNCTION FIELD-EFFECT TRANSISTOR WITH SPACERS |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080083955A1 (en) * | 2006-10-04 | 2008-04-10 | Kanarsky Thomas S | Intrinsically stressed liner and fabrication methods thereof |
US20130241004A1 (en) * | 2012-03-14 | 2013-09-19 | Huaxiang Yin | Semiconductor device and method of manufacturing the same |
US11183430B2 (en) * | 2018-06-07 | 2021-11-23 | International Business Machines Corporation | Self-limiting liners for increasing contact trench volume in n-type and p-type transistors |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE602007000665D1 (en) | 2006-06-12 | 2009-04-23 | St Microelectronics Sa | Process for the preparation of Si1-yGey based zones with different Ge contents on one and the same substrate by means of condensation of germanium |
US8211761B2 (en) | 2006-08-16 | 2012-07-03 | Globalfoundries Singapore Pte. Ltd. | Semiconductor system using germanium condensation |
US7692213B2 (en) | 2007-08-07 | 2010-04-06 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit system employing a condensation process |
US7851790B2 (en) | 2008-12-30 | 2010-12-14 | Intel Corporation | Isolated Germanium nanowire on Silicon fin |
US8211772B2 (en) * | 2009-12-23 | 2012-07-03 | Intel Corporation | Two-dimensional condensation for uniaxially strained semiconductor fins |
US9171715B2 (en) | 2012-09-05 | 2015-10-27 | Asm Ip Holding B.V. | Atomic layer deposition of GeO2 |
US9330899B2 (en) | 2012-11-01 | 2016-05-03 | Asm Ip Holding B.V. | Method of depositing thin film |
US9299809B2 (en) * | 2012-12-17 | 2016-03-29 | Globalfoundries Inc. | Methods of forming fins for a FinFET device wherein the fins have a high germanium content |
KR102251060B1 (en) | 2015-04-06 | 2021-05-14 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing semiconductor devices |
US9786664B2 (en) * | 2016-02-10 | 2017-10-10 | International Business Machines Corporation | Fabricating a dual gate stack of a CMOS structure |
US10079233B2 (en) * | 2016-09-28 | 2018-09-18 | International Business Machines Corporation | Semiconductor device and method of forming the semiconductor device |
US10854715B2 (en) * | 2018-04-13 | 2020-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Supportive layer in source/drains of FinFET devices |
-
2018
- 2018-06-07 US US16/002,559 patent/US10665511B2/en active Active
-
2019
- 2019-09-09 US US16/564,666 patent/US11183430B2/en active Active
-
2021
- 2021-09-15 US US17/475,595 patent/US20220005735A1/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080083955A1 (en) * | 2006-10-04 | 2008-04-10 | Kanarsky Thomas S | Intrinsically stressed liner and fabrication methods thereof |
US20130241004A1 (en) * | 2012-03-14 | 2013-09-19 | Huaxiang Yin | Semiconductor device and method of manufacturing the same |
US11183430B2 (en) * | 2018-06-07 | 2021-11-23 | International Business Machines Corporation | Self-limiting liners for increasing contact trench volume in n-type and p-type transistors |
Also Published As
Publication number | Publication date |
---|---|
US20190378764A1 (en) | 2019-12-12 |
US20190393103A1 (en) | 2019-12-26 |
US11183430B2 (en) | 2021-11-23 |
US10665511B2 (en) | 2020-05-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11456383B2 (en) | Semiconductor device having a contact plug with an air gap spacer | |
US11183430B2 (en) | Self-limiting liners for increasing contact trench volume in n-type and p-type transistors | |
US11901411B2 (en) | Semiconductor device and method | |
US11823949B2 (en) | FinFet with source/drain regions comprising an insulator layer | |
US10840147B1 (en) | Fin cut forming single and double diffusion breaks | |
US11217679B2 (en) | Semiconductor device and method | |
KR20200050324A (en) | Fin field-effect transistor device and method | |
US20230387246A1 (en) | Methods of forming gate structures with uniform gate length | |
US20230035349A1 (en) | Semiconductor Device and Method | |
US20230352589A1 (en) | Source/drain regions of finfet devices and methods of forming same | |
US10950506B2 (en) | Forming single and double diffusion breaks | |
US11757020B2 (en) | Semiconductor device and method | |
US11495661B2 (en) | Semiconductor device including gate barrier layer | |
US11688807B2 (en) | Semiconductor device and methods of forming | |
US11527621B2 (en) | Gate electrode deposition and structure formed thereby | |
US11810948B2 (en) | Semiconductor device and method | |
US20230008994A1 (en) | Semiconductor device with dielectric layer and method of forming the same | |
US20230260832A1 (en) | Semiconductor Devices and Methods | |
US20230008494A1 (en) | Gate structures in transistor devices and methods of forming same | |
US20230065620A1 (en) | Semiconductor device and method | |
US20230163075A1 (en) | Semiconductor Device and Method | |
US20220384611A1 (en) | Dielectric layer on semiconductor device and method of forming the same | |
US20230043635A1 (en) | Semiconductor device and method | |
US20230317859A1 (en) | Transistor gate structures and methods of forming thereof | |
US20230343822A1 (en) | Transistor Gate Structures and Methods of Forming the Same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHENG, KANGGUO;LEE, CHOONGHYUN;LI, JUNTAO;AND OTHERS;REEL/FRAME:057488/0515 Effective date: 20180605 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: ADVISORY ACTION MAILED |
|
STCV | Information on status: appeal procedure |
Free format text: NOTICE OF APPEAL FILED |
|
STCV | Information on status: appeal procedure |
Free format text: EXAMINER'S ANSWER TO APPEAL BRIEF MAILED |
|
STCV | Information on status: appeal procedure |
Free format text: ON APPEAL -- AWAITING DECISION BY THE BOARD OF APPEALS |