US20210326066A1 - Dynamic Memory Controller and Method for Use Therewith - Google Patents
Dynamic Memory Controller and Method for Use Therewith Download PDFInfo
- Publication number
- US20210326066A1 US20210326066A1 US16/853,233 US202016853233A US2021326066A1 US 20210326066 A1 US20210326066 A1 US 20210326066A1 US 202016853233 A US202016853233 A US 202016853233A US 2021326066 A1 US2021326066 A1 US 2021326066A1
- Authority
- US
- United States
- Prior art keywords
- memory
- interface
- controller
- processor
- memory controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 211
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000012937 correction Methods 0.000 claims abstract description 16
- 238000001514 detection method Methods 0.000 claims abstract description 14
- 230000002093 peripheral effect Effects 0.000 claims description 12
- 239000011159 matrix material Substances 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 17
- 239000000047 product Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 12
- 238000004891 communication Methods 0.000 description 9
- 230000006870 function Effects 0.000 description 9
- 238000007726 management method Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 7
- 238000003491 array Methods 0.000 description 6
- 239000000872 buffer Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 239000000835 fiber Substances 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000013519 translation Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 239000011370 conductive nanoparticle Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000012005 ligant binding assay Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000012782 phase change material Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
- G06F11/108—Parity data distribution in semiconductor storages, e.g. in SSD
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0634—Configuration or reconfiguration of storage systems by changing the state or mode of one or more devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
Definitions
- a memory controller in a storage system can be implemented as an application-specific integrated circuit (ASIC) and often has a memory interface for communicating with a memory of the storage system and a host interface for communicating with a host (e.g., for receiving read/write commands from the host and for receiving data from and sending data to the host).
- ASIC application-specific integrated circuit
- the memory interface and the host interface can be designed to work with a specific protocol or standard.
- FIG. 1A is a block diagram of a non-volatile storage system of an embodiment.
- FIG. 1B is a block diagram illustrating a storage module of an embodiment.
- FIG. 1C is a block diagram illustrating a hierarchical storage system of an embodiment.
- FIG. 2 is a block diagram illustrating components of the controller of the non-volatile storage system illustrated in FIG. 1A according to an embodiment.
- FIG. 3 is a block diagram illustrating components of the non-volatile storage system illustrated in FIG. 1A according to an embodiment.
- FIG. 4 is a block diagram of a controller of an embodiment.
- FIG. 5 is a block diagram of a controller of an embodiment with fixed and configurable hardware components.
- FIG. 6 is a flow chart of a method for using a controller of an embodiment.
- a memory controller comprising fixed components (e.g., in an application-specific integrated circuit (ASIC)) and dynamically-programmable components (e.g., outside of the ASIC).
- the dynamically-programmable components can be used to configure the memory controller to be used with any number of selected host and/or memory types, as well as to enable the memory controller with different error detection/correction functionality.
- the dynamically-programmable components can be used to provide the memory controller with other types of functionality.
- Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the attached drawings.
- FIG. 1A is a block diagram illustrating a non-volatile storage system 100 (sometimes referred to herein as a storage device or just device) according to an embodiment of the subject matter described herein.
- non-volatile storage system 100 includes a controller 102 and non-volatile memory that may be made up of one or more non-volatile memory die 104 .
- the term die refers to the collection of non-volatile memory cells, and associated circuitry for managing the physical operation of those non-volatile memory cells, that are formed on a single semiconductor substrate.
- Controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to non-volatile memory die 104 .
- the controller 102 (which may be a non-volatile memory controller (e.g., a flash, resistive random-access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random-access memory (MRAM) controller)) can take the form of processing circuitry, a microprocessor or processor, and a computer-readable medium that stores computer-readable program code (e.g., firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example.
- the controller 102 can be configured with hardware and/or firmware to perform the various functions described below and shown in the flow diagrams.
- the components shown as being internal to the controller can also be stored external to the controller, and other components can be used. Additionally, the phrase “operatively in communication with” could mean directly in communication with or indirectly (wired or wireless) in communication with through one or more components, which may or may not be shown or described herein.
- a non-volatile memory controller is a device that manages data stored on non-volatile memory and communicates with a host, such as a computer or electronic device.
- a non-volatile memory controller can have various functionality in addition to the specific functionality described herein.
- the non-volatile memory controller can format the non-volatile memory to ensure the memory is operating properly, map out bad non-volatile memory cells, and allocate spare cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the non-volatile memory controller and implement other features.
- a host needs to read data from or write data to the non-volatile memory, it can communicate with the non-volatile memory controller.
- the non-volatile memory controller can convert the logical address received from the host to a physical address in the non-volatile memory. (Alternatively, the host can provide the physical address.)
- the non-volatile memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so the full block can be erased and reused).
- wear leveling distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to
- garbage collection after a block is full, moving only the valid pages of data to a new block, so the full block can be erased and reused.
- the structure for the “means” recited in the claims can include, for example, some or all of the structures of the controller described herein, programmed or manufactured as appropriate to cause the controller to operate to perform the recited functions.
- Non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random-access memory (ReRAM), magnetoresistive random-access memory (MRAM), phase-change memory (PCM), NAND flash memory cells and/or NOR flash memory cells.
- the memory cells can take the form of solid-state (e.g., flash) memory cells and can be one-time programmable, few-time programmable, or many-time programmable.
- the memory cells can also be single-level cells (SLC), multiple-level cells (MLC), triple-level cells (TLC), or use other memory cell level technologies, now known or later developed. Also, the memory cells can be fabricated in a two-dimensional or three-dimensional fashion.
- the interface between controller 102 and non-volatile memory die 104 may be any suitable flash interface, such as Toggle Mode 200 , 400 , or 800 .
- storage system 100 may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, storage system 100 may be part of an embedded storage system.
- SD secure digital
- micro-SD micro secure digital
- non-volatile storage system 100 (sometimes referred to herein as a storage module) includes a single channel between controller 102 and non-volatile memory die 104
- the subject matter described herein is not limited to having a single memory channel.
- 2, 4, 8 or more memory channels may exist between the controller and the memory device, depending on controller capabilities.
- more than a single channel may exist between the controller and the memory die, even if a single channel is shown in the drawings.
- FIG. 1B illustrates a storage module 200 that includes plural non-volatile storage systems 100 .
- storage module 200 may include a storage controller 202 that interfaces with a host and with storage system 204 , which includes a plurality of non-volatile storage systems 100 .
- the interface between storage controller 202 and non-volatile storage systems 100 may be a bus interface, such as a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe) interface, or double-data-rate (DDR) interface.
- Storage module 200 in one embodiment, may be a solid state drive (SSD), or non-volatile dual in-line memory module (NVDIMM), such as found in server PC or portable computing devices, such as laptop computers, and tablet computers.
- SSD solid state drive
- NVDIMM non-volatile dual in-line memory module
- FIG. 1C is a block diagram illustrating a hierarchical storage system.
- a hierarchical storage system 250 includes a plurality of storage controllers 202 , each of which controls a respective storage system 204 .
- Host systems 252 may access memories within the storage system via a bus interface.
- the bus interface may be a Non-Volatile Memory Express (NVMe) or fiber channel over Ethernet (FCoE) interface.
- NVMe Non-Volatile Memory Express
- FCoE fiber channel over Ethernet
- the system illustrated in FIG. 1C may be a rack mountable mass storage system that is accessible by multiple host computers, such as would be found in a data center or other location where mass storage is needed.
- FIG. 2 is a block diagram illustrating components of controller 102 in more detail.
- Controller 102 includes a front end module 108 that interfaces with a host, a back end module 110 that interfaces with the one or more non-volatile memory die 104 , and various other modules that perform functions which will now be described in detail.
- a module may take the form of a packaged functional hardware unit designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry that usually performs a particular function of related functions, or a self-contained hardware or software component that interfaces with a larger system, for example.
- the controller 102 may sometimes be referred to herein as a NAND controller or a flash controller, but it should be understood that the controller 102 can be used with any suitable memory technology, example of some of which are provided below.
- a buffer manager/bus controller 114 manages buffers in random access memory (RAM) 116 and controls the internal bus arbitration of controller 102 .
- a read only memory (ROM) 118 stores system boot code. Although illustrated in FIG. 2 as located separately from the controller 102 , in other embodiments one or both of the RAM 116 and ROM 118 may be located within the controller. In yet other embodiments, portions of RAM and ROM may be located both within the controller 102 and outside the controller.
- Front end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide the electrical interface with the host or next level storage controller.
- PHY physical layer interface
- the choice of the type of host interface 120 can depend on the type of memory being used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, serially attached small computer system interface (SAS), Fibre Channel, universal serial bus (USB), PCIe, and NVMe.
- SAS serially attached small computer system interface
- USB universal serial bus
- PCIe universal serial bus
- NVMe NVMe.
- the host interface 120 typically facilitates transfer for data, control signals, and timing signals.
- Back end module 110 includes an error correction code (ECC) engine 124 that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the non-volatile memory.
- ECC error correction code
- a command sequencer 126 generates command sequences, such as program and erase command sequences, to be transmitted to non-volatile memory die 104 .
- a RAID (Redundant Array of Independent Drives) module 128 manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the memory device 104 . In some cases, the RAID module 128 may be a part of the ECC engine 124 .
- a memory interface 130 provides the command sequences to non-volatile memory die 104 and receives status information from non-volatile memory die 104 .
- memory interface 130 may be a double data rate (DDR) interface, such as a Toggle Mode 200 , 400 , or 800 interface.
- DDR double data rate
- a flash control layer 132 controls the overall operation of back end module 110 .
- the storage system 100 also includes other discrete components 140 , such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with controller 102 .
- other discrete components 140 such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with controller 102 .
- one or more of the physical layer interface 122 , RAID module 128 , media management layer 138 and buffer management/bus controller 114 are optional components that are not necessary in the controller 102 .
- FIG. 3 is a block diagram illustrating components of non-volatile memory die 104 in more detail.
- Non-volatile memory die 104 includes peripheral circuitry 141 and non-volatile memory array 142 .
- Non-volatile memory array 142 includes the non-volatile memory cells used to store data.
- the non-volatile memory cells may be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells and/or NOR flash memory cells in a two dimensional and/or three dimensional configuration.
- Non-volatile memory die 104 further includes a data cache 156 that caches data.
- Peripheral circuitry 141 includes a state machine 152 that provides status information to the controller 102 .
- the flash control layer 132 (which will be referred to herein as the flash translation layer (FTL) or, more generally, the “media management layer,” as the memory may not be flash) handles flash errors and interfaces with the host.
- the FTL which may be an algorithm in firmware, is responsible for the internals of memory management and translates writes from the host into writes to the memory 104 .
- the FTL may be needed because the memory 104 may have limited endurance, may only be written in multiples of pages, and/or may not be written unless it is erased as a block.
- the FTL understands these potential limitations of the memory 104 , which may not be visible to the host. Accordingly, the FTL attempts to translate the writes from host into writes into the memory 104 .
- the FTL may include a logical-to-physical address (L2P) map (sometimes referred to herein as a table or data structure) and allotted cache memory. In this way, the FTL translates logical block addresses (“LBAs”) from the host to physical addresses in the memory 104 .
- LBAs logical block addresses
- the FTL can include other features, such as, but not limited to, power-off recovery (so that the data structures of the FTL can be recovered in the event of a sudden power loss) and wear leveling (so that the wear across memory blocks is even to prevent certain blocks from excessive wear, which would result in a greater chance of failure).
- the controller 102 is implemented as an application-specific integrated circuit (ASIC), all of its components are static.
- ASIC application-specific integrated circuit
- the memory interface 130 sometimes referred to herein as the flash interface module (FIM) when the memory 104 is NAND flash memory
- FIM flash interface module
- the controller 102 can only work with memory having that number of channels. If more channels are desired to increase the capacity of the memory 104 or the performance of the storage system 100 , the controller ASIC would need to be redesigned to support the increased number of channels.
- a similar problem can occur with the host interface 120 .
- the controller ASIC would need to be redesigned if the controller 102 is to be used with a host having a different interface (e.g., UFS, USB, PCIe, SD, SATA, or NVMe). So, a number of controller ASICs may need to be designed for each product or product line, as a single controller ASIC will not work for all the products and their different interfaces. Further, a new controller ASIC would be needed if a new memory technology is developed that is not supported by the controller. Redesigning the controller ASIC is a non-trivial task and can require a large amount of design resources and other inventory, which can increase the expense of the controller 102 and delay its delivery to market.
- the controller 102 in this embodiment comprises fixed hardware components 410 (e.g., components whose basic functionality is not configurable after manufacture) which can be implemented in an ASIC and dynamically-programmable hardware components 420 which can be implemented with registers that dynamically configure the functionality of the components.
- fixed hardware components 410 e.g., components whose basic functionality is not configurable after manufacture
- dynamically-programmable hardware components 420 which can be implemented with registers that dynamically configure the functionality of the components.
- a product team can provide a single controller design to be used with various host and memory products and provide updated configuration files to the controller 102 as needed. This will enable product teams to be able to configure the controller 102 for the end-product requirements and quickly ship the product to market with less expenditure than with conventional controller designs.
- the dynamically-programmable hardware components 420 can be used to implement any desired functionality of the controller 102 , such as, but not limited to, different host interfaces, different memory interfaces (e.g., FIM channels), different clock configurations, and different error corrections/detection mechanisms.
- different host interfaces e.g., SRAM
- different memory interfaces e.g., FIM channels
- different clock configurations e.g., a clock configurations
- error corrections/detection mechanisms e.g., error corrections/detection mechanisms.
- FIG. 5 is an illustration of one example implementation of a controller 102 of an embodiment.
- this controller 102 has fixed hardware components 410 and dynamically-programmable hardware components 420 .
- the fixed hardware components 410 comprise a multi-layer matrix (MLM) interconnect 500 that is in communication with a MLM interconnect bus interface 510 , RAM 520 , a flash memory interface 530 , one or more processors (here, central processing units (CPUs 1 and 2) 540 , a peripheral, debug, and trace interface 550 , a security and electrical fuse (Efuse) module 570 , and a set of (one or more) analog components 570 .
- MLM multi-layer matrix
- the MLM interconnect 500 functions as a system bus to connect the various components in the fixed hardware components 410 section of the controller 102 , as well as to a corresponding MLM interconnect 525 in the dynamically-programmable hardware components section 420 of the controller 102 .
- the MLM interconnect 500 can perform various functions, such as logical-to-physical address translation and arbitration of commands from the processor(s) 540 .
- the MLM interconnect bus interface 510 connects the MLM interconnect bus 500 to the host interface module 505 in the dynamically-programmable hardware components section 420 of the controller 102 .
- the RAM 520 can be used to store computer-readable program code read from the memory 104 and executed by the processor(s) 540 .
- the RAM 520 can also be used to store data sent by the host to be written in the memory 104 and/or data read from the memory 104 to be sent to the host.
- the flash memory interface 530 connects to the flash interface multiplexor and channel selector 515 in the dynamically-programmable hardware components section 420 of the controller 102 .
- the processor(s) 540 can execute computer-readable program code (e.g., read from the memory 104 and stored in the RAM 520 ).
- the peripheral, debug, and trace interface 550 is an interface that connects to peripheral, debug, and trace components.
- Peripherals can take any suitable form, such as, but not limited to, a universal asynchronous receiver/transmitter (UART), a general-purpose input/output component (GPIO), a timer, a watchdog component, and a Joint Test Action Group (JTAP) component.
- the peripherals can interrupt some or all of the processor(s) 545 , 555 in the controller 102 .
- the peripheral, debug, and trace interface 550 can also be used to debug firmware running on the processor(s) 540 , as well as the processor(s) 545 in the dynamically-programmable hardware components section 420 .
- the security and electrical fuse (Efuse) module 570 controls data safety. If a hack is detected, the fuse is blown, and the controller 102 is disabled.
- the analog components 570 can include, but are not limited to, a power supply controller, clock crystals, phase-locked loops (PLLs), and a switching architecture.
- the analog components 570 and the MLM interconnect 500 also communicate with an error detection/correction module (here, a low-density parity-check code (LDPC) module) 545 in the dynamically-programmable hardware components section 420 of the controller 102 .
- LDPC low-density parity-check code
- the fixed hardware components 410 are part of the controller's ASIC. Because these components form the common logic of the controller 102 , the fact that the functionality of these fixed components is not configurable is not an impediment to the flexibility of this controller 102 . It should be noted that while the processor(s) 540 are in the fixed hardware components section 410 of the controller 102 , the processor(s) 540 can be programmable with computer-readable program code.
- section 420 of the controller 102 that section 420 comprises the host interface module 505 , the flash interface multiplexor and channel selector 515 (which may be part of the overall memory interface module), the MLM interconnect 525 , a clock management module 535 , the LDPC core engine 545 , and one or more processors (here, CPUs) 555 . While FIG. 5 shows arrows illustrating communication between various components, it should be understood that additional communication channels can be present and are not shown in FIG. 5 to simplify the drawing.
- the host interface module 505 is configured to provide an interface (e.g., USB, SD, PCie, SAT A, etc.) to a host
- the MLM interconnect module 525 is configured to provide an interface between the host interface module 505 and the MLM interconnect bus interface 510 in the fixed hardware component section 410 of the controller 102 .
- the dock management module 535 is used to configure the analog components 570 for the required clock configurations of various modules.
- the LDPC engine 545 is used to provide error detection/correction functionality (e.g., encoding error bits for data to be stored in the memory 104 and decoding the error bits when the data is later read from the memory 104 to detect and possibly correct errors).
- the flash interface multiplexor and channel selector 515 is used to choose the number of flash interface channels to interface with the memory 104 , which can enhance the storage capacity of the storage system 100 .
- the flash interface multiplexor and channel selector 515 can also have high-end input-output modules to support the highest speed possible on the flash interface.
- Each of these components comprises a register that can be programmed with values by the processor(s) 540 in the fixed hardware component section 410 of the controller 102 to alter the functionality of those components.
- the fixed hardware component section 410 of the controller 102 is implemented in an ASIC with 28 nm/16 nm nodes, and the dynamically-programmable hardware components section 420 of the controller 102 has 5 nm nodes. This can allow the controller 102 to support various product requirements for several years.
- communication between the fixed hardware component section 410 of the controller 102 and the dynamically-programmable hardware components section 420 of the controller 102 happens over high-speed memory-mapped interfaces or streaming interfaces.
- the dynamically-programmable hardware components section 420 of the controller 102 also comprises one or more processors (here, CPUs) 555 , which can communication with the processor(s) 540 in the fixed hardware component section 410 of the controller 102 for load sharing (e.g., the processor(s) 555 can take care of any additional load that not taken care by the processor(s) 540 in the fixed hardware component section 410 of the controller 102 ).
- All the processors 540 , 555 can take any suitable form, such as, but not limited to, a reduced instruction set processor (RISC) or an Argonaut RISC (ARC) processor
- RISC reduced instruction set processor
- ARC Argonaut RISC
- various components in the dynamically-programmable hardware components section 420 of the controller 102 comprise registers that can be programmed with values by the processor(s) 540 in the fixed hardware component section 410 of the controller 102 to alter the functionality of those components and provide the flexibility noted above that conventional controllers do not have.
- the flow chart 600 in FIG. 6 and the following paragraphs provide an example of the dynamic reconfiguration capability of the controller 102 to implement different logic for different product requirements in the time-division domain. It should be noted that this is merely an example, and other implementations can be used.
- the processor(s) 540 in the fixed hardware component section 410 of the controller 102 initially load the RAM 520 with instruction code that the processor(s) 540 execute to boot up the controller 102 upon a power-on reset (POR) of the storage system 100 (act 610 ).
- the processor(s) 540 then program the flash interface multiplexor and channel selector 515 with a low-speed BM connection to the memory 104 (act 620 ).
- the processor(s) 540 read a configuration file from the memory 104 and store it in RAM 520 (act 630 ).
- the configuration file stores values that can be programmed into the registers in the components in the dynamically-programmable hardware components section 420 of the controller 102 .
- the processor(s) 540 program the registers in various ones of the components in the dynamically-programmable hardware components section 420 of the controller 102 (act 640 ). This enables the intended logic formed inside these programmable components.
- the processor(s) 540 can write values specified in the configuration file to program the flash interface multiplexor and channel selector 515 to configure the controller 102 as a PCIe NAND controller with four FLM channels.
- the processor(s) 540 can also write values specified in the configuration file to program the host interface 505 as a USB host interface and program the MLM interconnect 525 accordingly.
- the processor(s) 540 can write values specified in the configuration file to the LDPC engine 545 to configure that with certain error detection/correction functionality and to the clock management module 535 to configure that with the appropriate clock and timing values.
- the processor(s) 545 in the dynamically-programmable hardware components section 420 of the controller 102 configure the analog components 570 in the fixed hardware component section 410 of the controller 102 to provide the required clocks frequencies for the logic blocks in controller 102 (act 650 ).
- the processor(s) 545 handover control to the processor(s) 540 in the fixed hardware component section 410 of the controller 102 (act 660 ), and those processor(s) 540 then load firmware from the memory 104 and complete the boot-up process (act 670 ).
- the processor(s) 545 in the dynamically-programmable hardware components section 420 of the controller 102 can take on additional load from the processor(s) 540 in the fixed hardware component section 410 of the controller 102 , as needed (act 680 ). In this way, the processor(s) 545 can provide a load-sharing capability.
- these embodiments can allow a controller to be provided to market faster and less expensive, as the controller of this embodiment can be used with a wide variety of existing and future hosts and memories. Unlike a dedicated ASIC, the controller of these embodiments does not need to be redesigned for each host and memory product, as a single controller can be used with multiple products and port to new host and memory technologies. That is, the flexible solution of the dynamic reconfiguration of the programmable hardware components allows different logic to be implemented at different times.
- the controller of these embodiments can require less power consumption and less firmware overhead.
- the entire programmable hardware logic can be switched off, leaving only the ASIC part active, to save power and allow the controller to operate in a low-power and low-performance mode. If high performance is required, the programmable logic can be configured accordingly. Also, the programmable logic can be configured to provide stimulus to the ASIC part to debug the logic in the ASIC.
- the programmable nature of the controller makes it easy to fix bugs and to update the controller after product release.
- the controller can be updated with the latest LDPC after the release of product and whenever new memory technology is available.
- any suitable type of memory can be used.
- Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information.
- volatile memory devices such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices
- non-volatile memory devices such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information.
- ReRAM resistive random access memory
- the memory devices can be formed from passive and/or active elements, in any combinations.
- passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc.
- active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.
- Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible.
- flash memory devices in a NAND configuration typically contain memory elements connected in series.
- a NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group.
- memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array.
- NAND and NOR memory configurations are examples, and memory elements may be otherwise configured.
- the semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.
- the semiconductor memory elements are arranged in a single plane or a single memory device level.
- memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements.
- the substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed.
- the substrate may include a semiconductor such as silicon.
- the memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations.
- the memory elements may each have two or more electrodes or contact lines, such as bit lines and wordlines.
- a three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).
- a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels.
- a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column.
- the columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes.
- Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.
- the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device levels.
- the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels.
- Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels.
- Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
- a monolithic three dimensional memory array typically, one or more memory device levels are formed above a single substrate.
- the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate.
- the substrate may include a semiconductor such as silicon.
- the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array.
- layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.
- non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.
- Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements.
- memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading.
- This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate.
- a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Quality & Reliability (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
- A memory controller in a storage system can be implemented as an application-specific integrated circuit (ASIC) and often has a memory interface for communicating with a memory of the storage system and a host interface for communicating with a host (e.g., for receiving read/write commands from the host and for receiving data from and sending data to the host). The memory interface and the host interface can be designed to work with a specific protocol or standard.
-
FIG. 1A is a block diagram of a non-volatile storage system of an embodiment. -
FIG. 1B is a block diagram illustrating a storage module of an embodiment. -
FIG. 1C is a block diagram illustrating a hierarchical storage system of an embodiment. -
FIG. 2 is a block diagram illustrating components of the controller of the non-volatile storage system illustrated inFIG. 1A according to an embodiment. -
FIG. 3 is a block diagram illustrating components of the non-volatile storage system illustrated inFIG. 1A according to an embodiment. -
FIG. 4 is a block diagram of a controller of an embodiment. -
FIG. 5 is a block diagram of a controller of an embodiment with fixed and configurable hardware components. -
FIG. 6 is a flow chart of a method for using a controller of an embodiment. - By way of introduction, the below embodiments relate to a dynamic memory controller and method for use therewith. In one embodiment, a memory controller is provided comprising fixed components (e.g., in an application-specific integrated circuit (ASIC)) and dynamically-programmable components (e.g., outside of the ASIC). The dynamically-programmable components can be used to configure the memory controller to be used with any number of selected host and/or memory types, as well as to enable the memory controller with different error detection/correction functionality. The dynamically-programmable components can be used to provide the memory controller with other types of functionality. Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the attached drawings.
- Turning now to the drawings, storage systems suitable for use in implementing aspects of these embodiments are shown in
FIGS. 1A-1C .FIG. 1A is a block diagram illustrating a non-volatile storage system 100 (sometimes referred to herein as a storage device or just device) according to an embodiment of the subject matter described herein. Referring toFIG. 1A ,non-volatile storage system 100 includes acontroller 102 and non-volatile memory that may be made up of one or more non-volatile memory die 104. As used herein, the term die refers to the collection of non-volatile memory cells, and associated circuitry for managing the physical operation of those non-volatile memory cells, that are formed on a single semiconductor substrate.Controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to non-volatile memory die 104. - The controller 102 (which may be a non-volatile memory controller (e.g., a flash, resistive random-access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random-access memory (MRAM) controller)) can take the form of processing circuitry, a microprocessor or processor, and a computer-readable medium that stores computer-readable program code (e.g., firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example. The
controller 102 can be configured with hardware and/or firmware to perform the various functions described below and shown in the flow diagrams. Also, some of the components shown as being internal to the controller can also be stored external to the controller, and other components can be used. Additionally, the phrase “operatively in communication with” could mean directly in communication with or indirectly (wired or wireless) in communication with through one or more components, which may or may not be shown or described herein. - As used herein, a non-volatile memory controller is a device that manages data stored on non-volatile memory and communicates with a host, such as a computer or electronic device. A non-volatile memory controller can have various functionality in addition to the specific functionality described herein. For example, the non-volatile memory controller can format the non-volatile memory to ensure the memory is operating properly, map out bad non-volatile memory cells, and allocate spare cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the non-volatile memory controller and implement other features. In operation, when a host needs to read data from or write data to the non-volatile memory, it can communicate with the non-volatile memory controller. If the host provides a logical address to which data is to be read/written, the non-volatile memory controller can convert the logical address received from the host to a physical address in the non-volatile memory. (Alternatively, the host can provide the physical address.) The non-volatile memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so the full block can be erased and reused). Also, the structure for the “means” recited in the claims can include, for example, some or all of the structures of the controller described herein, programmed or manufactured as appropriate to cause the controller to operate to perform the recited functions.
- Non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random-access memory (ReRAM), magnetoresistive random-access memory (MRAM), phase-change memory (PCM), NAND flash memory cells and/or NOR flash memory cells. The memory cells can take the form of solid-state (e.g., flash) memory cells and can be one-time programmable, few-time programmable, or many-time programmable. The memory cells can also be single-level cells (SLC), multiple-level cells (MLC), triple-level cells (TLC), or use other memory cell level technologies, now known or later developed. Also, the memory cells can be fabricated in a two-dimensional or three-dimensional fashion.
- The interface between
controller 102 and non-volatile memory die 104 may be any suitable flash interface, such as ToggleMode 200, 400, or 800. In one embodiment,storage system 100 may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment,storage system 100 may be part of an embedded storage system. - Although, in the example illustrated in
FIG. 1A , non-volatile storage system 100 (sometimes referred to herein as a storage module) includes a single channel betweencontroller 102 and non-volatile memory die 104, the subject matter described herein is not limited to having a single memory channel. For example, in some storage system architectures (such as the ones shown inFIGS. 1B and 1C ), 2, 4, 8 or more memory channels may exist between the controller and the memory device, depending on controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the controller and the memory die, even if a single channel is shown in the drawings. -
FIG. 1B illustrates astorage module 200 that includes pluralnon-volatile storage systems 100. As such,storage module 200 may include astorage controller 202 that interfaces with a host and withstorage system 204, which includes a plurality ofnon-volatile storage systems 100. The interface betweenstorage controller 202 andnon-volatile storage systems 100 may be a bus interface, such as a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe) interface, or double-data-rate (DDR) interface.Storage module 200, in one embodiment, may be a solid state drive (SSD), or non-volatile dual in-line memory module (NVDIMM), such as found in server PC or portable computing devices, such as laptop computers, and tablet computers. -
FIG. 1C is a block diagram illustrating a hierarchical storage system. Ahierarchical storage system 250 includes a plurality ofstorage controllers 202, each of which controls arespective storage system 204.Host systems 252 may access memories within the storage system via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) or fiber channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated inFIG. 1C may be a rack mountable mass storage system that is accessible by multiple host computers, such as would be found in a data center or other location where mass storage is needed. -
FIG. 2 is a block diagram illustrating components ofcontroller 102 in more detail.Controller 102 includes afront end module 108 that interfaces with a host, aback end module 110 that interfaces with the one or more non-volatile memory die 104, and various other modules that perform functions which will now be described in detail. A module may take the form of a packaged functional hardware unit designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry that usually performs a particular function of related functions, or a self-contained hardware or software component that interfaces with a larger system, for example. Thecontroller 102 may sometimes be referred to herein as a NAND controller or a flash controller, but it should be understood that thecontroller 102 can be used with any suitable memory technology, example of some of which are provided below. - Referring again to modules of the
controller 102, a buffer manager/bus controller 114 manages buffers in random access memory (RAM) 116 and controls the internal bus arbitration ofcontroller 102. A read only memory (ROM) 118 stores system boot code. Although illustrated inFIG. 2 as located separately from thecontroller 102, in other embodiments one or both of theRAM 116 andROM 118 may be located within the controller. In yet other embodiments, portions of RAM and ROM may be located both within thecontroller 102 and outside the controller. -
Front end module 108 includes ahost interface 120 and a physical layer interface (PHY) 122 that provide the electrical interface with the host or next level storage controller. The choice of the type ofhost interface 120 can depend on the type of memory being used. Examples ofhost interfaces 120 include, but are not limited to, SATA, SATA Express, serially attached small computer system interface (SAS), Fibre Channel, universal serial bus (USB), PCIe, and NVMe. Thehost interface 120 typically facilitates transfer for data, control signals, and timing signals. -
Back end module 110 includes an error correction code (ECC)engine 124 that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the non-volatile memory. Acommand sequencer 126 generates command sequences, such as program and erase command sequences, to be transmitted to non-volatile memory die 104. A RAID (Redundant Array of Independent Drives)module 128 manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into thememory device 104. In some cases, theRAID module 128 may be a part of theECC engine 124. Amemory interface 130 provides the command sequences to non-volatile memory die 104 and receives status information from non-volatile memory die 104. In one embodiment,memory interface 130 may be a double data rate (DDR) interface, such as aToggle Mode 200, 400, or 800 interface. Aflash control layer 132 controls the overall operation ofback end module 110. - The
storage system 100 also includes otherdiscrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface withcontroller 102. In alternative embodiments, one or more of thephysical layer interface 122,RAID module 128,media management layer 138 and buffer management/bus controller 114 are optional components that are not necessary in thecontroller 102. -
FIG. 3 is a block diagram illustrating components of non-volatile memory die 104 in more detail. Non-volatile memory die 104 includesperipheral circuitry 141 andnon-volatile memory array 142.Non-volatile memory array 142 includes the non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells and/or NOR flash memory cells in a two dimensional and/or three dimensional configuration. Non-volatile memory die 104 further includes adata cache 156 that caches data.Peripheral circuitry 141 includes astate machine 152 that provides status information to thecontroller 102. - Returning again to
FIG. 2 , the flash control layer 132 (which will be referred to herein as the flash translation layer (FTL) or, more generally, the “media management layer,” as the memory may not be flash) handles flash errors and interfaces with the host. In particular, the FTL, which may be an algorithm in firmware, is responsible for the internals of memory management and translates writes from the host into writes to thememory 104. The FTL may be needed because thememory 104 may have limited endurance, may only be written in multiples of pages, and/or may not be written unless it is erased as a block. The FTL understands these potential limitations of thememory 104, which may not be visible to the host. Accordingly, the FTL attempts to translate the writes from host into writes into thememory 104. - The FTL may include a logical-to-physical address (L2P) map (sometimes referred to herein as a table or data structure) and allotted cache memory. In this way, the FTL translates logical block addresses (“LBAs”) from the host to physical addresses in the
memory 104. The FTL can include other features, such as, but not limited to, power-off recovery (so that the data structures of the FTL can be recovered in the event of a sudden power loss) and wear leveling (so that the wear across memory blocks is even to prevent certain blocks from excessive wear, which would result in a greater chance of failure). - If the
controller 102 is implemented as an application-specific integrated circuit (ASIC), all of its components are static. For example, because the memory interface 130 (sometimes referred to herein as the flash interface module (FIM) when thememory 104 is NAND flash memory) can only support a fixed number FIM channels, thecontroller 102 can only work with memory having that number of channels. If more channels are desired to increase the capacity of thememory 104 or the performance of thestorage system 100, the controller ASIC would need to be redesigned to support the increased number of channels. A similar problem can occur with thehost interface 120. Because the host interface 120 (sometimes referred to herein as the host interface module (HIM)) is also static, the controller ASIC would need to be redesigned if thecontroller 102 is to be used with a host having a different interface (e.g., UFS, USB, PCIe, SD, SATA, or NVMe). So, a number of controller ASICs may need to be designed for each product or product line, as a single controller ASIC will not work for all the products and their different interfaces. Further, a new controller ASIC would be needed if a new memory technology is developed that is not supported by the controller. Redesigning the controller ASIC is a non-trivial task and can require a large amount of design resources and other inventory, which can increase the expense of thecontroller 102 and delay its delivery to market. - To address this issue, one embodiment provides a
single controller 102 that can shared across products and be flexible enough to adapt to new memory technologies. As shown inFIG. 4 , thecontroller 102 in this embodiment comprises fixed hardware components 410 (e.g., components whose basic functionality is not configurable after manufacture) which can be implemented in an ASIC and dynamically-programmable hardware components 420 which can be implemented with registers that dynamically configure the functionality of the components. Because thiscontroller 102 is dynamic in nature, a product team can provide a single controller design to be used with various host and memory products and provide updated configuration files to thecontroller 102 as needed. This will enable product teams to be able to configure thecontroller 102 for the end-product requirements and quickly ship the product to market with less expenditure than with conventional controller designs. - The dynamically-
programmable hardware components 420 can be used to implement any desired functionality of thecontroller 102, such as, but not limited to, different host interfaces, different memory interfaces (e.g., FIM channels), different clock configurations, and different error corrections/detection mechanisms. The following paragraphs provide an example of one implementation. It should be understood that this is merely an example, and other implementations are possible. - Returning to the drawings,
FIG. 5 is an illustration of one example implementation of acontroller 102 of an embodiment. As shown inFIG. 5 , thiscontroller 102 has fixedhardware components 410 and dynamically-programmable hardware components 420. In this example, the fixedhardware components 410 comprise a multi-layer matrix (MLM)interconnect 500 that is in communication with a MLMinterconnect bus interface 510,RAM 520, aflash memory interface 530, one or more processors (here, central processing units (CPUs 1 and 2) 540, a peripheral, debug, andtrace interface 550, a security and electrical fuse (Efuse)module 570, and a set of (one or more)analog components 570. - The
MLM interconnect 500 functions as a system bus to connect the various components in the fixedhardware components 410 section of thecontroller 102, as well as to acorresponding MLM interconnect 525 in the dynamically-programmablehardware components section 420 of thecontroller 102. TheMLM interconnect 500 can perform various functions, such as logical-to-physical address translation and arbitration of commands from the processor(s) 540. The MLMinterconnect bus interface 510 connects theMLM interconnect bus 500 to thehost interface module 505 in the dynamically-programmablehardware components section 420 of thecontroller 102. - The
RAM 520 can be used to store computer-readable program code read from thememory 104 and executed by the processor(s) 540. TheRAM 520 can also be used to store data sent by the host to be written in thememory 104 and/or data read from thememory 104 to be sent to the host. Theflash memory interface 530 connects to the flash interface multiplexor andchannel selector 515 in the dynamically-programmablehardware components section 420 of thecontroller 102. The processor(s) 540 can execute computer-readable program code (e.g., read from thememory 104 and stored in the RAM 520). - The peripheral, debug, and
trace interface 550 is an interface that connects to peripheral, debug, and trace components. Peripherals can take any suitable form, such as, but not limited to, a universal asynchronous receiver/transmitter (UART), a general-purpose input/output component (GPIO), a timer, a watchdog component, and a Joint Test Action Group (JTAP) component. In one embodiment, the peripherals can interrupt some or all of the processor(s) 545, 555 in thecontroller 102. The peripheral, debug, andtrace interface 550 can also be used to debug firmware running on the processor(s) 540, as well as the processor(s) 545 in the dynamically-programmablehardware components section 420. The security and electrical fuse (Efuse)module 570 controls data safety. If a hack is detected, the fuse is blown, and thecontroller 102 is disabled. Theanalog components 570 can include, but are not limited to, a power supply controller, clock crystals, phase-locked loops (PLLs), and a switching architecture. Theanalog components 570 and theMLM interconnect 500 also communicate with an error detection/correction module (here, a low-density parity-check code (LDPC) module) 545 in the dynamically-programmablehardware components section 420 of thecontroller 102. - In one embodiment, the fixed
hardware components 410 are part of the controller's ASIC. Because these components form the common logic of thecontroller 102, the fact that the functionality of these fixed components is not configurable is not an impediment to the flexibility of thiscontroller 102. It should be noted that while the processor(s) 540 are in the fixedhardware components section 410 of thecontroller 102, the processor(s) 540 can be programmable with computer-readable program code. - Turning now to the dynamically-programmable
hardware components section 420 of thecontroller 102, thatsection 420 comprises thehost interface module 505, the flash interface multiplexor and channel selector 515 (which may be part of the overall memory interface module), theMLM interconnect 525, aclock management module 535, theLDPC core engine 545, and one or more processors (here, CPUs) 555. WhileFIG. 5 shows arrows illustrating communication between various components, it should be understood that additional communication channels can be present and are not shown inFIG. 5 to simplify the drawing. - The
host interface module 505 is configured to provide an interface (e.g., USB, SD, PCie, SAT A, etc.) to a host, and theMLM interconnect module 525 is configured to provide an interface between thehost interface module 505 and the MLMinterconnect bus interface 510 in the fixedhardware component section 410 of thecontroller 102. Thedock management module 535 is used to configure theanalog components 570 for the required clock configurations of various modules. TheLDPC engine 545 is used to provide error detection/correction functionality (e.g., encoding error bits for data to be stored in thememory 104 and decoding the error bits when the data is later read from thememory 104 to detect and possibly correct errors). The flash interface multiplexor andchannel selector 515 is used to choose the number of flash interface channels to interface with thememory 104, which can enhance the storage capacity of thestorage system 100. The flash interface multiplexor andchannel selector 515 can also have high-end input-output modules to support the highest speed possible on the flash interface. - Each of these components comprises a register that can be programmed with values by the processor(s) 540 in the fixed
hardware component section 410 of thecontroller 102 to alter the functionality of those components. In one embodiment the fixedhardware component section 410 of thecontroller 102 is implemented in an ASIC with 28 nm/16 nm nodes, and the dynamically-programmablehardware components section 420 of thecontroller 102 has 5 nm nodes. This can allow thecontroller 102 to support various product requirements for several years. In one embodiment, communication between the fixedhardware component section 410 of thecontroller 102 and the dynamically-programmablehardware components section 420 of thecontroller 102 happens over high-speed memory-mapped interfaces or streaming interfaces. - As mentioned above, the dynamically-programmable
hardware components section 420 of thecontroller 102 also comprises one or more processors (here, CPUs) 555, which can communication with the processor(s) 540 in the fixedhardware component section 410 of thecontroller 102 for load sharing (e.g., the processor(s) 555 can take care of any additional load that not taken care by the processor(s) 540 in the fixedhardware component section 410 of the controller 102). All theprocessors - As noted above, various components in the dynamically-programmable
hardware components section 420 of thecontroller 102 comprise registers that can be programmed with values by the processor(s) 540 in the fixedhardware component section 410 of thecontroller 102 to alter the functionality of those components and provide the flexibility noted above that conventional controllers do not have. Theflow chart 600 inFIG. 6 and the following paragraphs provide an example of the dynamic reconfiguration capability of thecontroller 102 to implement different logic for different product requirements in the time-division domain. It should be noted that this is merely an example, and other implementations can be used. - As shown in
FIG. 6 , the processor(s) 540 in the fixedhardware component section 410 of thecontroller 102 initially load theRAM 520 with instruction code that the processor(s) 540 execute to boot up thecontroller 102 upon a power-on reset (POR) of the storage system 100 (act 610). The processor(s) 540 then program the flash interface multiplexor andchannel selector 515 with a low-speed BM connection to the memory 104 (act 620). Next, using this established connection, the processor(s) 540 read a configuration file from thememory 104 and store it in RAM 520 (act 630). The configuration file stores values that can be programmed into the registers in the components in the dynamically-programmablehardware components section 420 of thecontroller 102. - With the configuration file, the processor(s) 540 program the registers in various ones of the components in the dynamically-programmable
hardware components section 420 of the controller 102 (act 640). This enables the intended logic formed inside these programmable components. For example, the processor(s) 540 can write values specified in the configuration file to program the flash interface multiplexor andchannel selector 515 to configure thecontroller 102 as a PCIe NAND controller with four FLM channels. The processor(s) 540 can also write values specified in the configuration file to program thehost interface 505 as a USB host interface and program theMLM interconnect 525 accordingly. Further, the processor(s) 540 can write values specified in the configuration file to theLDPC engine 545 to configure that with certain error detection/correction functionality and to theclock management module 535 to configure that with the appropriate clock and timing values. - After the
clock management module 535 is programmed with the appropriate values, the processor(s) 545 in the dynamically-programmablehardware components section 420 of thecontroller 102 configure theanalog components 570 in the fixedhardware component section 410 of thecontroller 102 to provide the required clocks frequencies for the logic blocks in controller 102 (act 650). Next, the processor(s) 545 handover control to the processor(s) 540 in the fixedhardware component section 410 of the controller 102 (act 660), and those processor(s) 540 then load firmware from thememory 104 and complete the boot-up process (act 670). - Finally, the processor(s) 545 in the dynamically-programmable
hardware components section 420 of thecontroller 102 can take on additional load from the processor(s) 540 in the fixedhardware component section 410 of thecontroller 102, as needed (act 680). In this way, the processor(s) 545 can provide a load-sharing capability. - There are several advantages associated with the embodiments. For example, these embodiments can allow a controller to be provided to market faster and less expensive, as the controller of this embodiment can be used with a wide variety of existing and future hosts and memories. Unlike a dedicated ASIC, the controller of these embodiments does not need to be redesigned for each host and memory product, as a single controller can be used with multiple products and port to new host and memory technologies. That is, the flexible solution of the dynamic reconfiguration of the programmable hardware components allows different logic to be implemented at different times.
- Also as compared to a conventional ASIC-based controller, the controller of these embodiments can require less power consumption and less firmware overhead. In an instant, the entire programmable hardware logic can be switched off, leaving only the ASIC part active, to save power and allow the controller to operate in a low-power and low-performance mode. If high performance is required, the programmable logic can be configured accordingly. Also, the programmable logic can be configured to provide stimulus to the ASIC part to debug the logic in the ASIC.
- Further, the programmable nature of the controller makes it easy to fix bugs and to update the controller after product release. For example, the controller can be updated with the latest LDPC after the release of product and whenever new memory technology is available.
- Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.
- The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.
- Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be otherwise configured.
- The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.
- In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.
- The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and wordlines.
- A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).
- As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.
- By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device levels. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
- Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.
- Then again, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.
- Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.
- One of skill in the art will recognize that this invention is not limited to the two dimensional and three dimensional structures described but cover all relevant memory structures within the spirit and scope of the invention as described herein and as understood by one of skill in the art.
- It is intended that the foregoing detailed description be understood as an illustration of selected forms that the invention can take and not as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of any of the embodiments described herein can be used alone or in combination with one another.
Claims (20)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/853,233 US11150842B1 (en) | 2020-04-20 | 2020-04-20 | Dynamic memory controller and method for use therewith |
DE102021107443.6A DE102021107443A1 (en) | 2020-04-20 | 2021-03-24 | DYNAMIC MEMORY CONTROL AND METHOD OF USING IT |
CN202110376144.7A CN113535612A (en) | 2020-04-20 | 2021-04-08 | Dynamic memory controller and method of use |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/853,233 US11150842B1 (en) | 2020-04-20 | 2020-04-20 | Dynamic memory controller and method for use therewith |
Publications (2)
Publication Number | Publication Date |
---|---|
US11150842B1 US11150842B1 (en) | 2021-10-19 |
US20210326066A1 true US20210326066A1 (en) | 2021-10-21 |
Family
ID=77920102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/853,233 Active 2040-06-10 US11150842B1 (en) | 2020-04-20 | 2020-04-20 | Dynamic memory controller and method for use therewith |
Country Status (3)
Country | Link |
---|---|
US (1) | US11150842B1 (en) |
CN (1) | CN113535612A (en) |
DE (1) | DE102021107443A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220292227A1 (en) * | 2021-03-15 | 2022-09-15 | Kabushiki Kaisha Toshiba | Storage device |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2023037877A (en) * | 2021-09-06 | 2023-03-16 | キオクシア株式会社 | memory system |
CN117724664A (en) * | 2024-02-18 | 2024-03-19 | 芯来智融半导体科技(上海)有限公司 | Data writing method, device, equipment and storage medium |
Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030110340A1 (en) * | 2001-12-10 | 2003-06-12 | Jim Butler | Tracking deferred data transfers on a system-interconnect bus |
US20040083308A1 (en) * | 2002-10-24 | 2004-04-29 | Sebastian Bino J. | Network configuration synchronization for hardware accelerated network protocol |
US20040083285A1 (en) * | 2002-10-25 | 2004-04-29 | Alex Nicolson | Abstracted node discovery |
US20110040924A1 (en) * | 2009-08-11 | 2011-02-17 | Selinger Robert D | Controller and Method for Detecting a Transmission Error Over a NAND Interface Using Error Detection Code |
US20120128107A1 (en) * | 2010-11-23 | 2012-05-24 | Siano Mobile Silicon Ltd. | Receiver with configurable clock frequencies |
US20120260007A1 (en) * | 2011-04-11 | 2012-10-11 | Jibbe Mahmoud K | Varying host interface signaling speeds in a storage array |
US20150154108A1 (en) * | 2013-12-02 | 2015-06-04 | SanDisk Technologies, Inc. | Multi-die write management |
US20160274803A1 (en) * | 2015-03-20 | 2016-09-22 | Burlywood, LLC | Storage emulation in a storage controller |
US20160328347A1 (en) * | 2015-05-08 | 2016-11-10 | Samsung Electronics Co., Ltd. | Multi-protocol io infrastructure for a flexible storage platform |
US20170123707A1 (en) * | 2015-10-29 | 2017-05-04 | Micron Technology, Inc. | Memory cells configured in multiple configuration modes |
US20180004688A1 (en) * | 2016-07-01 | 2018-01-04 | Intel Corporation | Load reduced nonvolatile memory interface |
US20190138440A1 (en) * | 2017-11-07 | 2019-05-09 | SK Hynix Inc. | Memory system and operating method thereof |
US20190146695A1 (en) * | 2017-11-10 | 2019-05-16 | Samsung Electronics Co., Ltd. | Memory device and method of controlling power of the same |
US20190303147A1 (en) * | 2018-03-31 | 2019-10-03 | Micron Technology, Inc. | Execution Control of a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric |
US20210157526A1 (en) * | 2019-11-21 | 2021-05-27 | SK Hynix Inc. | Memory device and method of operating the same |
US20210157525A1 (en) * | 2019-11-21 | 2021-05-27 | SK Hynix Inc. | Memory controller and operating method thereof |
US20210173785A1 (en) * | 2019-12-04 | 2021-06-10 | SK Hynix Inc. | Storage device and method of operating the same |
US20210216469A1 (en) * | 2020-01-10 | 2021-07-15 | SK Hynix Inc. | Memory controller and method of operating the same |
US20210243080A1 (en) * | 2018-03-31 | 2021-08-05 | Micron Technology, Inc. | Efficient Loop Execution for a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8060670B2 (en) | 2004-03-17 | 2011-11-15 | Super Talent Electronics, Inc. | Method and systems for storing and accessing data in USB attached-SCSI (UAS) and bulk-only-transfer (BOT) based flash-memory device |
US8151037B1 (en) | 2008-05-28 | 2012-04-03 | Marvell International Ltd. | Interface for solid-state memory |
TW201005654A (en) | 2008-07-24 | 2010-02-01 | Jmicron Technology Corp | Host controller disposed in multi-function card reader |
US8225019B2 (en) | 2008-09-22 | 2012-07-17 | Micron Technology, Inc. | SATA mass storage device emulation on a PCIe interface |
US8656256B2 (en) * | 2010-07-07 | 2014-02-18 | Stec, Inc. | Apparatus and method for multi-mode operation of a flash memory device |
US8589723B2 (en) | 2010-12-22 | 2013-11-19 | Intel Corporation | Method and apparatus to provide a high availability solid state drive |
US8874820B2 (en) | 2010-12-28 | 2014-10-28 | Silicon Image, Inc. | Mechanism for facilitating a configurable port-type peripheral component interconnect express/serial advanced technology attachment host controller architecture |
KR20130049332A (en) * | 2011-11-04 | 2013-05-14 | 삼성전자주식회사 | Memory system and operating method thereof |
CN203224819U (en) | 2013-04-08 | 2013-10-02 | 深圳市祈飞科技有限公司 | Mainboard |
JP2014241057A (en) * | 2013-06-12 | 2014-12-25 | ソニー株式会社 | Interface control circuit, memory system, and method of controlling interface control circuit |
US20160259754A1 (en) | 2015-03-02 | 2016-09-08 | Samsung Electronics Co., Ltd. | Hard disk drive form factor solid state drive multi-card adapter |
TWI602127B (en) | 2016-10-21 | 2017-10-11 | 宇瞻科技股份有限公司 | Electronic card and detecting method thereof |
CN206557760U (en) | 2017-02-28 | 2017-10-13 | 郑州云海信息技术有限公司 | A kind of hard disk of compatible with PCI E interface and SATA interface |
CN107092570A (en) | 2017-05-27 | 2017-08-25 | 郑州云海信息技术有限公司 | The adaptive configuring method and system of a kind of onboard M.2 hard disk of server |
CN107291649A (en) | 2017-06-20 | 2017-10-24 | 郑州云海信息技术有限公司 | The design method and device of a kind of flexible support PCIE and SATA agreements M.2 self-identifying |
-
2020
- 2020-04-20 US US16/853,233 patent/US11150842B1/en active Active
-
2021
- 2021-03-24 DE DE102021107443.6A patent/DE102021107443A1/en not_active Withdrawn
- 2021-04-08 CN CN202110376144.7A patent/CN113535612A/en active Pending
Patent Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030110340A1 (en) * | 2001-12-10 | 2003-06-12 | Jim Butler | Tracking deferred data transfers on a system-interconnect bus |
US20040083308A1 (en) * | 2002-10-24 | 2004-04-29 | Sebastian Bino J. | Network configuration synchronization for hardware accelerated network protocol |
US20040083285A1 (en) * | 2002-10-25 | 2004-04-29 | Alex Nicolson | Abstracted node discovery |
US20110040924A1 (en) * | 2009-08-11 | 2011-02-17 | Selinger Robert D | Controller and Method for Detecting a Transmission Error Over a NAND Interface Using Error Detection Code |
US20120128107A1 (en) * | 2010-11-23 | 2012-05-24 | Siano Mobile Silicon Ltd. | Receiver with configurable clock frequencies |
US20120260007A1 (en) * | 2011-04-11 | 2012-10-11 | Jibbe Mahmoud K | Varying host interface signaling speeds in a storage array |
US20150154108A1 (en) * | 2013-12-02 | 2015-06-04 | SanDisk Technologies, Inc. | Multi-die write management |
US20160274803A1 (en) * | 2015-03-20 | 2016-09-22 | Burlywood, LLC | Storage emulation in a storage controller |
US20160328347A1 (en) * | 2015-05-08 | 2016-11-10 | Samsung Electronics Co., Ltd. | Multi-protocol io infrastructure for a flexible storage platform |
US10452596B2 (en) * | 2015-10-29 | 2019-10-22 | Micron Technology, Inc. | Memory cells configured in multiple configuration modes |
US20170123707A1 (en) * | 2015-10-29 | 2017-05-04 | Micron Technology, Inc. | Memory cells configured in multiple configuration modes |
US20180004688A1 (en) * | 2016-07-01 | 2018-01-04 | Intel Corporation | Load reduced nonvolatile memory interface |
US20190138440A1 (en) * | 2017-11-07 | 2019-05-09 | SK Hynix Inc. | Memory system and operating method thereof |
US20190146695A1 (en) * | 2017-11-10 | 2019-05-16 | Samsung Electronics Co., Ltd. | Memory device and method of controlling power of the same |
US20190303147A1 (en) * | 2018-03-31 | 2019-10-03 | Micron Technology, Inc. | Execution Control of a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric |
US20210243080A1 (en) * | 2018-03-31 | 2021-08-05 | Micron Technology, Inc. | Efficient Loop Execution for a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric |
US20210157526A1 (en) * | 2019-11-21 | 2021-05-27 | SK Hynix Inc. | Memory device and method of operating the same |
US20210157525A1 (en) * | 2019-11-21 | 2021-05-27 | SK Hynix Inc. | Memory controller and operating method thereof |
US20210173785A1 (en) * | 2019-12-04 | 2021-06-10 | SK Hynix Inc. | Storage device and method of operating the same |
US20210216469A1 (en) * | 2020-01-10 | 2021-07-15 | SK Hynix Inc. | Memory controller and method of operating the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220292227A1 (en) * | 2021-03-15 | 2022-09-15 | Kabushiki Kaisha Toshiba | Storage device |
Also Published As
Publication number | Publication date |
---|---|
DE102021107443A1 (en) | 2021-10-21 |
CN113535612A (en) | 2021-10-22 |
US11150842B1 (en) | 2021-10-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20170249155A1 (en) | Memory System and Method for Fast Firmware Download | |
US11150842B1 (en) | Dynamic memory controller and method for use therewith | |
US9582435B2 (en) | Memory system and method for efficient padding of memory pages | |
WO2021247093A1 (en) | Storage system and method for retention-based zone determination | |
US11036407B1 (en) | Storage system and method for smart folding | |
US11567777B2 (en) | Storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array | |
US11086786B2 (en) | Storage system and method for caching a single mapping entry for a random read command | |
US10474391B2 (en) | Storage system and method for executing file-based firmware commands and collecting response data | |
US11698751B2 (en) | Data storage device and method for low-latency power state transitions by having power islanding in a host memory buffer | |
US11138065B1 (en) | Storage system and method for fast low-density parity check (LDPC) encoding | |
US11281399B2 (en) | Dual-interface storage system and method for use therewith | |
US20220197557A1 (en) | Storage System and Method for Dual Fast Release and Slow Release Responses | |
US20210397348A1 (en) | Storage System and Method for Using Host-Assisted Variable Zone Speed Grade Modes to Minimize Overprovisioning | |
US20210382780A1 (en) | Storage System and Method for Crash Analysis | |
US11030106B2 (en) | Storage system and method for enabling host-driven regional performance in memory | |
US9558009B1 (en) | Expedited find sector to decrease boot time | |
US11921653B2 (en) | Data storage device and method for lane detection and configuration | |
US20230385068A1 (en) | Data Storage Device and Method for Storage-Class-Memory-Accelerated Boot Partition Optimization | |
US11237838B2 (en) | Storage system and method for enabling a direct accessible boot block in a memory die | |
US11537325B2 (en) | Storage system and method for token provisioning for faster data access | |
US11899598B2 (en) | Data storage device and method for lane selection based on thermal conditions | |
US11797445B2 (en) | Data storage device and method for preventing data loss during an ungraceful shutdown | |
US11442665B2 (en) | Storage system and method for dynamic selection of a host interface | |
US20230409234A1 (en) | Data Storage Device and Method for Host Multi-Command Queue Grouping Based on Write-Size Alignment in a Multi-Queue-Depth Environment | |
US20230384971A1 (en) | Data Storage Device and Method for Device-Initiated Hibernation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: WESTERN DIGITAL TECHNOLOGIES, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BOMMANA, SESIBHUSHANA RAO;PANDA, MUKESH;SIGNING DATES FROM 20200420 TO 20200428;REEL/FRAME:052510/0692 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS AGENT, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNOR:WESTERN DIGITAL TECHNOLOGIES, INC.;REEL/FRAME:053482/0453 Effective date: 20200511 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: WESTERN DIGITAL TECHNOLOGIES, INC., CALIFORNIA Free format text: RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453;ASSIGNOR:JPMORGAN CHASE BANK, N.A.;REEL/FRAME:058966/0279 Effective date: 20220203 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., ILLINOIS Free format text: PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT;ASSIGNOR:WESTERN DIGITAL TECHNOLOGIES, INC.;REEL/FRAME:064715/0001 Effective date: 20230818 Owner name: JPMORGAN CHASE BANK, N.A., ILLINOIS Free format text: PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT;ASSIGNOR:WESTERN DIGITAL TECHNOLOGIES, INC.;REEL/FRAME:067045/0156 Effective date: 20230818 |
|
AS | Assignment |
Owner name: SANDISK TECHNOLOGIES, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WESTERN DIGITAL TECHNOLOGIES, INC.;REEL/FRAME:067567/0682 Effective date: 20240503 |