US20210202761A1 - Trench capacitor profile to decrease substrate warpage - Google Patents

Trench capacitor profile to decrease substrate warpage Download PDF

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Publication number
US20210202761A1
US20210202761A1 US16/728,452 US201916728452A US2021202761A1 US 20210202761 A1 US20210202761 A1 US 20210202761A1 US 201916728452 A US201916728452 A US 201916728452A US 2021202761 A1 US2021202761 A1 US 2021202761A1
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United States
Prior art keywords
trench
substrate
width
pillar structure
capacitor
Prior art date
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Granted
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US16/728,452
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US11063157B1 (en
Inventor
Hsin-Li Cheng
Jyun-Ying LIN
Alexander Kalnitsky
Shih-Fen Huang
Shu-Hui SU
Ting-Chen Hsu
Tuo-Hsin Chien
Felix Ying-Kit Tsui
Shi-Min Wu
Yu-Chi Chang
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US16/728,452 priority Critical patent/US11063157B1/en
Priority to DE102020101253.5A priority patent/DE102020101253B4/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, SHIH-FEN, KALNITSKY, ALEXANDER, CHANG, YU-CHI, CHENG, HSIN-LI, CHIEN, TUO-HSIN, HSU, TING-CHEN, LIN, JYUN-YING, SU, Shu-hui, TSUI, FELIX YING-KIT, WU, SHI-MIN
Priority to KR1020200037838A priority patent/KR102302524B1/en
Priority to TW109145598A priority patent/TWI751851B/en
Priority to CN202011563976.1A priority patent/CN113053877A/en
Publication of US20210202761A1 publication Critical patent/US20210202761A1/en
Priority to US17/370,067 priority patent/US11769792B2/en
Publication of US11063157B1 publication Critical patent/US11063157B1/en
Application granted granted Critical
Priority to US18/362,146 priority patent/US20230378251A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/88—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors

Definitions

  • FIG. 1 illustrates a cross-sectional view of some embodiments of an integrated circuit (IC) including a trench capacitor disposed within a trench and laterally adjacent to a cavity within the trench.
  • IC integrated circuit
  • FIGS. 7-14 illustrate cross-sectional views of some embodiments of a method of forming an integrated chip (IC) having a trench capacitor disposed within a trench and laterally adjacent to a cavity within the trench.
  • IC integrated chip
  • FIG. 15 illustrates a flowchart of some embodiments of a method for forming an IC having a trench capacitor disposed within a trench and laterally adjacent to a cavity within the trench.
  • the pillar structure 101 has a first width w 1 that is aligned with the front-side surface 102 f of the semiconductor substrate 102 , and further has a second width w 2 that is disposed vertically at a first point beneath the front-side surface 102 f .
  • the first width w 1 is greater than the second width w 2 .
  • a width of the pillar structure 101 continuously decreases from the front-side surface 102 f of the semiconductor substrate 102 to the first point. This, in part, ensures that a cavity 103 will exist in each of the trenches 102 t .
  • the capacitor electrode layers 110 a - d and the capacitor dielectric layers 112 a - d are deposited (e.g., by one or more ALD processes) such that they will conform to a shape of the pillar structure 101 . Because the first width w 1 of the pillar structure 101 is greater than the second width w 2 of the pillar structure 101 , the cavity 103 will be present in each trench 102 t after depositing the capacitor electrode layers 110 a - d and the capacitor dielectric layers 112 a - d.
  • the first width w 1 of the pillar structure 101 is within a range of about 0.1 to 0.2 micrometers. In further embodiments, if the first width w 1 is less than about 0.1 micrometers, then the pillar structure 101 is too thin such that it may collapse due to force applied by layers of the trench capacitor 106 . In yet further embodiments, if the first width w 1 is greater than about 0.2 micrometers, then a number of trenches 102 t that may be formed within the semiconductor substrate 102 is reduced and/or an opening of each trench 102 t is too small to facilitate proper deposition of layers of the trench capacitor 106 within the trenches 102 t .
  • the second width w 2 of the pillar structure 101 is within a range of about 0.07 to 0.17 micrometers. In further embodiments, if the second width w 2 is less than about 0.07 micrometers, then the pillar structure 101 is too thin such that it may collapse due to force applied by layers of the trench capacitor 106 . In yet further embodiments, if the second width w 2 is greater than about 0.17 micrometers, then a size of the cavity 103 may be reduced.
  • the first width w 1 is greater than the second width w 2 .
  • a difference between the first width w 1 and the second width w 2 is greater than about 30 nanometers.
  • the size of the cavity 103 may be reduced, thereby resulting in warpage and/or cracking of the semiconductor substrate 102 .
  • the IC 200 includes an interconnect structure 117 overlying a front-side surface 102 f of a semiconductor substrate 102 .
  • the semiconductor substrate 102 may, for example, be or comprise a bulk substrate (e.g., bulk silicon), a silicon-on-insulator (SOI) substrate, or another suitable substrate and/or may comprise a first doping type (e.g., p-type).
  • a doped region 104 is disposed within the semiconductor substrate 102 and may comprise the first doping type with a higher doping concentration than the semiconductor substrate 102 .
  • the interconnect structure 117 includes an interconnect dielectric structure 122 , a plurality of conductive vias 118 , and a plurality of conductive wires 120 .
  • the interconnect dielectric structure 122 may, for example, include one or more inter-level dielectric (ILD) layers.
  • the one or more ILD layers may, for example, respectively be or comprise an oxide, such as silicon dioxide, a low-k dielectric material, an extreme low-k dielectric material, any combination of the foregoing, or another suitable dielectric material.
  • the plurality of conductive vias and wires 118 , 120 are configured to electrically couple semiconductor devices disposed over and/or within the semiconductor substrate 102 to one another.
  • the conductive vias and wires 118 , 120 may, for example, respectively be or comprise tungsten, copper, aluminum, titanium nitride, tantalum nitride, any combination of the foregoing, or the like.
  • the pillar structure 101 has a first width w 1 that is horizontally aligned with the front-side surface 102 f of the semiconductor substrate 102 , and further has a second width w 2 that is disposed at a first point 202 vertically offset from the front-side surface 102 f .
  • the first width w 1 is greater than the second width w 2 .
  • the width of the pillar structure 101 may continuously decrease from the front-side surface 102 f of the semiconductor substrate 102 to the first point 202 .
  • a first height h 1 of the pillar structure 101 is defined from the front-side surface 102 f of the semiconductor substrate 102 to the first point 202 .
  • the first height h 1 is, for example, greater than 0.05 micrometers or within a range of about 0.05 to 4 micrometers. In further embodiments, if, for example, the first height h 1 is less than 0.05 micrometers, then a size of the cavity 103 may be reduced which may increase an amount of stress induced on the semiconductor substrate 102 . In yet further embodiments, the width of the pillar structure 101 continuously decreases across the first height h 1 in a direction away from the front-side surface 102 f of the semiconductor substrate 102 . In some embodiments, the first width w 1 of the pillar structure 101 is within a range of about 0.1 to 0.2 micrometers.
  • the second width w 2 of the pillar structure 101 is within a range of about 0.07 to 0.17 micrometers.
  • a first length L 1 of the trench 102 t is within a range of about 0.3 to 0.4 micrometers.
  • the first length L 1 is aligned with the front-side surface 102 f of the semiconductor substrate 102 and may define an opening of the trench 102 t .
  • an opening of the trench 102 t is too small such that layers of the trench capacitor 106 may not properly be deposited within the trench 102 t .
  • a trench pitch of the trench 102 t is equal to the sum of the first width w 1 of the pillar structure 101 and the first length L 1 of the trench 102 t (e.g., w 1 +L 1 ). In some embodiments, the trench pitch is within a range of about 0.4 to 0.6 micrometers.
  • the trench pitch is less than about 0.4 micrometers, then the opening of the trench 102 t may be too small such that the layers of the trench capacitor may not properly fill the trench 102 t . In yet further embodiments, if the trench pitch is greater than about 0.6 micrometers, then a capacitance density of the trench capacitor 106 may be reduced.
  • a second height h 2 of the pillar structure 101 is defined from the front-side surface 102 f of the semiconductor substrate 102 to a second point 204 .
  • the second point 204 is disposed vertically beneath the first point 202 in a direction away from the front-side surface 102 f .
  • the second height h 2 is, for example, about 6 micrometers, or within a range of about 0.595 to 7.65 micrometers.
  • a width of the pillar structure 101 continuously increases from the first point 202 to the second point 204 .
  • a third height h 3 of the pillar structure 101 is defined from the front-side surface 102 f of the semiconductor substrate 102 to a third point 206 .
  • the third point 206 may be aligned with a lower surface 102 ls of the semiconductor substrate 102 .
  • the lower surface 102 ls of the semiconductor substrate 102 defines a bottom surface of the trench 102 t and/or is aligned with a bottom surface of the trench segments 106 ts .
  • the third height h 3 may be about 7 micrometers, about 8.5 micrometers, or within a range of about 6.5 to 8.5 micrometers.
  • a second length L 2 of the trench 102 t is aligned with the second point 204 . In some embodiments, the second length L 2 is within a range of about 0.21 to 0.36 micrometers.
  • the second length L 2 is within a range of about 70 to 90 percent of the first length L 1 (e.g., within a range of about 0.7*L 1 to 0.9*L 1 ).
  • a third length L 3 of the trench 102 t is aligned with the third point 206 and/or is aligned with the lower surface 102 ls of the semiconductor substrate 102 .
  • the third length L 3 is within a range of about 0.3 to 0.4 micrometers or within a range of about 0.24 to 0.4 micrometers.
  • the third length L 3 is within a range of about 80 to 100 percent of the first length L 1 (e.g., within a range of about 0.8*L 1 to L 1 ).
  • the third length L 3 is substantially equal to the first length L 1 . In some embodiments, if the third length L 3 is less than about 0.8*L 1 , then a size of the cavity 103 is reduced which may increase an amount of stress induced on the semiconductor substrate 102 . In further embodiments, if the third length L 3 is greater than the first length L 1 , then the layers of the trench capacitor 106 may not be properly disposed along a corner of the trench 102 t . This, in part, may result in delamination between the capacitor dielectric layers 112 a - d and/or the capacitor electrode layers 110 a - d.
  • a third angle 902 is defined between a sidewall of the pillar structure 101 and a substantially horizontal line 904 .
  • the substantially horizontal line 904 is horizontally aligned with the second point 204 and is parallel with the front-side surface 102 f of the semiconductor substrate 102 .
  • the third angle 902 is within a range of about 90 to 93 degrees.
  • the third height h 3 of the pillar structure 101 is defined from the front-side surface 102 f of the semiconductor substrate 102 to the third point 206 .
  • the third point 206 may be aligned with the lower surface 102 ls of the semiconductor substrate 102 .
  • the third height h 3 may be about 7 micrometers, about 8.5 micrometers, or within a range of about 6.5 to 8.5 micrometers.
  • a removal process e.g., a wet etch
  • the sidewall protection layer 802 may remain in place during the patterning process of FIG. 9 , such that the sidewall protection layer 802 may prevent damage to sidewalls of the semiconductor substrate 102 that define an upper portion of the trench 102 t and/or the pillar structure 101 (e.g., the region between the front-side surface 102 f and the second point 204 ).
  • the patterning processes of FIGS. 7 and 9 are performed such that the trenches 102 t respectively have a high aspect ratio (e.g., an aspect ratio greater than about 20:1).
  • a process for patterning each capacitor electrode layer 110 a - d and/or capacitor dielectric layer 112 a - d includes: forming a masking layer (not shown) over the target capacitor electrode layer and/or capacitor dielectric layer; exposing unmasked regions of the target capacitor electrode layer and/or capacitor dielectric layer to one or more etchants, thereby reducing a width of the target layer(s); and performing a removal process (e.g., a wet etch process) to remove the masking layer.
  • a first patterning process according to a first masking layer may be performed on a first capacitor electrode layer 110 a
  • a second patterning process according to a second masking layer may be performed on a second capacitor electrode layer 110 b and a first capacitor dielectric layer 112 a
  • additional patterning processes may be performed for the remaining capacitor layers.
  • an etch stop layer 116 is formed over an upper surface of the trench capacitor 106 .
  • the etch stop layer 116 may be deposited by CVD, PVD, ALD, or another suitable growth or deposition process.
  • the etch stop layer 116 may, for example, be or comprise silicon nitride, silicon carbide, or another suitable dielectric material.
  • FIG. 15 illustrates a method 1500 of forming an integrated circuit (IC) including a trench capacitor disposed within a trench and laterally adjacent to a cavity within the trench according to the present disclosure.
  • IC integrated circuit
  • FIG. 15 illustrates a method 1500 of forming an integrated circuit (IC) including a trench capacitor disposed within a trench and laterally adjacent to a cavity within the trench according to the present disclosure.
  • the method 1500 is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

Description

  • FIG. 1 illustrates a cross-sectional view of some embodiments of an integrated circuit (IC) including a trench capacitor disposed within a trench and laterally adjacent to a cavity within the trench.
  • FIGS. 7-14 illustrate cross-sectional views of some embodiments of a method of forming an integrated chip (IC) having a trench capacitor disposed within a trench and laterally adjacent to a cavity within the trench.
  • FIG. 15 illustrates a flowchart of some embodiments of a method for forming an IC having a trench capacitor disposed within a trench and laterally adjacent to a cavity within the trench.
  • In some embodiments, the pillar structure 101 has a first width w1 that is aligned with the front-side surface 102 f of the semiconductor substrate 102, and further has a second width w2 that is disposed vertically at a first point beneath the front-side surface 102 f. The first width w1 is greater than the second width w2. In further embodiments, a width of the pillar structure 101 continuously decreases from the front-side surface 102 f of the semiconductor substrate 102 to the first point. This, in part, ensures that a cavity 103 will exist in each of the trenches 102 t. For example, during fabrication of the trench capacitor 106, the capacitor electrode layers 110 a-d and the capacitor dielectric layers 112 a-d are deposited (e.g., by one or more ALD processes) such that they will conform to a shape of the pillar structure 101. Because the first width w1 of the pillar structure 101 is greater than the second width w2 of the pillar structure 101, the cavity 103 will be present in each trench 102 t after depositing the capacitor electrode layers 110 a-d and the capacitor dielectric layers 112 a-d.
  • In some embodiments, the first width w1 of the pillar structure 101 is within a range of about 0.1 to 0.2 micrometers. In further embodiments, if the first width w1 is less than about 0.1 micrometers, then the pillar structure 101 is too thin such that it may collapse due to force applied by layers of the trench capacitor 106. In yet further embodiments, if the first width w1 is greater than about 0.2 micrometers, then a number of trenches 102 t that may be formed within the semiconductor substrate 102 is reduced and/or an opening of each trench 102 t is too small to facilitate proper deposition of layers of the trench capacitor 106 within the trenches 102 t. In various embodiments, the second width w2 of the pillar structure 101 is within a range of about 0.07 to 0.17 micrometers. In further embodiments, if the second width w2 is less than about 0.07 micrometers, then the pillar structure 101 is too thin such that it may collapse due to force applied by layers of the trench capacitor 106. In yet further embodiments, if the second width w2 is greater than about 0.17 micrometers, then a size of the cavity 103 may be reduced. In such embodiments, reduction of the size of the cavity 103 increases a stress applied to the semiconductor substrate 102 as the capacitor electrode layers 110 a-d and capacitor dielectric layers 112 a-d expand, thereby resulting in warpage and/or cracking of the semiconductor substrate 102. In various embodiments, the first width w1 is greater than the second width w2. In further embodiments, a difference between the first width w1 and the second width w2 (e.g., w1-w2) is greater than about 30 nanometers. In some embodiments, if the difference between the first width w1 and the second width w2 is less than about 30 nanometers, then the size of the cavity 103 may be reduced, thereby resulting in warpage and/or cracking of the semiconductor substrate 102.
  • The IC 200 includes an interconnect structure 117 overlying a front-side surface 102 f of a semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 may, for example, be or comprise a bulk substrate (e.g., bulk silicon), a silicon-on-insulator (SOI) substrate, or another suitable substrate and/or may comprise a first doping type (e.g., p-type). A doped region 104 is disposed within the semiconductor substrate 102 and may comprise the first doping type with a higher doping concentration than the semiconductor substrate 102. The interconnect structure 117 includes an interconnect dielectric structure 122, a plurality of conductive vias 118, and a plurality of conductive wires 120. The interconnect dielectric structure 122 may, for example, include one or more inter-level dielectric (ILD) layers. The one or more ILD layers may, for example, respectively be or comprise an oxide, such as silicon dioxide, a low-k dielectric material, an extreme low-k dielectric material, any combination of the foregoing, or another suitable dielectric material. The plurality of conductive vias and wires 118, 120 are configured to electrically couple semiconductor devices disposed over and/or within the semiconductor substrate 102 to one another. In further embodiments, the conductive vias and wires 118, 120 may, for example, respectively be or comprise tungsten, copper, aluminum, titanium nitride, tantalum nitride, any combination of the foregoing, or the like.
  • The pillar structure 101 has a first width w1 that is horizontally aligned with the front-side surface 102 f of the semiconductor substrate 102, and further has a second width w2 that is disposed at a first point 202 vertically offset from the front-side surface 102 f. In some embodiments, the first width w1 is greater than the second width w2. Further, the width of the pillar structure 101 may continuously decrease from the front-side surface 102 f of the semiconductor substrate 102 to the first point 202. In further embodiments, a first height h1 of the pillar structure 101 is defined from the front-side surface 102 f of the semiconductor substrate 102 to the first point 202. In yet further embodiments, the first height h1 is, for example, greater than 0.05 micrometers or within a range of about 0.05 to 4 micrometers. In further embodiments, if, for example, the first height h1 is less than 0.05 micrometers, then a size of the cavity 103 may be reduced which may increase an amount of stress induced on the semiconductor substrate 102. In yet further embodiments, the width of the pillar structure 101 continuously decreases across the first height h1 in a direction away from the front-side surface 102 f of the semiconductor substrate 102. In some embodiments, the first width w1 of the pillar structure 101 is within a range of about 0.1 to 0.2 micrometers. In various embodiments, the second width w2 of the pillar structure 101 is within a range of about 0.07 to 0.17 micrometers. In some embodiments, a first length L1 of the trench 102 t is within a range of about 0.3 to 0.4 micrometers. The first length L1 is aligned with the front-side surface 102 f of the semiconductor substrate 102 and may define an opening of the trench 102 t. In some embodiments, if the first length L1 is less than about 0.3 micrometers, then an opening of the trench 102 t is too small such that layers of the trench capacitor 106 may not properly be deposited within the trench 102 t. In further embodiments, if the first length L1 is greater than about 0.4 micrometers, then a number of trenches 102 t that may be formed within the semiconductor substrate 102 is reduced and/or the first width w1 is reduced such that the pillar structure 101 is too thin and may collapse due to force applied by layers of the trench capacitor 106. In some embodiments, a trench pitch of the trench 102 t is equal to the sum of the first width w1 of the pillar structure 101 and the first length L1 of the trench 102 t (e.g., w1+L1). In some embodiments, the trench pitch is within a range of about 0.4 to 0.6 micrometers. In further embodiments, if the trench pitch is less than about 0.4 micrometers, then the opening of the trench 102 t may be too small such that the layers of the trench capacitor may not properly fill the trench 102 t. In yet further embodiments, if the trench pitch is greater than about 0.6 micrometers, then a capacitance density of the trench capacitor 106 may be reduced.
  • A second height h2 of the pillar structure 101 is defined from the front-side surface 102 f of the semiconductor substrate 102 to a second point 204. The second point 204 is disposed vertically beneath the first point 202 in a direction away from the front-side surface 102 f. In some embodiments, the second height h2 is, for example, about 6 micrometers, or within a range of about 0.595 to 7.65 micrometers. In some embodiments, a width of the pillar structure 101 continuously increases from the first point 202 to the second point 204. A third height h3 of the pillar structure 101 is defined from the front-side surface 102 f of the semiconductor substrate 102 to a third point 206. The third point 206 may be aligned with a lower surface 102 ls of the semiconductor substrate 102. In some embodiments, the lower surface 102 ls of the semiconductor substrate 102 defines a bottom surface of the trench 102 t and/or is aligned with a bottom surface of the trench segments 106 ts. In some embodiments, the third height h3 may be about 7 micrometers, about 8.5 micrometers, or within a range of about 6.5 to 8.5 micrometers. A second length L2 of the trench 102 t is aligned with the second point 204. In some embodiments, the second length L2 is within a range of about 0.21 to 0.36 micrometers. In further embodiments, the second length L2 is within a range of about 70 to 90 percent of the first length L1 (e.g., within a range of about 0.7*L1 to 0.9*L1). A third length L3 of the trench 102 t is aligned with the third point 206 and/or is aligned with the lower surface 102 ls of the semiconductor substrate 102. In some embodiments, the third length L3 is within a range of about 0.3 to 0.4 micrometers or within a range of about 0.24 to 0.4 micrometers. In further embodiments, the third length L3 is within a range of about 80 to 100 percent of the first length L1 (e.g., within a range of about 0.8*L1 to L1). Thus, in some embodiments, the third length L3 is substantially equal to the first length L1. In some embodiments, if the third length L3 is less than about 0.8*L1, then a size of the cavity 103 is reduced which may increase an amount of stress induced on the semiconductor substrate 102. In further embodiments, if the third length L3 is greater than the first length L1, then the layers of the trench capacitor 106 may not be properly disposed along a corner of the trench 102 t. This, in part, may result in delamination between the capacitor dielectric layers 112 a-d and/or the capacitor electrode layers 110 a-d.
  • A third angle 902 is defined between a sidewall of the pillar structure 101 and a substantially horizontal line 904. In some embodiments, the substantially horizontal line 904 is horizontally aligned with the second point 204 and is parallel with the front-side surface 102 f of the semiconductor substrate 102. In some embodiments, the third angle 902 is within a range of about 90 to 93 degrees. The third height h3 of the pillar structure 101 is defined from the front-side surface 102 f of the semiconductor substrate 102 to the third point 206. The third point 206 may be aligned with the lower surface 102 ls of the semiconductor substrate 102. In some embodiments, the third height h3 may be about 7 micrometers, about 8.5 micrometers, or within a range of about 6.5 to 8.5 micrometers. In yet further embodiments, after performing the one or more dry etches of FIG. 9, a removal process (e.g., a wet etch) may be performed to remove the sidewall protection layer 802. In further embodiments, the sidewall protection layer 802 may remain in place during the patterning process of FIG. 9, such that the sidewall protection layer 802 may prevent damage to sidewalls of the semiconductor substrate 102 that define an upper portion of the trench 102 t and/or the pillar structure 101 (e.g., the region between the front-side surface 102 f and the second point 204). This in turn may ensure the dimensions (e.g., w1, w2, L1, h1, h2, and/or L2) defined by the patterning process of FIG. 7 are not substantially changed during the patterning process of FIG. 9. In further embodiments, the patterning processes of FIGS. 7 and 9 are performed such that the trenches 102 t respectively have a high aspect ratio (e.g., an aspect ratio greater than about 20:1).
  • As illustrated in cross-sectional view 1100 of FIG. 11, the capacitor electrode layers 110 a-d and/or capacitor dielectric layers 112 a-d are patterned, thereby defining a trench capacitor 106. In some embodiments, a process for patterning each capacitor electrode layer 110 a-d and/or capacitor dielectric layer 112 a-d includes: forming a masking layer (not shown) over the target capacitor electrode layer and/or capacitor dielectric layer; exposing unmasked regions of the target capacitor electrode layer and/or capacitor dielectric layer to one or more etchants, thereby reducing a width of the target layer(s); and performing a removal process (e.g., a wet etch process) to remove the masking layer. For example, a first patterning process according to a first masking layer (not shown) may be performed on a first capacitor electrode layer 110 a, a second patterning process according to a second masking layer (not shown) may be performed on a second capacitor electrode layer 110 b and a first capacitor dielectric layer 112 a, and additional patterning processes may be performed for the remaining capacitor layers. Further, an etch stop layer 116 is formed over an upper surface of the trench capacitor 106. In some embodiments, the etch stop layer 116 may be deposited by CVD, PVD, ALD, or another suitable growth or deposition process. In some embodiments, the etch stop layer 116 may, for example, be or comprise silicon nitride, silicon carbide, or another suitable dielectric material.
  • FIG. 15 illustrates a method 1500 of forming an integrated circuit (IC) including a trench capacitor disposed within a trench and laterally adjacent to a cavity within the trench according to the present disclosure. Although the method 1500 is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

Claims (23)

1. An integrated circuit (IC) comprising:
a substrate comprising sidewalls that define a trench, wherein the trench extends into a front-side surface of the substrate;
a trench capacitor comprising a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate; and
a pillar structure disposed within the substrate and abutting the trench, wherein the pillar structure has a first width and a second width less than the first width, wherein the first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.
2. The IC of claim 1, wherein the width of the pillar structure continuously increases from the first point to a second point, wherein the second point is disposed beneath the first point.
3. The IC of claim 2, wherein the width of the pillar structure continuously decreases from the second point to a third point, wherein the third point is disposed beneath the second point, and wherein the third point is aligned with a lower surface of the substrate that defines a bottom of the trench.
4. (canceled)
5. (canceled)
6. The IC of claim 1, wherein the plurality of capacitor dielectric layers comprises an uppermost capacitor dielectric layer that continuously lines the trench and seals the cavity within the trench.
7. The IC of claim 1, further comprising:
an insulator layer that continuously extends from the front-side surface of the substrate to the sidewalls of the substrate that define the trench, wherein the insulator layer is disposed between the trench capacitor and the substrate, wherein a thickness of the insulator layer is greater than a thickness of the capacitor electrode layers and the capacitor dielectric layers, respectively.
8. The IC of claim 7, wherein the insulator layer continuously extends along sidewalls and an upper surface of the pillar structure.
9. The IC of claim 7, wherein the insulator layer comprises a first dielectric material and the capacitor dielectric layers comprise a second dielectric material different than the first dielectric material.
10. A semiconductor structure comprising:
a substrate;
a trench capacitor comprising a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers overlying a front-side surface of the substrate, wherein the capacitor electrode layers and the capacitor dielectric layers define a first trench segment and a second trench segment protruding into the substrate and further define a first cavity and a second cavity recessed into the substrate respectively at the first and second trench segments; and
a pillar structure disposed laterally between the first trench segment and the second trench segment, wherein a width of the pillar structure continuously decreases in a first direction from the front-side surface towards a bottom surface of the first and second trench segments.
11. The semiconductor structure of claim 10, wherein the pillar structure comprises a first slanted sidewall segment, a second slanted sidewall segment, and a third slanted sidewall segment, wherein the second slanted sidewall segment is disposed vertically between the first and third slanted sidewall segments, wherein the first and third slanted sidewall segments are angled in a same direction that is opposite a direction of an angle of the second slanted sidewall segment.
12. The semiconductor structure of claim 10, wherein widths of the first and second cavities continuously increase in the first direction.
13. The semiconductor structure of claim 10, wherein the pillar structure continuously decreases in the first direction along a first vertical distance, wherein a first width of the pillar structure is greater than the first vertical distance, and wherein the first width is aligned with the front-side surface of the substrate.
14. The semiconductor structure of claim 10, further comprising:
an insulator layer disposed between the substrate and the first and second trench segments, wherein the insulator layer continuously extends along sidewalls and an upper surface of the pillar structure, wherein a thickness of the insulator layer continuously increases in the first direction.
15. The semiconductor structure of claim 14, wherein the insulator layer comprises silicon dioxide and the capacitor dielectric layers respectively comprise a high-k dielectric material.
16. The semiconductor structure of claim 14, wherein a first thickness of the insulator layer disposed along an upper surface of the pillar structure is less than a second thickness of the insulator layer disposed along a sidewall of the pillar structure.
17. (canceled)
18. A method for forming a trench capacitor, the method comprising:
performing a first patterning process on a front-side surface of a substrate to define an upper portion of a trench and an upper portion of a pillar structure, wherein the first patterning process is performed such that a width of the pillar structure decreases from the front-side surface to a first point below the front-side surface;
performing a second patterning process on the substrate to expand the trench and increase a height of the pillar structure; and
forming a plurality of capacitor dielectric layers and a plurality of capacitor electrode layers within the trench such that a cavity is defined between sidewalls of an uppermost capacitor dielectric layer, wherein the cavity is disposed within the trench, and wherein the uppermost capacitor dielectric layer seals the cavity.
19. The method of claim 18, further comprising:
forming a sidewall protection layer along sidewalls of the substrate that define the trench, wherein the sidewall protection layer is formed after the first patterning process and before the second patterning process.
20. The method of claim 18, wherein the second patterning process is performed such that the width of the pillar structure continuously decreases from a second point to a lower surface of the substrate, wherein the second point is disposed vertically beneath the first point and the lower surface of the substrate defines a bottom surface of the trench.
21. The IC of claim 6, wherein the uppermost capacitor dielectric layer comprises inner sidewalls that define the cavity.
22. The IC of claim 1, wherein a width of the cavity continuously decreases from the first point in a direction towards a bottom surface of the trench capacitor.
23. The semiconductor structure of claim 10, wherein the plurality of capacitor dielectric layers comprises an uppermost capacitor dielectric layer that abuts the first cavity and the second cavity, wherein the uppermost capacitor dielectric layer seals the first cavity and the second cavity.
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KR1020200037838A KR102302524B1 (en) 2019-12-27 2020-03-27 Trench capacitor profile to decrease substrate warpage
TW109145598A TWI751851B (en) 2019-12-27 2020-12-22 Integrated circuit, semiconductor structure and method for forming trench capacitor
CN202011563976.1A CN113053877A (en) 2019-12-27 2020-12-25 Integrated circuit, semiconductor structure and method for forming groove capacitor
US17/370,067 US11769792B2 (en) 2019-12-27 2021-07-08 Trench capacitor profile to decrease substrate warpage
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230009146A1 (en) * 2021-07-08 2023-01-12 Key Foundry Co., Ltd. Manufacturing method for deep trench capacitor with scalloped profile
TWI832264B (en) * 2021-08-02 2024-02-11 台灣積體電路製造股份有限公司 Integrated chip with multi-layer trench capacitor structure and forming method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230009576A (en) * 2021-07-09 2023-01-17 주식회사 키파운드리 Method of manufacturing a trench capacitor having improved wafer bow
US20230092429A1 (en) * 2021-09-23 2023-03-23 Qualcomm Incorporated High density silicon based capacitor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190074349A1 (en) * 2017-09-01 2019-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Low warpage high density trench capacitor
US20200066922A1 (en) * 2018-08-27 2020-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Film scheme for a high density trench capacitor
US20200176552A1 (en) * 2018-11-30 2020-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Cap structure for trench capacitors

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895255A (en) * 1994-11-30 1999-04-20 Kabushiki Kaisha Toshiba Shallow trench isolation formation with deep trench cap
US5937296A (en) * 1996-12-20 1999-08-10 Siemens Aktiengesellschaft Memory cell that includes a vertical transistor and a trench capacitor
US6103585A (en) * 1998-06-09 2000-08-15 Siemens Aktiengesellschaft Method of forming deep trench capacitors
EP0981164A3 (en) 1998-08-18 2003-10-15 International Business Machines Corporation Low resistance fill for deep trench capacitor
US6297527B1 (en) * 1999-05-12 2001-10-02 Micron Technology, Inc. Multilayer electrode for ferroelectric and high dielectric constant capacitors
US6188096B1 (en) * 1999-06-09 2001-02-13 International Business Machines Corporation DRAM cell capacitor having increased trench capacitance
DE19956078B4 (en) * 1999-11-22 2006-12-28 Infineon Technologies Ag Method for producing an insulation collar in a trench capacitor
US6437385B1 (en) * 2000-06-29 2002-08-20 International Business Machines Corporation Integrated circuit capacitor
DE10109564A1 (en) 2001-02-28 2002-09-12 Infineon Technologies Ag Trench capacitor and process for its manufacture
DE10128326C1 (en) * 2001-06-12 2003-02-13 Infineon Technologies Ag Fabrication of trench capacitor for memory cell, by forming trench in substrate, providing lower capacitor electrode adjoining wall of trench in lower trench region, and providing storage dielectric and upper capacitor electrode
DE10130934A1 (en) * 2001-06-27 2003-01-16 Infineon Technologies Ag Trench capacitor and corresponding manufacturing process
US6960365B2 (en) * 2002-01-25 2005-11-01 Infineon Technologies Ag Vertical MIMCap manufacturing method
US6897508B2 (en) * 2002-05-01 2005-05-24 Sundew Technologies, Llc Integrated capacitor with enhanced capacitance density and method of fabricating same
DE10337858B4 (en) * 2003-08-18 2007-04-05 Infineon Technologies Ag Trench capacitor and method of making a trench capacitor
US8049264B2 (en) * 2005-01-28 2011-11-01 Qimonda Ag Method for producing a dielectric material on a semiconductor device and semiconductor device
US20070232011A1 (en) 2006-03-31 2007-10-04 Freescale Semiconductor, Inc. Method of forming an active semiconductor device over a passive device and semiconductor component thereof
JP2008159988A (en) * 2006-12-26 2008-07-10 Elpida Memory Inc Semiconductor device, and method for manufacturing the semiconductor device
US20090096001A1 (en) * 2007-10-15 2009-04-16 Qimonda Ag Integrated Circuit and Method of Manufacturing the Same
US7671394B2 (en) * 2007-10-17 2010-03-02 International Business Machines Corporation Embedded trench capacitor having a high-k node dielectric and a metallic inner electrode
US7910451B2 (en) * 2008-04-04 2011-03-22 International Business Machines Corporation Simultaneous buried strap and buried contact via formation for SOI deep trench capacitor
US8101497B2 (en) * 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
US7943474B2 (en) * 2009-02-24 2011-05-17 International Business Machines Corporation EDRAM including metal plates
US8492818B2 (en) * 2010-09-14 2013-07-23 International Business Machines Corporation High capacitance trench capacitor
US8647945B2 (en) * 2010-12-03 2014-02-11 International Business Machines Corporation Method of forming substrate contact for semiconductor on insulator (SOI) substrate
US8492874B2 (en) * 2011-02-04 2013-07-23 Qualcomm Incorporated High density metal-insulator-metal trench capacitor
JP5689392B2 (en) * 2011-09-02 2015-03-25 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of semiconductor device
US8916435B2 (en) * 2011-09-09 2014-12-23 International Business Machines Corporation Self-aligned bottom plate for metal high-K dielectric metal insulator metal (MIM) embedded dynamic random access memory
US8901706B2 (en) * 2012-01-06 2014-12-02 International Business Machines Corporation Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches
DE102013100025B4 (en) 2012-01-06 2022-02-17 Maxim Integrated Products, Inc. Semiconductor component with a capacitor integrated therein and method for its production
US9978829B2 (en) * 2012-11-26 2018-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Low impedance high density deep trench capacitor
TWI538226B (en) * 2013-12-13 2016-06-11 華亞科技股份有限公司 Manufacturing method of stacked capacitor having high structural strength
US20180047807A1 (en) * 2016-08-10 2018-02-15 Globalfoundries Inc. Deep trench capacitors with a diffusion pad
JP6891502B2 (en) * 2017-01-16 2021-06-18 セイコーエプソン株式会社 Electro-optics, electronic equipment
KR101952869B1 (en) * 2017-05-29 2019-02-27 삼성전기주식회사 Capacitor
JP6818712B2 (en) 2018-03-22 2021-01-20 株式会社東芝 Semiconductor device
JP7178187B2 (en) * 2018-06-27 2022-11-25 太陽誘電株式会社 trench capacitor
US11018169B2 (en) * 2019-08-19 2021-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Metal-insulator-metal capacitor structure to increase capacitance density

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190074349A1 (en) * 2017-09-01 2019-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Low warpage high density trench capacitor
US10276651B2 (en) * 2017-09-01 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Low warpage high density trench capacitor
US20190245031A1 (en) * 2017-09-01 2019-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Low warpage high density trench capacitor
US20200066922A1 (en) * 2018-08-27 2020-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Film scheme for a high density trench capacitor
US20200176552A1 (en) * 2018-11-30 2020-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Cap structure for trench capacitors

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230009146A1 (en) * 2021-07-08 2023-01-12 Key Foundry Co., Ltd. Manufacturing method for deep trench capacitor with scalloped profile
US11854817B2 (en) * 2021-07-08 2023-12-26 Key Foundry Co., Ltd. Manufacturing method for deep trench capacitor with scalloped profile
TWI832264B (en) * 2021-08-02 2024-02-11 台灣積體電路製造股份有限公司 Integrated chip with multi-layer trench capacitor structure and forming method thereof
US11916100B2 (en) 2021-08-02 2024-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer trench capacitor structure

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