US20200402914A1 - Method for forming semiconductor device structure with conductive line - Google Patents
Method for forming semiconductor device structure with conductive line Download PDFInfo
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- US20200402914A1 US20200402914A1 US17/010,530 US202017010530A US2020402914A1 US 20200402914 A1 US20200402914 A1 US 20200402914A1 US 202017010530 A US202017010530 A US 202017010530A US 2020402914 A1 US2020402914 A1 US 2020402914A1
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Images
Classifications
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
Definitions
- FIGS. 1A-1M are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.
- FIGS. 2A-2C are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.
- FIGS. 3A-3H are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.
- FIGS. 4A-4F are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.
- FIGS. 1A -IM are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.
- a semiconductor substrate 110 is provided.
- the semiconductor substrate 110 is a bulk semiconductor substrate, such as a semiconductor wafer.
- the semiconductor substrate 110 is a silicon wafer.
- the semiconductor substrate 110 may include silicon or another elementary semiconductor material such as germanium.
- the semiconductor substrate 110 includes a compound semiconductor.
- the compound semiconductor may include silicon germanium, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable compound semiconductor, or a combination thereof.
- the semiconductor substrate 110 includes a semiconductor-on-insulator (SOI) substrate.
- SOI substrate may be fabricated using a wafer bonding process, a silicon film transfer process, a separation by implantation of oxygen (SIMOX) process, another applicable method, or a combination thereof.
- SIMOX separation by implantation of oxygen
- various device elements are formed in and/or over the semiconductor substrate 110 .
- the device elements are not shown in figures for the purpose of simplicity and clarity. Examples of the various device elements include transistors, diodes, another suitable element, or a combination thereof.
- the transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.
- MOSFET metal oxide semiconductor field effect transistors
- CMOS complementary metal oxide semiconductor
- BJT bipolar junction transistors
- high-voltage transistors high-frequency transistors
- PFETs/NFETs p-channel and/or n-channel field effect transistors
- PFETs/NFETs p-channel and/or n-channel field effect transistors
- FEOL semiconductor fabrication processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or a combination thereof.
- isolation features are formed in the semiconductor substrate 110 .
- the isolation features are used to define active regions and electrically isolate various device elements formed in and/or over the semiconductor substrate 110 in the active regions.
- the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof.
- STI shallow trench isolation
- LOC local oxidation of silicon
- an interconnection structure (not shown) is formed over the semiconductor substrate 110 in regions 110 A and 110 B.
- the regions 110 A and 110 B may be referred to as a narrow line width region and a wide line width region, but embodiments of the disclosure are not limited thereto.
- the interconnection structure includes multiple dielectric layers containing an interlayer dielectric (ILD) layer and one or more inter-metal dielectric (IMD) layers.
- the interconnection structure also includes multiple conductive features formed in the ILD and IMD layers.
- the conductive features may include conductive lines, conductive vias, and/or conductive contacts.
- Various processes, such as back-end-of-line (BEOL) semiconductor fabrication processes, are performed to form the interconnection structure.
- the integrated circuit devices include logic devices, memory devices (e.g., static random access memories, SRAMs), radio frequency (RF) devices, input/output (I/O) devices, system-on-chip (SoC) devices, image sensor devices, other applicable types of devices, or a combination thereof.
- memory devices e.g., static random access memories, SRAMs
- RF radio frequency
- I/O input/output
- SoC system-on-chip
- image sensor devices other applicable types of devices, or a combination thereof.
- a dielectric layer 120 is deposited over the semiconductor substrate 110 in the regions 110 A and 110 B.
- the dielectric layer 120 may serve as an ILD or IMD layer of an interconnection structure.
- the dielectric layer 120 covers device elements formed in and/or over the semiconductor substrate 110 .
- FIG. 1A shows that the dielectric layer 120 is a single layer, embodiments of the disclosure are not limited thereto. In some other embodiments, the dielectric layer 120 is a multi-layer structure including dielectric sub-layers (not shown).
- the dielectric layer 120 is made of or includes an insulating material, such as silicon oxide, silicon oxynitride, a low dielectric constant (low-k) material, an extreme low-k (ELK) material, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), one or more other suitable materials, or a combination thereof.
- the dielectric layer 120 is deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a spin-on process, a spray coating process, one or more other applicable processes, or a combination thereof.
- CVD chemical vapor deposition
- ALD atomic layer deposition
- spray coating process one or more other applicable processes, or a combination thereof.
- the low-k or ELK material may have a smaller dielectric constant than that of silicon dioxide.
- the low-k material may have a dielectric constant in a range from about 1.5 to about 3.5.
- the ELK material may have a dielectric constant, which is less than about 2.5 or in a range from about 1.5 to about 2.5.
- RC resistance capacitance
- the dielectric layer 120 is made of or includes a porous dielectric material, an organic polymer, an organic silica glass, SiOF series material, a hydrogen silsesquioxane (HSQ) series material, a methyl silsesquioxane (MSQ) series material, carbon doped silicon oxide, amorphous fluorinated carbon, parylene, benzocyclobutenes (BCB), polytetrafluoroethylene (PTFE) (Teflon), silicon oxycarbide polymers (SiOC), a porous organic series material, a spin-on inorganic dielectric, a spin-on organic dielectric material, one or more other suitable materials, or a combination thereof.
- HSQ hydrogen silsesquioxane
- MSQ methyl silsesquioxane
- CDB benzocyclobutenes
- PTFE polytetrafluoroethylene
- SiOC silicon oxycarbide polymers
- conductive features are formed in the dielectric layer 120 in the regions 110 A and 110 B.
- the conductive features may be electrically connected to gate structures or power devices formed on the semiconductor substrate 110 or doped regions formed in the semiconductor substrate 110 .
- the conductive features in the region 110 A may be electrically connected to the gate structures and the doped regions, and the conductive features in the region 110 B may be electrically connected to the power devices.
- the conductive features may include conductive lines, conductive vias, conductive contacts, or a combination thereof.
- the conductive features are made of or include a conductive material, such as a metal material (e.g., copper, aluminum, tungsten, titanium, cobalt, nickel, gold, platinum, or a combination thereof).
- a metal material e.g., copper, aluminum, tungsten, titanium, cobalt, nickel, gold, platinum, or a combination thereof.
- Various processes, including deposition, etching, planarization, or the like, may be used to form the conductive features in the dielectric layer 120 .
- a mask layer 130 is deposited over the dielectric layer 120 , in accordance with some embodiments.
- the mask layer 130 is also referred to as an anti-reflective coating (ARC) layer, in accordance with some embodiments.
- ARC anti-reflective coating
- the mask layer 130 may absorb light thereby minimizing reflection during a subsequent photolithography process so as to enhance the resolution of the photolithography process.
- the mask layer 130 is made of or includes an anti-reflective material, such as SiON, SiCN, SiN, HfO, Al 2 O 3 , Ta 2 O 5 , ZrO, one or more other suitable materials, or a combination thereof.
- the mask layer 130 is a nitrogen-free anti-reflective coating (NFARC) layer.
- NFARC nitrogen-free anti-reflective coating
- the mask layer 130 is deposited using a spray coating process, a spin-on process, a CVD process, an ALD process, one or more other applicable processes, or a combination thereof.
- a hard mask layer 140 is deposited over the mask layer 130 .
- the hard mask layer 140 is made of or includes titanium nitride (TiN), SiON, one or more other suitable materials, or a combination thereof.
- the hard mask layer 140 is a multi-layer structure, such as oxide-nitride-oxide (ONO) layers.
- the hard mask layer 140 is deposited using a PVD process (such as a radio-frequency PVD (RFPVD) process), a CVD process, an ALD process, one or more other applicable processes, or a combination thereof.
- a mask layer 150 is deposited over the hard mask layer 140 , in accordance with some embodiments.
- the mask layer 150 is also referred to as an anti-reflective coating (ARC) layer, in accordance with some embodiments.
- the mask layer 150 is made of or includes an anti-reflective material, such as SiON, SiCN, SiN, HfO, Al 2 O 3 , Ta 2 O 5 , ZrO, one or more other suitable materials, or a combination thereof.
- the mask layer 150 and the mask layer 130 are made of or include the same material. In some embodiments, the dielectric layer 120 and the mask layer 150 are made of different materials. In some embodiments, the hard mask layer 140 and the mask layer 150 are made of different materials.
- the mask layer 150 is a nitrogen-free anti-reflective coating (NFARC) layer.
- NFARC nitrogen-free anti-reflective coating
- the mask layer 150 is deposited using a spray coating process, a spin-on process, a CVD process, an ALD process, one or more other applicable processes, or a combination thereof.
- a patterned mask structure M 1 is formed over the mask layer 150 , in accordance with some embodiments.
- the patterned mask structure M 1 is a multi-layer mask structure, in accordance with some embodiments.
- the patterned mask structure M 1 includes a lower layer 160 , a middle layer 170 and an upper layer 180 , in accordance with some embodiments.
- the lower layer 160 , the middle layer 170 and the upper layer 180 are sequentially deposited over the mask layer 150 , in accordance with some embodiments.
- the lower layer 160 is made of or includes a polymer material.
- the middle layer 170 is made of or includes a silicon-containing material, such as a silicon-containing polymer material.
- the upper layer 180 is made of or includes a photoresist material.
- the lower layer 160 , the middle layer 170 and the upper layer 180 are deposited using a PVD process, a CVD process, a spin-on process, another applicable process, or a combination thereof.
- the upper layer 180 is patterned to form trenches 182 in the upper layer 180 , in accordance with some embodiments.
- the trenches 182 partially expose the middle layer 170 .
- the upper layer 180 is patterned by a photolithography process.
- the middle layer 170 is patterned or etched using the patterned upper layer 180 as an etch mask. As a result, the trenches 182 are transferred into the middle layer 170 (not shown).
- the patterned upper layer 180 may be removed during the patterning of the middle layer 170 .
- the lower layer 160 is then patterned or etched using the patterned middle layer 170 as an etch mask.
- the trenches 182 are transferred into the lower layer 160 (not shown).
- the patterned middle layer 170 may be removed during the patterning of the lower layer 160 .
- the patterned lower layer 160 is subsequently used as an etch mask to pattern the mask layer 150 .
- the mask layer 150 is patterned or etched using the patterned lower layer 160 as an etch mask, in accordance with some embodiments.
- trenches 151 and 153 are formed in the mask layer 150 , in accordance with some embodiments.
- the trenches 151 and 153 penetrate through the mask layer 150 , in accordance with some embodiments.
- the trenches 151 and 153 partially expose the hard mask layer 140 thereunder, in accordance with some embodiments.
- the patterned lower layer 160 may be removed during the patterning of the mask layer 150 .
- the middle layer 170 , the lower layer 160 , and the mask layer 150 are sequentially patterned using one or more etching processes.
- the etching process may be a dry etching process, one or more other applicable processes, or a combination thereof.
- a patterned mask structure M 2 is formed over the mask layer 150 , in accordance with some embodiments.
- the patterned mask structure M 2 is a multi-layer mask structure, in accordance with some embodiments.
- the patterned mask structure M 2 includes a lower layer 190 , a middle layer 200 , and an upper layer 210 , in accordance with some embodiments.
- the lower layer 190 , the middle layer 200 , and the upper layer 210 are sequentially deposited over the mask layer 150 , in accordance with some embodiments.
- the lower layer 190 is made of or includes a polymer material.
- the middle layer 200 is made of or includes a silicon-containing material, such as a silicon-containing polymer material.
- the upper layer 210 is made of or includes a photoresist material.
- the lower layer 190 , the middle layer 200 and the upper layer 210 are deposited using a PVD process, a CVD process, a spin-on process, another applicable process, or a combination thereof.
- the upper layer 210 is patterned to form trenches 212 in the upper layer 210 , in accordance with some embodiments.
- the trenches 212 partially expose the middle layer 200 .
- the upper layer 210 is patterned by a photolithography process.
- the middle layer 200 is patterned or etched using the patterned upper layer 210 as an etch mask. As a result, the trenches 212 are transferred into the middle layer 200 (not shown).
- the patterned upper layer 210 may be removed during the patterning of the middle layer 200 .
- the lower layer 190 is then patterned or etched using the patterned middle layer 200 as an etch mask. As a result, the trenches 212 are transferred into the lower layer 190 (not shown).
- the patterned middle layer 200 may be removed during the patterning of the lower layer 190 .
- the patterned lower layer 190 is subsequently used as an etch mask to pattern the mask layer 150 .
- the mask layer 150 is patterned and etched using the patterned lower layer 190 as an etch mask.
- trenches 152 and 154 are formed in the mask layer 150 .
- the trenches 152 and 154 penetrate through the mask layer 150 .
- the trenches 152 and 154 partially expose the hard mask layer 140 thereunder, in accordance with some embodiments.
- the patterned lower layer 190 may be removed during the patterning of the mask layer 150 .
- the middle layer 200 , the lower layer 190 and the mask layer 150 are sequentially patterned using one or more etching processes.
- the etching process may be a dry etching process, one or more other applicable processes, or a combination thereof.
- the trenches 151 , 152 , 153 , and 154 respectively have widths W 1 , W 2 , W 3 and W 4 , in accordance with some embodiments.
- the widths W 1 , W 2 , W 3 and W 4 are substantially equal to each other, in accordance with some embodiments.
- the term “substantially equal to” means “within 10%”, in accordance with some embodiments.
- the term “substantially equal to” means the difference between the widths W 1 , W 2 , W 3 and W 4 is within 10% of the average width of the trenches 151 , 152 , 153 , and 154 , in accordance with some embodiments.
- the trenches 151 , 152 , 153 , and 154 have inner walls N 1 , N 2 , N 3 , and N 4 and bottom surfaces B 1 , B 2 , B 3 and B 4 , in accordance with some embodiments.
- a mask layer 220 is deposited over the mask layer 150 and in the trenches 151 , 152 , 153 , and 154 , in accordance with some embodiments.
- the mask layer 220 conformally covers a top surface 155 of the mask layer 150 , the inner walls N 1 , N 2 , N 3 , and N 4 , and the bottom surfaces B 1 , B 2 , B 3 and B 4 , in accordance with some embodiments.
- the mask layer 220 is in direct contact with the mask layers 140 and 150 , in accordance with some embodiments.
- a first thickness T 1 of the mask layer 220 over the top surface 155 is greater than a second thickness T 2 of the mask layer 220 over the inner walls N 1 , N 2 , N 3 , and N 4 .
- the second thickness T 2 is greater than a third thickness T 3 of the mask layer 220 over the bottom surfaces B 1 , B 2 , B 3 and B 4 , in accordance with some embodiments.
- the mask layer 220 is also referred to as an anti-reflective coating (ARC) layer, in accordance with some embodiments.
- the mask layer 220 is made of or includes an anti-reflective material, such as SiON, SiCN, SiN, HfO, Al 2 O 3 , Ta 2 O 5 , ZrO, one or more other suitable materials, or a combination thereof.
- the mask layer 220 and the mask layer 150 are made of or include the same material.
- the mask layer 220 is a nitrogen-free anti-reflective coating (NFARC) layer.
- NFARC nitrogen-free anti-reflective coating
- the mask layer 220 is deposited using a CVD process, an ALD process, one or more other applicable processes, or a combination thereof.
- the mask layer 220 covering the bottom surfaces B 1 , B 2 , B 3 , and B 4 is removed to form trenches 222 , 224 , 226 , and 228 in the mask layer 220 , in accordance with some embodiments.
- the trenches 222 , 224 , 226 , and 228 respectively expose the bottom surfaces B 1 , B 2 , B 3 , and B 4 , in accordance with some embodiments.
- the trenches 222 and 224 respectively have widths W 5 and W 6 , in accordance with some embodiments.
- the width W 5 or W 6 is less than the width W 1 , W 2 , W 3 , or W 4 , in accordance with some embodiments.
- the remaining mask layer 220 covers the inner walls N 1 , N 2 , N 3 , and N 4 and the top surface 155 , in accordance with some embodiments.
- the removal process includes a dry etching process (e.g., an anisotropic etching process) or a wet etching process, in accordance with some embodiments.
- the dry etching process includes a plasma etching process, in accordance with some embodiments.
- a photoresist layer 230 is formed over the mask layer 220 in the region 110 A, in accordance with some embodiments.
- the photoresist layer 230 is filled in the trenches 151 and 152 , in accordance with some embodiments.
- the mask layer 220 in the region 110 B is removed, in accordance with some embodiments.
- the removal process includes an etching process, such as a dry etching process, in accordance with some embodiments.
- the photoresist layer 230 is removed, in accordance with some embodiments.
- the mask layer 220 has a sidewall 229 aligned with the boundary between the regions 110 A and 110 B, in accordance with some embodiments.
- a ratio of the thickness T 2 of the mask layer 220 over the inner wall N 1 to the width W 1 of the trench 151 ranges from about 0.16 to about 0.4.
- a ratio of the width W 5 of the trench 222 to the width W 1 of the trench 151 ranges from about 0.16 to about 0.66.
- a distance D 1 between the trenches 222 and 224 is less than a distance D 2 between the trenches 153 and 154 .
- the mask layers 150 and 220 are used as an etch mask in subsequent processes for forming conductive lines, in accordance with some embodiments.
- the widths W 1 , W 2 , W 3 , and W 4 of the trenches 151 , 152 , 153 , and 154 are substantially equal to each other, the mask layer 220 formed over the inner walls N 1 and N 2 of the trenches 151 and 152 has the trenches 222 and 224 that are narrower than the trenches 151 , 152 , 153 , and 154 . Therefore, the formation of the mask layer 220 may narrow the subsequently formed conductive lines by using the mask layer 220 as an etch mask.
- portions of the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 under the trenches 222 , 224 , 153 , and 154 are removed to form trenches R 1 , R 2 , R 3 , and R 4 in the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 , in accordance with some embodiments.
- the trenches R 1 , R 2 , R 3 , and R 4 pass through the hard mask layer 140 and the mask layer 130 and penetrate into the dielectric layer 120 , in accordance with some embodiments.
- the trenches R 1 , R 2 , R 3 , and R 4 respectively have widths W 7 , W 8 , W 9 , and W 10 , in accordance with some embodiments.
- the width W 7 or W 8 is less than the width W 9 or W 10 , in accordance with some embodiments.
- the removal process includes an etching process using the mask layers 150 and 220 as an etch mask, in accordance with some embodiments.
- the mask layers 150 and 220 may be consumed during the removal process. In some embodiments, an upper portion of the hard mask layer 140 is consumed during the removal process.
- the hard mask layer 140 remaining in the region 110 A is thicker than the hard mask layer 140 remaining in the region 110 B. That is, a thickness T 9 of the hard mask layer 140 in the region 110 A is greater than a thickness T 10 of the hard mask layer 140 in the region 110 B, in accordance with some embodiments.
- the hard mask layer 140 remaining in the region 110 A is also referred to as a thick portion
- the hard mask layer 140 remaining in the region 110 B is also referred to as a thin portion.
- the boundary between the thick portion and the thin portion is substantially aligned with the sidewall 229 of the mask layer 220 (as shown in FIG. 1J ).
- a barrier layer 240 is deposited over the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 , in accordance with some embodiments.
- the barrier layer 240 may prevent metal ions of a subsequently deposited conductive material (which will be described in more detail later) from diffusing into the dielectric layer 120 during thermal processes or cycles.
- the barrier layer 240 may also be referred to as a diffusion barrier layer.
- the barrier layer 240 is made of or includes a refractory metal material, such as tantalum (Ta), titanium (Ti), tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof.
- a refractory metal material such as tantalum (Ta), titanium (Ti), tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof.
- the barrier layer 240 is deposited using a PVD process, an ALD process, one or more other applicable processes, or a combination thereof.
- the barrier layer 240 is deposited conformally.
- a conductive material layer 250 is formed over the barrier layer 240 , in accordance with some embodiments.
- the trenches R 1 , R 2 , R 3 , and R 4 are filled with the conductive material layer 250 and the barrier layer 240 , in accordance with some embodiments.
- the conductive material layer 250 is made of or includes a metal material, such as copper, aluminum, tungsten, titanium, nickel, gold, platinum, silver, one or more other suitable materials, or a combination thereof.
- the conductive material layer 250 may be a single layer or have multiple stacked layers.
- the conductive material layer 250 is deposited using an electroplating process, a PVD process, a CVD process, an electroless plating process, another applicable process, or a combination thereof.
- the conductive material layer 250 and the barrier layer 240 outside of the trenches R 1 , R 2 , R 3 , and R 4 , the hard mask layer 140 , and the mask layer 130 are removed, in accordance with some embodiments.
- the conductive material layer 250 and the barrier layer 240 remaining in the trenches R 1 , R 2 , R 3 , and R 4 forms conductive structures L 1 , L 2 , L 3 , and L 4 respectively in the trenches R 1 , R 2 , R 3 , and R 4 , in accordance with some embodiments.
- the conductive structures L, L 2 , L 3 , and L 4 include conductive lines, in accordance with some embodiments.
- the conductive structures L 1 , L 2 , L 3 , and L 4 respectively have widths (or line widths) W 11 , W 12 , W 13 , and W 14 in accordance with some embodiments. Since the width W 7 or W 8 is less than the width W 9 or W 10 (as shown in FIG. 1K ), the width W 11 or W 12 is less than the width W 13 or W 14 .
- the widths W 11 and W 12 are substantially equal to each other, in accordance with some embodiments.
- the widths W 13 and W 14 are substantially equal to each other, in accordance with some embodiments.
- the conductive structures L 1 and L 2 are positioned in the region 110 A, and the conductive structures L 3 and L 4 are positioned in the region 110 B, in accordance with some embodiments.
- the distance D 1 between the conductive structures L 1 and L 2 is less than the distance D 2 between the conductive structures L 3 and L 4 , in accordance with some embodiments.
- the regions 110 A and 110 B may be respectively referred to as a small pitch region and a large pitch region.
- a pitch of a region is equal to a sum of a width of one of conductive structures and a spacing between two adjacent conductive structures in the region.
- the pitch of the region 110 A is equal to a sum of the width W 11 (or W 12 ) and the distance D 1 , in accordance with some embodiments.
- the pitch of the region 110 B is equal to a sum of the width W 13 (or W 14 ) and the distance D 2 , in accordance with some embodiments. Since the width W 11 (or W 12 ) is less than the W 13 (or W 14 ) and the distance D 1 is less than the distance D 2 , the pitch of the region 110 A is less than the pitch of the region 110 B.
- the removal process includes a planarization process, in accordance with some embodiments. Therefore, top surfaces S 1 , S 2 , S 3 , S 4 , and 122 of the conductive structures L 1 , L 2 , L 3 , and L 4 and the dielectric layer 120 are coplanar, in accordance with some embodiments.
- FIGS. 2A-2C are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.
- the embodiment of FIGS. 2A-2C is similar to the embodiment of FIGS. 1A-M , except that the embodiment of FIGS. 2A-2C removes the mask layer 220 in the region 110 B firstly (as shown in FIG. 2B ) and then removes the mask layer 220 covers the bottom surfaces B 1 and B 2 (as shown in FIG. 2C ), in accordance with some embodiments.
- a photoresist layer 230 is formed over the mask layer 220 in the region 110 A, in accordance with some embodiments.
- the mask layer 220 in the region 110 B is removed, in accordance with some embodiments.
- the removal process includes an etching process using the photoresist layer 230 as an etch mask, in accordance with some embodiments.
- the photoresist layer 230 is removed, in accordance with some embodiments.
- the mask layer 220 covering the bottom surfaces B 1 and B 2 is removed to form trenches 222 and 224 in the mask layer 220 , in accordance with some embodiments.
- the trenches 222 and 224 respectively expose the bottom surfaces B 1 and B 2 , in accordance with some embodiments.
- the steps of FIGS. 1K-M are performed to form the conductive structures L 1 , L 2 , L 3 , and L 4 (as shown in FIG. 1M ), in accordance with some embodiments.
- FIGS. 3A-3H are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.
- a mask layer 310 is formed over the top surface 155 of the mask layer 150 and the inner walls N 1 , N 2 , N 3 , and N 4 of the trenches 151 , 152 , 153 , and 154 , in accordance with some embodiments.
- a thickness T 4 of the mask layer 310 over the inner walls N 1 , N 2 , N 3 , and N 4 increases in a direction V 1 away from the dielectric layer 120 .
- the mask layer 310 has trenches 312 , 314 , 316 , and 318 respectively in the trenches 151 , 152 , 153 , and 154 , in accordance with some embodiments.
- the trenches 312 , 314 , 316 , and 318 respectively expose the bottom surfaces B 1 , B 2 , B 3 , and B 4 of the trenches 151 , 152 , 153 , and 154 , in accordance with some embodiments.
- the mask layer 310 covering the top surface 155 is thicker than the mask layer 310 covering the inner walls N 1 , N 2 , N 3 , and N 4 of the trenches 151 , 152 , 153 , and 154 , in accordance with some embodiments. That is, a maximum thickness T 5 of the mask layer 310 covering the top surface 155 is greater than a maximum thickness T 4 ′ of the mask layer 310 over the inner walls N 1 , N 2 , N 3 , and N 4 , in accordance with some embodiments.
- the mask layer 310 is also referred to as an anti-bombardment layer, in accordance with some embodiments.
- the mask layer 310 is used to maintain the height of the mask layer 150 thereunder for a longer time during subsequent etching processes (e.g. dry etching processes) for forming trenches in the dielectric layer 120 , in accordance with some embodiments.
- the mask layer 310 is made of an anti-bombardment material, such as a nitride material (e.g., titanium nitride or tantalum nitride), in accordance with some embodiments.
- the mask layer 310 is formed using a CVD process or an ALD process, in accordance with some embodiments.
- the mask layer 310 is deposited at a first deposition pressure, in accordance with some embodiments.
- the mask layer 310 is deposited with a first deposition power, in accordance with some embodiments.
- a mask layer 220 is formed over the mask layer 310 and the hard mask layer 140 exposed by the trenches 151 , 152 , 153 , and 154 , in accordance with some embodiments.
- the mask layer 220 covers the inner walls N 1 , N 2 , N 3 , and N 4 and the bottom surfaces B 1 , B 2 , B 3 and B 4 of the trenches 151 , 152 , 153 , and 154 , in accordance with some embodiments.
- the mask layer 220 is also referred to as an anti-chemical etching protective layer, in accordance with some embodiments.
- the mask layer 220 is used to protect the inner walls N 1 , N 2 , N 3 , and N 4 during subsequent etching processes (e.g. dry etching processes) for forming trenches in the dielectric layer 120 , in accordance with some embodiments.
- the mask layer 220 is in direct contact with the mask layers 150 and 310 and the hard mask layer 140 , in accordance with some embodiments.
- a first thickness T 6 of the mask layer 220 over the top surface 155 is greater than a second thickness T 7 of the mask layer 220 over the inner walls N 1 , N 2 , N 3 , and N 4 .
- the second thickness T 7 is greater than a third thickness T 8 of the mask layer 220 over the bottom surfaces B 1 , B 2 , B 3 and B 4 , in accordance with some embodiments.
- the mask layers 220 and 310 are made of different materials, in accordance with some embodiments.
- the mask layer 220 is made of or includes an anti-chemical etching material, such as a nitride material (e.g, SiON, SiCN, SiN) or a low temperature oxide material (e.g., silicon dioxide), in accordance with some embodiments.
- the mask layer 220 is deposited using a CVD process, an ALD process, one or more other applicable processes, or a combination thereof.
- the mask layer 220 is deposited at a second deposition pressure, in accordance with some embodiments.
- the mask layer 220 is deposited with a second deposition power, in accordance with some embodiments. If the deposition pressure is high and the deposition power is low, the deposited layer tends to be deposited outside of the trenches. If the deposition pressure is low and the deposition power is large, the deposited layer tends to be deposited in the trenches. Therefore, the first deposition pressure is greater than the second deposition pressure, in accordance with some embodiments. The first deposition power is less than the second deposition power, in accordance with some embodiments.
- the mask layer 220 over the bottom surfaces B 1 , B 2 , B 3 and B 4 is removed, in accordance with some embodiments.
- the removal process forms trenches 222 , 224 , 226 , and 228 in the mask layer 220 , in accordance with some embodiments.
- the trenches 222 , 224 , 226 , and 228 are respectively positioned in the trenches 312 , 314 , 316 , and 318 , in accordance with some embodiments.
- the trenches 222 , 224 , 226 , and 228 respectively expose the bottom surfaces B 1 , B 2 , B 3 and B 4 , in accordance with some embodiments.
- the removal process includes an etching process, such a dry etching process or a wet etching process, in accordance with some embodiments.
- a photoresist layer 230 is formed over the mask layer 220 in the region 110 A, in accordance with some embodiments.
- the photoresist layer 230 is filled in the trenches 151 and 152 , in accordance with some embodiments.
- the mask layers 220 and 310 in the region 110 B are removed, in accordance with some embodiments.
- the removal process includes an etching process, such as a dry etching process, in accordance with some embodiments.
- the photoresist layer 230 is removed, in accordance with some embodiments.
- a distance D 1 between the trenches 222 and 224 is less than a distance D 2 between the trenches 153 and 154 .
- the mask layers 150 , 220 , and 310 are used as an etch mask in subsequent processes for forming conductive lines, in accordance with some embodiments.
- portions of the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 under the trenches 222 , 224 , 153 , and 154 are removed to form trenches R 1 , R 2 , R 3 , and R 4 in the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 , in accordance with some embodiments.
- the trenches R 1 , R 2 , R 3 , and R 4 pass through the hard mask layer 140 and the mask layer 130 and penetrate into the dielectric layer 120 , in accordance with some embodiments.
- the trenches R 1 , R 2 , R 3 , and R 4 respectively have widths W 7 , W 8 , W 9 , and W 10 , in accordance with some embodiments.
- the width W 7 or W 8 is less than the width W 9 or W 10 , in accordance with some embodiments.
- the removal process includes an etching process using the mask layers 150 , 220 , and 310 as an etch mask, in accordance with some embodiments.
- the mask layers 150 , 220 , and 310 may be consumed during the removal process. In some embodiments, an upper portion of the hard mask layer 140 is consumed during the removal process.
- the mask layer (or the anti-bombardment layer) 310 covers the top surface 155 of the mask layer 150 , the height of the mask layer 150 is maintained for a longer time during the removal process, as shown in FIGS. 3F and 3G , in accordance with some embodiments.
- the mask layer 220 is made of an anti-chemical etching material, the widths W 5 and W 6 of the trenches 222 and 224 of the mask layer 220 are maintained for a longer time during the removal process, as shown in FIGS. 3F and 3G , in accordance with some embodiments. Therefore, the formation of the mask layers 220 and 310 may improve the yield of the trenches R 1 and R 2 , as shown in FIGS. 3F and 3G .
- a barrier layer 240 is deposited over the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 , in accordance with some embodiments.
- the barrier layer 240 may prevent metal ions of a subsequently deposited conductive material (which will be described in more detail later) from diffusing into the dielectric layer 120 during thermal processes or cycles.
- the barrier layer 240 may also be referred to as a diffusion barrier layer.
- the barrier layer 240 is made of or includes a refractory metal material, such as tantalum (Ta), titanium (Ti), tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof.
- a refractory metal material such as tantalum (Ta), titanium (Ti), tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof.
- the barrier layer 240 is deposited using a PVD process, an ALD process, one or more other applicable processes, or a combination thereof.
- the barrier layer 240 is deposited conformally.
- a conductive material layer 250 is formed over the barrier layer 240 , in accordance with some embodiments.
- the trenches R 1 , R 2 , R 3 , and R 4 are filled with the conductive material layer 250 and the barrier layer 240 , in accordance with some embodiments.
- the conductive material layer 250 and the barrier layer 240 outside of the trenches R 1 , R 2 , R 3 , and R 4 , the hard mask layer 140 , and the mask layer 130 are removed, in accordance with some embodiments.
- the conductive material layer 250 and the barrier layer 240 remaining in the trenches R 1 , R 2 , R 3 , and R 4 forms conductive structures L 1 , L 2 , L 3 , and L 4 respectively in the trenches R 1 , R 2 , R 3 , and R 4 , in accordance with some embodiments.
- the conductive structures L 1 , L 2 , L 3 , and L 4 include conductive lines, in accordance with some embodiments.
- the conductive structures L 1 , L 2 , L 3 , and L 4 respectively have widths (or line widths) W 11 , W 12 , W 13 , and W 14 , in accordance with some embodiments. Since the width W 7 or W 8 is less than the width W 9 or W 10 (as shown in FIG. 3G ), the width W 11 or W 12 is less than the width W 13 or W 14 .
- the conductive structures L 1 and L 2 are positioned in the region 110 A, and the conductive structures L 3 and L 4 are positioned in the region 110 B, in accordance with some embodiments.
- the distance D 1 between the conductive structures L 1 and L 2 is less than the distance D 2 between the conductive structures L 3 and L 4 , in accordance with some embodiments.
- the removal process includes a planarization process, in accordance with some embodiments. Therefore, top surfaces S 1 , S 2 , S 3 , S 4 , and 122 of the conductive structures L 1 , L 2 , L 3 , and L 4 and the dielectric layer 120 are coplanar, in accordance with some embodiments.
- FIGS. 4A-4F are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.
- a mask layer 220 is conformally formed over the top surface 155 of the mask layer 150 , the inner walls N 1 , N 2 , N 3 , and N 4 , and the bottom surfaces B 1 , B 2 , B 3 , and B 4 of the trenches 151 , 152 , 153 , and 154 , in accordance with some embodiments.
- the mask layer 220 is made of or includes an anti-chemical etching material, such as a nitride material (e.g, SiON, SiCN, or SiN) or a low temperature oxide material (e.g., silicon dioxide), in accordance with some embodiments.
- an anti-chemical etching material such as a nitride material (e.g, SiON, SiCN, or SiN) or a low temperature oxide material (e.g., silicon dioxide), in accordance with some embodiments.
- the mask layer 220 over the bottom surfaces B 1 , B 2 , B 3 , and B 4 is removed, in accordance with some embodiments.
- the mask layer 220 has trenches 222 , 224 , 226 , and 228 , in accordance with some embodiments.
- a mask layer 310 is formed over the mask layer 220 , in accordance with some embodiments.
- the mask layer 310 covers a top surface 221 of the mask layer 220 and inner walls 222 a , 224 a , 226 a , and 228 a of the trenches 222 , 224 , 226 , and 228 , in accordance with some embodiments.
- a thickness T 4 of the mask layer 310 over the inner walls 222 a , 224 a , 226 a , and 228 a increases in a direction V 1 away from the dielectric layer 120 .
- the mask layer 310 is made of an anti-bombardment material, such as a nitride material (e.g., titanium nitride or tantalum nitride), in accordance with some embodiments.
- the mask layers 220 and 310 are made of different materials, in accordance with some embodiments.
- the mask layers 220 and 310 in the region 110 B are removed, in accordance with some embodiments.
- portions of the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 under the trenches 222 , 224 , 153 , and 154 are removed to form trenches R 1 , R 2 , R 3 , and R 4 in the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 , in accordance with some embodiments.
- the trenches R 1 , R 2 , R 3 , and R 4 pass through the hard mask layer 140 and the mask layer 130 and penetrate into the dielectric layer 120 , in accordance with some embodiments.
- the removal process includes an etching process using the mask layers 150 , 220 , and 310 as an etch mask, in accordance with some embodiments.
- the mask layers 150 , 220 , and 310 may be consumed during the removal process. In some embodiments, an upper portion of the hard mask layer 140 is consumed during the removal process.
- the mask layer (or the anti-bombardment layer) 310 covers the top surface 155 of the mask layer 150 , the height of the mask layer 150 is maintained for a longer time during the removal process, as shown in FIGS. 4D and 4E , in accordance with some embodiments.
- the mask layer 220 is made of an anti-chemical etching material, the widths W 5 and W 6 of the trenches 222 and 224 of the mask layer 220 are maintained for a longer time during the removal process, as shown in FIGS. 4D and 4E , in accordance with some embodiments. Therefore, the formation of the mask layers 220 and 310 may improve the yield of the trenches R 1 and R 2 , as shown in FIGS. 4D and 4E .
- a barrier layer 240 is deposited over the hard mask layer 140 , the mask layer 130 , and the dielectric layer 120 , in accordance with some embodiments.
- a conductive material layer 250 is formed over the barrier layer 240 , in accordance with some embodiments.
- the conductive material layer 250 and the barrier layer 240 outside of the trenches R 1 , R 2 , R 3 , and R 4 , the hard mask layer 140 , and the mask layer 130 are removed, in accordance with some embodiments.
- the conductive material layer 250 and the barrier layer 240 remaining in the trenches R 1 , R 2 , R 3 , and R 4 forms conductive structures L 1 , L 2 , L 3 , and L 4 respectively in the trenches R 1 , R 2 , R 3 , and R 4 , in accordance with some embodiments.
- the conductive structures L 1 , L 2 , L 3 , and L 4 include conductive lines, in accordance with some embodiments.
- the conductive structures L 1 , L 2 , L 3 , and L 4 respectively have widths (or line widths) W 11 , W 12 , W 13 , and W 14 , in accordance with some embodiments.
- the width W 11 or W 12 is less than the width W 13 or W 14 , in accordance with some embodiments.
- the distance D 1 between the conductive structures L 1 and L 2 is less than the distance D 2 between the conductive structures L 3 and L 4 , in accordance with some embodiments.
- the removal process includes a planarization process, in accordance with some embodiments. Therefore, top surfaces S, S 2 , S 3 , S 4 , and 122 of the conductive structures L 1 , L 2 , L 3 , and L 4 and the dielectric layer 120 are coplanar, in accordance with some embodiments.
- methods for forming semiconductor device structures include: forming a first mask layer over a dielectric layer; conformally forming a second mask layer over an inner wall of a first trench of the first mask layer; and removing the dielectric layer through the first trench to form a second trench in the dielectric layer.
- the formation of the second mask layer over the inner wall is able to narrow the second trench.
- a method for forming a semiconductor device structure includes forming a first mask layer over a dielectric layer.
- the first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface.
- the method includes forming an anti-bombardment layer over a first top surface of the first mask layer.
- the method includes forming a second mask layer over the first inner wall of the first trench.
- the second mask layer has a second trench, the second trench exposes the bottom surface and is over a first portion of the dielectric layer, and the second mask layer and the anti-bombardment layer are made of different materials.
- the method includes removing the first portion, the first mask layer, the anti-bombardment layer, and the second mask layer to form a third trench in the dielectric layer.
- the method includes forming a conductive structure in the third trench.
- a method for forming a semiconductor device structure includes forming a first mask layer over a dielectric layer.
- the first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface.
- the method includes forming an anti-bombardment layer over a top surface of the first mask layer and the first inner wall of the first trench.
- the anti-bombardment layer over the top surface is thicker than the anti-bombardment layer over the first inner wall.
- the method includes forming a second mask layer over the anti-bombardment layer over the first inner wall.
- the method includes partially removing the dielectric layer through the first trench to form a second trench in the dielectric layer.
- the method includes forming a conductive structure in the second trench.
- a method for forming a semiconductor device structure includes forming a first mask layer over a dielectric layer.
- the method includes forming a second mask layer over the first mask layer.
- the second mask layer has a first trench, and the first trench has a first inner wall and a bottom surface.
- the method includes forming a third mask layer over the first inner wall.
- the third mask layer has a second trench over a first portion of the first mask layer and a second portion of the dielectric layer.
- the method includes removing the first portion of the first mask layer, the second portion of the dielectric layer, the second mask layer, and the third mask layer to form a third trench in the dielectric layer.
- the method includes forming a conductive structure in the third trench.
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Abstract
A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface. The method includes forming an anti-bombardment layer over a first top surface of the first mask layer. The method includes forming a second mask layer over the first inner wall of the first trench. The method includes removing the first portion, the first mask layer, the anti-bombardment layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.
Description
- This application is a Continuation of U.S. application Ser. No. 16/715,215, filed on Dec. 16, 2019, which is a Divisional of U.S. application Ser. No. 15/884,760, filed on Jan. 31, 2018, which claims the benefit of U.S. Provisional Application No. 62/583,121, filed on Nov. 8, 2017, the entirety of which is incorporated by reference herein.
- The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs.
- In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs.
- However, since feature sizes (e.g., line widths) continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIGS. 1A-1M are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. -
FIGS. 2A-2C are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. -
FIGS. 3A-3H are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. -
FIGS. 4A-4F are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.
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FIGS. 1A -IM are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown inFIG. 1A , asemiconductor substrate 110 is provided. In some embodiments, thesemiconductor substrate 110 is a bulk semiconductor substrate, such as a semiconductor wafer. For example, thesemiconductor substrate 110 is a silicon wafer. - The
semiconductor substrate 110 may include silicon or another elementary semiconductor material such as germanium. In some other embodiments, thesemiconductor substrate 110 includes a compound semiconductor. The compound semiconductor may include silicon germanium, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable compound semiconductor, or a combination thereof. - In some embodiments, the
semiconductor substrate 110 includes a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a wafer bonding process, a silicon film transfer process, a separation by implantation of oxygen (SIMOX) process, another applicable method, or a combination thereof. - In some embodiments, various device elements are formed in and/or over the
semiconductor substrate 110. The device elements are not shown in figures for the purpose of simplicity and clarity. Examples of the various device elements include transistors, diodes, another suitable element, or a combination thereof. - For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc. Various processes, such as front-end-of-line (FEOL) semiconductor fabrication processes, are performed to form the various device elements. The FEOL semiconductor fabrication processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or a combination thereof.
- In some embodiments, isolation features (not shown) are formed in the
semiconductor substrate 110. The isolation features are used to define active regions and electrically isolate various device elements formed in and/or over thesemiconductor substrate 110 in the active regions. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof. - In some embodiments, an interconnection structure (not shown) is formed over the
semiconductor substrate 110 inregions regions - The interconnection structure includes multiple dielectric layers containing an interlayer dielectric (ILD) layer and one or more inter-metal dielectric (IMD) layers. The interconnection structure also includes multiple conductive features formed in the ILD and IMD layers. The conductive features may include conductive lines, conductive vias, and/or conductive contacts. Various processes, such as back-end-of-line (BEOL) semiconductor fabrication processes, are performed to form the interconnection structure.
- Various device elements are interconnected through the interconnection structure over the
semiconductor substrate 110 to form integrated circuit devices. The integrated circuit devices include logic devices, memory devices (e.g., static random access memories, SRAMs), radio frequency (RF) devices, input/output (I/O) devices, system-on-chip (SoC) devices, image sensor devices, other applicable types of devices, or a combination thereof. - As shown in
FIG. 1A , adielectric layer 120 is deposited over thesemiconductor substrate 110 in theregions dielectric layer 120 may serve as an ILD or IMD layer of an interconnection structure. Thedielectric layer 120 covers device elements formed in and/or over thesemiconductor substrate 110. AlthoughFIG. 1A shows that thedielectric layer 120 is a single layer, embodiments of the disclosure are not limited thereto. In some other embodiments, thedielectric layer 120 is a multi-layer structure including dielectric sub-layers (not shown). - In some embodiments, the
dielectric layer 120 is made of or includes an insulating material, such as silicon oxide, silicon oxynitride, a low dielectric constant (low-k) material, an extreme low-k (ELK) material, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), one or more other suitable materials, or a combination thereof. In some embodiments, thedielectric layer 120 is deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a spin-on process, a spray coating process, one or more other applicable processes, or a combination thereof. - The low-k or ELK material may have a smaller dielectric constant than that of silicon dioxide. For example, the low-k material may have a dielectric constant in a range from about 1.5 to about 3.5. The ELK material may have a dielectric constant, which is less than about 2.5 or in a range from about 1.5 to about 2.5. As the density of semiconductor devices increases and the size of circuit elements becomes smaller, the resistance capacitance (RC) delay time increasingly dominates circuit performance. Therefore, using a low-k or ELK material as the
dielectric layer 120 is helpful in reducing the RC delay. - A wide variety of low-k or ELK material may be used for forming the
dielectric layer 120. In some embodiments, thedielectric layer 120 is made of or includes a porous dielectric material, an organic polymer, an organic silica glass, SiOF series material, a hydrogen silsesquioxane (HSQ) series material, a methyl silsesquioxane (MSQ) series material, carbon doped silicon oxide, amorphous fluorinated carbon, parylene, benzocyclobutenes (BCB), polytetrafluoroethylene (PTFE) (Teflon), silicon oxycarbide polymers (SiOC), a porous organic series material, a spin-on inorganic dielectric, a spin-on organic dielectric material, one or more other suitable materials, or a combination thereof. - Multiple conductive features (not shown) are formed in the
dielectric layer 120 in theregions semiconductor substrate 110 or doped regions formed in thesemiconductor substrate 110. The conductive features in theregion 110A may be electrically connected to the gate structures and the doped regions, and the conductive features in theregion 110B may be electrically connected to the power devices. - The conductive features may include conductive lines, conductive vias, conductive contacts, or a combination thereof. In some embodiments, the conductive features are made of or include a conductive material, such as a metal material (e.g., copper, aluminum, tungsten, titanium, cobalt, nickel, gold, platinum, or a combination thereof). Various processes, including deposition, etching, planarization, or the like, may be used to form the conductive features in the
dielectric layer 120. - As shown in
FIG. 1A , amask layer 130 is deposited over thedielectric layer 120, in accordance with some embodiments. Themask layer 130 is also referred to as an anti-reflective coating (ARC) layer, in accordance with some embodiments. Themask layer 130 may absorb light thereby minimizing reflection during a subsequent photolithography process so as to enhance the resolution of the photolithography process. In some embodiments, themask layer 130 is made of or includes an anti-reflective material, such as SiON, SiCN, SiN, HfO, Al2O3, Ta2O5, ZrO, one or more other suitable materials, or a combination thereof. - In some embodiments, the
mask layer 130 is a nitrogen-free anti-reflective coating (NFARC) layer. By keeping an interface between thedielectric layer 120 and themask layer 130 nitrogen free, little or no nitrogen diffuses into thedielectric layer 120 so as to prevent contamination. Themask layer 130 is deposited using a spray coating process, a spin-on process, a CVD process, an ALD process, one or more other applicable processes, or a combination thereof. - As shown in
FIG. 1A , ahard mask layer 140 is deposited over themask layer 130. Thehard mask layer 140 is made of or includes titanium nitride (TiN), SiON, one or more other suitable materials, or a combination thereof. In some other embodiments, thehard mask layer 140 is a multi-layer structure, such as oxide-nitride-oxide (ONO) layers. Thehard mask layer 140 is deposited using a PVD process (such as a radio-frequency PVD (RFPVD) process), a CVD process, an ALD process, one or more other applicable processes, or a combination thereof. - As shown in
FIG. 1A , amask layer 150 is deposited over thehard mask layer 140, in accordance with some embodiments. Themask layer 150 is also referred to as an anti-reflective coating (ARC) layer, in accordance with some embodiments. Themask layer 150 is made of or includes an anti-reflective material, such as SiON, SiCN, SiN, HfO, Al2O3, Ta2O5, ZrO, one or more other suitable materials, or a combination thereof. - In some embodiments, the
mask layer 150 and themask layer 130 are made of or include the same material. In some embodiments, thedielectric layer 120 and themask layer 150 are made of different materials. In some embodiments, thehard mask layer 140 and themask layer 150 are made of different materials. - In some embodiments, the
mask layer 150 is a nitrogen-free anti-reflective coating (NFARC) layer. Themask layer 150 is deposited using a spray coating process, a spin-on process, a CVD process, an ALD process, one or more other applicable processes, or a combination thereof. - Afterwards, as shown in
FIG. 1B , a patterned mask structure M1 is formed over themask layer 150, in accordance with some embodiments. The patterned mask structure M1 is a multi-layer mask structure, in accordance with some embodiments. The patterned mask structure M1 includes alower layer 160, amiddle layer 170 and anupper layer 180, in accordance with some embodiments. - As shown in
FIG. 1B , thelower layer 160, themiddle layer 170 and theupper layer 180 are sequentially deposited over themask layer 150, in accordance with some embodiments. In some embodiments, thelower layer 160 is made of or includes a polymer material. In some embodiments, themiddle layer 170 is made of or includes a silicon-containing material, such as a silicon-containing polymer material. In some embodiments, theupper layer 180 is made of or includes a photoresist material. In some embodiments, thelower layer 160, themiddle layer 170 and theupper layer 180 are deposited using a PVD process, a CVD process, a spin-on process, another applicable process, or a combination thereof. - The
upper layer 180 is patterned to formtrenches 182 in theupper layer 180, in accordance with some embodiments. Thetrenches 182 partially expose themiddle layer 170. Theupper layer 180 is patterned by a photolithography process. Afterwards, themiddle layer 170 is patterned or etched using the patternedupper layer 180 as an etch mask. As a result, thetrenches 182 are transferred into the middle layer 170 (not shown). - The patterned
upper layer 180 may be removed during the patterning of themiddle layer 170. Similarly, thelower layer 160 is then patterned or etched using the patternedmiddle layer 170 as an etch mask. As a result, thetrenches 182 are transferred into the lower layer 160 (not shown). The patternedmiddle layer 170 may be removed during the patterning of thelower layer 160. - The patterned
lower layer 160 is subsequently used as an etch mask to pattern themask layer 150. As shown inFIG. 1C , themask layer 150 is patterned or etched using the patternedlower layer 160 as an etch mask, in accordance with some embodiments. As a result,trenches mask layer 150, in accordance with some embodiments. Thetrenches mask layer 150, in accordance with some embodiments. Thetrenches hard mask layer 140 thereunder, in accordance with some embodiments. The patternedlower layer 160 may be removed during the patterning of themask layer 150. - In some embodiments, the
middle layer 170, thelower layer 160, and themask layer 150 are sequentially patterned using one or more etching processes. The etching process may be a dry etching process, one or more other applicable processes, or a combination thereof. - Afterwards, as shown in
FIG. 1D , a patterned mask structure M2 is formed over themask layer 150, in accordance with some embodiments. The patterned mask structure M2 is a multi-layer mask structure, in accordance with some embodiments. The patterned mask structure M2 includes alower layer 190, amiddle layer 200, and anupper layer 210, in accordance with some embodiments. - As shown in
FIG. 1D , thelower layer 190, themiddle layer 200, and theupper layer 210 are sequentially deposited over themask layer 150, in accordance with some embodiments. In some embodiments, thelower layer 190 is made of or includes a polymer material. In some embodiments, themiddle layer 200 is made of or includes a silicon-containing material, such as a silicon-containing polymer material. In some embodiments, theupper layer 210 is made of or includes a photoresist material. In some embodiments, thelower layer 190, themiddle layer 200 and theupper layer 210 are deposited using a PVD process, a CVD process, a spin-on process, another applicable process, or a combination thereof. - The
upper layer 210 is patterned to formtrenches 212 in theupper layer 210, in accordance with some embodiments. Thetrenches 212 partially expose themiddle layer 200. Theupper layer 210 is patterned by a photolithography process. - Afterwards, the
middle layer 200 is patterned or etched using the patternedupper layer 210 as an etch mask. As a result, thetrenches 212 are transferred into the middle layer 200 (not shown). The patternedupper layer 210 may be removed during the patterning of themiddle layer 200. Similarly, thelower layer 190 is then patterned or etched using the patternedmiddle layer 200 as an etch mask. As a result, thetrenches 212 are transferred into the lower layer 190 (not shown). The patternedmiddle layer 200 may be removed during the patterning of thelower layer 190. - The patterned
lower layer 190 is subsequently used as an etch mask to pattern themask layer 150. As shown inFIG. 1E , themask layer 150 is patterned and etched using the patternedlower layer 190 as an etch mask. As a result,trenches mask layer 150. Thetrenches mask layer 150. Thetrenches hard mask layer 140 thereunder, in accordance with some embodiments. The patternedlower layer 190 may be removed during the patterning of themask layer 150. - In some embodiments, the
middle layer 200, thelower layer 190 and themask layer 150 are sequentially patterned using one or more etching processes. The etching process may be a dry etching process, one or more other applicable processes, or a combination thereof. - Afterwards, as shown in
FIG. 1E , thetrenches - For example, the term “substantially equal to” means the difference between the widths W1, W2, W3 and W4 is within 10% of the average width of the
trenches trenches - Thereafter, as shown in
FIG. 1F , amask layer 220 is deposited over themask layer 150 and in thetrenches mask layer 220 conformally covers atop surface 155 of themask layer 150, the inner walls N1, N2, N3, and N4, and the bottom surfaces B1, B2, B3 and B4, in accordance with some embodiments. Themask layer 220 is in direct contact with the mask layers 140 and 150, in accordance with some embodiments. - In some embodiments, a first thickness T1 of the
mask layer 220 over thetop surface 155 is greater than a second thickness T2 of themask layer 220 over the inner walls N1, N2, N3, and N4. The second thickness T2 is greater than a third thickness T3 of themask layer 220 over the bottom surfaces B1, B2, B3 and B4, in accordance with some embodiments. - The
mask layer 220 is also referred to as an anti-reflective coating (ARC) layer, in accordance with some embodiments. Themask layer 220 is made of or includes an anti-reflective material, such as SiON, SiCN, SiN, HfO, Al2O3, Ta2O5, ZrO, one or more other suitable materials, or a combination thereof. - In some embodiments, the
mask layer 220 and themask layer 150 are made of or include the same material. In some embodiments, themask layer 220 is a nitrogen-free anti-reflective coating (NFARC) layer. Themask layer 220 is deposited using a CVD process, an ALD process, one or more other applicable processes, or a combination thereof. - As shown in
FIG. 1G , themask layer 220 covering the bottom surfaces B1, B2, B3, and B4 is removed to formtrenches mask layer 220, in accordance with some embodiments. Thetrenches - The
trenches mask layer 220 covers the inner walls N1, N2, N3, and N4 and thetop surface 155, in accordance with some embodiments. The removal process includes a dry etching process (e.g., an anisotropic etching process) or a wet etching process, in accordance with some embodiments. The dry etching process includes a plasma etching process, in accordance with some embodiments. - As shown in
FIG. 1H , aphotoresist layer 230 is formed over themask layer 220 in theregion 110A, in accordance with some embodiments. Thephotoresist layer 230 is filled in thetrenches FIG. 1I , themask layer 220 in theregion 110B is removed, in accordance with some embodiments. The removal process includes an etching process, such as a dry etching process, in accordance with some embodiments. - As shown in
FIG. 1J , thephotoresist layer 230 is removed, in accordance with some embodiments. Themask layer 220 has asidewall 229 aligned with the boundary between theregions mask layer 220 over the inner wall N1 to the width W1 of thetrench 151 ranges from about 0.16 to about 0.4. In some embodiments, a ratio of the width W5 of thetrench 222 to the width W1 of thetrench 151 ranges from about 0.16 to about 0.66. In some embodiments, a distance D1 between thetrenches trenches - The mask layers 150 and 220 are used as an etch mask in subsequent processes for forming conductive lines, in accordance with some embodiments. Although the widths W1, W2, W3, and W4 of the
trenches mask layer 220 formed over the inner walls N1 and N2 of thetrenches trenches trenches mask layer 220 may narrow the subsequently formed conductive lines by using themask layer 220 as an etch mask. - As shown in
FIG. 1K , portions of thehard mask layer 140, themask layer 130, and thedielectric layer 120 under thetrenches hard mask layer 140, themask layer 130, and thedielectric layer 120, in accordance with some embodiments. - The trenches R1, R2, R3, and R4 pass through the
hard mask layer 140 and themask layer 130 and penetrate into thedielectric layer 120, in accordance with some embodiments. The trenches R1, R2, R3, and R4 respectively have widths W7, W8, W9, and W10, in accordance with some embodiments. The width W7 or W8 is less than the width W9 or W10, in accordance with some embodiments. - The removal process includes an etching process using the mask layers 150 and 220 as an etch mask, in accordance with some embodiments. The mask layers 150 and 220 may be consumed during the removal process. In some embodiments, an upper portion of the
hard mask layer 140 is consumed during the removal process. - Since the
mask layer 220 covers thehard mask layer 140 in theregion 110A during the removal process, thehard mask layer 140 remaining in theregion 110A is thicker than thehard mask layer 140 remaining in theregion 110B. That is, a thickness T9 of thehard mask layer 140 in theregion 110A is greater than a thickness T10 of thehard mask layer 140 in theregion 110B, in accordance with some embodiments. In some embodiments, thehard mask layer 140 remaining in theregion 110A is also referred to as a thick portion, and thehard mask layer 140 remaining in theregion 110B is also referred to as a thin portion. In some embodiments, the boundary between the thick portion and the thin portion is substantially aligned with thesidewall 229 of the mask layer 220 (as shown inFIG. 1J ). - As shown in
FIG. 1L , abarrier layer 240 is deposited over thehard mask layer 140, themask layer 130, and thedielectric layer 120, in accordance with some embodiments. Thebarrier layer 240 may prevent metal ions of a subsequently deposited conductive material (which will be described in more detail later) from diffusing into thedielectric layer 120 during thermal processes or cycles. Thebarrier layer 240 may also be referred to as a diffusion barrier layer. - In some embodiments, the
barrier layer 240 is made of or includes a refractory metal material, such as tantalum (Ta), titanium (Ti), tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof. In some embodiments, thebarrier layer 240 is deposited using a PVD process, an ALD process, one or more other applicable processes, or a combination thereof. In some embodiments, thebarrier layer 240 is deposited conformally. - As shown in
FIG. 1L , aconductive material layer 250 is formed over thebarrier layer 240, in accordance with some embodiments. The trenches R1, R2, R3, and R4 are filled with theconductive material layer 250 and thebarrier layer 240, in accordance with some embodiments. In some embodiments, theconductive material layer 250 is made of or includes a metal material, such as copper, aluminum, tungsten, titanium, nickel, gold, platinum, silver, one or more other suitable materials, or a combination thereof. - The
conductive material layer 250 may be a single layer or have multiple stacked layers. Theconductive material layer 250 is deposited using an electroplating process, a PVD process, a CVD process, an electroless plating process, another applicable process, or a combination thereof. - As shown in
FIG. 1M , theconductive material layer 250 and thebarrier layer 240 outside of the trenches R1, R2, R3, and R4, thehard mask layer 140, and themask layer 130 are removed, in accordance with some embodiments. Theconductive material layer 250 and thebarrier layer 240 remaining in the trenches R1, R2, R3, and R4 forms conductive structures L1, L2, L3, and L4 respectively in the trenches R1, R2, R3, and R4, in accordance with some embodiments. - The conductive structures L, L2, L3, and L4 include conductive lines, in accordance with some embodiments. The conductive structures L1, L2, L3, and L4 respectively have widths (or line widths) W11, W12, W13, and W14 in accordance with some embodiments. Since the width W7 or W8 is less than the width W9 or W10 (as shown in
FIG. 1K ), the width W11 or W12 is less than the width W13 or W14. The widths W11 and W12 are substantially equal to each other, in accordance with some embodiments. The widths W13 and W14 are substantially equal to each other, in accordance with some embodiments. - The conductive structures L1 and L2 are positioned in the
region 110A, and the conductive structures L3 and L4 are positioned in theregion 110B, in accordance with some embodiments. The distance D1 between the conductive structures L1 and L2 is less than the distance D2 between the conductive structures L3 and L4, in accordance with some embodiments. - The
regions region 110A is equal to a sum of the width W11 (or W12) and the distance D1, in accordance with some embodiments. The pitch of theregion 110B is equal to a sum of the width W13 (or W14) and the distance D2, in accordance with some embodiments. Since the width W11 (or W12) is less than the W13 (or W14) and the distance D1 is less than the distance D2, the pitch of theregion 110A is less than the pitch of theregion 110B. - The removal process includes a planarization process, in accordance with some embodiments. Therefore, top surfaces S1, S2, S3, S4, and 122 of the conductive structures L1, L2, L3, and L4 and the
dielectric layer 120 are coplanar, in accordance with some embodiments. -
FIGS. 2A-2C are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. The embodiment ofFIGS. 2A-2C is similar to the embodiment ofFIGS. 1A-M , except that the embodiment ofFIGS. 2A-2C removes themask layer 220 in theregion 110B firstly (as shown inFIG. 2B ) and then removes themask layer 220 covers the bottom surfaces B1 and B2 (as shown inFIG. 2C ), in accordance with some embodiments. - After the step of
FIG. 1F , as shown inFIG. 2A , aphotoresist layer 230 is formed over themask layer 220 in theregion 110A, in accordance with some embodiments. Afterwards, as shown inFIG. 2B , themask layer 220 in theregion 110B is removed, in accordance with some embodiments. The removal process includes an etching process using thephotoresist layer 230 as an etch mask, in accordance with some embodiments. - As shown in
FIG. 2C , thephotoresist layer 230 is removed, in accordance with some embodiments. As shown inFIG. 2C , themask layer 220 covering the bottom surfaces B1 and B2 is removed to formtrenches mask layer 220, in accordance with some embodiments. Thetrenches FIGS. 1K-M are performed to form the conductive structures L1, L2, L3, and L4 (as shown inFIG. 1M ), in accordance with some embodiments. -
FIGS. 3A-3H are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. After the step ofFIG. 1E , as shown inFIG. 3A , amask layer 310 is formed over thetop surface 155 of themask layer 150 and the inner walls N1, N2, N3, and N4 of thetrenches - In some embodiments, a thickness T4 of the
mask layer 310 over the inner walls N1, N2, N3, and N4 increases in a direction V1 away from thedielectric layer 120. Themask layer 310 has trenches 312, 314, 316, and 318 respectively in thetrenches trenches - The
mask layer 310 covering thetop surface 155 is thicker than themask layer 310 covering the inner walls N1, N2, N3, and N4 of thetrenches mask layer 310 covering thetop surface 155 is greater than a maximum thickness T4′ of themask layer 310 over the inner walls N1, N2, N3, and N4, in accordance with some embodiments. - The
mask layer 310 is also referred to as an anti-bombardment layer, in accordance with some embodiments. Themask layer 310 is used to maintain the height of themask layer 150 thereunder for a longer time during subsequent etching processes (e.g. dry etching processes) for forming trenches in thedielectric layer 120, in accordance with some embodiments. - The
mask layer 310 is made of an anti-bombardment material, such as a nitride material (e.g., titanium nitride or tantalum nitride), in accordance with some embodiments. Themask layer 310 is formed using a CVD process or an ALD process, in accordance with some embodiments. Themask layer 310 is deposited at a first deposition pressure, in accordance with some embodiments. Themask layer 310 is deposited with a first deposition power, in accordance with some embodiments. - As shown in
FIG. 3B , amask layer 220 is formed over themask layer 310 and thehard mask layer 140 exposed by thetrenches mask layer 220 covers the inner walls N1, N2, N3, and N4 and the bottom surfaces B1, B2, B3 and B4 of thetrenches - The
mask layer 220 is also referred to as an anti-chemical etching protective layer, in accordance with some embodiments. Themask layer 220 is used to protect the inner walls N1, N2, N3, and N4 during subsequent etching processes (e.g. dry etching processes) for forming trenches in thedielectric layer 120, in accordance with some embodiments. Themask layer 220 is in direct contact with the mask layers 150 and 310 and thehard mask layer 140, in accordance with some embodiments. - In some embodiments, a first thickness T6 of the
mask layer 220 over thetop surface 155 is greater than a second thickness T7 of themask layer 220 over the inner walls N1, N2, N3, and N4. The second thickness T7 is greater than a third thickness T8 of themask layer 220 over the bottom surfaces B1, B2, B3 and B4, in accordance with some embodiments. - The mask layers 220 and 310 are made of different materials, in accordance with some embodiments. The
mask layer 220 is made of or includes an anti-chemical etching material, such as a nitride material (e.g, SiON, SiCN, SiN) or a low temperature oxide material (e.g., silicon dioxide), in accordance with some embodiments. Themask layer 220 is deposited using a CVD process, an ALD process, one or more other applicable processes, or a combination thereof. - The
mask layer 220 is deposited at a second deposition pressure, in accordance with some embodiments. Themask layer 220 is deposited with a second deposition power, in accordance with some embodiments. If the deposition pressure is high and the deposition power is low, the deposited layer tends to be deposited outside of the trenches. If the deposition pressure is low and the deposition power is large, the deposited layer tends to be deposited in the trenches. Therefore, the first deposition pressure is greater than the second deposition pressure, in accordance with some embodiments. The first deposition power is less than the second deposition power, in accordance with some embodiments. - As shown in
FIG. 3C , themask layer 220 over the bottom surfaces B1, B2, B3 and B4 is removed, in accordance with some embodiments. The removal process formstrenches mask layer 220, in accordance with some embodiments. Thetrenches trenches - As shown in
FIG. 3D , aphotoresist layer 230 is formed over themask layer 220 in theregion 110A, in accordance with some embodiments. Thephotoresist layer 230 is filled in thetrenches FIG. 3E , the mask layers 220 and 310 in theregion 110B are removed, in accordance with some embodiments. The removal process includes an etching process, such as a dry etching process, in accordance with some embodiments. - As shown in
FIG. 3F , thephotoresist layer 230 is removed, in accordance with some embodiments. In some embodiments, a distance D1 between thetrenches trenches - As shown in
FIG. 3G , portions of thehard mask layer 140, themask layer 130, and thedielectric layer 120 under thetrenches hard mask layer 140, themask layer 130, and thedielectric layer 120, in accordance with some embodiments. - The trenches R1, R2, R3, and R4 pass through the
hard mask layer 140 and themask layer 130 and penetrate into thedielectric layer 120, in accordance with some embodiments. The trenches R1, R2, R3, and R4 respectively have widths W7, W8, W9, and W10, in accordance with some embodiments. The width W7 or W8 is less than the width W9 or W10, in accordance with some embodiments. - The removal process includes an etching process using the mask layers 150, 220, and 310 as an etch mask, in accordance with some embodiments. The mask layers 150, 220, and 310 may be consumed during the removal process. In some embodiments, an upper portion of the
hard mask layer 140 is consumed during the removal process. - Since the mask layer (or the anti-bombardment layer) 310 covers the
top surface 155 of themask layer 150, the height of themask layer 150 is maintained for a longer time during the removal process, as shown inFIGS. 3F and 3G , in accordance with some embodiments. Since themask layer 220 is made of an anti-chemical etching material, the widths W5 and W6 of thetrenches mask layer 220 are maintained for a longer time during the removal process, as shown inFIGS. 3F and 3G , in accordance with some embodiments. Therefore, the formation of the mask layers 220 and 310 may improve the yield of the trenches R1 and R2, as shown inFIGS. 3F and 3G . - As shown in
FIG. 3G , abarrier layer 240 is deposited over thehard mask layer 140, themask layer 130, and thedielectric layer 120, in accordance with some embodiments. Thebarrier layer 240 may prevent metal ions of a subsequently deposited conductive material (which will be described in more detail later) from diffusing into thedielectric layer 120 during thermal processes or cycles. Thebarrier layer 240 may also be referred to as a diffusion barrier layer. - In some embodiments, the
barrier layer 240 is made of or includes a refractory metal material, such as tantalum (Ta), titanium (Ti), tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof. In some embodiments, thebarrier layer 240 is deposited using a PVD process, an ALD process, one or more other applicable processes, or a combination thereof. In some embodiments, thebarrier layer 240 is deposited conformally. - As shown in
FIG. 3G , aconductive material layer 250 is formed over thebarrier layer 240, in accordance with some embodiments. The trenches R1, R2, R3, and R4 are filled with theconductive material layer 250 and thebarrier layer 240, in accordance with some embodiments. - As shown in
FIG. 3H , theconductive material layer 250 and thebarrier layer 240 outside of the trenches R1, R2, R3, and R4, thehard mask layer 140, and themask layer 130 are removed, in accordance with some embodiments. Theconductive material layer 250 and thebarrier layer 240 remaining in the trenches R1, R2, R3, and R4 forms conductive structures L1, L2, L3, and L4 respectively in the trenches R1, R2, R3, and R4, in accordance with some embodiments. - The conductive structures L1, L2, L3, and L4 include conductive lines, in accordance with some embodiments. The conductive structures L1, L2, L3, and L4 respectively have widths (or line widths) W11, W12, W13, and W14, in accordance with some embodiments. Since the width W7 or W8 is less than the width W9 or W10 (as shown in
FIG. 3G ), the width W11 or W12 is less than the width W13 or W14. - The conductive structures L1 and L2 are positioned in the
region 110A, and the conductive structures L3 and L4 are positioned in theregion 110B, in accordance with some embodiments. The distance D1 between the conductive structures L1 and L2 is less than the distance D2 between the conductive structures L3 and L4, in accordance with some embodiments. - The removal process includes a planarization process, in accordance with some embodiments. Therefore, top surfaces S1, S2, S3, S4, and 122 of the conductive structures L1, L2, L3, and L4 and the
dielectric layer 120 are coplanar, in accordance with some embodiments. -
FIGS. 4A-4F are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. After the step ofFIG. 1E , as shown inFIG. 4A , amask layer 220 is conformally formed over thetop surface 155 of themask layer 150, the inner walls N1, N2, N3, and N4, and the bottom surfaces B1, B2, B3, and B4 of thetrenches mask layer 220 is made of or includes an anti-chemical etching material, such as a nitride material (e.g, SiON, SiCN, or SiN) or a low temperature oxide material (e.g., silicon dioxide), in accordance with some embodiments. - As shown in
FIG. 4B , themask layer 220 over the bottom surfaces B1, B2, B3, and B4 is removed, in accordance with some embodiments. Themask layer 220 hastrenches FIG. 4C , amask layer 310 is formed over themask layer 220, in accordance with some embodiments. - The
mask layer 310 covers atop surface 221 of themask layer 220 andinner walls trenches mask layer 310 over theinner walls dielectric layer 120. Themask layer 310 is made of an anti-bombardment material, such as a nitride material (e.g., titanium nitride or tantalum nitride), in accordance with some embodiments. The mask layers 220 and 310 are made of different materials, in accordance with some embodiments. - As shown in
FIG. 4D , the mask layers 220 and 310 in theregion 110B are removed, in accordance with some embodiments. As shown inFIG. 4E , portions of thehard mask layer 140, themask layer 130, and thedielectric layer 120 under thetrenches hard mask layer 140, themask layer 130, and thedielectric layer 120, in accordance with some embodiments. - The trenches R1, R2, R3, and R4 pass through the
hard mask layer 140 and themask layer 130 and penetrate into thedielectric layer 120, in accordance with some embodiments. The removal process includes an etching process using the mask layers 150, 220, and 310 as an etch mask, in accordance with some embodiments. The mask layers 150, 220, and 310 may be consumed during the removal process. In some embodiments, an upper portion of thehard mask layer 140 is consumed during the removal process. - Since the mask layer (or the anti-bombardment layer) 310 covers the
top surface 155 of themask layer 150, the height of themask layer 150 is maintained for a longer time during the removal process, as shown inFIGS. 4D and 4E , in accordance with some embodiments. Since themask layer 220 is made of an anti-chemical etching material, the widths W5 and W6 of thetrenches mask layer 220 are maintained for a longer time during the removal process, as shown inFIGS. 4D and 4E , in accordance with some embodiments. Therefore, the formation of the mask layers 220 and 310 may improve the yield of the trenches R1 and R2, as shown inFIGS. 4D and 4E . - As shown in
FIG. 4E , abarrier layer 240 is deposited over thehard mask layer 140, themask layer 130, and thedielectric layer 120, in accordance with some embodiments. As shown inFIG. 4E , aconductive material layer 250 is formed over thebarrier layer 240, in accordance with some embodiments. - As shown in
FIG. 4F , theconductive material layer 250 and thebarrier layer 240 outside of the trenches R1, R2, R3, and R4, thehard mask layer 140, and themask layer 130 are removed, in accordance with some embodiments. Theconductive material layer 250 and thebarrier layer 240 remaining in the trenches R1, R2, R3, and R4 forms conductive structures L1, L2, L3, and L4 respectively in the trenches R1, R2, R3, and R4, in accordance with some embodiments. - The conductive structures L1, L2, L3, and L4 include conductive lines, in accordance with some embodiments. The conductive structures L1, L2, L3, and L4 respectively have widths (or line widths) W11, W12, W13, and W14, in accordance with some embodiments. The width W11 or W12 is less than the width W13 or W14, in accordance with some embodiments. The distance D1 between the conductive structures L1 and L2 is less than the distance D2 between the conductive structures L3 and L4, in accordance with some embodiments.
- The removal process includes a planarization process, in accordance with some embodiments. Therefore, top surfaces S, S2, S3, S4, and 122 of the conductive structures L1, L2, L3, and L4 and the
dielectric layer 120 are coplanar, in accordance with some embodiments. - In accordance with some embodiments, methods for forming semiconductor device structures are provided. The methods (for forming the semiconductor device structure) include: forming a first mask layer over a dielectric layer; conformally forming a second mask layer over an inner wall of a first trench of the first mask layer; and removing the dielectric layer through the first trench to form a second trench in the dielectric layer. The formation of the second mask layer over the inner wall is able to narrow the second trench.
- In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface. The method includes forming an anti-bombardment layer over a first top surface of the first mask layer. The method includes forming a second mask layer over the first inner wall of the first trench. The second mask layer has a second trench, the second trench exposes the bottom surface and is over a first portion of the dielectric layer, and the second mask layer and the anti-bombardment layer are made of different materials. The method includes removing the first portion, the first mask layer, the anti-bombardment layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.
- In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface. The method includes forming an anti-bombardment layer over a top surface of the first mask layer and the first inner wall of the first trench. The anti-bombardment layer over the top surface is thicker than the anti-bombardment layer over the first inner wall. The method includes forming a second mask layer over the anti-bombardment layer over the first inner wall. The method includes partially removing the dielectric layer through the first trench to form a second trench in the dielectric layer. The method includes forming a conductive structure in the second trench.
- In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The method includes forming a second mask layer over the first mask layer. The second mask layer has a first trench, and the first trench has a first inner wall and a bottom surface. The method includes forming a third mask layer over the first inner wall. The third mask layer has a second trench over a first portion of the first mask layer and a second portion of the dielectric layer. The method includes removing the first portion of the first mask layer, the second portion of the dielectric layer, the second mask layer, and the third mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. A method for forming a semiconductor device structure, comprising:
forming a first mask layer over a dielectric layer, wherein the first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface;
forming an anti-bombardment layer over a first top surface of the first mask layer;
forming a second mask layer over the first inner wall of the first trench, wherein the second mask layer has a second trench, the second trench exposes the bottom surface and is over a first portion of the dielectric layer, and the second mask layer and the anti-bombardment layer are made of different materials;
removing the first portion, the first mask layer, the anti-bombardment layer, and the second mask layer to form a third trench in the dielectric layer; and
forming a conductive structure in the third trench.
2. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the forming of the second mask layer over the first inner wall is performed after forming the anti-bombardment layer over the first top surface of the first mask layer.
3. The method for forming the semiconductor device structure as claimed in claim 2 , wherein the second mask layer is further formed over a second top surface of the anti-bombardment layer.
4. The method for forming the semiconductor device structure as claimed in claim 2 , wherein the anti-bombardment layer is further formed over the first inner wall of the first trench.
5. The method for forming the semiconductor device structure as claimed in claim 4 , wherein a thickness of the anti-bombardment layer over the first inner wall decreases toward the dielectric layer.
6. The method for forming the semiconductor device structure as claimed in claim 4 , wherein the second mask layer covers the anti-bombardment layer over the first inner wall.
7. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the forming of the second mask layer over the first inner wall is performed before forming the anti-bombardment layer over the first top surface of the first mask layer.
8. The method for forming the semiconductor device structure as claimed in claim 7 , wherein the anti-bombardment layer covers a second top surface of the second mask layer.
9. The method for forming the semiconductor device structure as claimed in claim 8 , wherein the anti-bombardment layer further covers a second inner wall of the second trench of the second mask layer.
10. The method for forming the semiconductor device structure as claimed in claim 9 , wherein a thickness of the anti-bombardment layer over the second inner wall decreases toward the dielectric layer.
11. A method for forming a semiconductor device structure, comprising:
forming a first mask layer over a dielectric layer, wherein the first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface;
forming an anti-bombardment layer over a top surface of the first mask layer and the first inner wall of the first trench, wherein the anti-bombardment layer over the top surface is thicker than the anti-bombardment layer over the first inner wall;
forming a second mask layer over the anti-bombardment layer over the first inner wall;
partially removing the dielectric layer through the first trench to form a second trench in the dielectric layer; and
forming a conductive structure in the second trench.
12. The method for forming the semiconductor device structure as claimed in claim 11 , wherein the first mask layer, the anti-bombardment layer, and the second mask layer are consumed during partially removing the dielectric layer through the first trench.
13. The method for forming the semiconductor device structure as claimed in claim 11 , wherein the first mask layer further has a third trench, the third trench has a second inner wall, the anti-bombardment layer and the second mask layer expose the second inner wall, the partially removing of the dielectric layer through the first trench further comprises partially removing the dielectric layer through the third trench to form a fourth trench in the dielectric layer, and the forming of the conductive structure in the second trench further comprises forming the conductive structure in the fourth trench.
14. The method for forming the semiconductor device structure as claimed in claim 13 , wherein the second trench is narrower than the fourth trench.
15. The method for forming the semiconductor device structure as claimed in claim 11 , wherein the second mask layer and the anti-bombardment layer are made of different materials.
16. A method for forming a semiconductor device structure, comprising:
forming a first mask layer over a dielectric layer;
forming a second mask layer over the first mask layer, wherein the second mask layer has a first trench, and the first trench has a first inner wall and a bottom surface;
forming a third mask layer over the first inner wall, wherein the third mask layer has a second trench over a first portion of the first mask layer and a second portion of the dielectric layer;
removing the first portion of the first mask layer, the second portion of the dielectric layer, the second mask layer, and the third mask layer to form a third trench in the dielectric layer; and
forming a conductive structure in the third trench.
17. The method for forming the semiconductor device structure as claimed in claim 16 , wherein the forming of the conductive structure in the third trench comprises:
forming a conductive material layer over the first mask layer and in the third trench; and
removing the first mask layer and the conductive material layer outside of the third trench.
18. The method for forming the semiconductor device structure as claimed in claim 16 , wherein the third mask layer is further formed over a third portion of a top surface of the second mask layer.
19. The method for forming the semiconductor device structure as claimed in claim 16 , wherein after removing the first portion of the first mask layer, the second portion of the dielectric layer, the second mask layer, and the third mask layer, the remaining first mask layer originally under the third mask layer is thicker than the remaining first mask layer originally exposed by the third mask layer.
20. The method for forming the semiconductor device structure as claimed in claim 16 , wherein the first mask layer and the second mask layer are made of different materials.
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