US20200371866A1 - Memory with error correction circuit - Google Patents
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- US20200371866A1 US20200371866A1 US16/420,200 US201916420200A US2020371866A1 US 20200371866 A1 US20200371866 A1 US 20200371866A1 US 201916420200 A US201916420200 A US 201916420200A US 2020371866 A1 US2020371866 A1 US 2020371866A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/1016—Error in accessing a memory location, i.e. addressing error
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/1028—Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
Definitions
- the disclosure relates to a memory circuit, and more particularly to a memory with an error correction circuit.
- ECC error correction code circuit
- DRAM dynamic random access memory
- a memory 100 includes a first error correction circuit ECC 1 , a second error correction circuit ECC 2 , a plurality of memory cell columns MCC and a plurality of sensing drive circuits SD, wherein the first error correction circuit ECC 1 and the second error correction circuit ECC 2 are both capable of correcting single-bit errors.
- Each of the memory cell columns MCC includes a plurality of memory cell blocks MC connected to each other in series and each of the memory cell blocks MC further includes a plurality of memory cells (not shown).
- the plurality of sensing drive circuits SD are respectively coupled to the plurality of memory cell columns MCC and each of the sensing drive circuits SD is coupled to the first error correction circuit ECC 1 or the second error correction circuit ECC 2 .
- the sensing drive circuits SD on the left side of the memory 100 are coupled to the first error correction circuit ECC 1 and the sensing drive circuits SD on the right side of the memory 100 are coupled to the second error correction circuit ECC 2 .
- the error correction circuit (the first error correction circuit ECC 1 , for example) may fail to accurately correct a multiple-bit error.
- the error correction circuit may fail to accurately correct a multiple-bit error.
- the disclosure proposes a memory with an error correction circuit to respond to a situation in which a 2-bit error occurs due to failure of adjacent memory cells.
- the disclosure provides a memory with an error correction circuit, the memory including a first error correction circuit, a second error correction circuit, a plurality of memory cell columns and a plurality of sensing drive circuits.
- the first error correction circuit performs error correction on first partial data to generate first partial write data or first partial read data.
- the second error correction circuit performs error correction on second partial data to generate second partial write data or second partial read data.
- the plurality of sensing drive circuits are respectively coupled to the plurality of memory cell columns and are coupled to the first error correction circuit and the second error correction circuit. In a write mode, the plurality of sensing drive circuits respectively receive a plurality of first partial write bits of the first partial write data and respectively receive a plurality of second partial write bits of the second partial write data.
- Each of the sensing drive circuits combines the first partial write bits with the corresponding second partial write bits and writes them to corresponding memory cell columns.
- the plurality of sensing drive circuits respectively sense stored data in the plurality of memory cell columns to generate a plurality of the first partial read data and the second partial read data.
- two adjacent memory cells are respectively coupled to the first error correction circuit and the second error correction circuit.
- the two adjacent memory cells fail and cause a read error, from the viewpoint of the first error correction cell, only one read error exists.
- the first error correction circuit and the second error correction circuit can respond to and correct single-bit errors.
- FIG. 1 is a conventional memory with an error correction circuit.
- FIG. 2 illustrates a memory with an error correction circuit according to an embodiment of the disclosure.
- FIG. 3 is a schematic diagram of a memory cell block in a first row of each memory cell column.
- a memory 200 includes a first error correction circuit ECC 1 , a second error correction circuit ECC 2 , a plurality of sensing drive circuits SD, an address decoder ADD and a memory cell array, wherein the memory cell array includes a plurality of memory cell columns MCC and a plurality of memory cell rows MCR, and each of the memory cell columns MCC includes a plurality of memory cell blocks MC connected in series and each of the memory cell blocks MC includes a plurality of memory cells M (as shown in FIG. 3 ).
- the plurality of memory cell columns MCC are respectively coupled to the plurality of sensing drive circuits SD through the address decoder ADD, and each of the sensing drive circuits SD is coupled to the first error correction circuit ECC 1 and the second error correction circuit ECC 2 at the same time, wherein the first error correction circuit ECC 1 and the second error correction circuit ECC 2 can perform error correction on a single-bit error.
- the address decoder ADD may include a column decoder (not shown) and a row decoder (not shown).
- the memory 200 may allow data D of specific size to be read therefrom or written thereto.
- the data D is split into first partial data D 1 and second partial data D 2 .
- the first error correction circuit ECC 1 generates first partial write data ECCD 1 including a first error correction code according to the first partial data D 1 ; similarly, the second error correction circuit ECC 2 generates second partial write data ECCD 2 including a second error correction code according to the second partial data D 2 .
- the data D may be of, for example, 256 bits, and the first partial data D 1 and the second partial data D 2 are of 128 bits.
- the first partial write data ECCD 1 and the second partial write data ECCD 2 are of 136 bits, wherein the first error correction code of 8 bits and the second error correction code of 8 bits are included.
- the first partial write data ECCD 1 may be split into a plurality of first partial write bits DB 1 (having a size of, for example, 4 bits) and the second partial write data ECCD 2 may be split into a plurality of second partial write bits DB 2 .
- Each of the sensing drive circuits SD receives the first partial write bit DB 1 and the second partial write bit DB 2 at the same time, combines the first partial write bit DB 1 with the second partial write bit DB 2 , designates an address by the address decoder ADD, and then writes the combined first partial write bit DB 1 and second partial write bit DB 2 to the designated address of the corresponding memory cell column MCC.
- the sensing drive circuit SD 1 receives the first partial write bit DB 1 and the second partial write bit DB 2 , combines the first partial write bit DB 1 and the second partial write bit DB 2 and writes them to the designated address of a corresponding memory cell column MCC( 1 ).
- This address is designated by the address decoder ADD, and is, for example, the memory cell block MC in a first row of a memory cell column MCC( 1 ) shown in FIG. 3 .
- the first error correction code (of 8 bits, for example) generated by the first error correction circuit ECC 1 and included in the first partial write data ECCD 1 is also split into two first partial write bits DB 1 (of 4 bits, for example) which are received respectively by a sensing drive circuit SD(P) and a sensing drive circuit SD(P+1).
- the second error correction code (of 8 bits, for example) generated by the second error correction circuit ECC 2 and included in the second partial write data ECCD 2 is split into two second partial write bits DB 2 (of 4 bits, for example) which are received respectively by the sensing drive circuit SD(P) and the sensing drive circuit SD(P+1).
- the sensing drive circuit SD(P) receives a portion of the first error correction code and a portion of the second error correction code respectively and so does the sensing drive circuit SD(P+1) (referred to as second error correction code memory cell column). Then, similarly, the sensing drive circuit SD(P) combines the portion of the first error correction code with the portion of the second error correction code and writes them to a designated address in a corresponding memory cell column MCC(P), and so does the sensing drive circuit SD(P+1).
- the plurality of memory cell columns MCC include a total of N columns, wherein the first error correction code memory cell column and the second error correction code memory cell column are respectively located in a P-th column and a (P+1)-th column and are disposed adjacent to each other (as shown in FIG. 2 ), wherein P and N are both natural numbers and 1 ⁇ P ⁇ N.
- the first error correction code memory cell column and the second error correction code memory cell column are located at center positions in the plurality of memory cell columns MCC.
- first data code memory cell columns the memory cell columns on the left side of the first error correction code memory cell column
- second data code memory cell columns the memory cell columns on the right side of the second error correction code memory cell column
- each of the sensing drive circuits SD senses and reads a data byte from a designated address (designated by the address decoder ADD) of the corresponding memory cell column MCC and splits the data byte into a first partial read bit and a second partial read bit.
- the first partial read bit and the second partial read bit are also referred to as DB 1 and DB 2 , respectively.
- the sensing drive circuit SD sends the first partial read bit DB 1 and the second partial read bit DB 2 respectively to the first error correction circuit ECC 1 and the second error correction circuit ECC 2 for error correction.
- a plurality of first partial read bits DB 1 are combined into first partial read data (including the first error correction code) and are received by the first error correction circuit ECC 1 ; similarly, a plurality of second partial read bits DB 2 are combined into second partial read data (including the second error correction code) and are received by the second error correction circuit ECC 2 .
- the first partial read data and the second partial read data are also referred to as ECCD 1 and ECCD 2 , respectively.
- the first error correction circuit ECC 1 performs error correction on the first partial read data ECCD 1 and generates the first partial data D 1 .
- the second error correction circuit ECC 2 performs error correction on the second partial read data ECCD 2 and generates the second partial data D 2 .
- the first partial data D 1 and the second partial data D 2 are combined and output as the data D.
- the plurality of first partial read bits DB 1 and the plurality of second partial read bits DB 2 are both of 4 bits
- the first partial read data ECCD 1 and the second partial read data ECCD 2 are both of 136 bits
- the first error correction code and the second error correction code may both be of 8 bits
- the data D is of 256 bits.
- Each memory cell block MC includes a plurality of first memory cells M 1 , a plurality of second memory cells M 2 , a sub-word line driver SWD, a first bit line sensor BLSA 1 , a second bit line sensor BLSA 2 , a plurality of first selective switches SW 1 and a plurality of second selective switches SW 2 .
- FIG. 2 only bit line sensors BLSA are shown to indicate the first bit line sensor BLSA 1 and the second bit line sensor BLSA 2 collectively.
- each of the first memory cells M 1 and each of the second memory cells M 2 include a transistor T and a capacitor C, wherein the capacitor C is coupled between the transistor T and a reference potential terminal.
- a control terminal of the transistor T is coupled to the sub-word line driver SWD through a word line WL and is controlled by the sub-word line driver SWD.
- the transistor T is connected in series between the capacitor C and a corresponding bit line.
- the transistor T (the transistor in the first memory cell M 1 ) is coupled to the first bit line sensor BLSA 1
- the transistor T (the transistor in the second memory cell M 2 ) is coupled to the second bit line sensor BLSA 2 .
- the first bit line sensor BLSA 1 senses stored data in the first memory cell M 1 through a first bit line BL 1
- the second bit line sensor BLSA 2 senses stored data in the second memory cell M 2 through a second bit line BL 2
- the first bit line sensor BLSA 1 is coupled to a main input/output line MIO through a row switch RSW.
- the second bit line sensor BLSA 2 is coupled to the main input/output line MIO through the row switch RSW.
- a bit line BL connected to the first memory cell M 1 is referred to as the first bit line BL 1 and a bit line BL connected to the second memory cell M 2 as the second bit line BL 2 .
- the transistor T may be a metal-oxide-semiconductor field-effect transistor (MOSFET), and the memory cells M located in the same memory cell row MCR may be controlled by the same word line WL.
- MOSFET metal-oxide-semiconductor field-effect transistor
- a sensing drive circuit SD( 1 ) turns on the transistors T of all the memory cells M of the memory cell blocks MC( 11 ) through the sub-word line driver SWD.
- the sensing drive circuit SD( 1 ) controls the row switch RSW to be switched on and controls a column selective line CSL 0 to send a selective signal S to switch on the first selective switches SW 1 and the second selective switches SW 2 of the memory cell blocks MC( 11 ) so as to connect the main input/output line MIO to the memory cell blocks MC( 11 ).
- a plurality of the first bit line sensors BLSA 1 are connected to the plurality of first memory cells M 1 through a plurality of the first bit lines BL 1
- a plurality of the second bit line sensors BLSA 2 are connected to the plurality of second memory cells M 2 through a plurality of the second bit lines BL 2 .
- the sensing drive circuit SD( 1 ) writes the combined first partial write bit DB 1 and second partial write bit DB 2 to the memory cells M of the memory cell block MC( 11 ) respectively by the first bit line sensor BLSA 1 and the second bit line sensor BLSA 2 through the main input/output line MIO.
- the first bit line BL 1 which is coupled to the switched-on first selective switch SW 1 is referred to as a first selected bit line; similarly, the second bit line BL 2 which is coupled to the switched-on second selective switch SW 2 is referred to as a second selected bit line.
- the sensing drive circuit SD( 1 ) controls the row switch RSW to be switched on and controls the column selective line CSL 0 to send the selective signal S to switch on the first selective switches SW 1 and the second selective switches SW 2 of the memory cell block MC( 11 ) so as to connect the main input/output line MIO to the first bit line sensor BLSA 1 and the second bit line sensor BLSA 2 of the memory cell block MC( 11 ).
- a plurality of the first bit line sensors BLSA 1 are connected to the plurality of first memory cells M 1 through a plurality of the first bit lines BL 1
- a plurality of the second bit line sensors BLSA 2 are connected to the plurality of second memory cells M 2 through a plurality of the second bit lines BL 2 .
- the sensing drive circuit SD( 1 ) senses the stored data from the first memory cells M 1 of the memory cell block MC( 11 ) and transmits the stored data to the first error correction circuit ECC 1 through the first bit line sensors BLSA 1 and the main input/output line MIO.
- the sensing drive circuit SD( 1 ) senses the stored data from the second memory cells M 2 of the memory cell block MC( 11 ) and transmits the stored data to the second error correction circuit ECC 2 through the second bit line sensors BLSA 2 and the main input/output line MIO. That is to say, two adjacent memory cells M in the memory cell block MC respectively correspond to the first error correction circuit ECC 1 and the second error correction circuit ECC 2 .
- the first error correction circuit ECC 1 and the second error correction circuit ECC 2 can perform error correction on the single-bit error.
- the memory with an error correction circuit of the disclosure has an improved error correction effect and decreases the use of spare memory. Moreover, by arranging the first memory cell M 1 and the second memory cell M 2 in a staggered manner, electrical interference between them can be reduced.
- two adjacent memory cells are respectively coupled to a first error correction circuit and a second error correction circuit.
- the two adjacent memory cells fail, from the viewpoint of each of the first error correction circuit and the second error correction circuit, only a single-bit error needs to be dealt with. Therefore, at the same cost, the memory with an error correction circuit of the disclosure has an improved error correction effect and decreases the use of spare memory.
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Abstract
Description
- The disclosure relates to a memory circuit, and more particularly to a memory with an error correction circuit.
- An error correction code (ECC) circuit is integrated on a dynamic random access memory (DRAM) chip. Since error correction code circuits capable of correcting 2-bit errors require larger circuit area and longer error correction time, error correction code circuits capable of correcting single-bit errors are generally used.
- With reference to
FIG. 1 , amemory 100 includes a first error correction circuit ECC1, a second error correction circuit ECC2, a plurality of memory cell columns MCC and a plurality of sensing drive circuits SD, wherein the first error correction circuit ECC1 and the second error correction circuit ECC2 are both capable of correcting single-bit errors. Each of the memory cell columns MCC includes a plurality of memory cell blocks MC connected to each other in series and each of the memory cell blocks MC further includes a plurality of memory cells (not shown). The plurality of sensing drive circuits SD are respectively coupled to the plurality of memory cell columns MCC and each of the sensing drive circuits SD is coupled to the first error correction circuit ECC1 or the second error correction circuit ECC2. InFIG. 1 , for example, the sensing drive circuits SD on the left side of thememory 100 are coupled to the first error correction circuit ECC1 and the sensing drive circuits SD on the right side of thememory 100 are coupled to the second error correction circuit ECC2. - When adjacent memory cells fail at the same time and the failed adjacent memory cells are coupled to the same error correction circuit, the error correction circuit (the first error correction circuit ECC1, for example) may fail to accurately correct a multiple-bit error. To avoid the above issue, in the related art, those skilled in the art often use a spare memory with an error correction circuit, thus resulting in an increase in circuit area and manufacturing cost.
- For the above issue, the disclosure proposes a memory with an error correction circuit to respond to a situation in which a 2-bit error occurs due to failure of adjacent memory cells.
- The disclosure provides a memory with an error correction circuit, the memory including a first error correction circuit, a second error correction circuit, a plurality of memory cell columns and a plurality of sensing drive circuits. The first error correction circuit performs error correction on first partial data to generate first partial write data or first partial read data. The second error correction circuit performs error correction on second partial data to generate second partial write data or second partial read data. The plurality of sensing drive circuits are respectively coupled to the plurality of memory cell columns and are coupled to the first error correction circuit and the second error correction circuit. In a write mode, the plurality of sensing drive circuits respectively receive a plurality of first partial write bits of the first partial write data and respectively receive a plurality of second partial write bits of the second partial write data. Each of the sensing drive circuits combines the first partial write bits with the corresponding second partial write bits and writes them to corresponding memory cell columns. In a read mode, the plurality of sensing drive circuits respectively sense stored data in the plurality of memory cell columns to generate a plurality of the first partial read data and the second partial read data.
- Based on the above, two adjacent memory cells are respectively coupled to the first error correction circuit and the second error correction circuit. When the two adjacent memory cells fail and cause a read error, from the viewpoint of the first error correction cell, only one read error exists. Similarly, from the viewpoint of the second error correction cell, only one read error exists. As a result, the first error correction circuit and the second error correction circuit can respond to and correct single-bit errors.
- In order to make the above features and advantages of the disclosure comprehensible, embodiments accompanied with drawings are described in details below.
-
FIG. 1 is a conventional memory with an error correction circuit. -
FIG. 2 illustrates a memory with an error correction circuit according to an embodiment of the disclosure. -
FIG. 3 is a schematic diagram of a memory cell block in a first row of each memory cell column. - With reference to
FIG. 2 , amemory 200 includes a first error correction circuit ECC1, a second error correction circuit ECC2, a plurality of sensing drive circuits SD, an address decoder ADD and a memory cell array, wherein the memory cell array includes a plurality of memory cell columns MCC and a plurality of memory cell rows MCR, and each of the memory cell columns MCC includes a plurality of memory cell blocks MC connected in series and each of the memory cell blocks MC includes a plurality of memory cells M (as shown inFIG. 3 ). The plurality of memory cell columns MCC are respectively coupled to the plurality of sensing drive circuits SD through the address decoder ADD, and each of the sensing drive circuits SD is coupled to the first error correction circuit ECC1 and the second error correction circuit ECC2 at the same time, wherein the first error correction circuit ECC1 and the second error correction circuit ECC2 can perform error correction on a single-bit error. The address decoder ADD may include a column decoder (not shown) and a row decoder (not shown). - The
memory 200 may allow data D of specific size to be read therefrom or written thereto. In a write mode of the memory, the data D is split into first partial data D1 and second partial data D2. The first error correction circuit ECC1 generates first partial write data ECCD1 including a first error correction code according to the first partial data D1; similarly, the second error correction circuit ECC2 generates second partial write data ECCD2 including a second error correction code according to the second partial data D2. In the present embodiment, the data D may be of, for example, 256 bits, and the first partial data D1 and the second partial data D2 are of 128 bits. The first partial write data ECCD1 and the second partial write data ECCD2 are of 136 bits, wherein the first error correction code of 8 bits and the second error correction code of 8 bits are included. - Next, the first partial write data ECCD1 may be split into a plurality of first partial write bits DB1 (having a size of, for example, 4 bits) and the second partial write data ECCD2 may be split into a plurality of second partial write bits DB2. Each of the sensing drive circuits SD receives the first partial write bit DB1 and the second partial write bit DB2 at the same time, combines the first partial write bit DB1 with the second partial write bit DB2, designates an address by the address decoder ADD, and then writes the combined first partial write bit DB1 and second partial write bit DB2 to the designated address of the corresponding memory cell column MCC.
- Take a sensing drive circuit SD1 as an example, the sensing drive circuit SD1 receives the first partial write bit DB1 and the second partial write bit DB2, combines the first partial write bit DB1 and the second partial write bit DB2 and writes them to the designated address of a corresponding memory cell column MCC(1). This address is designated by the address decoder ADD, and is, for example, the memory cell block MC in a first row of a memory cell column MCC(1) shown in
FIG. 3 . - Still with reference to
FIG. 2 , in the present embodiment, the first error correction code (of 8 bits, for example) generated by the first error correction circuit ECC1 and included in the first partial write data ECCD1 is also split into two first partial write bits DB1 (of 4 bits, for example) which are received respectively by a sensing drive circuit SD(P) and a sensing drive circuit SD(P+1). Similarly, the second error correction code (of 8 bits, for example) generated by the second error correction circuit ECC2 and included in the second partial write data ECCD2 is split into two second partial write bits DB2 (of 4 bits, for example) which are received respectively by the sensing drive circuit SD(P) and the sensing drive circuit SD(P+1). That is to say, the sensing drive circuit SD(P) (referred to as first error correction code memory cell column) receives a portion of the first error correction code and a portion of the second error correction code respectively and so does the sensing drive circuit SD(P+1) (referred to as second error correction code memory cell column). Then, similarly, the sensing drive circuit SD(P) combines the portion of the first error correction code with the portion of the second error correction code and writes them to a designated address in a corresponding memory cell column MCC(P), and so does the sensing drive circuit SD(P+1). - In the present embodiment, the plurality of memory cell columns MCC include a total of N columns, wherein the first error correction code memory cell column and the second error correction code memory cell column are respectively located in a P-th column and a (P+1)-th column and are disposed adjacent to each other (as shown in
FIG. 2 ), wherein P and N are both natural numbers and 1<P<N. In another embodiment, the first error correction code memory cell column and the second error correction code memory cell column are located at center positions in the plurality of memory cell columns MCC. For convenience of description, in the drawing, the memory cell columns on the left side of the first error correction code memory cell column are referred to as first data code memory cell columns, and the memory cell columns on the right side of the second error correction code memory cell column are referred to as second data code memory cell columns. - In a read mode of the
memory 200, each of the sensing drive circuits SD senses and reads a data byte from a designated address (designated by the address decoder ADD) of the corresponding memory cell column MCC and splits the data byte into a first partial read bit and a second partial read bit. For convenience of description, the first partial read bit and the second partial read bit are also referred to as DB1 and DB2, respectively. Next, the sensing drive circuit SD sends the first partial read bit DB1 and the second partial read bit DB2 respectively to the first error correction circuit ECC1 and the second error correction circuit ECC2 for error correction. With reference toFIG. 2 , a plurality of first partial read bits DB1 are combined into first partial read data (including the first error correction code) and are received by the first error correction circuit ECC1; similarly, a plurality of second partial read bits DB2 are combined into second partial read data (including the second error correction code) and are received by the second error correction circuit ECC2. - For convenience of description, the first partial read data and the second partial read data are also referred to as ECCD1 and ECCD2, respectively. Next, in accordance with the first error correction code in the first partial read data ECCD1, the first error correction circuit ECC1 performs error correction on the first partial read data ECCD1 and generates the first partial data D1. Similarly, in accordance with the second error correction code in the second partial read data ECCD2, the second error correction circuit ECC2 performs error correction on the second partial read data ECCD2 and generates the second partial data D2. Finally, the first partial data D1 and the second partial data D2 are combined and output as the data D. In the present embodiment, the plurality of first partial read bits DB1 and the plurality of second partial read bits DB2 are both of 4 bits, the first partial read data ECCD1 and the second partial read data ECCD2 are both of 136 bits, the first error correction code and the second error correction code may both be of 8 bits, and the data D is of 256 bits.
- The details of how each sensing drive circuit SD writes a data byte to a designated address of a corresponding memory cell column MCC and reads the data byte from the designated address of the corresponding memory cell column MCC will be explained below with reference to
FIG. 3 . Each memory cell block MC includes a plurality of first memory cells M1, a plurality of second memory cells M2, a sub-word line driver SWD, a first bit line sensor BLSA1, a second bit line sensor BLSA2, a plurality of first selective switches SW1 and a plurality of second selective switches SW2. InFIG. 2 , only bit line sensors BLSA are shown to indicate the first bit line sensor BLSA1 and the second bit line sensor BLSA2 collectively. InFIG. 3 , each of the first memory cells M1 and each of the second memory cells M2 include a transistor T and a capacitor C, wherein the capacitor C is coupled between the transistor T and a reference potential terminal. A control terminal of the transistor T is coupled to the sub-word line driver SWD through a word line WL and is controlled by the sub-word line driver SWD. The transistor T is connected in series between the capacitor C and a corresponding bit line. The transistor T (the transistor in the first memory cell M1) is coupled to the first bit line sensor BLSA1, or the transistor T (the transistor in the second memory cell M2) is coupled to the second bit line sensor BLSA2. The first bit line sensor BLSA1 senses stored data in the first memory cell M1 through a first bit line BL1, and the second bit line sensor BLSA2 senses stored data in the second memory cell M2 through a second bit line BL2. The first bit line sensor BLSA1 is coupled to a main input/output line MIO through a row switch RSW. Similarly, the second bit line sensor BLSA2 is coupled to the main input/output line MIO through the row switch RSW. For convenience of description, a bit line BL connected to the first memory cell M1 is referred to as the first bit line BL1 and a bit line BL connected to the second memory cell M2 as the second bit line BL2. In the present embodiment, the transistor T may be a metal-oxide-semiconductor field-effect transistor (MOSFET), and the memory cells M located in the same memory cell row MCR may be controlled by the same word line WL. - With reference to
FIG. 2 andFIG. 3 together, in a write mode of thememory 200, if a write address designated by the address decoder ADD corresponds to the memory cell block (referred to as MC(11)) in the first row of the memory cell column MCC(1), a sensing drive circuit SD(1) turns on the transistors T of all the memory cells M of the memory cell blocks MC(11) through the sub-word line driver SWD. In addition, the sensing drive circuit SD(1) controls the row switch RSW to be switched on and controls a column selective line CSL0 to send a selective signal S to switch on the first selective switches SW1 and the second selective switches SW2 of the memory cell blocks MC(11) so as to connect the main input/output line MIO to the memory cell blocks MC(11). A plurality of the first bit line sensors BLSA1 are connected to the plurality of first memory cells M1 through a plurality of the first bit lines BL1, and a plurality of the second bit line sensors BLSA2 are connected to the plurality of second memory cells M2 through a plurality of the second bit lines BL2. Then, the sensing drive circuit SD(1) writes the combined first partial write bit DB1 and second partial write bit DB2 to the memory cells M of the memory cell block MC(11) respectively by the first bit line sensor BLSA1 and the second bit line sensor BLSA2 through the main input/output line MIO. - For convenience of description, the first bit line BL1 which is coupled to the switched-on first selective switch SW1 is referred to as a first selected bit line; similarly, the second bit line BL2 which is coupled to the switched-on second selective switch SW2 is referred to as a second selected bit line.
- In the read mode of the
memory 200, it is assumed that a read address designated by the address decoder ADD corresponds to the memory cell block MC(11). Similarly, the sensing drive circuit SD(1) controls the row switch RSW to be switched on and controls the column selective line CSL0 to send the selective signal S to switch on the first selective switches SW1 and the second selective switches SW2 of the memory cell block MC(11) so as to connect the main input/output line MIO to the first bit line sensor BLSA1 and the second bit line sensor BLSA2 of the memory cell block MC(11). A plurality of the first bit line sensors BLSA1 are connected to the plurality of first memory cells M1 through a plurality of the first bit lines BL1, and a plurality of the second bit line sensors BLSA2 are connected to the plurality of second memory cells M2 through a plurality of the second bit lines BL2. Then, the sensing drive circuit SD(1) senses the stored data from the first memory cells M1 of the memory cell block MC(11) and transmits the stored data to the first error correction circuit ECC1 through the first bit line sensors BLSA1 and the main input/output line MIO. The sensing drive circuit SD(1) senses the stored data from the second memory cells M2 of the memory cell block MC(11) and transmits the stored data to the second error correction circuit ECC2 through the second bit line sensors BLSA2 and the main input/output line MIO. That is to say, two adjacent memory cells M in the memory cell block MC respectively correspond to the first error correction circuit ECC1 and the second error correction circuit ECC2. - When two adjacent memory cells (the first memory cell M1 and the second memory cell M2 of the memory cell block MC(11) in
FIG. 3 , for example) fail and cause an error in the stored data, since the two adjacent memory cells M1 and M2 are respectively coupled to the first error correction circuit ECC1 and the second error correction circuit ECC2, from the viewpoint of the first error correction circuit ECC1, only one read error exists (the data read from the first memory cell M1, for example); similarly, from the viewpoint of the second error correction circuit ECC2, only one read error exist (the data read from the second memory cell M2, for example). Therefore, the first error correction circuit ECC1 and the second error correction circuit ECC2 can perform error correction on the single-bit error. For those skilled in the art, at the same cost, the memory with an error correction circuit of the disclosure has an improved error correction effect and decreases the use of spare memory. Moreover, by arranging the first memory cell M1 and the second memory cell M2 in a staggered manner, electrical interference between them can be reduced. - Although the disclosure has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit and the scope of the disclosure. Accordingly, the scope of the disclosure will be defined by the attached claims and their equivalents and not by the above detailed descriptions.
- In the disclosure, two adjacent memory cells are respectively coupled to a first error correction circuit and a second error correction circuit. When the two adjacent memory cells fail, from the viewpoint of each of the first error correction circuit and the second error correction circuit, only a single-bit error needs to be dealt with. Therefore, at the same cost, the memory with an error correction circuit of the disclosure has an improved error correction effect and decreases the use of spare memory.
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US4677589A (en) * | 1985-07-26 | 1987-06-30 | Advanced Micro Devices, Inc. | Dynamic random access memory cell having a charge amplifier |
US5127014A (en) * | 1990-02-13 | 1992-06-30 | Hewlett-Packard Company | Dram on-chip error correction/detection |
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US7779334B2 (en) * | 2006-06-26 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory having an ECC system |
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