US20200328753A1 - Successive approximation register analog to digital converter and offset detection method thereof - Google Patents
Successive approximation register analog to digital converter and offset detection method thereof Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/1023—Offset correction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
Definitions
- the disclosure generally relates to analog-to-digital converter (ADC), and more particularly to “top-plate swapping” technique to detect a comparator offset in a successive approximation register (SAR) ADC that is capable of enhancing the performance and robustness of the SAR ADC.
- ADC analog-to-digital converter
- SAR successive approximation register
- ADCs with moderate resolution and gigahertz sampling rate are in high demand for a large number of applications in different fields such as wireless communication and consumer electronics.
- the time interleaving (TI) structure is widely adopted.
- TI time interleaving
- Such a structure suffers from offset mismatch, gain mismatch and timing skew, which would degrade the performance of TI ADC.
- demand for better performance of the ADC has grown recently, there has grown a need for a more creative technique to efficiently detect offset mismatch.
- a SAR ADC and a method of detecting offset that are capable of enhancing the performance and robustness of the SAR ADC are introduced.
- the SAR ADC includes a switch circuit, a comparator and a calibration circuit.
- the switch circuit is configured to perform a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal.
- the comparator is coupled to the switching circuit and is configured to compare the first intermediate analog signal and the second intermediate analog signal before the swapping operation to generate a least-significant-bit value.
- the comparator is further configured to compare the first swapped analog signal and the second swapped analog signal after the swapping operation to generate a calibration bit value.
- the calibration circuit is configured to determine whether the comparator has an offset according to the least-significant-bit value and the calibration bit value.
- the method of detecting an offset of a comparator includes steps of comparing a first intermediate analog signal and a second intermediate analog signal to determine a least-significant-bit value; performing a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal; comparing the first swapped analog signal and the second swapped analog signal after the swapping operation to generate a calibration bit value; and determining whether the comparator has the offset according to the least-significant-bit value and the calibration bit value.
- FIG. 1 is a schematic diagram illustrating a successive approximation register (SAR) analog to digital converter (ADC) in accordance with some embodiments.
- SAR successive approximation register
- ADC analog to digital converter
- FIGS. 2 through 3 are schematic diagrams illustrating a switching circuit of a SAR ADC in accordance with some embodiments.
- FIG. 4 is schematic diagram illustrating a detail structure of a calibration circuit of a SAR ADC in accordance with some embodiments.
- FIG. 5 is schematic diagram illustrating a comparator of a SAR ADC in accordance with some embodiments.
- FIGS. 6A and 6B are timing diagrams illustrating waveforms of signals without and with comparator offset in accordance with some embodiments.
- FIG. 7 is a flowchart diagram illustrating a method of detecting offset of a comparator in accordance with some embodiments.
- the SAR ADC 100 may include input terminals IN 1 and IN 2 , switches SWa and SWb, capacitor arrays 110 a and 110 b, a switching circuit 120 , a comparator 130 , a SAR logic 140 and a calibration circuit 150 .
- the input terminals IN 1 and IN 2 are configured to receive analog input signals Vip and Vin, respectively.
- the SAR ADC 100 may covert the analog input signals Vip and Vin to a digital output OUT that corresponds to the analog input signals Vip and Vin.
- the switch SWa is coupled between the input terminal IN 1 and the capacitor array 110 a; and the switch SWb is coupled between the input terminal IN 2 and the capacitor array 110 b.
- the switches SWa and SWb are switched on or off according to at least one control signal.
- the at least one control signal for controlling the switches SWa and SWb are a clock signal that are generated by a clock generator (not shown).
- a clock generator not shown
- the disclosure is not limited thereto, an any control signal that are capable of switching on or off the switches SWa and SWb falls within the scope of the disclosure.
- the capacitor array 110 a may include a plurality of capacitors (not shown) arranged in array.
- the capacitor array 110 a is configured to receive the analog input signal Vip and reference signals Vrefp and Vrefn, and is configured to generate an intermediate analog signal DACp according to the analog input signal Vip and the reference signals Vrefp and Vrefn.
- the capacitor array 110 b may include a plurality of capacitors (not shown) arranged in array.
- the capacitor array 110 b is configured to receive the analog input signal Vin and reference signals Vrefp and Vrefn, and is configured to generate an intermediate analog signal DACn according to the analog input signal Vin and the reference signals Vrefp and Vrefn.
- the SAR ADC 100 may further include a sample and hold circuit (not shown) that is configured to sample and hold the analog input signals Vip and Vin to generate the sampled signals corresponding to the analog input signals Vip and Vin.
- the capacitor arrays 110 a and 110 b may act as capacitive digital-to-analog converter (CDAC) that may generate the intermediate analog signals DACp and DACn according to the reference signals Vrefp, Vrefn and the sampled signals corresponding to the analog input signals Vip and Vin.
- CDAC capacitive digital-to-analog converter
- the switch circuit 120 is coupled between the capacitor arrays 110 a, 110 b and the comparator 130 .
- the switch circuit 120 is configured to receive the intermediate analog signals DACp and DACn from the capacitor arrays 110 a and 110 b and output signals P and N (e.g., may also be referred to as top-swap voltages) to the comparator 130 according to a control signal CLK_LSB.
- the switch circuit 120 may perform a swapping operation (or a top-plate swapping operation) to interchange the intermediate analog signals DACp and DACn to generate the signals P and N. For example, before the swapping operation, the intermediate analog signal DACp is outputted as the signal P, and the intermediate analog signal DACn is outputted as the signal N.
- the switch circuit 120 After the swapping operation, the intermediate analog signal DACp is outputted as the signal N, and the intermediate analog signal DACn is outputted as the signal P. In some embodiments, after a least-significant-bit (LSB) of the digital output OUT has been decided, the switch circuit 120 performs the swapping operation to interchange the intermediate analog signals DACp and DACn.
- LSB least-significant-bit
- the comparator 130 is coupled to the switching circuit 120 to receive the signals P and N from the switching circuit 120 .
- the comparator 130 is configured to compare the signals P and N to generate a comparison result CMP.
- the intermediate analog signals DACp and DACn have not been interchanged and are outputted as the signals P and N, respectively.
- the comparator 130 may compare the signals P and N to generate a first comparison result.
- the intermediate analog signals DACp and DACn are interchanged and are outputted as the signals N and P, respectively.
- the comparator 130 may compare the signals P and N to generate a second comparison result.
- the first comparison result may be used to determine a LSB B LSB and a calibration bit Bcal.
- the SAR logic 140 is coupled to the comparator 130 and is configured to generate a digital output OUT according to the comparison result CMP.
- the SAR logic 140 may store a digital value having a plurality of bits, and each bit of the digital value is updated during a sequence of comparation operations performed by the comparator 130 .
- the digital output OUT is generated at an end of the sequence of the comparison operations. For example, the sequence of the comparison operations is ended when the comparison operation for determining the LSB B LSB is completed, and the value of the LSB B LSB is updated.
- the SAR logic 140 may control the switch circuit 120 to perform the swapping operation (e.g., “top-swap operation”) to interchange the intermediate analog signals DACp and DACn to generate the swapped analog signals.
- An additional comparison operation is performed to compare the swapped analog signal to determine value of the calibration bit Bcal.
- the SAR logic 140 may provide the LSB B LSB and the calibration bit Bcal to the calibration circuit 150 .
- the calibration circuit 150 is coupled between the comparator 130 and the SAR logic 140 , and is configured to detect offset of the comparator 130 according to the LSB B LSB and the calibration bit Bcal. The calibration circuit 150 is further configured to correct the detected offset of the comparator 130 .
- the switch circuit 220 includes input terminals 2201 and 2202 , a control terminal 2203 , and output terminals 2204 and 2205 .
- the input terminals 2201 and 2202 are configured to receive the intermediate analog signals DACp and DACn, respectively;
- the control terminal 2203 is configured to receive a control signal (e.g., CLK_LSB);
- the output terminals 2204 and 2205 are configured to output the signals P and N.
- the switch circuit 220 may generate the signals P and N according to the control signal (e.g., CLK_LSB) and the intermediate analog signals DACp and DACn.
- the switch circuit 220 includes a plurality of switches SW 1 through SW 4 , in which each of the switches SW 1 through SW 4 is coupled between one of the input terminals 2201 and 2201 of the switch circuit 220 and one of the output terminals 2204 and 2205 of the switch circuit 220 .
- the switch SW 1 is coupled between the input terminal 2201 and the output terminal 2204 ;
- the switch SW 2 is coupled between the input terminal 2201 and the output terminal 2205 ;
- the switch SW 3 is coupled between the input terminal 2202 and the output terminal 2204 ;
- the switch SW 4 is coupled between the input terminal 2202 and the output terminal 2205 .
- the switch circuit 220 before the swapping operation, is configured to turn on the switches SW 1 and SW 4 to electrically connect the input terminals 2201 and 2202 to the output terminals 2204 and 2205 , respectively.
- the switch circuit 220 is configured to turn on the switches SW 2 and SW 3 to electrically connect the input terminals 2201 and 2202 to the output terminals 2205 and 2204 , respectively.
- the switch circuit 220 is a double bootstrapped switch that is adopted with monotonic switching, thereby improving a linearity of the switch circuit 220 is improved.
- the switch SWx may include a boost capacitor Cs and a transistor Ms.
- the drain terminal D of the transistor Ms is coupled to the input terminal 2201 or 2201 of the switch circuit 220
- the source terminal S of the transistor Ms is coupled to the output terminal 2204 or 2205 of the switch circuit 220 .
- the boost capacitor Cs is pre-charged to a level of a bias voltage Vbias.
- the level of the bias voltage Vbias is smaller than the level of a reference voltage Vdd to improve a reliability of the switch circuit 220 .
- the boost capacitor Cs may generate a boosted voltage which is provided to a gate of the transistor Ms.
- a level of the boosted voltage is Vdd+Vbias.
- the transistor Ms is controlled by the boosted voltage to perform the switching operation of the switch SWx to electrically connect or electrically insulate the input terminals 2201 and 2202 to the output terminals 2204 and 2205 .
- FIG. 4 shows a detection circuit 451 that includes a first detection circuit 451 a and a second detection circuit 451 b in accordance with some embodiments.
- the first detection circuit 451 a is configured to generate a plurality of control signals ⁇ p 1 through ⁇ pk according to the comparison results B LSB and Bcal, in which k is a natural number.
- the second detection circuit 451 b is configured to generate a plurality of control signals ⁇ n 1 through ⁇ nk according to values of B LSB _bar and Bcal_bar, in which the values of B LSB _bar and Bcal_bar are inverted values of B LSB and Bcal.
- the first detection circuit 451 a includes a logic circuit 4511 a, a logic circuit 4512 a and a plurality of flip-flops FFP 1 through FFPk.
- the logic circuit 4511 a is configured to determine whether the value of the LSB B LSB is same as the value of the calibration bit Bcal.
- the logic circuit 4511 a is an AND gate that is configured to perform an AND logic operation to determine whether the value of the LSB B LSB is same as the value of the calibration bit Bcal.
- the logic circuit 4512 a is configured to keep tracking an offset variation based on the LSB B LSB and the calibration bit Bcal. By keep tracking the offset variation of the comparator through the LSB B LSB and the calibration bit Bcal, the logic circuit 4512 a may determine whether a polarity of the offset changes. The logic circuit 4512 a may reset the control signals ⁇ p 1 through ⁇ pk via the flip-flops FFP 1 through FFPk when it determines that the polarity of the offset changes.
- the logic circuit 4512 a is a NOR gate that is configured to perform a NOR logic operation to the LSB B LSB and the calibration bit Bcal, but the disclosure is not limited thereto.
- the flip-flops FFP 1 through FFPk are configured to generate the control signals ⁇ p 1 through ⁇ pk according to outputs of the logic circuits 4511 a and 4512 a.
- the second detection circuit 451 b includes a logic circuit 4511 b, a logic circuit 4512 b and a plurality of flip-flops FFN 1 through FFNk.
- the logic circuit 4511 b is configured to determine whether the value of the bit B LSB _bar is same as the value of the bit Bcal_bar.
- the logic circuit 4512 b is configured to keep tracking an offset variation based on the bit B LSB _bar and the bit Bcal_bar. By keep tracking the offset variation of the comparator, the logic circuit 4512 b may determine whether a polarity of the offset changes.
- the logic circuit 4512 b may reset the control signals ⁇ n 1 through ⁇ nk via the flip-flops FFN 1 through FFNk when it determines that the polarity of the offset changes.
- the flip-flops FFN 1 through FFNk are configured to generate the control signals ⁇ n 1 through ⁇ nk according to outputs of the logic circuits 4511 b and 4512 b.
- the logic circuit 4511 b is an AND gate and the logic circuit 4512 b is a NOR gate, but the disclosure is not limited thereto.
- control signals ⁇ p 1 through ⁇ pk and ⁇ n 1 through ⁇ nk generated by the first and second detection circuits 451 a and 451 b are used to correct the offset of the comparator.
- the detection circuit 451 is operated in a background without interrupting the ADC operation. In this way, the performance of the SAR ADC is improved.
- FIG. 5 shows a comparator 530 in accordance with some embodiments of the disclosure.
- the comparator 530 includes a first pair of transistors M 1 and M 2 , a second pair of transistors M 3 and M 4 , and a transistor M 0 .
- the transistor M 0 may serve as a current source; the first pair of transistors M 1 and M 2 are configured to receive the input signals Vip and Vin; and the second pair of transistors M 3 and M 4 receive a clock signal clkc.
- the comparator 530 is configured to compare the input signals Vip and Vin and output the comparison results (V+, V ⁇ ) at connection node between the transistors M 1 and M 3 and a connection node between the transistors M 2 and M 4 .
- the comparator 530 may further include a plurality of capacitors C and a plurality of switches SP 2 through SPk and SN 2 through SNk, in which each of the switches SP 2 through SPk and SN 2 through SNk is coupled between a reference node and one of the capacitors C.
- the reference node may receive a reference voltage (e.g., voltage with a ground voltage level).
- Each of the capacitors C of the comparator 530 is coupled to the one of the connection nodes that output the comparison results (V+, V ⁇ ) of the comparator 530 .
- Each of the switches SP 2 through SPk and SN 2 through SNk is controlled to be switched on or off according to a control signal among the control signals ⁇ p 2 through ⁇ pk and ⁇ n 2 through ⁇ nk.
- the switches SP 2 through SPk are controlled by the control signals ⁇ p 2 through ⁇ nk; and the switches SN 2 through SNk are controlled by the control signals ⁇ n 2 through ⁇ nk.
- the control signals ⁇ p 2 through ⁇ pk and ⁇ n 2 through ⁇ nk are generated by the detecting circuit (e.g., detecting circuit 451 as shown in FIG. 4 ).
- the comparator 530 is configured to switch on or off each of the switches SP 2 through SPk and SN 2 through SNk according to the control signals ⁇ p 2 through ⁇ pk and ⁇ n 2 through ⁇ nk to correct the offset of the comparator 530 .
- FIG. 6A illustrates signal waveforms of a SAR ADC that includes an offset-free comparator in accordance with some embodiments.
- the signals P and N are inputted to the comparator of the SAR ADC (e.g., the comparator 130 of the SAR ADC 100 illustrated in FIG. 1 ).
- comparison operations are performed to determine values of bits B 0 , B 1 , B 2 and B LSB , respectively.
- a swapping operation is performed to interchange the signals P and N.
- the signal P before the swapping operation is the signal N after the swapping operation; and the signal N before the swapping operation is the signal P after the swapping operation.
- the arrows ARR 1 and ARR 2 shown in FIG. 6A illustrate the swapping operation.
- a comparison operation is performed to compare the swapped signals P and N to determine the calibration bit Bcal.
- the values of the LSB B LSB and the calibration bit Bcal are used to detect and correct the offset of the comparator 130 .
- the value of the LSB B LSB when the value of the LSB B LSB is different from the value of the calibration bit Bcal, it determines that the comparator of the SAR ADC is offset-free comparator. As shown in FIG. 6A , the value of the LSB B LSB is “0” which is different from the value (e.g., “1”) of the calibration bit Bcal. In this way, whether the comparator of the SAR ADC has offset is determined according to the values of LSB B LSB and the calibration bit Bcal.
- FIG. 6B illustrates signal waveforms of a SAR ADC that includes a comparator with offset in accordance with some embodiments.
- the signal P which is influenced by the offset is represented as dotted lines OFS_P.
- the swapping operation is performed, and the swapped signals are compared to determine the value of the calibration bit.
- the value of the calibration bit Bcal is “1” which is same as the value of the LSB B LSB . As such, it may determine that the comparator has offset.
- a polarity of offset may be determined according to the values of the LSB B LSB and calibration bit Bcal. For example, when the LSB B LSB is same as calibration bit Bcal at a high logic state (e.g., “1”), the offset of the comparator is the positive offset. When the when the LSB B LSB is same as calibration bit Bcal at a low logic state (e.g., “0”), the offset of the comparator is the negative offset.
- a voltage difference of the swapped signals after the swapping operation is larger than a voltage difference of the signals before the swapping operation.
- a method of detecting offset of a comparator of a SAR ADC in accordance with some embodiments is illustrated.
- a first intermediate analog signal is compared with a second intermediate analog signal to determine a least-significant-bit value.
- a swapping operation is performed on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal.
- the first swapped analog signal is compared with the second swapped analog signal after the swapping operation to generate a calibration bit value.
- whether the comparator has the offset is determined according to the least-significant-bit value and the calibration bit value.
- offset detection technique is performed based on a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal.
- the first intermediate analog signal is compared with the second intermediate analog signal to determine a least-significant-bit value.
- the first swapped analog signal is compared with the second swapped analog signal to generate the calibration bit value.
- the least-significant-bit value and the calibration bit value are used to detect whether the comparator has the offset, a polarity of the offset and is used to generate a plurality of control signal to correct the detected offset.
- the offset detection and calibration technique may be performed in background which is well embedded in the SAR ADC operation.
- the offset detection and calibration technique does not require dummy channel/comparator, but only needs a few simple auxiliary digital circuits. As a result, the performance of the ADC is improved at a low manufacturing cost.
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Abstract
Description
- This application claims the priority benefit of U.S. provisional application Ser. No. 62/831,199, filed on Apr. 9, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
- The disclosure generally relates to analog-to-digital converter (ADC), and more particularly to “top-plate swapping” technique to detect a comparator offset in a successive approximation register (SAR) ADC that is capable of enhancing the performance and robustness of the SAR ADC.
- ADCs with moderate resolution and gigahertz sampling rate are in high demand for a large number of applications in different fields such as wireless communication and consumer electronics. To achieve such high speed, the time interleaving (TI) structure is widely adopted. However, such a structure suffers from offset mismatch, gain mismatch and timing skew, which would degrade the performance of TI ADC. As demand for better performance of the ADC has grown recently, there has grown a need for a more creative technique to efficiently detect offset mismatch.
- Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present disclosure.
- A SAR ADC and a method of detecting offset that are capable of enhancing the performance and robustness of the SAR ADC are introduced.
- In some embodiments, the SAR ADC includes a switch circuit, a comparator and a calibration circuit. The switch circuit is configured to perform a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal. The comparator is coupled to the switching circuit and is configured to compare the first intermediate analog signal and the second intermediate analog signal before the swapping operation to generate a least-significant-bit value. The comparator is further configured to compare the first swapped analog signal and the second swapped analog signal after the swapping operation to generate a calibration bit value. The calibration circuit is configured to determine whether the comparator has an offset according to the least-significant-bit value and the calibration bit value.
- In some embodiments, the method of detecting an offset of a comparator includes steps of comparing a first intermediate analog signal and a second intermediate analog signal to determine a least-significant-bit value; performing a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal; comparing the first swapped analog signal and the second swapped analog signal after the swapping operation to generate a calibration bit value; and determining whether the comparator has the offset according to the least-significant-bit value and the calibration bit value.
- To make the disclosure more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
- The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
-
FIG. 1 is a schematic diagram illustrating a successive approximation register (SAR) analog to digital converter (ADC) in accordance with some embodiments. -
FIGS. 2 through 3 are schematic diagrams illustrating a switching circuit of a SAR ADC in accordance with some embodiments. -
FIG. 4 is schematic diagram illustrating a detail structure of a calibration circuit of a SAR ADC in accordance with some embodiments. -
FIG. 5 is schematic diagram illustrating a comparator of a SAR ADC in accordance with some embodiments. -
FIGS. 6A and 6B are timing diagrams illustrating waveforms of signals without and with comparator offset in accordance with some embodiments. -
FIG. 7 is a flowchart diagram illustrating a method of detecting offset of a comparator in accordance with some embodiments. - It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present disclosure. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Unless limited otherwise, the terms “connected,” “coupled,” and “mounted,” and variations thereof herein are used broadly and encompass direct and indirect connections, couplings, and mountings.
- Referring to
FIG. 1 , a schematic diagram of a successive approximation register (SAR) analog to digital converter (ADC) 100 is illustrated. The SARADC 100 may include input terminals IN1 and IN2, switches SWa and SWb,capacitor arrays switching circuit 120, acomparator 130, aSAR logic 140 and acalibration circuit 150. The input terminals IN1 and IN2 are configured to receive analog input signals Vip and Vin, respectively. The SAR ADC 100 may covert the analog input signals Vip and Vin to a digital output OUT that corresponds to the analog input signals Vip and Vin. - The switch SWa is coupled between the input terminal IN1 and the
capacitor array 110 a; and the switch SWb is coupled between the input terminal IN2 and thecapacitor array 110 b. The switches SWa and SWb are switched on or off according to at least one control signal. In some embodiments, the at least one control signal for controlling the switches SWa and SWb are a clock signal that are generated by a clock generator (not shown). However, the disclosure is not limited thereto, an any control signal that are capable of switching on or off the switches SWa and SWb falls within the scope of the disclosure. - The
capacitor array 110 a may include a plurality of capacitors (not shown) arranged in array. In some embodiments, thecapacitor array 110 a is configured to receive the analog input signal Vip and reference signals Vrefp and Vrefn, and is configured to generate an intermediate analog signal DACp according to the analog input signal Vip and the reference signals Vrefp and Vrefn. Similarly, thecapacitor array 110 b may include a plurality of capacitors (not shown) arranged in array. In some embodiments, thecapacitor array 110 b is configured to receive the analog input signal Vin and reference signals Vrefp and Vrefn, and is configured to generate an intermediate analog signal DACn according to the analog input signal Vin and the reference signals Vrefp and Vrefn. - In some embodiments, the SAR
ADC 100 may further include a sample and hold circuit (not shown) that is configured to sample and hold the analog input signals Vip and Vin to generate the sampled signals corresponding to the analog input signals Vip and Vin. In addition, thecapacitor arrays - The
switch circuit 120 is coupled between thecapacitor arrays comparator 130. Theswitch circuit 120 is configured to receive the intermediate analog signals DACp and DACn from thecapacitor arrays comparator 130 according to a control signal CLK_LSB. In some embodiments, theswitch circuit 120 may perform a swapping operation (or a top-plate swapping operation) to interchange the intermediate analog signals DACp and DACn to generate the signals P and N. For example, before the swapping operation, the intermediate analog signal DACp is outputted as the signal P, and the intermediate analog signal DACn is outputted as the signal N. After the swapping operation, the intermediate analog signal DACp is outputted as the signal N, and the intermediate analog signal DACn is outputted as the signal P. In some embodiments, after a least-significant-bit (LSB) of the digital output OUT has been decided, theswitch circuit 120 performs the swapping operation to interchange the intermediate analog signals DACp and DACn. - The
comparator 130 is coupled to theswitching circuit 120 to receive the signals P and N from theswitching circuit 120. Thecomparator 130 is configured to compare the signals P and N to generate a comparison result CMP. In some embodiments, before the swapping operation, the intermediate analog signals DACp and DACn have not been interchanged and are outputted as the signals P and N, respectively. Thecomparator 130 may compare the signals P and N to generate a first comparison result. After the swapping operation, the intermediate analog signals DACp and DACn are interchanged and are outputted as the signals N and P, respectively. Thecomparator 130 may compare the signals P and N to generate a second comparison result. The first comparison result may be used to determine a LSB BLSB and a calibration bit Bcal. - The
SAR logic 140 is coupled to thecomparator 130 and is configured to generate a digital output OUT according to the comparison result CMP. In some embodiments, theSAR logic 140 may store a digital value having a plurality of bits, and each bit of the digital value is updated during a sequence of comparation operations performed by thecomparator 130. The digital output OUT is generated at an end of the sequence of the comparison operations. For example, the sequence of the comparison operations is ended when the comparison operation for determining the LSB BLSB is completed, and the value of the LSB BLSB is updated. After the LSB BLSB is determined, theSAR logic 140 may control theswitch circuit 120 to perform the swapping operation (e.g., “top-swap operation”) to interchange the intermediate analog signals DACp and DACn to generate the swapped analog signals. An additional comparison operation is performed to compare the swapped analog signal to determine value of the calibration bit Bcal. TheSAR logic 140 may provide the LSB BLSB and the calibration bit Bcal to thecalibration circuit 150. - The
calibration circuit 150 is coupled between thecomparator 130 and theSAR logic 140, and is configured to detect offset of thecomparator 130 according to the LSB BLSB and the calibration bit Bcal. Thecalibration circuit 150 is further configured to correct the detected offset of thecomparator 130. - Referring to
FIG. 2 , aswitch circuit 220 in accordance with some embodiments are illustrated. Theswitch circuit 220 includesinput terminals control terminal 2203, andoutput terminals input terminals control terminal 2203 is configured to receive a control signal (e.g., CLK_LSB); and theoutput terminals switch circuit 220 may generate the signals P and N according to the control signal (e.g., CLK_LSB) and the intermediate analog signals DACp and DACn. In some embodiments, theswitch circuit 220 includes a plurality of switches SW1 through SW4, in which each of the switches SW1 through SW4 is coupled between one of theinput terminals switch circuit 220 and one of theoutput terminals switch circuit 220. For example, the switch SW1 is coupled between theinput terminal 2201 and theoutput terminal 2204; the switch SW2 is coupled between theinput terminal 2201 and theoutput terminal 2205; the switch SW3 is coupled between theinput terminal 2202 and theoutput terminal 2204; and the switch SW4 is coupled between theinput terminal 2202 and theoutput terminal 2205. In some embodiments, before the swapping operation, theswitch circuit 220 is configured to turn on the switches SW1 and SW4 to electrically connect theinput terminals output terminals switch circuit 220 is configured to turn on the switches SW2 and SW3 to electrically connect theinput terminals output terminals switch circuit 220 is a double bootstrapped switch that is adopted with monotonic switching, thereby improving a linearity of theswitch circuit 220 is improved. - Referring to
FIG. 3 , a structure of a switch SWx which may be any one of the switches SW1 through SW4 of theswitch circuit 220 in accordance with some embodiments is illustrated. The switch SWx may include a boost capacitor Cs and a transistor Ms. The drain terminal D of the transistor Ms is coupled to theinput terminal switch circuit 220, and the source terminal S of the transistor Ms is coupled to theoutput terminal switch circuit 220. - At the beginning, the boost capacitor Cs is pre-charged to a level of a bias voltage Vbias. In some embodiments, the level of the bias voltage Vbias is smaller than the level of a reference voltage Vdd to improve a reliability of the
switch circuit 220. When the control signal CLK_LSB arrives, the boost capacitor Cs may generate a boosted voltage which is provided to a gate of the transistor Ms. For example, a level of the boosted voltage is Vdd+Vbias. The transistor Ms is controlled by the boosted voltage to perform the switching operation of the switch SWx to electrically connect or electrically insulate theinput terminals output terminals -
FIG. 4 shows adetection circuit 451 that includes afirst detection circuit 451 a and asecond detection circuit 451 b in accordance with some embodiments. Thefirst detection circuit 451 a is configured to generate a plurality of control signals ϕp1 through ϕpk according to the comparison results BLSB and Bcal, in which k is a natural number. Thesecond detection circuit 451 b is configured to generate a plurality of control signals ϕn1 through ϕnk according to values of BLSB_bar and Bcal_bar, in which the values of BLSB_bar and Bcal_bar are inverted values of BLSB and Bcal. - In some embodiments, the
first detection circuit 451 a includes alogic circuit 4511 a, alogic circuit 4512 a and a plurality of flip-flops FFP1 through FFPk. Thelogic circuit 4511 a is configured to determine whether the value of the LSB BLSB is same as the value of the calibration bit Bcal. In some embodiments, thelogic circuit 4511 a is an AND gate that is configured to perform an AND logic operation to determine whether the value of the LSB BLSB is same as the value of the calibration bit Bcal. - The
logic circuit 4512 a is configured to keep tracking an offset variation based on the LSB BLSB and the calibration bit Bcal. By keep tracking the offset variation of the comparator through the LSB BLSB and the calibration bit Bcal, thelogic circuit 4512 a may determine whether a polarity of the offset changes. Thelogic circuit 4512 a may reset the control signals ϕp1 through ϕpk via the flip-flops FFP1 through FFPk when it determines that the polarity of the offset changes. In some embodiments, thelogic circuit 4512 a is a NOR gate that is configured to perform a NOR logic operation to the LSB BLSB and the calibration bit Bcal, but the disclosure is not limited thereto. The flip-flops FFP1 through FFPk are configured to generate the control signals ϕp1 through ϕpk according to outputs of thelogic circuits - In some embodiments, the
second detection circuit 451 b includes alogic circuit 4511 b, alogic circuit 4512 b and a plurality of flip-flops FFN1 through FFNk. Thelogic circuit 4511 b is configured to determine whether the value of the bit BLSB_bar is same as the value of the bit Bcal_bar. Thelogic circuit 4512 b is configured to keep tracking an offset variation based on the bit BLSB_bar and the bit Bcal_bar. By keep tracking the offset variation of the comparator, thelogic circuit 4512 b may determine whether a polarity of the offset changes. Thelogic circuit 4512 b may reset the control signals ϕn1 through ϕnk via the flip-flops FFN1 through FFNk when it determines that the polarity of the offset changes. The flip-flops FFN1 through FFNk are configured to generate the control signals ϕn1 through ϕnk according to outputs of thelogic circuits logic circuit 4511 b is an AND gate and thelogic circuit 4512 b is a NOR gate, but the disclosure is not limited thereto. - In some embodiments, the control signals ϕp1 through ϕpk and ϕn1 through ϕnk generated by the first and
second detection circuits detection circuit 451 is operated in a background without interrupting the ADC operation. In this way, the performance of the SAR ADC is improved. -
FIG. 5 shows acomparator 530 in accordance with some embodiments of the disclosure. Thecomparator 530 includes a first pair of transistors M1 and M2, a second pair of transistors M3 and M4, and a transistor M0. The transistor M0 may serve as a current source; the first pair of transistors M1 and M2 are configured to receive the input signals Vip and Vin; and the second pair of transistors M3 and M4 receive a clock signal clkc. Thecomparator 530 is configured to compare the input signals Vip and Vin and output the comparison results (V+, V−) at connection node between the transistors M1 and M3 and a connection node between the transistors M2 and M4. - In some embodiments, the
comparator 530 may further include a plurality of capacitors C and a plurality of switches SP2 through SPk and SN2 through SNk, in which each of the switches SP2 through SPk and SN2 through SNk is coupled between a reference node and one of the capacitors C. The reference node may receive a reference voltage (e.g., voltage with a ground voltage level). Each of the capacitors C of thecomparator 530 is coupled to the one of the connection nodes that output the comparison results (V+, V−) of thecomparator 530. Each of the switches SP2 through SPk and SN2 through SNk is controlled to be switched on or off according to a control signal among the control signals ϕp2 through ϕpk and ϕn2 through ϕnk. For example, the switches SP2 through SPk are controlled by the control signals ϕp2 through ϕnk; and the switches SN2 through SNk are controlled by the control signals ϕn2 through ϕnk. The control signals ϕp2 through ϕpk and ϕn2 through ϕnk are generated by the detecting circuit (e.g., detectingcircuit 451 as shown inFIG. 4 ). Thecomparator 530 is configured to switch on or off each of the switches SP2 through SPk and SN2 through SNk according to the control signals ϕp2 through ϕpk and ϕn2 through ϕnk to correct the offset of thecomparator 530. -
FIG. 6A illustrates signal waveforms of a SAR ADC that includes an offset-free comparator in accordance with some embodiments. The signals P and N are inputted to the comparator of the SAR ADC (e.g., thecomparator 130 of theSAR ADC 100 illustrated inFIG. 1 ). In time periods T0, T1, T2 and T3, comparison operations are performed to determine values of bits B0, B1, B2 and BLSB, respectively. After the value of BLSB is determined, a swapping operation is performed to interchange the signals P and N. As a result of the swapping operation, the signal P before the swapping operation is the signal N after the swapping operation; and the signal N before the swapping operation is the signal P after the swapping operation. The arrows ARR1 and ARR2 shown inFIG. 6A illustrate the swapping operation. In the period T4 after the swapping operation, a comparison operation is performed to compare the swapped signals P and N to determine the calibration bit Bcal. The values of the LSB BLSB and the calibration bit Bcal are used to detect and correct the offset of thecomparator 130. - In some embodiments, when the value of the LSB BLSB is different from the value of the calibration bit Bcal, it determines that the comparator of the SAR ADC is offset-free comparator. As shown in
FIG. 6A , the value of the LSB BLSB is “0” which is different from the value (e.g., “1”) of the calibration bit Bcal. In this way, whether the comparator of the SAR ADC has offset is determined according to the values of LSB BLSB and the calibration bit Bcal. -
FIG. 6B illustrates signal waveforms of a SAR ADC that includes a comparator with offset in accordance with some embodiments. As a result of the offset, the signal P which is influenced by the offset is represented as dotted lines OFS_P. After the swapping operation is performed, and the swapped signals are compared to determine the value of the calibration bit. As the example shown inFIG. 6B , the value of the calibration bit Bcal is “1” which is same as the value of the LSB BLSB. As such, it may determine that the comparator has offset. - In some embodiments, a polarity of offset (e.g., positive offset or negative offset) may be determined according to the values of the LSB BLSB and calibration bit Bcal. For example, when the LSB BLSB is same as calibration bit Bcal at a high logic state (e.g., “1”), the offset of the comparator is the positive offset. When the when the LSB BLSB is same as calibration bit Bcal at a low logic state (e.g., “0”), the offset of the comparator is the negative offset.
- If the comparator has the offset, a voltage difference of the swapped signals after the swapping operation is larger than a voltage difference of the signals before the swapping operation. As such, it is beneficial for the comparator to determine the value of the calibration bit Bcal. Besides, this can significantly diminish the probability of metastability compared to other offset calibration techniques.
- Referring to
FIG. 7 , a method of detecting offset of a comparator of a SAR ADC in accordance with some embodiments is illustrated. In step S710, a first intermediate analog signal is compared with a second intermediate analog signal to determine a least-significant-bit value. In step S720, a swapping operation is performed on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal. In step S730, the first swapped analog signal is compared with the second swapped analog signal after the swapping operation to generate a calibration bit value. In step S740, whether the comparator has the offset is determined according to the least-significant-bit value and the calibration bit value. - From the above embodiments, offset detection technique is performed based on a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal. Before the swapping operation is performed, the first intermediate analog signal is compared with the second intermediate analog signal to determine a least-significant-bit value. After the swapping operation is performed, the first swapped analog signal is compared with the second swapped analog signal to generate the calibration bit value. The least-significant-bit value and the calibration bit value are used to detect whether the comparator has the offset, a polarity of the offset and is used to generate a plurality of control signal to correct the detected offset. In the present application, the offset detection and calibration technique may be performed in background which is well embedded in the SAR ADC operation. The offset detection and calibration technique does not require dummy channel/comparator, but only needs a few simple auxiliary digital circuits. As a result, the performance of the ADC is improved at a low manufacturing cost.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.
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