US20200279933A1 - Interlayer dielectric replacement techniques with protection for source/drain contacts - Google Patents
Interlayer dielectric replacement techniques with protection for source/drain contacts Download PDFInfo
- Publication number
- US20200279933A1 US20200279933A1 US16/290,182 US201916290182A US2020279933A1 US 20200279933 A1 US20200279933 A1 US 20200279933A1 US 201916290182 A US201916290182 A US 201916290182A US 2020279933 A1 US2020279933 A1 US 2020279933A1
- Authority
- US
- United States
- Prior art keywords
- source
- interlayer dielectric
- dielectric layer
- layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 201
- 239000011229 interlayer Substances 0.000 title claims abstract description 69
- 239000010410 layer Substances 0.000 claims abstract description 514
- 239000004065 semiconductor Substances 0.000 claims abstract description 237
- 230000008569 process Effects 0.000 claims abstract description 149
- 230000005669 field effect Effects 0.000 claims abstract description 35
- 239000000956 alloy Substances 0.000 claims abstract description 34
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 33
- 239000003989 dielectric material Substances 0.000 claims description 58
- 239000000463 material Substances 0.000 claims description 58
- 238000001465 metallisation Methods 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 42
- 238000000151 deposition Methods 0.000 claims description 41
- 239000007769 metal material Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000000059 patterning Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 5
- 229910000676 Si alloy Inorganic materials 0.000 claims description 5
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 claims description 3
- PNXKRHWROOZWSO-UHFFFAOYSA-N [Si].[Ru] Chemical compound [Si].[Ru] PNXKRHWROOZWSO-UHFFFAOYSA-N 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 abstract description 23
- 229910021332 silicide Inorganic materials 0.000 abstract description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 17
- 238000004519 manufacturing process Methods 0.000 description 25
- 125000006850 spacer group Chemical group 0.000 description 15
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 14
- 230000008021 deposition Effects 0.000 description 12
- 238000012545 processing Methods 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000002019 doping agent Substances 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910016344 CuSi Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910019895 RuSi Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
- 239000000908 ammonium hydroxide Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000001741 metal-organic molecular beam epitaxy Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- HMMGMWAXVFQUOA-UHFFFAOYSA-N octamethylcyclotetrasiloxane Chemical compound C[Si]1(C)O[Si](C)(C)O[Si](C)(C)O[Si](C)(C)O1 HMMGMWAXVFQUOA-UHFFFAOYSA-N 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052774 Proactinium Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910004490 TaAl Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- -1 WAl Inorganic materials 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 229910007880 ZrAl Inorganic materials 0.000 description 1
- ZILJFRYKLPPLTO-UHFFFAOYSA-N [C].[B].[Si] Chemical compound [C].[B].[Si] ZILJFRYKLPPLTO-UHFFFAOYSA-N 0.000 description 1
- XWCMFHPRATWWFO-UHFFFAOYSA-N [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] Chemical compound [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] XWCMFHPRATWWFO-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- JQJCSZOEVBFDKO-UHFFFAOYSA-N lead zinc Chemical compound [Zn].[Pb] JQJCSZOEVBFDKO-UHFFFAOYSA-N 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002135 nanosheet Substances 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- KJXBRHIPHIVJCS-UHFFFAOYSA-N oxo(oxoalumanyloxy)lanthanum Chemical compound O=[Al]O[La]=O KJXBRHIPHIVJCS-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- UVGLBOPDEUYYCS-UHFFFAOYSA-N silicon zirconium Chemical compound [Si].[Zr] UVGLBOPDEUYYCS-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02592—Microstructure amorphous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Definitions
- This disclosure generally relates to semiconductor fabrication techniques and, in particular, middle-of the-line fabrication techniques for FET (field effect transistor) devices.
- a FinFET device comprises a three-dimensional fin-shaped FET structure which includes at least one vertical semiconductor fin structure formed on a substrate, a gate structure formed over a portion of the vertical semiconductor fin, and source/drain regions formed from portions of the vertical semiconductor fin which extend from both sides of the gate structure. The portion of the vertical semiconductor fin that is covered by the gate structure between the source/drain regions comprises a channel region of the FinFET device.
- a reduction in the parasitic capacitance between active devices can be achieved by utilizing a low-k dielectric material to form an initial interlayer dielectric (ILD) layer at the contact/transistor level, which encapsulates the source/drain contacts and metal gate structures.
- ILD interlayer dielectric
- the low-k dielectric material that forms the initial ILD layer can become damaged and contaminated as a result of the various fabrication processes (e.g., reactive ion etching, thermal annealing, chemical mechanical polishing, etc.) that are utilized to form source/drain contacts (e.g., trench silicide contacts) and metal gates (e.g., replacement metal gate process), etc., wherein such damage and contamination leads to an undesirable increase in the effective dielectric constant of the initial low-k ILD layer.
- various fabrication processes e.g., reactive ion etching, thermal annealing, chemical mechanical polishing, etc.
- source/drain contacts e.g., trench silicide contacts
- metal gates e.g., replacement metal gate process
- Embodiments of the invention include device and methods for fabricating a semiconductor integrated circuit (IC) device, which implement an ILD replacement process to replace an initial sacrificial ILD layer with a low-k ILD layer, while forming silicide or dielectric capping layers to protect source/drain contacts from etch damage during the ILD replacement process.
- IC semiconductor integrated circuit
- a method for fabricating a semiconductor integrated circuit (IC) device comprises: forming a field-effect transistor device on a semiconductor substrate, wherein the field-effect transistor device comprise a gate structure and source/drain layers; forming a sacrificial interlayer dielectric layer to encapsulate the field-effect transistor device; performing a metallization process to form metallic source/drain contacts in the sacrificial interlayer dielectric layer in contact with source/drain layers of the field-effect transistor device; depositing a semiconductor layer on the sacrificial interlayer dielectric layer and the metallic source/drain contacts; performing a thermal anneal process to induce a reaction between the semiconductor layer and the metallic source-drain contacts to form metal-semiconductor alloy capping layers in upper surface regions of the metallic source/drain contacts; removing unreacted portions of the semiconductor layer remaining after the thermal anneal process; performing an etch process to remove the sacrificial interlayer dielectric layer, wherein the etch process is selective to the
- a method for fabricating a semiconductor IC device comprises: forming a field-effect transistor device on a semiconductor substrate, wherein the field-effect transistor device comprises a gate structure and source/drain layers; forming a sacrificial interlayer dielectric layer to encapsulate the field-effect transistor device, wherein an upper surface of the sacrificial interlayer dielectric layer is disposed above an upper surface of the gate structure of the field-effect transistor device; performing a metallization process to form metallic source/drain contacts in the sacrificial interlayer dielectric layer in contact with the source/drain layers of the field-effect transistor device; performing a metal recess process to recess exposed surfaces of the metallic source/drain contacts to a target level below an upper surface of the sacrificial interlayer dielectric layer; forming dielectric capping layers on the recessed surfaces of the metallic source/drain contacts; performing an etch process to remove the sacrificial interlayer dielectric layer, wherein the etch process is selective to the dielectric
- Another embodiment includes a semiconductor integrated circuit device which comprises: a field-effect transistor device disposed on a semiconductor substrate, wherein the field-effect transistor device comprises a gate structure and first and second source/drain layers; a low-k interlayer dielectric layer encapsulating the field-effect transistor device; first and second metallic source/drain contacts disposed in the low-k interlayer dielectric layer in contact with the first and second source/drain layers, respectively, of the field-effect transistor device; and first and second metal-semiconductor alloy capping layers disposed in upper surface regions of the first and second metallic source/drain contacts, respectively.
- the first and second metal-semiconductor alloy capping layers comprise a cobalt-silicon alloy or a ruthenium-silicon alloy
- the low-k interlayer dielectric layer comprises dielectric material having a dielectric constant k of about 3.0 or less.
- FIGS. 1A, 1B, 1C, and 1D are schematic views of a semiconductor IC device at an intermediate stage of fabrication after performing an interlayer dielectric layer replacement process to replace a sacrificial ILD layer with a low-k ILD dielectric layer, according to an embodiment of the invention, wherein:
- FIG. 1A is a schematic cross-sectional side view of the semiconductor IC device along line 1 A- 1 A shown in FIG. 1D ;
- FIG. 1B is a schematic cross-sectional side view of the semiconductor IC device along line 1 B- 1 B shown in FIG. 1D ;
- FIG. 1C is a schematic cross-sectional side view of the semiconductor IC device along line 1 C- 1 C shown in FIG. 1D ;
- FIG. 1D is a schematic top plan view of the semiconductor IC device shown in FIGS. 1A, 1B and 1C .
- FIGS. 2A through 7 schematically illustrate a process for fabricating a semiconductor IC device in which an interlayer dielectric layer replacement process is implemented to replace an initial sacrificial ILD layer with a low-k ILD layer, according to an embodiment of the invention, wherein:
- FIG. 2A is a schematic cross-sectional side view of the semiconductor IC device at an intermediate stage of fabrication in which FinFET devices with source/drain layers and metal gate structures are formed on a semiconductor substrate and encapsulated in sacrificial ILD layers;
- FIG. 2B is a schematic cross-sectional side view of the semiconductor IC device along line 2 B- 2 B shown in FIG. 2A ;
- FIG. 3A is a schematic cross-sectional side view of the semiconductor IC device shown in FIG. 2A after forming an etch mask and patterning the sacrificial ILD layers using the etch mask to form source/drain contact openings that expose source/drain layers;
- FIG. 3B is a schematic cross-sectional side view of the semiconductor IC device along line 3 B- 3 B shown in FIG. 3A ;
- FIG. 4A is a schematic cross-sectional side view of the semiconductor IC device shown in FIG. 3A after stripping away a remaining portion of the etch mask, performing a source/drain contact metallization process to fill the source/drain contact openings with contact metallization, and after forming a semiconductor layer over the sacrificial ILD layer and the contact metallization;
- FIG. 4B is a schematic cross-sectional side view of the semiconductor IC device along line 4 B- 4 B shown in FIG. 4A ;
- FIG. 5 is a schematic cross-sectional side view of the semiconductor IC device of FIG. 4A after performing a thermal anneal process to induce a reaction between the semiconductor material of the semiconductor layer and metallic material in an upper surface region of the contact metallization to form metal-semiconductor alloy capping layers;
- FIG. 6A is a schematic cross-sectional side view of the semiconductor IC device of FIG. 5 after stripping away unreacted portions of the semiconductor layer which remain following the thermal anneal process, and performing an etch process to remove the sacrificial ILD layers;
- FIG. 6B is a schematic cross-sectional side view of the semiconductor IC device along line 6 B- 6 B shown in FIG. 6A ;
- FIG. 7 is a schematic cross-sectional side view of the semiconductor IC device of FIG. 6A after depositing a layer of low-k dielectric material to replace the sacrificial ILD layers with a low-k ILD layer.
- FIGS. 8 through 10 schematically illustrate a process for fabricating a semiconductor IC device in which an interlayer dielectric layer replacement process is implemented to replace an initial sacrificial ILD layer with a low-k ILD layer, according to another embodiment of the invention, wherein:
- FIG. 8 is a schematic cross-sectional side view of the semiconductor IC device at an intermediate stage of fabrication wherein FinFET devices with source/drain layers and metal gate structures are formed on a semiconductor substrate and encapsulated in sacrificial ILD layers, and wherein source/drain contact metallization is formed within source/drain contact openings etched in the sacrificial ILD layers;
- FIG. 9 is a schematic cross-sectional side view of the semiconductor IC device of FIG. 8 after forming a protective dielectric capping layer on the contact metallization.
- FIG. 10 is a schematic cross-sectional side view of the semiconductor IC device of FIG. 9 after performing an etch back process to remove the sacrificial ILD layers and after depositing a layer of low-k dielectric material to replace the sacrificial ILD layers with a low-k ILD layer.
- FIGS. 11 through 13 schematically illustrate a process for fabricating a semiconductor IC device in which an interlayer dielectric layer replacement process is implemented to replace an initial sacrificial ILD with a low-k ILD dielectric layer, according to another embodiment of the invention, wherein:
- FIG. 11 is a schematic cross-sectional side view of the semiconductor IC device at an intermediate stage of fabrication wherein FinFET devices with source/drain layers and metal gate structures are formed on a semiconductor substrate and encapsulated in a sacrificial ILD layer, and after forming an etch mask and patterning the sacrificial ILD layer using the etch mask to form discrete source/drain contact openings to expose the source/drain layers;
- FIG. 12 is a schematic cross-sectional side view of the semiconductor IC device shown in FIG. 11 after stripping away a remaining portion of the etch mask, performing a source/drain contact metallization process to fill the source/drain contact openings with metallization to form discrete metallic source/drain contacts, forming a semiconductor layer over the sacrificial ILD layer and the discrete metallic source/drain contacts, and after performing a thermal anneal process to induce a reaction between semiconductor material of the semiconductor layer and metallic material in upper surface regions of the discrete metallic source/drain contacts to form metal-semiconductor alloy capping layers; and
- FIG. 13 is a schematic cross-sectional side view of the semiconductor IC device of FIG. 12 after stripping away unreacted portions of the semiconductor layer which remain following the thermal anneal process, removing the sacrificial ILD layer, and after depositing a layer of low-k dielectric material to form a low-k ILD layer.
- Embodiments of the invention will now be described in further detail with regard devices and methods for fabricating a semiconductor IC device, which implement an ILD replacement process to replace an initial sacrificial ILD layer with a low-k ILD layer, while forming silicide or dielectric capping layers to protect source/drain contacts from etch damage during the ILD replacement process.
- ILD replacement process to replace an initial sacrificial ILD layer with a low-k ILD layer
- silicide or dielectric capping layers to protect source/drain contacts from etch damage during the ILD replacement process.
- FIGS. 1A, 1B, 1C, and 1D are schematic views of a semiconductor integrated circuit device 100 at an intermediate stage of fabrication after performing an ILD layer replacement process to replace a sacrificial ILD layer with a low-k ILD layer, according to an embodiment of the invention.
- FIG. 1D is a schematic top plan view (X-Y plane) of the semiconductor integrated circuit device 100
- FIGS. 1A, 1B and 1C are cross-sectional side views of the semiconductor IC device 100 along planes that are represented by respective lines shown in FIG. 1D .
- FIG. 1A is a schematic cross-sectional side view (Y-Z plane) of the semiconductor IC device 100 along line 1 A- 1 A in FIG. 1D .
- FIG. 1B is a schematic cross-sectional side view (X-Z plane) of the semiconductor IC device 100 along line 1 B- 1 B in FIG. 1D .
- FIG. 1C is a schematic cross-sectional side view (Y-Z plane) of the semiconductor IC device 100 along line 1 C- 1 C in FIG. 1D .
- the semiconductor IC device 100 comprises a semiconductor substrate 110 , a shallow trench isolation (STI) layer 120 , a plurality of vertical semiconductor fins 115 , gate structures G 1 , G 2 , and G 3 , source/drain (S/D) layers 140 , source/drain contacts 150 (e.g., trench silicide (T/S contacts), and a low-k ILD layer 170 .
- the gate structures G 1 , G 2 , and G 3 comprise high-k dielectric/metal gate (HKMG) structures 130 , gate capping layers 132 , and gate sidewall spacer 134 , which are formed over respective channel regions of the vertical semiconductor fins 115 .
- HKMG high-k dielectric/metal gate
- the gate structures G 1 , G 2 , and G 3 are formed using a replacement metal gate (RMG) process in which dummy gate structures are initially formed and then replaced with the HKMG structures 130 using known methods.
- the gate capping layers 132 and gate sidewall spacers 134 are formed of dielectric materials such as silicon nitride (SiN), silicon boron carbon nitride (SiBCN), and other types of dielectric materials commonly used to form gate capping layers and gate sidewall spacers.
- the portions of the vertical semiconductor fins 115 which are disposed between the gate structures G 1 , G 2 , and G 3 serve as source/drain regions for first and second FinFET devices D 1 and D 2 .
- the source/drain layers 140 comprise epitaxial semiconductor layers that are grown on the portions of the vertical semiconductor fins 115 that are disposed between the gate structures G 1 , G 1 , and G 3 . As shown in the exemplary embodiment of FIGS.
- each FinFET device D 1 and D 2 is a multi-fin FinFET structure comprising two vertical semiconductor fins 115 , wherein the source/drain layers formed on portions of adjacent vertical semiconductor fins 115 are merged to form common source/drain layers 140 , and wherein the source/drain layers 140 on each side of the gate structure G 2 are commonly connected to a respective single vertical source/drain contact 150 .
- the middle gate structure G 2 comprises a functional gate structure of the first and second FinFET devices D 1 and D 2
- the gate structures G 1 and G 3 are non-functional gate structures that are utilized for purposes of, e.g., facilitating uniform formation of the source/drain layers 140 and the source/drain contacts 150 on each side of the functional gate structure G 2 , and providing isolation for the source/drain layers 140 , etc.
- the functional gate structure G 2 extends over the channel regions of the vertical semiconductor fins 115 for both FinFET devices D 1 and D 2 . In this configuration, the gate structure G 2 serves as a common gate structure for the FinFET devices D 1 and D 2 , with the source/drain layers 140 formed on opposing sides of the functional gate structure G 2 .
- the end portions of the vertical semiconductor fins 115 of the FinFET devices D 1 and D 2 terminate inside the non-functional gate structures G 1 and G 3 and, thus, are not exposed on the opposite sides of the gate structures G 1 and G 3 .
- the vertical semiconductor fins 115 of the non-functioning gate structures G 1 and G 3 are not functional FET channel layers, and the non-functioning gate structures G 1 and G 3 merely serve as structures to confine the epitaxial growth of the semiconductor material which forms the source/drain layers 140 , as well as confine the size of the source/drain contacts 150 .
- the ILD layer 170 comprises a low-k dielectric material which is formed as part of an ILD replacement process module following a RMG process module and a source/drain contact process module.
- the ILD replacement process is performed to remove portions of an initial sacrificial ILD layer 125 (e.g., silicon oxide material) disposed between the gate structures G 1 , G 2 and G 3 and the source/drain contacts 150 (see FIG. 1B ).
- the initial sacrificial ILD layer 125 can be formed of a material such as silicon oxide, and replaced with a low-k dielectric material (e.g., k ⁇ 3.0, where is wherein k denotes a relative dielectric constant).
- the ILD layer 170 can be formed with Octamethylcyclotetrasiloxane (OMCTS), SiCOH, porous dielectrics, and other known ultra-low-k (ULK) dielectric materials (with k less than about 2.7) which would provide low dielectric permittivity, resulting in power consumption and signal delay in the semiconductor integrated circuit device 100 .
- OCTS Octamethylcyclotetrasiloxane
- ULK ultra-low-k
- embodiments of the invention include various techniques that are incorporated as part the exemplary ILD replacement modules to protect the source/drain contacts 150 from damage when replacing the initial sacrificial ILD material 125 with the low-k dielectric material.
- FIGS. 2A through 7 schematically illustrate a process for fabricating a semiconductor integrated circuit device in which an ILD layer replacement process is implemented to replace an initial sacrificial ILD layer with a low-k ILD layer, according to an embodiment of the invention.
- FIGS. 2A and 2B are schematic views of the semiconductor IC device 100 at an intermediate stage of fabrication in which FinFET devices D 1 and D 2 with source/drain layers 140 and metal gate structures G 1 , G 2 , and G 3 are formed on a semiconductor substrate 110 and encapsulated in sacrificial ILD layers 125 and 125 - 1 .
- FIG. 2A is a schematic cross-sectional side view (Y-Z plane) of the semiconductor IC device of FIG.
- FIG. 2B is a schematic cross-sectional side view (X-Z plane) of the semiconductor IC device along line 2 B- 2 B shown in FIG. 2A .
- the intermediate device structure shown in FIGS. 2A and 2B can be fabricated using known methods and materials.
- the semiconductor substrate 110 may comprise various structures and layers of semiconductor material.
- the semiconductor substrate 110 is a bulk semiconductor substrate (e.g., wafer) that is formed of silicon (Si) or germanium (Ge), or other types of semiconductor substrate materials that are commonly used in bulk semiconductor fabrication processes such as a silicon-germanium alloy, compound semiconductor materials (e.g. III-V), etc.
- the semiconductor substrate 110 is an active semiconductor layer of an SOI (silicon-on-insulator) substrate, GeOI (germanium-on-insulator) substrate, or other type of semiconductor-on-insulator substrate, which comprises an insulating layer (e.g., oxide layer) disposed between a base substrate layer (e.g., silicon substrate) and the active semiconductor layer (e.g., Si, Ge, etc.) in which active circuit components are formed as part of a front-end-of-line (FEOL) structure.
- SOI silicon-on-insulator
- GeOI germanium-on-insulator
- insulating layer e.g., oxide layer
- the X-Y plane represents a plane that is parallel to the plane of the semiconductor substrate 110 (e.g., wafer) being processed.
- the STI layer 120 and the vertical semiconductor fins 115 can be fabricated using various methods.
- the vertical semiconductor fins 115 can be formed by patterning an active silicon layer (e.g., crystalline silicon, crystalline SiGe, III-V compound semiconductor material, etc.) at the surface of a bulk semiconductor substrate or the SOI substrate to form a pattern of vertical semiconductor fins in different device regions across the semiconductor wafer, four of which are shown in FIG. 2B for ease of illustration.
- the vertical semiconductor fins 115 are patterned from a crystalline Si or SiGe layer that is epitaxially grown on top of a bulk silicon substrate or a bulk germanium substrate.
- a crystalline SiGe layer that is formed using an epitaxial growth process may comprise a relaxed SiGe layer or a strained SiGe layer.
- strain engineering is utilized to enhance the carrier mobility for MOS transistors, wherein different types of Si—SiGe heterostructures can be fabricated to obtain and/or optimize different properties for CMOS FET devices.
- silicon can be epitaxially grown on a SiGe substrate layer to form a strained Si layer.
- a strained SiGe layer can be epitaxially grown on a silicon substrate layer.
- a strained-Si/relaxed-SiGe structure provides a tensile strain which primarily improves electron mobility for n-type FET devices, while a strained-SiGe/relaxed-Si structure provides a compressive strain which primarily improves hole mobility for p-type FET devices.
- a layer of insulating material can be deposited to cover the vertical semiconductor fins 115 , and then planarized (via chemical-mechanical planarization (CMP)) down to the top of the vertical semiconductor fins 115 , and then further recessed using an etch-back process (e.g., dry etch process such as selective Reactive Ion Etch (ME) process, a wet etch process, or a combination of dry and wet etch processes) to form the STI layer 120 .
- CMP chemical-mechanical planarization
- ME selective Reactive Ion Etch
- a wet etch process a combination of dry and wet etch processes
- an upper surface of the isolation layer 120 is shown in phantom as a dashed line in FIGS. 1A and 2A to show the baseline active fin height H.
- the isolation layer 120 is selectively etched using RIE, although other etching processes may be employed. A timed etch can be performed to remove a desired amount of insulating material to expose the upper portions of the vertical semiconductor fin structures 115 .
- the vertical semiconductor fins 115 can be formed using a process in which the STI layer 120 is first deposited and then etched using RIE or deep RIE to form a pattern of trenches in the isolation layer 120 down to the semiconductor substrate 110 , which corresponds to a pattern of vertical semiconductor fins to be formed.
- the vertical semiconductor fins 115 are then formed by epitaxially growing crystalline semiconductor material, starting on the exposed surfaces of the semiconductor substrate 110 at the bottom of the trenches, using ART (aspect ratio trapping) techniques.
- ART enables selective epitaxial growth of crystalline Si, SiGe, or III-V compound semiconductor material, for example, to fill high aspect ratio trenches formed in an insulating layer, and thereby form high quality active channel layers for FinFET devices.
- the crystalline SiGe layer (or other types of epitaxial semiconductor layers) can be epitaxially grown using known techniques, such as CVD (chemical vapor deposition), MOCVD (metal-organic chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), MBE (molecular beam epitaxy), VPE (vapor-phase epitaxy), MOMBE (metal organic molecular beam epitaxy), or other known epitaxial growth techniques.
- CVD chemical vapor deposition
- MOCVD metal-organic chemical vapor deposition
- LPCVD low pressure chemical vapor deposition
- MBE molecular beam epitaxy
- VPE vapor-phase epitaxy
- MOMBE metal organic molecular beam epitaxy
- dummy gate structures are fabricated using any known process flow which comprises, e.g., sequentially depositing a dummy gate oxide layer (e.g., silicon oxide), a dummy gate electrode layer (e.g., polysilicon or amorphous silicon), and hardmask layer (e.g., SiN) over the substrate and patterning the layers to form dummy gate structures with dummy gate capping layers to define gate regions of the gate structures G 1 , G 2 , and G 3 .
- the gate sidewall spacers 134 are formed by depositing one or more conformal layers of dielectric materials over the dummy gate structures, and then patterning the conformally deposited dielectric layer(s) to form the gate sidewall spacers 134 .
- the gate sidewall spacers 134 are formed of one or more layers of dielectric material such as SiN, SiBCN, SiOCN, or other dielectric materials which are suitable for use as insulating gate sidewall spacers for gate structures of FinFET devices.
- the one or more layers of dielectric material can be deposited using plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable deposition methods which enable the deposition of thin films of dielectric material with high conformality, and then patterned using a directional dry etch process (e.g., RIE) as is known in the art.
- PECVD plasma-enhanced chemical vapor deposition
- ALD atomic layer deposition
- RIE directional dry etch process
- the process flow continues with forming the source/drain layers 140 on the exposed S/D regions of the vertical semiconductor fins 115 .
- the source/drain layers 140 are formed by growing epitaxial semiconductor material on the exposed surfaces of the S/D regions of the vertical semiconductor fins 115 adjacent to the gate structures G 1 , G 2 and G 3 .
- the type of epitaxial material and doping used to form the source/drain layers 140 will vary depending on whether the FinFET devices D 1 and D 2 are P-type or N-type devices. As shown in FIG.
- the source/drain layers 140 are epitaxially grown so that adjacent source/drain layers 140 formed on adjacent S/D regions of the vertical semiconductor fins 115 for the respective FinFET devices D 1 and D 2 and can merge (in the X-direction) to collectively form a single source/drain layer.
- the source/drain layers 140 are doped using known techniques.
- the source/drain layers 140 are “in-situ” doped during epitaxial growth by adding a dopant gas to the source deposition gas (i.e., the Si-containing gas).
- a dopant gas i.e., the Si-containing gas.
- Suitable n-type dopants include but are not limited to phosphorous (P) and arsenic (As), and suitable p-type dopants include but are not limited to boron (B).
- Exemplary dopant gases may include a boron-containing gas such as BH 3 for pFETs or a phosphorus or arsenic containing gas such as PH 3 or AsH 3 for nFETs, wherein the concentration of impurity in the gas phase determines its concentration in the epitaxially grown semiconductor material.
- a boron-containing gas such as BH 3 for pFETs or a phosphorus or arsenic containing gas such as PH 3 or AsH 3 for nFETs, wherein the concentration of impurity in the gas phase determines its concentration in the epitaxially grown semiconductor material.
- a boron-containing gas such as BH 3 for pFETs
- a phosphorus or arsenic containing gas such as PH 3 or AsH 3 for nFETs
- Dopant techniques include but are not limited to, ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, in-situ epitaxy growth, or any suitable combination of those techniques.
- the process flow continues with depositing and planarizing a layer of dielectric material to form the initial sacrificial ILD layer 125 .
- the sacrificial ILD layer 125 is formed, for example, by depositing a layer of insulating material over the surface of the semiconductor substrate to cover the dummy gate structures, and then planarizing the surface of the semiconductor substrate down to upper surface of a hard mask layer (or dummy gate capping layer) of the dummy gate structures.
- the sacrificial ILD layer 125 is formed of silicon oxide.
- the sacrificial ILD layer 125 may comprise a single deposited layer of insulating material, or multiple layers of insulating material (e.g., a first layer of a flowable oxide and a second layer of insulating material formed on the first layer).
- the sacrificial ILD layer 125 may be deposited using known deposition techniques, such as, for example, ALD, PECVD, PVD (physical vapor deposition), or spin-on deposition.
- an RMG process comprises removing the dummy gate capping layers to expose the underlying sacrificial material of the dummy gate electrode layers (sacrificial polysilicon layer, or amorphous silicon layer), removing the dummy gate electrode layers selective to the materials of the dummy gate oxide layer and the gate sidewall spacers 134 .
- the sacrificial dummy gate electrode layers can be removed using a selective dry etch or wet etch process with suitable etch chemistries, including ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH), or SF 6 plasma.
- etch chemistries including ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH), or SF 6 plasma.
- TMAH tetramethylammonium hydroxide
- SF 6 plasma SF 6 plasma.
- the etching of the dummy gate electrode layer is selective to the dummy gate oxide layer to thereby protect the portions of the vertical semiconductor fins 115 within the gate regions G 1 , G 2 and G 3 from being etched during the dummy gate electrode etch process.
- an oxide etch process is performed to etch away the dummy gate oxide layers selective to the materials of the vertical semiconductor fins 115 and the gate sidewall spacers 134 .
- the sacrificial materials (e.g., dummy polysilicon and oxide layers) of the dummy gate structures are etched away without damaging the exposed portions of the vertical semiconductor fins 115 within the gate regions G 1 , G 2 , and G 3 .
- the HKMG structures 130 are formed by depositing one or more conformal layers of high-k gate dielectric material to conformally cover the exposed surfaces of the vertical semiconductor fins 115 within the gate regions G 1 , G 2 , and G 3 , followed by the deposition of one or more layers of metallic material over the conformal deposited high-k gate dielectric material to fill the gate regions G 1 , G 2 and G 3 with the metallic material.
- the conformal high-k gate dielectric layers are formed of a high-k dielectric material having a dielectric constant (k) of about 3.9 or greater.
- the gate dielectric material can include but is not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium zirconium oxide, and nitride films thereof.
- the high-k dielectric may comprise lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
- the high-k dielectric material may further include dopants such as lanthanum and aluminum.
- the conformal gate dielectric layer is formed with a thickness in a range of about 0.5 nm to about 2.0 nm, which will vary depending on the target application.
- the conformal layer of high-k gate dielectric material is deposited using known methods such as ALD, for example, which allows for high conformality of the gate dielectric material.
- the layers of metallic material for the HKMG structures 130 can include one or more conformal work function metal (WFM) layers that are deposited over the conformal layer of high-k gate dielectric material.
- WFM conformal work function metal
- a total thickness of the conformal WFM material is in a range of 2 nm to about 5 nm.
- the WFM layers are used to obtain target work functions which are suitable for the type (e.g., n-type or p-type) of FinFET devices D 1 and D 2 that are to be formed and, thus, allow for tuning of the threshold voltages of the FinFET devices D 1 and D 2 .
- the WFM layers can include titanium nitride (TiN), and an aluminum (Al) containing alloy material such as titanium aluminum carbide (TiAlC), TiAl, AlC, etc.
- the WFM layer may include, e.g., TaN, Zr, W, Hf, Ti, Al, Ru, Pa, ZrAl, WAl, TaAl, HfAl, TiAlC, TaC, TiC, TaMgC, or other types, compositions, or alloys of work function metals that are commonly used to obtain target work functions for threshold voltage tuning.
- the HKMG structures 130 comprise metallic gate electrode layers that are formed over the WFM layers to fill the gate regions G 1 G 2 and G 3 with a lower resistance metal material such as tungsten, titanium, tantalum, cobalt, ruthenium, zirconium, copper, aluminum, platinum, tin, silver, etc.
- the layer of conductive material may further comprise dopants that are incorporated during or after deposition.
- the layer of conductive material is deposited using a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, sputtering, etc.
- a planarization process (e.g., CMP) is performed to polish the surface of the semiconductor structure down to the sacrificial ILD layer 125 , and remove the overburden portions of the layers of gate dielectric and metallic materials.
- the gate capping layers 132 are then fabricated by a process which comprises recessing the upper surfaces of the HKMG structures 130 to a target level below the planarized surface of the substrate, depositing a layer of dielectric material (e.g., SiN) to fill the recessed regions above the recessed surfaces of the HKMG structures 130 , and then planarizing the surface of the semiconductor structure down to the upper surface of the sacrificial ILD layer 125 to remove the overburden dielectric material and, thus, form the gate capping layers 132 .
- An additional layer of sacrificial layer of ILD material 125 - 1 is then deposited and planarized, resulting in the semiconductor structure shown in FIGS. 2A and 2B .
- the additional layer of sacrificial ILD material 125 - 1 is formed with a thickness T 1 in a range of about 10 nanometers (nm) to about 50 nm for the purpose of serving as a patterning layer to facilitate the formation of a source/drain contact in subsequent process steps.
- the process flow then continues with middle-of-the-line (MOL) processing to form the vertical source/drain contacts 150 and replace the sacrificial ILD layer 125 with the low-k ILD layer 170 , using a process flow as FIGS. 3A through 7 .
- MOL middle-of-the-line
- FIGS. 3A and 3B are schematic cross-sectional views of the semiconductor IC device shown in FIGS. 2A and 2B , respectively, after forming an etch mask 127 and patterning the sacrificial ILD layers 125 and 125 - 1 using the etch mask 127 to form source/drain contact openings 128 to expose the source/drain layers 140 .
- the source/drain contact openings 128 are formed using known methods.
- the etch mask 127 is formed by depositing and lithographically patterning an organic planarizing layer (OPL) using known methods. As shown in FIG.
- OPL organic planarizing layer
- the etch mask 127 can be formed with an opening 127 - 1 that exposes the functional gate G 2 and portions of the non-functional gates G 1 and G 3 .
- the opening 127 - 1 defines a “merged source/drain contact opening” (e.g., trench) that exposes the gate structure G 2 and the source/drain layers 140 of the field-effect transistor device
- An anisotropic dry etch process (e.g., ME) is performed to etch the contact openings 128 between the gate structures G 1 , G 2 , and G 3 down to a level that exposes at least upper portions of the source/drain layers 140 , or to other target levels depending on the desired amount of contact area between the source/drain layers 140 and bottom regions of the vertical source/drain contacts to be formed in the contact openings 128 .
- the dry etch process results in some vertical erosion of the exposed gate sidewall spacers 134 and gate capping layers 132 of the gate structures G 1 , G 2 , and G 3 .
- the gate sidewall spacers 134 and gate capping layers 132 are initially formed with an extra thickness to ensure that a sufficient amount of dielectric material of the gate sidewall spacers 134 and the gate capping layers 132 (with reduced thickness) remains above the HKMG structures 130 to properly encapsulate the HKMG structures 130 .
- FIGS. 4A and 4B are schematic cross-sectional side views of the semiconductor IC device shown in FIGS. 3A and 3B , respectively, after stripping away a remaining portion of the etch mask 127 , performing a source/drain contact metallization process to fill the source/drain contact openings 128 with contact metallization 150 A, and after forming a semiconductor layer 160 over the sacrificial ILD layer 125 - 1 and the contact metallization 150 A.
- FIGS. 4A and 4B are schematic cross-sectional side views of the semiconductor IC device shown in FIGS. 3A and 3B , respectively, after stripping away a remaining portion of the etch mask 127 , performing a source/drain contact metallization process to fill the source/drain contact openings 128 with contact metallization 150 A, and after forming a semiconductor layer 160 over the sacrificial ILD layer 125 - 1 and the contact metallization 150 A.
- the contact metallization 150 A forms a merged source/drain contact structure in which the source/drain contacts within the contact openings 128 are initially connected by overburden metallic material of the contact metallization 150 A disposed above the gate structure G 2 .
- the etch mask 127 can be removed using standard OPL stripping methods.
- the contact metallization 150 A is formed by a process which comprises forming a stack of layers over the source/drain layers 140 in the contact 128 openings, wherein the layers comprise epitaxial contact layers formed on the source/drain layers 140 , metallic contact liner layers formed on the epitaxial contact layers, and a metallic fill layer formed over the metallic contact liner layers.
- a thermal anneal process is subsequently performed at some point in the fabrication process to induce a reaction between the epitaxial contact layers and the metallic contact liner layers to form silicide contact layers on the source/drain layers 140 , thereby forming the vertical TS source/drain contacts 150 .
- the epitaxial contact layers are omitted so the metallic contact liner layers are directly formed on the source/drain layers 140 .
- the epitaxial contact layers comprise epitaxial material that is epitaxially grown on the exposed surfaces of the source/drain layers 140 at the bottom of the contact openings 128 .
- a preclean process can be performed prior to forming the epitaxial contact layers to remove any surface impurities or oxides from the exposed surfaces of the epitaxial source/drain layers 140 , which would otherwise increase the contact resistance or resistivity of the resulting trenches silicide contacts.
- the epitaxial contact layers are formed of an epitaxial material which is the same or similar to the epitaxial material of the source/drain layers 140 , but with higher doping levels than the source/drain layers 140 .
- the metallic contact liner layers comprise a thin layer of metallic material which, during a subsequent thermal anneal process, combines with the epitaxial contact layers to form trench silicide layers (or metallic-semiconductor alloy layers) as part of a salicidation process.
- silicide contacts are formed using transition metals such as nickel, cobalt, titanium, platinum, tungsten, tantalum, an alloy such as titanium-aluminum (TiAl) or titanium-nitride (TiN), etc., or any other suitable metallic material.
- the metallic contact liner layers can be deposited via ALD or CVD (in which case the metallic contact liners are conformally deposited on bottom and sidewall surfaces of the contact openings 128 ) or by PVD (in which case the metallic contact liners are primarily deposited on the bottom of the contact openings 128 ).
- a metallic fill layer is then deposited over the metallic contact liners to fill the remaining spaces in the contact openings 128 with metallic material.
- the metallic fill material comprises cobalt.
- the metallic fill material comprises ruthenium.
- the metallic fill material comprises copper.
- Metallic materials such as cobalt and ruthenium are exemplary of preferred metals utilized for the contact fill process as such metals can be deposited using relatively low deposition temperatures with deposition methods such as CVD, PECVD, PVD, ALD, etc.
- a barrier layer and/or seed layer is conformally deposited to line the sidewall and bottom surfaces of the contact openings.
- the barrier layer (or seed layer) is formed of a metallic material such as TiN or TaN.
- the barrier layer serves to prevent the diffusion of metallic material from the metallic fill layer into the surrounding ILD layer (e.g., the low-k ILD layer 170 which is subsequently formed).
- a seed layer serves as a wetting layer for the metallic fill deposition process.
- a planarization process e.g., chemical mechanical polishing (CMP) process
- CMP chemical mechanical polishing
- the semiconductor layer 160 is then formed on the planarized surface, resulting in the semiconductor structure shown in FIGS. 4A and 4B .
- the semiconductor layer 160 comprises an amorphous silicon layer which is formed by depositing a layer of silicon material using a PVD process.
- the PVD process enables the formation of a layer of amorphous silicon using a relatively low deposition temperature.
- the semiconductor layer 160 is formed using other types of semiconductor materials such as silicon germanium, germanium, etc.
- a thermal anneal process is performed at a suitable temperature and duration to induce a reaction between the semiconductor material of the semiconductor layer 160 and the metallic material in the upper surface region of the contact metallization 150 A form metal-semiconductor alloy capping layers (e.g., silicide capping layers).
- the thermal anneal process includes laser anneal, flash anneal, rapid thermal anneal, or any suitable combination of those techniques.
- FIG. 5 is a schematic cross-sectional side view of the semiconductor IC device of FIG.
- the thermal anneal process results in the formation of a thin metal-semiconductor capping layer 162 (e.g., CoSi, RuSi, CuSi, etc.) that is at least partially embedded in the upper surface region of the contact metallization 150 A.
- a thin metal-semiconductor capping layer 162 e.g., CoSi, RuSi, CuSi, etc.
- the metal-semiconductor alloy capping layer 162 serves as a protective capping layer to protect the contact metallization 150 A from damage and contamination as a result of the etch processes (e.g., RIE) and deposition processes that are subsequently performed to replace the sacrificial ILD layers 125 and 125 - 1 with the low-k ILD layer 170 .
- the formation of the protective metal-semiconductor capping layer 162 using the deposited semiconductor layer 160 and thermal anneal process ensures sufficient coverage of the protective capping layer 162 over the surface of the contact metallization 150 A.
- FIG. 6A is a schematic cross-sectional side view of the semiconductor IC device of FIG. 5 after stripping away an unreacted portion of the semiconductor layer 160 which remains following the thermal anneal process, and after performing an etch process to remove the sacrificial ILD layers 125 - 1 and 125 .
- FIG. 6B is a schematic cross-sectional side view of the semiconductor IC device along line 6 B- 6 B shown in FIG. 6A .
- the unreacted portion of the semiconductor layer 160 is removed selective to the protective capping layer 162 and the oxide materials of the sacrificial ILD layers 125 and 125 - 1 using known methods.
- the remaining unreacted portion of the semiconductor layer 160 can be removed using the same or similar selective dry etch or wet etch processes (e.g., ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH), or SF 6 plasma) as used in the RMG process discussed above for removing the sacrificial dummy gate electrode layer (e.g., sacrificial polysilicon or amorphous silicon).
- NH 4 OH ammonium hydroxide
- TMAH tetramethylammonium hydroxide
- SF 6 plasma SF 6 plasma
- an etch back process is performed to remove the sacrificial ILD layers 125 - 1 and 125 .
- the etch back process is performed using a dry etch process (e.g., RIE process) to etch the oxide materials of the sacrificial ILD layers 125 - 1 and 125 selective to the silicide material (e.g., CoSi, RuSi, or CuSi, etc.) of the protective capping layer 162 and the nitride materials (e.g., SiN) of the gate capping layers 132 and the gate sidewall spacers 134 .
- RIE process reactive etching process
- the etch back process is performed to etch the sacrificial ILD layer 125 down to the level of the STI layer 120 , resulting in the semiconductor IC device structure shown in FIGS. 6A and 6B .
- a residual amount of the original sacrificial ILD layer 125 may remain between the bottom surfaces of the source/drain layers 140 and the STI layer 120 .
- FIG. 7 is a schematic cross-sectional side view of the semiconductor IC device of FIG. 6A after depositing a layer of low-k dielectric material 170 A to replace the sacrificial ILD material.
- the low-k dielectric material 170 A comprises any type of low-k dielectric material which is suitable to serve as an ILD layer and which has a dielectric constant (k) of about 3.0 or less.
- the low-k dielectric layer 170 A may comprise a hybrid silica-based low-k dielectric material such as carbon-doped silicon glass (e.g., carbon-doped silicon glass (SiCOH) or organosilicate glass (SOG)), a fluorinated silicon glass (FSG), a low-k porous dielectric material, or a ULK (ultra-low-k) dielectric materials (with k less than about 2.5), etc.
- the low-k dielectric layer 170 A is deposited using, for example, CVD, PECVD, spin-on deposition, or other deposition techniques that are suitable for form low-k dielectric layers.
- a thin conformal liner layer is conformally deposited before depositing the low-k dielectric layer 170 A.
- the conformal liner layer serves as a diffusion barrier layer to prevent diffusion of the metallic material of the source/drain contacts 150 into the low-k dielectric ILD layer 170 .
- the conformal liner layer can be formed of any material such as SiN, SiON, or SiCN, which is suitable to serve as a diffusion barrier for the given application.
- a CMP process is performed to polish the surface of the semiconductor substrates down to a target level, as shown in FIG. 7 by a dashed line labeled “CMP level.”
- the CMP process is performed to remove the protective capping layer 162 , and to remove the merged portion of the contact metallization 150 A above the gate structure G 2 to form the discrete source/drain contacts 150 .
- the CMP process further serves to planarize the surface of the semiconductor IC device to remove the overburden dielectric material 170 A and make the upper surfaces of the gate structures G 1 , G 2 , and G 3 coplanar, resulting in the semiconductor IC device shown in FIGS. 1A, 1B, 1C and 1D with the low-k ILD layer 170 .
- MOL processing can continue to form MOL contacts and vertical vias (e.g., gate contacts, source/drain via contacts, etc.).
- a back-end-of-line (BEOL) process module can be performed to fabricate a BEOL interconnect structure which provides connections to/between the MOL contacts, and other active or passive devices that are formed as part of the front-end-of-line (FEOL) layer.
- BEOL back-end-of-line
- FIGS. 8 through 10 schematically illustrate a process for fabricating a semiconductor IC device in which an interlayer dielectric layer replacement process is implemented to replace an initial sacrificial ILD layer with a low-k ILD layer, according to another embodiment of the invention.
- the fabrication process schematically illustrated in FIGS. 8-10 provides an alternate embodiment for fabricating the semiconductor IC device 100 shown in FIGS. 1A-1D , in which the sacrificial material of the ILD layers 125 and 125 - 2 is replaced with the low-k ILD layer 170 while protecting the contact metallization 150 A using a nitride capping layer.
- FIG. 8 is a schematic cross-sectional side view of the semiconductor IC device 100 at an intermediate stage of fabrication wherein FinFET devices D 1 and D 2 with the source/drain layers 140 and metal gate structures G 1 , G 2 , and G 3 are formed on the semiconductor substrate 110 and encapsulated in sacrificial ILD layers 125 and 125 - 2 , and wherein source/drain contact metallization 150 A is formed within source/drain contact openings etched in the sacrificial ILD layers 125 and 125 - 2 .
- the intermediate semiconductor IC device structure shown in FIG. 8 is fabricated using the same or similar fabrication techniques as discussed above in conjunction with FIGS. 2A through 4B .
- the additional layer of sacrificial ILD material 125 - 2 that is formed on the planarized surface of the sacrificial ILD layer 125 following the RMG process module is thicker than the additional layer of sacrificial ILD material 125 - 1 that is formed (see FIGS. 2A and 2B ) on the planarized surface of the sacrificial ILD layer 125 following the RMG process module in the previously described embodiment.
- the additional layer of sacrificial ILD material 125 - 2 is formed with a thickness T 2 in a range of about 20 nm to about 80 nm, which is thicker than T 1 (see, e.g., FIG. 2A ).
- the sacrificial ILD layer 125 - 2 is made thicker for the purpose of forming the protective dielectric capping layer 180 on top of the contact metallization 150 A.
- FIG. 9 is a schematic cross-sectional side view of the semiconductor IC device of FIG. 8 after forming a protective dielectric capping layer 180 on the contact metallization 150 A.
- the protective dielectric capping layer 180 is formed of a dielectric material that has etch selectivity with respect to the material (e.g., silicon oxide) of the sacrificial ILD layers 125 and 125 - 2 .
- the protective dielectric capping layer 180 is formed of silicon nitride.
- the protective dielectric capping layer 180 is formed by a process which comprises recessing the upper surface of the contact metallization 150 A to a target level below the planarized surface of the sacrificial ILD layer 125 - 2 and above the upper surfaces of the gate structures G 1 , G 2 and G 3 , depositing a layer of dielectric material (e.g., SiN) to fill the recessed region above the recessed surface of the contact metallization 150 A, and then planarizing the surface of the semiconductor structure down to the upper surface of the sacrificial ILD layer 125 - 2 to remove the overburden dielectric material and, thus, form the protective dielectric capping layer 180 .
- a layer of dielectric material e.g., SiN
- FIG. 10 is a schematic cross-sectional side view of the semiconductor IC device of FIG. 9 after performing an etch back process to remove the sacrificial ILD layers 125 - 2 and 125 and after depositing a layer of low-k dielectric material 170 A to replace the sacrificial ILD material.
- the sacrificial ILD layers 125 - 2 and 125 are etched away using a dry etch process (e.g., RIE process) to etch the oxide materials of the sacrificial ILD layers 125 - 2 and 125 selective to the SiN materials of the protective capping layer 180 , the gate capping layers 132 , and the gate sidewall spacers 134 .
- a dry etch process e.g., RIE process
- the etch back process is performed to recess the sacrificial ILD layer 125 down to the level of the STI layer 120 , resulting in the semiconductor IC device structure shown in FIG. 10 .
- the protective dielectric capping layer 180 serves to protect the contact metallization 150 A from damage and contamination as a result of the etch processes (e.g., RIE) and deposition processes that are subsequently performed to replace the sacrificial ILD layers 125 and 125 - 2 with the low-k ILD layer 170 .
- the low-k dielectric material 170 A comprises any type of low-k dielectric material which is suitable to serve as an ILD layer and which has a dielectric constant (k) of about 3.0 or less.
- a thin conformal liner layer is conformally deposited before depositing the low-k dielectric layer 170 A.
- the conformal liner layer serves as a diffusion barrier layer to prevent diffusion of the metallic material of the source/drain contacts 150 into the low-k dielectric ILD layer 170 A.
- a CMP process is performed to polish the surface of the semiconductor substrates down to a target level, as shown in FIG. 10 by a dashed line labeled “CMP level.”
- the CMP process is performed to remove the protective capping layer 180 , and to remove the merged portion of the contact metallization 150 A above the gate structure G 2 to form the discrete source/drain contacts 150 .
- the CMP process further serves to planarize the surface of the semiconductor IC device to remove the overburden dielectric material 170 A and make the upper surfaces of the gate structures G 1 , G 2 , and G 3 coplanar, resulting in the semiconductor IC device shown in FIGS. 1A, 1B, 1C and 1D with the low-k ILD layer 170 .
- FIGS. 11 through 13 schematically illustrate a process for fabricating a semiconductor IC device 200 in which an interlayer dielectric layer replacement process is implemented to replace an initial sacrificial ILD with a low-k ILD layer, according to another embodiment of the invention.
- the fabrication process schematically illustrated in FIGS. 11-13 provides an alternate embodiment for fabricating a semiconductor integrated circuit device with discrete source/drain contacts wherein a sacrificial ILD layer is replaced with the low-k ILD layer while protecting the discrete source/drain contacts with metal-semiconductor alloy capping layers.
- FIG. 11 is a schematic cross-sectional side view of the semiconductor IC device 200 at an intermediate stage of fabrication wherein FinFET devices D 1 and D 2 with source/drain layers 140 and metal gate structures G 1 , G 2 , and G 3 are formed on a semiconductor substrate 110 and encapsulated in a sacrificial ILD layer 125 , and after forming an etch mask 227 and patterning the sacrificial ILD layer 125 using the etch mask 227 to form discrete source/drain contact openings 228 that expose the source/drain layers 140 .
- the intermediate semiconductor IC device structure shown in FIG. 11 is fabricated using the same or similar fabrication techniques as discussed above in conjunction with FIGS. 2A through 3B .
- the etch mask 227 (e.g., patterned OPL) is formed with discrete openings aligned to individual source/drain layers 140 between the gate structures G 1 , G 2 , and G 3 , as compared to the embodiment shown in FIG. 3A where the etch mask 127 is patterned to form a merged contact opening that spans the functional gate structure G 2 and the source/drain layers 140 on opposing sides of the gate structure G 2 .
- FIG. 12 is a schematic cross-sectional side view of the semiconductor IC device shown in FIG. 11 after stripping away a remaining portion of the etch mask 227 , performing a source/drain contact metallization process to fill the source/drain contact openings 228 with metallization to form discrete metallic source/drain contacts 250 , forming a semiconductor layer 260 over the sacrificial ILD layer 125 and the discrete metallic source/drain contacts 250 , and after performing a thermal anneal process to induce a reaction between semiconductor material of the semiconductor layer 260 and metallic material in upper surface regions of the discrete metallic source/drain contacts 250 to form metal-semiconductor alloy capping layers 262 .
- the metallic source/drain contacts 250 , the semiconductor layer 260 , and the protective metal-semiconductor alloy capping layers 262 are formed of the same or similar materials and fabrication techniques as discussed above in conjunction with FIGS. 4A, 4B and 5 , the details of which will not be repeated.
- FIG. 13 is a schematic cross-sectional side view of the semiconductor IC device of FIG. 12 after stripping away the unreacted portions of the semiconductor layer 260 , removing the sacrificial ILD layer 125 , and after depositing a layer of low-k dielectric material 270 A to form a replacement low-k ILD layer.
- the etch processes for removing the remaining unreacted materials of the semiconductor layer 260 and the sacrificial ILD layer 125 are the same or similar to the etch processes discussed above in conjunction with FIGS. 6A, 6B and 7 .
- the low-k ILD material 270 A is formed using the same or similar materials and deposition methods as discussed above in conjunction with FIG. 7 for forming the low-k ILD layer 170 A, the details of which will not be repeated.
- a CMP process is performed on the semiconductor IC device structure of FIG. 13 down to an upper surface of the metal-semiconductor alloy capping layers 262 , as schematically shown in FIG.
- CMP level 1 a dashed line labeled “CMP level 1.”
- the CMP process can be performed to remove the overburden portion of the low-k dielectric layer 270 A and form the final low-k ILD layer 270 , without having to etch away the protective silicide capping layers 262 .
- MOL processing can continue to form MOL contacts and vertical vias (e.g., gate contacts, source/drain via contacts, etc.) wherein the silicide capping layers 262 can serve as landing surfaces on which MOL vias can be formed.
- a CMP process is performed on the semiconductor IC device structure of FIG. 13 down to target level indicated by a dashed line labeled “CMP level 2” to remove the protective silicide capping layers 262 in addition to the overburden portion of the low-k dielectric layer 270 A and form the low-k ILD layer 270 .
- the protective silicide capping layers 262 can be removed via CMP to expose the underlying metallization of the discrete source/drain contacts 250 and allow MOL source/drain via contacts, etc. to be formed in direct contact with the metallization of the source/drain contacts 250 (without the intervening silicide capping layer 262 ).
- MOL processing can continue to form MOL contacts and vertical vias followed by a BEOL process module to fabricate a BEOL interconnect structure which provides connections to/between the MOL contacts, and other active or passive devices that are formed as part of the FEOL layer.
- Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
- ILD replacement methods discussed herein can be applied to other transistor architectures, including but not limited to, nanowire transistors, nanosheet transistors, planar transistors, vertical transistors, fully depleted silicon-on-insulator (FDSOI) transistors, and partially depleted silicon-on-insulator (PDSOI) transistors.
- FDSOI fully depleted silicon-on-insulator
- PDSOI partially depleted silicon-on-insulator
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
- This disclosure generally relates to semiconductor fabrication techniques and, in particular, middle-of the-line fabrication techniques for FET (field effect transistor) devices.
- Continued innovations in semiconductor process technologies are enabling higher integration densities and device scaling. As semiconductor manufacturing technologies continue to evolve toward smaller design rules and higher integration densities (e.g., 14 nm technology node and beyond), integrated circuit devices and components become increasingly smaller, creating challenges in layout formation and device optimization. Currently, FinFET technologies are typically implemented for FET fabrication, as such technologies provide effective CMOS scaling solutions for FET fabrication at, and below, the 14 nm technology node. A FinFET device comprises a three-dimensional fin-shaped FET structure which includes at least one vertical semiconductor fin structure formed on a substrate, a gate structure formed over a portion of the vertical semiconductor fin, and source/drain regions formed from portions of the vertical semiconductor fin which extend from both sides of the gate structure. The portion of the vertical semiconductor fin that is covered by the gate structure between the source/drain regions comprises a channel region of the FinFET device.
- While technological improvements in source/drain contact fabrication techniques have provided a dramatic reduction in the resistance of FET devices, techniques for reducing the parasitic capacitance between active FET devices have become more crucial for improving device performance and reducing power consumption. In general, a reduction in the parasitic capacitance between active devices can be achieved by utilizing a low-k dielectric material to form an initial interlayer dielectric (ILD) layer at the contact/transistor level, which encapsulates the source/drain contacts and metal gate structures. However, the low-k dielectric material that forms the initial ILD layer can become damaged and contaminated as a result of the various fabrication processes (e.g., reactive ion etching, thermal annealing, chemical mechanical polishing, etc.) that are utilized to form source/drain contacts (e.g., trench silicide contacts) and metal gates (e.g., replacement metal gate process), etc., wherein such damage and contamination leads to an undesirable increase in the effective dielectric constant of the initial low-k ILD layer.
- Embodiments of the invention include device and methods for fabricating a semiconductor integrated circuit (IC) device, which implement an ILD replacement process to replace an initial sacrificial ILD layer with a low-k ILD layer, while forming silicide or dielectric capping layers to protect source/drain contacts from etch damage during the ILD replacement process.
- For example, in one embodiment, a method for fabricating a semiconductor integrated circuit (IC) device comprises: forming a field-effect transistor device on a semiconductor substrate, wherein the field-effect transistor device comprise a gate structure and source/drain layers; forming a sacrificial interlayer dielectric layer to encapsulate the field-effect transistor device; performing a metallization process to form metallic source/drain contacts in the sacrificial interlayer dielectric layer in contact with source/drain layers of the field-effect transistor device; depositing a semiconductor layer on the sacrificial interlayer dielectric layer and the metallic source/drain contacts; performing a thermal anneal process to induce a reaction between the semiconductor layer and the metallic source-drain contacts to form metal-semiconductor alloy capping layers in upper surface regions of the metallic source/drain contacts; removing unreacted portions of the semiconductor layer remaining after the thermal anneal process; performing an etch process to remove the sacrificial interlayer dielectric layer, wherein the etch process is selective to the metal-semiconductor alloy capping layers such that the metal-semiconductor alloy capping layers protect the metallic source/drain contacts from etch damage during the etch process; and forming a low-k interlayer dielectric layer in place of the removed sacrificial interlayer dielectric layer.
- In another embodiment, a method for fabricating a semiconductor IC device comprises: forming a field-effect transistor device on a semiconductor substrate, wherein the field-effect transistor device comprises a gate structure and source/drain layers; forming a sacrificial interlayer dielectric layer to encapsulate the field-effect transistor device, wherein an upper surface of the sacrificial interlayer dielectric layer is disposed above an upper surface of the gate structure of the field-effect transistor device; performing a metallization process to form metallic source/drain contacts in the sacrificial interlayer dielectric layer in contact with the source/drain layers of the field-effect transistor device; performing a metal recess process to recess exposed surfaces of the metallic source/drain contacts to a target level below an upper surface of the sacrificial interlayer dielectric layer; forming dielectric capping layers on the recessed surfaces of the metallic source/drain contacts; performing an etch process to remove the sacrificial interlayer dielectric layer, wherein the etch process is selective to the dielectric capping layers such that the dielectric capping layers protect the metallic source/drain contacts from etch damage during the etch process; and forming a low-k interlayer dielectric layer in place of the removed sacrificial interlayer dielectric layer.
- Another embodiment includes a semiconductor integrated circuit device which comprises: a field-effect transistor device disposed on a semiconductor substrate, wherein the field-effect transistor device comprises a gate structure and first and second source/drain layers; a low-k interlayer dielectric layer encapsulating the field-effect transistor device; first and second metallic source/drain contacts disposed in the low-k interlayer dielectric layer in contact with the first and second source/drain layers, respectively, of the field-effect transistor device; and first and second metal-semiconductor alloy capping layers disposed in upper surface regions of the first and second metallic source/drain contacts, respectively. In some embodiments, the first and second metal-semiconductor alloy capping layers comprise a cobalt-silicon alloy or a ruthenium-silicon alloy, and the low-k interlayer dielectric layer comprises dielectric material having a dielectric constant k of about 3.0 or less.
- Other embodiments will be described in the following detailed description of embodiments, which is to be read in conjunction with the accompanying figures.
-
FIGS. 1A, 1B, 1C, and 1D are schematic views of a semiconductor IC device at an intermediate stage of fabrication after performing an interlayer dielectric layer replacement process to replace a sacrificial ILD layer with a low-k ILD dielectric layer, according to an embodiment of the invention, wherein: -
FIG. 1A is a schematic cross-sectional side view of the semiconductor IC device alongline 1A-1A shown inFIG. 1D ; -
FIG. 1B is a schematic cross-sectional side view of the semiconductor IC device alongline 1B-1B shown inFIG. 1D ; -
FIG. 1C is a schematic cross-sectional side view of the semiconductor IC device alongline 1C-1C shown inFIG. 1D ; and -
FIG. 1D is a schematic top plan view of the semiconductor IC device shown inFIGS. 1A, 1B and 1C . -
FIGS. 2A through 7 schematically illustrate a process for fabricating a semiconductor IC device in which an interlayer dielectric layer replacement process is implemented to replace an initial sacrificial ILD layer with a low-k ILD layer, according to an embodiment of the invention, wherein: -
FIG. 2A is a schematic cross-sectional side view of the semiconductor IC device at an intermediate stage of fabrication in which FinFET devices with source/drain layers and metal gate structures are formed on a semiconductor substrate and encapsulated in sacrificial ILD layers; -
FIG. 2B is a schematic cross-sectional side view of the semiconductor IC device alongline 2B-2B shown inFIG. 2A ; -
FIG. 3A is a schematic cross-sectional side view of the semiconductor IC device shown inFIG. 2A after forming an etch mask and patterning the sacrificial ILD layers using the etch mask to form source/drain contact openings that expose source/drain layers; -
FIG. 3B is a schematic cross-sectional side view of the semiconductor IC device alongline 3B-3B shown inFIG. 3A ; -
FIG. 4A is a schematic cross-sectional side view of the semiconductor IC device shown inFIG. 3A after stripping away a remaining portion of the etch mask, performing a source/drain contact metallization process to fill the source/drain contact openings with contact metallization, and after forming a semiconductor layer over the sacrificial ILD layer and the contact metallization; -
FIG. 4B is a schematic cross-sectional side view of the semiconductor IC device alongline 4B-4B shown inFIG. 4A ; -
FIG. 5 is a schematic cross-sectional side view of the semiconductor IC device ofFIG. 4A after performing a thermal anneal process to induce a reaction between the semiconductor material of the semiconductor layer and metallic material in an upper surface region of the contact metallization to form metal-semiconductor alloy capping layers; -
FIG. 6A is a schematic cross-sectional side view of the semiconductor IC device ofFIG. 5 after stripping away unreacted portions of the semiconductor layer which remain following the thermal anneal process, and performing an etch process to remove the sacrificial ILD layers; -
FIG. 6B is a schematic cross-sectional side view of the semiconductor IC device alongline 6B-6B shown inFIG. 6A ; and -
FIG. 7 is a schematic cross-sectional side view of the semiconductor IC device ofFIG. 6A after depositing a layer of low-k dielectric material to replace the sacrificial ILD layers with a low-k ILD layer. -
FIGS. 8 through 10 schematically illustrate a process for fabricating a semiconductor IC device in which an interlayer dielectric layer replacement process is implemented to replace an initial sacrificial ILD layer with a low-k ILD layer, according to another embodiment of the invention, wherein: -
FIG. 8 is a schematic cross-sectional side view of the semiconductor IC device at an intermediate stage of fabrication wherein FinFET devices with source/drain layers and metal gate structures are formed on a semiconductor substrate and encapsulated in sacrificial ILD layers, and wherein source/drain contact metallization is formed within source/drain contact openings etched in the sacrificial ILD layers; -
FIG. 9 is a schematic cross-sectional side view of the semiconductor IC device ofFIG. 8 after forming a protective dielectric capping layer on the contact metallization; and -
FIG. 10 is a schematic cross-sectional side view of the semiconductor IC device ofFIG. 9 after performing an etch back process to remove the sacrificial ILD layers and after depositing a layer of low-k dielectric material to replace the sacrificial ILD layers with a low-k ILD layer. -
FIGS. 11 through 13 schematically illustrate a process for fabricating a semiconductor IC device in which an interlayer dielectric layer replacement process is implemented to replace an initial sacrificial ILD with a low-k ILD dielectric layer, according to another embodiment of the invention, wherein: -
FIG. 11 is a schematic cross-sectional side view of the semiconductor IC device at an intermediate stage of fabrication wherein FinFET devices with source/drain layers and metal gate structures are formed on a semiconductor substrate and encapsulated in a sacrificial ILD layer, and after forming an etch mask and patterning the sacrificial ILD layer using the etch mask to form discrete source/drain contact openings to expose the source/drain layers; -
FIG. 12 is a schematic cross-sectional side view of the semiconductor IC device shown inFIG. 11 after stripping away a remaining portion of the etch mask, performing a source/drain contact metallization process to fill the source/drain contact openings with metallization to form discrete metallic source/drain contacts, forming a semiconductor layer over the sacrificial ILD layer and the discrete metallic source/drain contacts, and after performing a thermal anneal process to induce a reaction between semiconductor material of the semiconductor layer and metallic material in upper surface regions of the discrete metallic source/drain contacts to form metal-semiconductor alloy capping layers; and -
FIG. 13 is a schematic cross-sectional side view of the semiconductor IC device ofFIG. 12 after stripping away unreacted portions of the semiconductor layer which remain following the thermal anneal process, removing the sacrificial ILD layer, and after depositing a layer of low-k dielectric material to form a low-k ILD layer. - Embodiments of the invention will now be described in further detail with regard devices and methods for fabricating a semiconductor IC device, which implement an ILD replacement process to replace an initial sacrificial ILD layer with a low-k ILD layer, while forming silicide or dielectric capping layers to protect source/drain contacts from etch damage during the ILD replacement process. It is to be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic illustrations that are not drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor IC devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor IC device structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor IC devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
- Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings. It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error is present, such as 1% or less than the stated amount.
- To provide spatial context to the different structural orientations of the semiconductor IC device structures shown throughout the drawings, XYZ Cartesian coordinates are shown in each of the drawings. The terms “vertical” or “vertical direction” or “vertical height” as used herein denote a Z-direction of the Cartesian coordinates shown in the drawings, and the terms “horizontal,” or “horizontal direction,” or “lateral direction” as used herein denote an X-direction and/or a Y-direction of the Cartesian coordinates shown in the drawings.
-
FIGS. 1A, 1B, 1C, and 1D are schematic views of a semiconductor integratedcircuit device 100 at an intermediate stage of fabrication after performing an ILD layer replacement process to replace a sacrificial ILD layer with a low-k ILD layer, according to an embodiment of the invention.FIG. 1D is a schematic top plan view (X-Y plane) of the semiconductor integratedcircuit device 100, whileFIGS. 1A, 1B and 1C are cross-sectional side views of thesemiconductor IC device 100 along planes that are represented by respective lines shown inFIG. 1D . In particular,FIG. 1A is a schematic cross-sectional side view (Y-Z plane) of thesemiconductor IC device 100 alongline 1A-1A inFIG. 1D .FIG. 1B is a schematic cross-sectional side view (X-Z plane) of thesemiconductor IC device 100 alongline 1B-1B inFIG. 1D .FIG. 1C is a schematic cross-sectional side view (Y-Z plane) of thesemiconductor IC device 100 alongline 1C-1C inFIG. 1D . - As shown in
FIGS. 1A, 1B, 1C and 1D , thesemiconductor IC device 100 comprises asemiconductor substrate 110, a shallow trench isolation (STI)layer 120, a plurality ofvertical semiconductor fins 115, gate structures G1, G2, and G3, source/drain (S/D) layers 140, source/drain contacts 150 (e.g., trench silicide (T/S contacts), and a low-k ILD layer 170. The gate structures G1, G2, and G3 comprise high-k dielectric/metal gate (HKMG)structures 130,gate capping layers 132, andgate sidewall spacer 134, which are formed over respective channel regions of thevertical semiconductor fins 115. In some embodiments, the gate structures G1, G2, and G3 are formed using a replacement metal gate (RMG) process in which dummy gate structures are initially formed and then replaced with theHKMG structures 130 using known methods. Thegate capping layers 132 andgate sidewall spacers 134 are formed of dielectric materials such as silicon nitride (SiN), silicon boron carbon nitride (SiBCN), and other types of dielectric materials commonly used to form gate capping layers and gate sidewall spacers. - As shown in
FIGS. 1A, 1B and 1D , the portions of thevertical semiconductor fins 115 which are disposed between the gate structures G1, G2, and G3 serve as source/drain regions for first and second FinFET devices D1 and D2. In some embodiments, the source/drain layers 140 comprise epitaxial semiconductor layers that are grown on the portions of thevertical semiconductor fins 115 that are disposed between the gate structures G1, G1, and G3. As shown in the exemplary embodiment ofFIGS. 1B and 1D , each FinFET device D1 and D2 is a multi-fin FinFET structure comprising twovertical semiconductor fins 115, wherein the source/drain layers formed on portions of adjacentvertical semiconductor fins 115 are merged to form common source/drain layers 140, and wherein the source/drain layers 140 on each side of the gate structure G2 are commonly connected to a respective single vertical source/drain contact 150. - In the example embodiment
FIGS. 1A-1D , the middle gate structure G2 comprises a functional gate structure of the first and second FinFET devices D1 and D2, while the gate structures G1 and G3 are non-functional gate structures that are utilized for purposes of, e.g., facilitating uniform formation of the source/drain layers 140 and the source/drain contacts 150 on each side of the functional gate structure G2, and providing isolation for the source/drain layers 140, etc. The functional gate structure G2 extends over the channel regions of thevertical semiconductor fins 115 for both FinFET devices D1 and D2. In this configuration, the gate structure G2 serves as a common gate structure for the FinFET devices D1 and D2, with the source/drain layers 140 formed on opposing sides of the functional gate structure G2. - On the other hand, the end portions of the
vertical semiconductor fins 115 of the FinFET devices D1 and D2 terminate inside the non-functional gate structures G1 and G3 and, thus, are not exposed on the opposite sides of the gate structures G1 and G3. As such, thevertical semiconductor fins 115 of the non-functioning gate structures G1 and G3 are not functional FET channel layers, and the non-functioning gate structures G1 and G3 merely serve as structures to confine the epitaxial growth of the semiconductor material which forms the source/drain layers 140, as well as confine the size of the source/drain contacts 150. - The
ILD layer 170 comprises a low-k dielectric material which is formed as part of an ILD replacement process module following a RMG process module and a source/drain contact process module. As explained in further detail below, the ILD replacement process is performed to remove portions of an initial sacrificial ILD layer 125 (e.g., silicon oxide material) disposed between the gate structures G1, G2 and G3 and the source/drain contacts 150 (seeFIG. 1B ). The initialsacrificial ILD layer 125 can be formed of a material such as silicon oxide, and replaced with a low-k dielectric material (e.g., k<3.0, where is wherein k denotes a relative dielectric constant). TheILD layer 170 can be formed with Octamethylcyclotetrasiloxane (OMCTS), SiCOH, porous dielectrics, and other known ultra-low-k (ULK) dielectric materials (with k less than about 2.7) which would provide low dielectric permittivity, resulting in power consumption and signal delay in the semiconductor integratedcircuit device 100. As further explained below, embodiments of the invention include various techniques that are incorporated as part the exemplary ILD replacement modules to protect the source/drain contacts 150 from damage when replacing the initialsacrificial ILD material 125 with the low-k dielectric material. -
FIGS. 2A through 7 schematically illustrate a process for fabricating a semiconductor integrated circuit device in which an ILD layer replacement process is implemented to replace an initial sacrificial ILD layer with a low-k ILD layer, according to an embodiment of the invention. To begin,FIGS. 2A and 2B are schematic views of thesemiconductor IC device 100 at an intermediate stage of fabrication in which FinFET devices D1 and D2 with source/drain layers 140 and metal gate structures G1, G2, and G3 are formed on asemiconductor substrate 110 and encapsulated in sacrificial ILD layers 125 and 125-1. In particular,FIG. 2A is a schematic cross-sectional side view (Y-Z plane) of the semiconductor IC device ofFIG. 1A at an initial stage of fabrication, andFIG. 2B is a schematic cross-sectional side view (X-Z plane) of the semiconductor IC device alongline 2B-2B shown inFIG. 2A . The intermediate device structure shown inFIGS. 2A and 2B can be fabricated using known methods and materials. - For example, while the
semiconductor substrate 110 is illustrated as a generic substrate layer, thesemiconductor substrate 110 may comprise various structures and layers of semiconductor material. In some embodiments, thesemiconductor substrate 110 is a bulk semiconductor substrate (e.g., wafer) that is formed of silicon (Si) or germanium (Ge), or other types of semiconductor substrate materials that are commonly used in bulk semiconductor fabrication processes such as a silicon-germanium alloy, compound semiconductor materials (e.g. III-V), etc. In other embodiments, thesemiconductor substrate 110 is an active semiconductor layer of an SOI (silicon-on-insulator) substrate, GeOI (germanium-on-insulator) substrate, or other type of semiconductor-on-insulator substrate, which comprises an insulating layer (e.g., oxide layer) disposed between a base substrate layer (e.g., silicon substrate) and the active semiconductor layer (e.g., Si, Ge, etc.) in which active circuit components are formed as part of a front-end-of-line (FEOL) structure. It is to be noted that in each drawing, the X-Y plane represents a plane that is parallel to the plane of the semiconductor substrate 110 (e.g., wafer) being processed. - The
STI layer 120 and thevertical semiconductor fins 115 can be fabricated using various methods. For example, for bulk and SOI substrate embodiments, thevertical semiconductor fins 115 can be formed by patterning an active silicon layer (e.g., crystalline silicon, crystalline SiGe, III-V compound semiconductor material, etc.) at the surface of a bulk semiconductor substrate or the SOI substrate to form a pattern of vertical semiconductor fins in different device regions across the semiconductor wafer, four of which are shown inFIG. 2B for ease of illustration. In one embodiment, thevertical semiconductor fins 115 are patterned from a crystalline Si or SiGe layer that is epitaxially grown on top of a bulk silicon substrate or a bulk germanium substrate. A crystalline SiGe layer that is formed using an epitaxial growth process may comprise a relaxed SiGe layer or a strained SiGe layer. As is known in the art, strain engineering is utilized to enhance the carrier mobility for MOS transistors, wherein different types of Si—SiGe heterostructures can be fabricated to obtain and/or optimize different properties for CMOS FET devices. For example, silicon can be epitaxially grown on a SiGe substrate layer to form a strained Si layer. Moreover, a strained SiGe layer can be epitaxially grown on a silicon substrate layer. A strained-Si/relaxed-SiGe structure provides a tensile strain which primarily improves electron mobility for n-type FET devices, while a strained-SiGe/relaxed-Si structure provides a compressive strain which primarily improves hole mobility for p-type FET devices. - After forming the
vertical semiconductor fins 115, a layer of insulating material can be deposited to cover thevertical semiconductor fins 115, and then planarized (via chemical-mechanical planarization (CMP)) down to the top of thevertical semiconductor fins 115, and then further recessed using an etch-back process (e.g., dry etch process such as selective Reactive Ion Etch (ME) process, a wet etch process, or a combination of dry and wet etch processes) to form theSTI layer 120. As shown inFIG. 2A , theSTI layer 120 is etched down to a target level to expose upper portions of the verticalsemiconductor fin structures 115, which defines a baseline active fin height H for the FinFET devices D1 and D2. For illustrative purposes, an upper surface of theisolation layer 120 is shown in phantom as a dashed line inFIGS. 1A and 2A to show the baseline active fin height H. In one embodiment of the invention, theisolation layer 120 is selectively etched using RIE, although other etching processes may be employed. A timed etch can be performed to remove a desired amount of insulating material to expose the upper portions of the verticalsemiconductor fin structures 115. - In another embodiment, the
vertical semiconductor fins 115 can be formed using a process in which theSTI layer 120 is first deposited and then etched using RIE or deep RIE to form a pattern of trenches in theisolation layer 120 down to thesemiconductor substrate 110, which corresponds to a pattern of vertical semiconductor fins to be formed. Thevertical semiconductor fins 115 are then formed by epitaxially growing crystalline semiconductor material, starting on the exposed surfaces of thesemiconductor substrate 110 at the bottom of the trenches, using ART (aspect ratio trapping) techniques. ART enables selective epitaxial growth of crystalline Si, SiGe, or III-V compound semiconductor material, for example, to fill high aspect ratio trenches formed in an insulating layer, and thereby form high quality active channel layers for FinFET devices. The crystalline SiGe layer (or other types of epitaxial semiconductor layers) can be epitaxially grown using known techniques, such as CVD (chemical vapor deposition), MOCVD (metal-organic chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), MBE (molecular beam epitaxy), VPE (vapor-phase epitaxy), MOMBE (metal organic molecular beam epitaxy), or other known epitaxial growth techniques. - Next, dummy gate structures are fabricated using any known process flow which comprises, e.g., sequentially depositing a dummy gate oxide layer (e.g., silicon oxide), a dummy gate electrode layer (e.g., polysilicon or amorphous silicon), and hardmask layer (e.g., SiN) over the substrate and patterning the layers to form dummy gate structures with dummy gate capping layers to define gate regions of the gate structures G1, G2, and G3. The
gate sidewall spacers 134 are formed by depositing one or more conformal layers of dielectric materials over the dummy gate structures, and then patterning the conformally deposited dielectric layer(s) to form thegate sidewall spacers 134. Thegate sidewall spacers 134 are formed of one or more layers of dielectric material such as SiN, SiBCN, SiOCN, or other dielectric materials which are suitable for use as insulating gate sidewall spacers for gate structures of FinFET devices. The one or more layers of dielectric material can be deposited using plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable deposition methods which enable the deposition of thin films of dielectric material with high conformality, and then patterned using a directional dry etch process (e.g., RIE) as is known in the art. - After forming the
gate sidewall spacers 134, the process flow continues with forming the source/drain layers 140 on the exposed S/D regions of thevertical semiconductor fins 115. In one embodiment of the invention, the source/drain layers 140 are formed by growing epitaxial semiconductor material on the exposed surfaces of the S/D regions of thevertical semiconductor fins 115 adjacent to the gate structures G1, G2 and G3. The type of epitaxial material and doping used to form the source/drain layers 140 will vary depending on whether the FinFET devices D1 and D2 are P-type or N-type devices. As shown inFIG. 2B , the source/drain layers 140 are epitaxially grown so that adjacent source/drain layers 140 formed on adjacent S/D regions of thevertical semiconductor fins 115 for the respective FinFET devices D1 and D2 and can merge (in the X-direction) to collectively form a single source/drain layer. - In some embodiments, the source/drain layers 140 are doped using known techniques. For example, in one embodiment, the source/drain layers 140 are “in-situ” doped during epitaxial growth by adding a dopant gas to the source deposition gas (i.e., the Si-containing gas). Suitable n-type dopants include but are not limited to phosphorous (P) and arsenic (As), and suitable p-type dopants include but are not limited to boron (B). Exemplary dopant gases may include a boron-containing gas such as BH3 for pFETs or a phosphorus or arsenic containing gas such as PH3 or AsH3 for nFETs, wherein the concentration of impurity in the gas phase determines its concentration in the epitaxially grown semiconductor material. The use of an in-situ doping process is merely an example. For instance, an ex-situ process may be used to introduce dopants into the source/drain layers. Other doping techniques can be used to incorporate dopants in the source/drain layers. Dopant techniques include but are not limited to, ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, in-situ epitaxy growth, or any suitable combination of those techniques.
- Following formation of the source/drain layers 140, the process flow continues with depositing and planarizing a layer of dielectric material to form the initial
sacrificial ILD layer 125. Thesacrificial ILD layer 125 is formed, for example, by depositing a layer of insulating material over the surface of the semiconductor substrate to cover the dummy gate structures, and then planarizing the surface of the semiconductor substrate down to upper surface of a hard mask layer (or dummy gate capping layer) of the dummy gate structures. In some embodiments, thesacrificial ILD layer 125 is formed of silicon oxide. Thesacrificial ILD layer 125 may comprise a single deposited layer of insulating material, or multiple layers of insulating material (e.g., a first layer of a flowable oxide and a second layer of insulating material formed on the first layer). Thesacrificial ILD layer 125 may be deposited using known deposition techniques, such as, for example, ALD, PECVD, PVD (physical vapor deposition), or spin-on deposition. - Following formation of the
sacrificial ILD layer 125, the process flow continues with a replacement metal gate (RMG) process to remove the sacrificial material (e.g., dummy gate electrode layers and dummy gate oxide layers) of the dummy gate structures, and form theHKMG structures 130 in place of the dummy gate structures. For example, an RMG process comprises removing the dummy gate capping layers to expose the underlying sacrificial material of the dummy gate electrode layers (sacrificial polysilicon layer, or amorphous silicon layer), removing the dummy gate electrode layers selective to the materials of the dummy gate oxide layer and thegate sidewall spacers 134. The sacrificial dummy gate electrode layers can be removed using a selective dry etch or wet etch process with suitable etch chemistries, including ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), or SF6 plasma. The etching of the dummy gate electrode layer is selective to the dummy gate oxide layer to thereby protect the portions of thevertical semiconductor fins 115 within the gate regions G1, G2 and G3 from being etched during the dummy gate electrode etch process. After the dummy gate electrode layers are removed, an oxide etch process is performed to etch away the dummy gate oxide layers selective to the materials of thevertical semiconductor fins 115 and thegate sidewall spacers 134. In this manner, the sacrificial materials (e.g., dummy polysilicon and oxide layers) of the dummy gate structures are etched away without damaging the exposed portions of thevertical semiconductor fins 115 within the gate regions G1, G2, and G3. - In one embodiment, the
HKMG structures 130 are formed by depositing one or more conformal layers of high-k gate dielectric material to conformally cover the exposed surfaces of thevertical semiconductor fins 115 within the gate regions G1, G2, and G3, followed by the deposition of one or more layers of metallic material over the conformal deposited high-k gate dielectric material to fill the gate regions G1, G2 and G3 with the metallic material. The conformal high-k gate dielectric layers are formed of a high-k dielectric material having a dielectric constant (k) of about 3.9 or greater. For example, the gate dielectric material can include but is not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium zirconium oxide, and nitride films thereof. In other embodiments, the high-k dielectric may comprise lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k dielectric material may further include dopants such as lanthanum and aluminum. In one embodiment of the invention, the conformal gate dielectric layer is formed with a thickness in a range of about 0.5 nm to about 2.0 nm, which will vary depending on the target application. The conformal layer of high-k gate dielectric material is deposited using known methods such as ALD, for example, which allows for high conformality of the gate dielectric material. - The layers of metallic material for the
HKMG structures 130 can include one or more conformal work function metal (WFM) layers that are deposited over the conformal layer of high-k gate dielectric material. In one embodiment, a total thickness of the conformal WFM material is in a range of 2 nm to about 5 nm. The WFM layers are used to obtain target work functions which are suitable for the type (e.g., n-type or p-type) of FinFET devices D1 and D2 that are to be formed and, thus, allow for tuning of the threshold voltages of the FinFET devices D1 and D2. For example, the WFM layers can include titanium nitride (TiN), and an aluminum (Al) containing alloy material such as titanium aluminum carbide (TiAlC), TiAl, AlC, etc. In other embodiments, the WFM layer may include, e.g., TaN, Zr, W, Hf, Ti, Al, Ru, Pa, ZrAl, WAl, TaAl, HfAl, TiAlC, TaC, TiC, TaMgC, or other types, compositions, or alloys of work function metals that are commonly used to obtain target work functions for threshold voltage tuning. - Furthermore, in some embodiments, the
HKMG structures 130 comprise metallic gate electrode layers that are formed over the WFM layers to fill the gate regions G1 G2 and G3 with a lower resistance metal material such as tungsten, titanium, tantalum, cobalt, ruthenium, zirconium, copper, aluminum, platinum, tin, silver, etc. The layer of conductive material may further comprise dopants that are incorporated during or after deposition. The layer of conductive material is deposited using a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, sputtering, etc. - Following the deposition of the layers of gate dielectric and metallic materials to form the
HKMG structures 130, a planarization process (e.g., CMP) is performed to polish the surface of the semiconductor structure down to thesacrificial ILD layer 125, and remove the overburden portions of the layers of gate dielectric and metallic materials. Thegate capping layers 132 are then fabricated by a process which comprises recessing the upper surfaces of theHKMG structures 130 to a target level below the planarized surface of the substrate, depositing a layer of dielectric material (e.g., SiN) to fill the recessed regions above the recessed surfaces of theHKMG structures 130, and then planarizing the surface of the semiconductor structure down to the upper surface of thesacrificial ILD layer 125 to remove the overburden dielectric material and, thus, form the gate capping layers 132. An additional layer of sacrificial layer of ILD material 125-1 is then deposited and planarized, resulting in the semiconductor structure shown inFIGS. 2A and 2B . The additional layer of sacrificial ILD material 125-1 is formed with a thickness T1 in a range of about 10 nanometers (nm) to about 50 nm for the purpose of serving as a patterning layer to facilitate the formation of a source/drain contact in subsequent process steps. The process flow then continues with middle-of-the-line (MOL) processing to form the vertical source/drain contacts 150 and replace thesacrificial ILD layer 125 with the low-k ILD layer 170, using a process flow asFIGS. 3A through 7 . - To begin,
FIGS. 3A and 3B are schematic cross-sectional views of the semiconductor IC device shown inFIGS. 2A and 2B , respectively, after forming anetch mask 127 and patterning the sacrificial ILD layers 125 and 125-1 using theetch mask 127 to form source/drain contact openings 128 to expose the source/drain layers 140. The source/drain contact openings 128 are formed using known methods. For example, in one embodiment, theetch mask 127 is formed by depositing and lithographically patterning an organic planarizing layer (OPL) using known methods. As shown inFIG. 3A , to relax the alignment budget of the lithographic process, theetch mask 127 can be formed with an opening 127-1 that exposes the functional gate G2 and portions of the non-functional gates G1 and G3. In this regard, the opening 127-1 defines a “merged source/drain contact opening” (e.g., trench) that exposes the gate structure G2 and the source/drain layers 140 of the field-effect transistor device - An anisotropic dry etch process (e.g., ME) is performed to etch the
contact openings 128 between the gate structures G1, G2, and G3 down to a level that exposes at least upper portions of the source/drain layers 140, or to other target levels depending on the desired amount of contact area between the source/drain layers 140 and bottom regions of the vertical source/drain contacts to be formed in thecontact openings 128. As shown inFIG. 3A , the dry etch process results in some vertical erosion of the exposedgate sidewall spacers 134 andgate capping layers 132 of the gate structures G1, G2, and G3. However, thegate sidewall spacers 134 andgate capping layers 132 are initially formed with an extra thickness to ensure that a sufficient amount of dielectric material of thegate sidewall spacers 134 and the gate capping layers 132 (with reduced thickness) remains above theHKMG structures 130 to properly encapsulate theHKMG structures 130. - Next,
FIGS. 4A and 4B are schematic cross-sectional side views of the semiconductor IC device shown inFIGS. 3A and 3B , respectively, after stripping away a remaining portion of theetch mask 127, performing a source/drain contact metallization process to fill the source/drain contact openings 128 withcontact metallization 150A, and after forming asemiconductor layer 160 over the sacrificial ILD layer 125-1 and thecontact metallization 150A. In the exemplary embodiment ofFIGS. 4A and 4B , thecontact metallization 150A forms a merged source/drain contact structure in which the source/drain contacts within thecontact openings 128 are initially connected by overburden metallic material of thecontact metallization 150A disposed above the gate structure G2. - The
etch mask 127 can be removed using standard OPL stripping methods. Further, in some embodiments where the vertical source/drain contacts 150 (FIG. 1A ) comprise trench silicide (TS) contacts, thecontact metallization 150A is formed by a process which comprises forming a stack of layers over the source/drain layers 140 in thecontact 128 openings, wherein the layers comprise epitaxial contact layers formed on the source/drain layers 140, metallic contact liner layers formed on the epitaxial contact layers, and a metallic fill layer formed over the metallic contact liner layers. A thermal anneal process is subsequently performed at some point in the fabrication process to induce a reaction between the epitaxial contact layers and the metallic contact liner layers to form silicide contact layers on the source/drain layers 140, thereby forming the vertical TS source/drain contacts 150. In some embodiments, the epitaxial contact layers are omitted so the metallic contact liner layers are directly formed on the source/drain layers 140. - The epitaxial contact layers comprise epitaxial material that is epitaxially grown on the exposed surfaces of the source/
drain layers 140 at the bottom of thecontact openings 128. Prior to forming the epitaxial contact layers, a preclean process can be performed to remove any surface impurities or oxides from the exposed surfaces of the epitaxial source/drain layers 140, which would otherwise increase the contact resistance or resistivity of the resulting trenches silicide contacts. In one embodiment, the epitaxial contact layers are formed of an epitaxial material which is the same or similar to the epitaxial material of the source/drain layers 140, but with higher doping levels than the source/drain layers 140. The metallic contact liner layers comprise a thin layer of metallic material which, during a subsequent thermal anneal process, combines with the epitaxial contact layers to form trench silicide layers (or metallic-semiconductor alloy layers) as part of a salicidation process. Typically, silicide contacts are formed using transition metals such as nickel, cobalt, titanium, platinum, tungsten, tantalum, an alloy such as titanium-aluminum (TiAl) or titanium-nitride (TiN), etc., or any other suitable metallic material. The metallic contact liner layers can be deposited via ALD or CVD (in which case the metallic contact liners are conformally deposited on bottom and sidewall surfaces of the contact openings 128) or by PVD (in which case the metallic contact liners are primarily deposited on the bottom of the contact openings 128). - A metallic fill layer is then deposited over the metallic contact liners to fill the remaining spaces in the
contact openings 128 with metallic material. In some embodiments, the metallic fill material comprises cobalt. In other embodiments, the metallic fill material comprises ruthenium. In other embodiments, the metallic fill material comprises copper. Metallic materials such as cobalt and ruthenium are exemplary of preferred metals utilized for the contact fill process as such metals can be deposited using relatively low deposition temperatures with deposition methods such as CVD, PECVD, PVD, ALD, etc. Furthermore, in some embodiments, before forming the metallic fill layer, a barrier layer and/or seed layer is conformally deposited to line the sidewall and bottom surfaces of the contact openings. For example, the barrier layer (or seed layer) is formed of a metallic material such as TiN or TaN. The barrier layer serves to prevent the diffusion of metallic material from the metallic fill layer into the surrounding ILD layer (e.g., the low-k ILD layer 170 which is subsequently formed). A seed layer serves as a wetting layer for the metallic fill deposition process. - Following the metal deposition process to fill the
contact opening 128, a planarization process (e.g., chemical mechanical polishing (CMP) process) is performed to remove the overburden metallic material from the upper surface of the sacrificial ILD layer 125-1, and form a planarized surface. Thesemiconductor layer 160 is then formed on the planarized surface, resulting in the semiconductor structure shown inFIGS. 4A and 4B . In one embodiment, thesemiconductor layer 160 comprises an amorphous silicon layer which is formed by depositing a layer of silicon material using a PVD process. The PVD process enables the formation of a layer of amorphous silicon using a relatively low deposition temperature. In other embodiments, thesemiconductor layer 160 is formed using other types of semiconductor materials such as silicon germanium, germanium, etc. - Following deposition of the
semiconductor layer 160, a thermal anneal process is performed at a suitable temperature and duration to induce a reaction between the semiconductor material of thesemiconductor layer 160 and the metallic material in the upper surface region of thecontact metallization 150A form metal-semiconductor alloy capping layers (e.g., silicide capping layers). In some embodiments, the thermal anneal process includes laser anneal, flash anneal, rapid thermal anneal, or any suitable combination of those techniques. For example,FIG. 5 is a schematic cross-sectional side view of the semiconductor IC device ofFIG. 4A after performing a thermal anneal process to induce a reaction between the semiconductor material of thesemiconductor layer 160 and the metallic material in the upper surface region of thecontact metallization 150A to form a metal-semiconductoralloy capping layer 162. Essentially, the thermal anneal process results in the formation of a thin metal-semiconductor capping layer 162 (e.g., CoSi, RuSi, CuSi, etc.) that is at least partially embedded in the upper surface region of thecontact metallization 150A. At the completion of the thermal anneal processing, there will exist a remaining, unreacted portion of thesemiconductor layer 160. - The metal-semiconductor
alloy capping layer 162 serves as a protective capping layer to protect thecontact metallization 150A from damage and contamination as a result of the etch processes (e.g., RIE) and deposition processes that are subsequently performed to replace the sacrificial ILD layers 125 and 125-1 with the low-k ILD layer 170. The formation of the protective metal-semiconductor capping layer 162 using the depositedsemiconductor layer 160 and thermal anneal process ensures sufficient coverage of theprotective capping layer 162 over the surface of thecontact metallization 150A. This is to be contrasted with conventional methods for fabricating protective capping layers on metallization layer using selective deposition techniques to selectively deposit metallic capping layers (e.g., tungsten) on the surfaces of the metallization, which can result in insufficient coverage (e.g., voids) of the selectively deposited metallic capping layers. - Next,
FIG. 6A is a schematic cross-sectional side view of the semiconductor IC device ofFIG. 5 after stripping away an unreacted portion of thesemiconductor layer 160 which remains following the thermal anneal process, and after performing an etch process to remove the sacrificial ILD layers 125-1 and 125.FIG. 6B is a schematic cross-sectional side view of the semiconductor IC device alongline 6B-6B shown inFIG. 6A . The unreacted portion of thesemiconductor layer 160 is removed selective to theprotective capping layer 162 and the oxide materials of the sacrificial ILD layers 125 and 125-1 using known methods. For example, when thesemiconductor layer 160 is formed of amorphous silicon, the remaining unreacted portion of thesemiconductor layer 160 can be removed using the same or similar selective dry etch or wet etch processes (e.g., ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), or SF6 plasma) as used in the RMG process discussed above for removing the sacrificial dummy gate electrode layer (e.g., sacrificial polysilicon or amorphous silicon). - Following the removal of the unreacted portion of the
semiconductor layer 160, an etch back process is performed to remove the sacrificial ILD layers 125-1 and 125. In some embodiments, the etch back process is performed using a dry etch process (e.g., RIE process) to etch the oxide materials of the sacrificial ILD layers 125-1 and 125 selective to the silicide material (e.g., CoSi, RuSi, or CuSi, etc.) of theprotective capping layer 162 and the nitride materials (e.g., SiN) of thegate capping layers 132 and thegate sidewall spacers 134. In some embodiments, the etch back process is performed to etch thesacrificial ILD layer 125 down to the level of theSTI layer 120, resulting in the semiconductor IC device structure shown inFIGS. 6A and 6B . In some embodiments, as schematically illustrated inFIG. 6B , a residual amount of the originalsacrificial ILD layer 125 may remain between the bottom surfaces of the source/drain layers 140 and theSTI layer 120. - Next,
FIG. 7 is a schematic cross-sectional side view of the semiconductor IC device ofFIG. 6A after depositing a layer of low-k dielectric material 170A to replace the sacrificial ILD material. In some embodiments, the low-k dielectric material 170A comprises any type of low-k dielectric material which is suitable to serve as an ILD layer and which has a dielectric constant (k) of about 3.0 or less. For example, the low-k dielectric layer 170A may comprise a hybrid silica-based low-k dielectric material such as carbon-doped silicon glass (e.g., carbon-doped silicon glass (SiCOH) or organosilicate glass (SOG)), a fluorinated silicon glass (FSG), a low-k porous dielectric material, or a ULK (ultra-low-k) dielectric materials (with k less than about 2.5), etc. The low-k dielectric layer 170A is deposited using, for example, CVD, PECVD, spin-on deposition, or other deposition techniques that are suitable for form low-k dielectric layers. - In some embodiments, a thin conformal liner layer is conformally deposited before depositing the low-
k dielectric layer 170A. The conformal liner layer serves as a diffusion barrier layer to prevent diffusion of the metallic material of the source/drain contacts 150 into the low-kdielectric ILD layer 170. The conformal liner layer can be formed of any material such as SiN, SiON, or SiCN, which is suitable to serve as a diffusion barrier for the given application. - Following the deposition of the low-k-
dielectric layer 170A, a CMP process is performed to polish the surface of the semiconductor substrates down to a target level, as shown inFIG. 7 by a dashed line labeled “CMP level.” The CMP process is performed to remove theprotective capping layer 162, and to remove the merged portion of thecontact metallization 150A above the gate structure G2 to form the discrete source/drain contacts 150. The CMP process further serves to planarize the surface of the semiconductor IC device to remove theoverburden dielectric material 170A and make the upper surfaces of the gate structures G1, G2, and G3 coplanar, resulting in the semiconductor IC device shown inFIGS. 1A, 1B, 1C and 1D with the low-k ILD layer 170. - Following the formation of the semiconductor structure shown in
FIGS. 1A-1D , any known sequence of processing steps can be performed to complete the fabrication of the semiconductor integrated circuit device, the details of which are not needed to understand embodiments of the invention. Briefly, MOL processing can continue to form MOL contacts and vertical vias (e.g., gate contacts, source/drain via contacts, etc.). Then, a back-end-of-line (BEOL) process module can be performed to fabricate a BEOL interconnect structure which provides connections to/between the MOL contacts, and other active or passive devices that are formed as part of the front-end-of-line (FEOL) layer. -
FIGS. 8 through 10 schematically illustrate a process for fabricating a semiconductor IC device in which an interlayer dielectric layer replacement process is implemented to replace an initial sacrificial ILD layer with a low-k ILD layer, according to another embodiment of the invention. The fabrication process schematically illustrated inFIGS. 8-10 provides an alternate embodiment for fabricating thesemiconductor IC device 100 shown inFIGS. 1A-1D , in which the sacrificial material of the ILD layers 125 and 125-2 is replaced with the low-k ILD layer 170 while protecting thecontact metallization 150A using a nitride capping layer. - To begin,
FIG. 8 is a schematic cross-sectional side view of thesemiconductor IC device 100 at an intermediate stage of fabrication wherein FinFET devices D1 and D2 with the source/drain layers 140 and metal gate structures G1, G2, and G3 are formed on thesemiconductor substrate 110 and encapsulated in sacrificial ILD layers 125 and 125-2, and wherein source/drain contact metallization 150A is formed within source/drain contact openings etched in the sacrificial ILD layers 125 and 125-2. The intermediate semiconductor IC device structure shown inFIG. 8 is fabricated using the same or similar fabrication techniques as discussed above in conjunction withFIGS. 2A through 4B . - However, in the exemplary embodiment of
FIG. 8 , the additional layer of sacrificial ILD material 125-2 that is formed on the planarized surface of thesacrificial ILD layer 125 following the RMG process module is thicker than the additional layer of sacrificial ILD material 125-1 that is formed (seeFIGS. 2A and 2B ) on the planarized surface of thesacrificial ILD layer 125 following the RMG process module in the previously described embodiment. For example, the additional layer of sacrificial ILD material 125-2 is formed with a thickness T2 in a range of about 20 nm to about 80 nm, which is thicker than T1 (see, e.g.,FIG. 2A ). In this embodiment, the sacrificial ILD layer 125-2 is made thicker for the purpose of forming the protectivedielectric capping layer 180 on top of thecontact metallization 150A. - Next,
FIG. 9 is a schematic cross-sectional side view of the semiconductor IC device ofFIG. 8 after forming a protectivedielectric capping layer 180 on thecontact metallization 150A. The protectivedielectric capping layer 180 is formed of a dielectric material that has etch selectivity with respect to the material (e.g., silicon oxide) of the sacrificial ILD layers 125 and 125-2. For example, in one embodiment, the protectivedielectric capping layer 180 is formed of silicon nitride. The protectivedielectric capping layer 180 is formed by a process which comprises recessing the upper surface of thecontact metallization 150A to a target level below the planarized surface of the sacrificial ILD layer 125-2 and above the upper surfaces of the gate structures G1, G2 and G3, depositing a layer of dielectric material (e.g., SiN) to fill the recessed region above the recessed surface of thecontact metallization 150A, and then planarizing the surface of the semiconductor structure down to the upper surface of the sacrificial ILD layer 125-2 to remove the overburden dielectric material and, thus, form the protectivedielectric capping layer 180. - Next,
FIG. 10 is a schematic cross-sectional side view of the semiconductor IC device ofFIG. 9 after performing an etch back process to remove the sacrificial ILD layers 125-2 and 125 and after depositing a layer of low-k dielectric material 170A to replace the sacrificial ILD material. In one embodiment, the sacrificial ILD layers 125-2 and 125 are etched away using a dry etch process (e.g., RIE process) to etch the oxide materials of the sacrificial ILD layers 125-2 and 125 selective to the SiN materials of theprotective capping layer 180, thegate capping layers 132, and thegate sidewall spacers 134. In some embodiments, the etch back process is performed to recess thesacrificial ILD layer 125 down to the level of theSTI layer 120, resulting in the semiconductor IC device structure shown inFIG. 10 . The protectivedielectric capping layer 180 serves to protect thecontact metallization 150A from damage and contamination as a result of the etch processes (e.g., RIE) and deposition processes that are subsequently performed to replace the sacrificial ILD layers 125 and 125-2 with the low-k ILD layer 170. - As noted above, the low-
k dielectric material 170A comprises any type of low-k dielectric material which is suitable to serve as an ILD layer and which has a dielectric constant (k) of about 3.0 or less. In some embodiments, a thin conformal liner layer is conformally deposited before depositing the low-k dielectric layer 170A. The conformal liner layer serves as a diffusion barrier layer to prevent diffusion of the metallic material of the source/drain contacts 150 into the low-kdielectric ILD layer 170A. - Following the deposition of the low-
k dielectric layer 170A, a CMP process is performed to polish the surface of the semiconductor substrates down to a target level, as shown inFIG. 10 by a dashed line labeled “CMP level.” The CMP process is performed to remove theprotective capping layer 180, and to remove the merged portion of thecontact metallization 150A above the gate structure G2 to form the discrete source/drain contacts 150. The CMP process further serves to planarize the surface of the semiconductor IC device to remove theoverburden dielectric material 170A and make the upper surfaces of the gate structures G1, G2, and G3 coplanar, resulting in the semiconductor IC device shown inFIGS. 1A, 1B, 1C and 1D with the low-k ILD layer 170. -
FIGS. 11 through 13 schematically illustrate a process for fabricating asemiconductor IC device 200 in which an interlayer dielectric layer replacement process is implemented to replace an initial sacrificial ILD with a low-k ILD layer, according to another embodiment of the invention. The fabrication process schematically illustrated inFIGS. 11-13 provides an alternate embodiment for fabricating a semiconductor integrated circuit device with discrete source/drain contacts wherein a sacrificial ILD layer is replaced with the low-k ILD layer while protecting the discrete source/drain contacts with metal-semiconductor alloy capping layers. - To begin,
FIG. 11 is a schematic cross-sectional side view of thesemiconductor IC device 200 at an intermediate stage of fabrication wherein FinFET devices D1 and D2 with source/drain layers 140 and metal gate structures G1, G2, and G3 are formed on asemiconductor substrate 110 and encapsulated in asacrificial ILD layer 125, and after forming an etch mask 227 and patterning thesacrificial ILD layer 125 using the etch mask 227 to form discrete source/drain contact openings 228 that expose the source/drain layers 140. The intermediate semiconductor IC device structure shown inFIG. 11 is fabricated using the same or similar fabrication techniques as discussed above in conjunction withFIGS. 2A through 3B . - However, in the exemplary embodiment of
FIG. 11 , no additional sacrificial ILD material is formed on the planarized surface of the initialsacrificial ILD layer 125 following the RMG process module. In addition, the etch mask 227 (e.g., patterned OPL) is formed with discrete openings aligned to individual source/drain layers 140 between the gate structures G1, G2, and G3, as compared to the embodiment shown inFIG. 3A where theetch mask 127 is patterned to form a merged contact opening that spans the functional gate structure G2 and the source/drain layers 140 on opposing sides of the gate structure G2. - Next,
FIG. 12 is a schematic cross-sectional side view of the semiconductor IC device shown inFIG. 11 after stripping away a remaining portion of the etch mask 227, performing a source/drain contact metallization process to fill the source/drain contact openings 228 with metallization to form discrete metallic source/drain contacts 250, forming asemiconductor layer 260 over thesacrificial ILD layer 125 and the discrete metallic source/drain contacts 250, and after performing a thermal anneal process to induce a reaction between semiconductor material of thesemiconductor layer 260 and metallic material in upper surface regions of the discrete metallic source/drain contacts 250 to form metal-semiconductor alloy capping layers 262. In some embodiments, the metallic source/drain contacts 250, thesemiconductor layer 260, and the protective metal-semiconductoralloy capping layers 262 are formed of the same or similar materials and fabrication techniques as discussed above in conjunction withFIGS. 4A, 4B and 5 , the details of which will not be repeated. - Next,
FIG. 13 is a schematic cross-sectional side view of the semiconductor IC device ofFIG. 12 after stripping away the unreacted portions of thesemiconductor layer 260, removing thesacrificial ILD layer 125, and after depositing a layer of low-k dielectric material 270A to form a replacement low-k ILD layer. In some embodiments, the etch processes for removing the remaining unreacted materials of thesemiconductor layer 260 and thesacrificial ILD layer 125 are the same or similar to the etch processes discussed above in conjunction withFIGS. 6A, 6B and 7 . In addition, the low-k ILD material 270A is formed using the same or similar materials and deposition methods as discussed above in conjunction withFIG. 7 for forming the low-k ILD layer 170A, the details of which will not be repeated. - As compared to the exemplary CMP process that is performed in
FIG. 7 to remove the metal-semiconductoralloy capping layer 162 and the upper portion of themerged contact metallization 150A to form the discrete source/drain contacts 150, in some embodiments, a CMP process is performed on the semiconductor IC device structure ofFIG. 13 down to an upper surface of the metal-semiconductoralloy capping layers 262, as schematically shown inFIG. 13 by a dashed line labeled “CMP level 1.” In this instance, since the source/drain contacts 250 are initially fabricated as discrete contacts (with no merged contact metallization) the CMP process can be performed to remove the overburden portion of the low-k dielectric layer 270A and form the final low-k ILD layer 270, without having to etch away the protective silicide capping layers 262. In this instance, MOL processing can continue to form MOL contacts and vertical vias (e.g., gate contacts, source/drain via contacts, etc.) wherein thesilicide capping layers 262 can serve as landing surfaces on which MOL vias can be formed. - In other embodiments, a CMP process is performed on the semiconductor IC device structure of
FIG. 13 down to target level indicated by a dashed line labeled “CMP level 2” to remove the protectivesilicide capping layers 262 in addition to the overburden portion of the low-k dielectric layer 270A and form the low-k ILD layer 270. In this instance, the protectivesilicide capping layers 262 can be removed via CMP to expose the underlying metallization of the discrete source/drain contacts 250 and allow MOL source/drain via contacts, etc. to be formed in direct contact with the metallization of the source/drain contacts 250 (without the intervening silicide capping layer 262). - Following the formation of the semiconductor structure shown in
FIG. 13 , any known sequence of processing steps can be performed to complete the fabrication of the semiconductor integrated circuit device, the details of which are not needed to understand embodiments of the invention. Briefly, MOL processing can continue to form MOL contacts and vertical vias followed by a BEOL process module to fabricate a BEOL interconnect structure which provides connections to/between the MOL contacts, and other active or passive devices that are formed as part of the FEOL layer. - It is to be understood that the methods discussed herein for fabricating FET devices and source/drain contacts encapsulated in low-k ILD layers can be readily incorporated within semiconductor processing flows, semiconductor IC devices, and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention. Besides FinFET devices, it is to be understood that the exemplary ILD replacement methods discussed herein can be applied to other transistor architectures, including but not limited to, nanowire transistors, nanosheet transistors, planar transistors, vertical transistors, fully depleted silicon-on-insulator (FDSOI) transistors, and partially depleted silicon-on-insulator (PDSOI) transistors.
- Although exemplary embodiments have been described herein with reference to the accompanying figures, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made therein by one skilled in the art without departing from the scope of the appended claims.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/290,182 US10770562B1 (en) | 2019-03-01 | 2019-03-01 | Interlayer dielectric replacement techniques with protection for source/drain contacts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/290,182 US10770562B1 (en) | 2019-03-01 | 2019-03-01 | Interlayer dielectric replacement techniques with protection for source/drain contacts |
Publications (2)
Publication Number | Publication Date |
---|---|
US20200279933A1 true US20200279933A1 (en) | 2020-09-03 |
US10770562B1 US10770562B1 (en) | 2020-09-08 |
Family
ID=72236223
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/290,182 Active US10770562B1 (en) | 2019-03-01 | 2019-03-01 | Interlayer dielectric replacement techniques with protection for source/drain contacts |
Country Status (1)
Country | Link |
---|---|
US (1) | US10770562B1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11164815B2 (en) * | 2019-09-28 | 2021-11-02 | International Business Machines Corporation | Bottom barrier free interconnects without voids |
US11211462B2 (en) * | 2020-03-05 | 2021-12-28 | International Business Machines Corporation | Using selectively formed cap layers to form self-aligned contacts to source/drain regions |
TWI811781B (en) * | 2021-01-15 | 2023-08-11 | 台灣積體電路製造股份有限公司 | Method of forming the semiconductor device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10084063B2 (en) * | 2014-06-23 | 2018-09-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5814530A (en) * | 1996-09-27 | 1998-09-29 | Xerox Corporation | Producing a sensor with doped microcrystalline silicon channel leads |
US5880018A (en) | 1996-10-07 | 1999-03-09 | Motorola Inc. | Method for manufacturing a low dielectric constant inter-level integrated circuit structure |
US6423628B1 (en) | 1999-10-22 | 2002-07-23 | Lsi Logic Corporation | Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines |
US6294448B1 (en) * | 2000-01-18 | 2001-09-25 | Taiwan Semiconductor Manufacturing Company | Method to improve TiSix salicide formation |
US6335249B1 (en) * | 2000-02-07 | 2002-01-01 | Taiwan Semiconductor Manufacturing Company | Salicide field effect transistors with improved borderless contact structures and a method of fabrication |
US7294934B2 (en) | 2002-11-21 | 2007-11-13 | Intel Corporation | Low-K dielectric structure and method |
KR100592735B1 (en) * | 2004-11-16 | 2006-06-26 | 한국전자통신연구원 | Transistor of semiconductor element and a method for fabricating the same |
KR100634004B1 (en) | 2005-06-27 | 2006-10-13 | 동부일렉트로닉스 주식회사 | Method for forming multi-line interconnection using low-k material and multi-line interconnection using the same |
US7410852B2 (en) * | 2006-04-21 | 2008-08-12 | International Business Machines Corporation | Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors |
US7615427B2 (en) | 2006-06-05 | 2009-11-10 | Chartered Semiconductor Manufacturing, Ltd. | Spacer-less low-k dielectric processes |
US7585716B2 (en) | 2007-06-27 | 2009-09-08 | International Business Machines Corporation | High-k/metal gate MOSFET with reduced parasitic capacitance |
US20090017586A1 (en) * | 2007-07-09 | 2009-01-15 | International Business Machines Corporation | Channel stress modification by capped metal-semiconductor layer volume change |
US7838373B2 (en) | 2008-07-30 | 2010-11-23 | Intel Corporation | Replacement spacers for MOSFET fringe capacitance reduction and processes of making same |
US20100176513A1 (en) | 2009-01-09 | 2010-07-15 | International Business Machines Corporation | Structure and method of forming metal interconnect structures in ultra low-k dielectrics |
US8436404B2 (en) | 2009-12-30 | 2013-05-07 | Intel Corporation | Self-aligned contacts |
US8796099B2 (en) * | 2012-12-05 | 2014-08-05 | International Business Machines Corporation | Inducing channel strain via encapsulated silicide formation |
US9129987B2 (en) | 2014-01-24 | 2015-09-08 | Global Foundries, Inc. | Replacement low-K spacer |
US9312145B2 (en) * | 2014-03-07 | 2016-04-12 | Globalfoundries Inc. | Conformal nitridation of one or more fin-type transistor layers |
US10032924B2 (en) * | 2014-03-31 | 2018-07-24 | The Hong Kong University Of Science And Technology | Metal oxide thin film transistor with channel, source and drain regions respectively capped with covers of different gas permeability |
CN110444509A (en) * | 2014-04-01 | 2019-11-12 | 应用材料公司 | Integrated metal separation pad and air gap interconnect |
US9472628B2 (en) | 2014-07-14 | 2016-10-18 | International Business Machines Corporation | Heterogeneous source drain region and extension region |
US9728466B1 (en) * | 2016-04-28 | 2017-08-08 | International Business Machines Corporation | Vertical field effect transistors with metallic source/drain regions |
US9773913B1 (en) * | 2016-05-06 | 2017-09-26 | International Business Machines Corporation | Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance |
US10008386B2 (en) * | 2016-09-12 | 2018-06-26 | International Business Machines Corporation | Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device |
US10186456B2 (en) * | 2017-04-20 | 2019-01-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming contact plugs with reduced corrosion |
CN109390353A (en) * | 2017-08-14 | 2019-02-26 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
US10276434B1 (en) * | 2018-01-02 | 2019-04-30 | International Business Machines Corporation | Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration |
US10559685B2 (en) * | 2018-06-13 | 2020-02-11 | International Business Machines Corporation | Vertical field effect transistor with reduced external resistance |
US10854503B2 (en) * | 2018-07-16 | 2020-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with air gap and method sealing the air gap |
-
2019
- 2019-03-01 US US16/290,182 patent/US10770562B1/en active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11164815B2 (en) * | 2019-09-28 | 2021-11-02 | International Business Machines Corporation | Bottom barrier free interconnects without voids |
US11211462B2 (en) * | 2020-03-05 | 2021-12-28 | International Business Machines Corporation | Using selectively formed cap layers to form self-aligned contacts to source/drain regions |
TWI811781B (en) * | 2021-01-15 | 2023-08-11 | 台灣積體電路製造股份有限公司 | Method of forming the semiconductor device |
US11996317B2 (en) | 2021-01-15 | 2024-05-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for forming isolation regions by depositing and oxidizing a silicon liner |
Also Published As
Publication number | Publication date |
---|---|
US10770562B1 (en) | 2020-09-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10566430B2 (en) | Field effect transistor devices having gate contacts formed in active region overlapping source/drain contacts | |
US10832907B2 (en) | Gate-all-around field-effect transistor devices having source/drain extension contacts to channel layers for reduced parasitic resistance | |
US10658484B2 (en) | Non-planar field effect transistor devices with wrap-around source/drain contacts | |
US9837410B1 (en) | Fabrication of vertical field effect transistors with uniform structural profiles | |
US11038015B2 (en) | Non-planar field effect transistor devices with low-resistance metallic gate structures | |
US11062960B2 (en) | Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices | |
US10790393B2 (en) | Utilizing multilayer gate spacer to reduce erosion of semiconductor Fin during spacer patterning | |
US11728340B2 (en) | Single diffusion break isolation for gate-all-around field-effect transistor devices | |
US10692772B2 (en) | Integrating metal-insulator-metal capacitors with fabrication of vertical field effect transistors | |
US11289573B2 (en) | Contact resistance reduction in nanosheet device structure | |
US10892331B2 (en) | Channel orientation of CMOS gate-all-around field-effect transistor devices for enhanced carrier mobility | |
US10770562B1 (en) | Interlayer dielectric replacement techniques with protection for source/drain contacts | |
US10840145B2 (en) | Vertical field-effect transistor devices with non-uniform thickness bottom spacers | |
US20190393098A1 (en) | Simple contact over gate on active area | |
US20230187551A1 (en) | Stacked complementary transistor structure for three-dimensional integration |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHENG, KANGGUO;LI, JUNTAO;GREENE, ANDREW;AND OTHERS;SIGNING DATES FROM 20190227 TO 20190301;REEL/FRAME:048481/0015 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |