US20200273794A1 - Semiconductor device and methods of forming the same - Google Patents
Semiconductor device and methods of forming the same Download PDFInfo
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- US20200273794A1 US20200273794A1 US16/283,838 US201916283838A US2020273794A1 US 20200273794 A1 US20200273794 A1 US 20200273794A1 US 201916283838 A US201916283838 A US 201916283838A US 2020273794 A1 US2020273794 A1 US 2020273794A1
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- dielectric layer
- adhesion promoter
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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Definitions
- FIG. 1A to FIG. 1H are schematic cross-sectional views illustrating a method of forming a semiconductor device according to a first embodiment of the disclosure.
- FIG. 2A to FIG. 2C are schematic cross-sectional views illustrating a method of forming a semiconductor device according to a second embodiment of the disclosure.
- FIG. 3A to FIG. 3D are schematic cross-sectional views illustrating a method of forming a semiconductor device according to a third embodiment of the disclosure.
- FIG. 4 to FIG. 6 schematic cross-sectional views respectively illustrating a semiconductor device according to some embodiments of the disclosure.
- first and first features are formed in direct contact
- additional features may be formed between the second and first features, such that the second and first features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath”, “below”, “lower”, “on”, “over”, “overlying”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the FIG.s.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIG.s.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- the fins may be patterned by any suitable method.
- the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes.
- double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
- a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.
- FIG. 1A to FIG. 1H are schematic cross-sectional views illustrating a method of forming a semiconductor device according to a first embodiment of the disclosure.
- a substrate 10 is provided.
- the substrate 10 is a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped.
- the substrate 10 may be a wafer, such as a silicon wafer.
- an SOI substrate is a layer of a semiconductor material (such as silicon) formed on an insulator layer.
- the insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like.
- the insulator layer is provided on a substrate, typically a silicon or glass substrate.
- the semiconductor material of the substrate 10 may include silicon; germanium; a compound semiconductor including silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof.
- SiC silicon carbide
- GaAs gallium arsenic
- GaP gallium phosphide
- InP indium phosphide
- InAs indium arsenide
- InSb indium antimonide
- an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof.
- the substrate 10 may be a P-type substrate, an N-type substrate or a combination thereof and may have doped regions therein.
- the substrate 10 may be configured for an NMOS device, a PMOS device, an N-type FinFET device, a P-type FinFET device, other kinds of devices (such as, multiple-gate transistors, gate-all-around transistors or nanowire transistors) or combinations thereof.
- the substrate 10 for NMOS device or N-type FinFET device may include Si, SiP, SiC, SiPC, InP, GaAs, AlAs, InAs, InAlAs, InGaAs or combinations thereof.
- the substrate 10 for PMOS device or P-type FinFET device may include Si, SiGe, SiGeB, Ge, InSb, GaSb, InGaSb or combinations thereof.
- the substrate 10 may include a plurality of fins FA, as shown the portion above the dashed line in FIG. 1A (for the sake of brevity, fins FA are merely illustrated in FIG. 1A and not shown in the following figures).
- the fins FA protrude from a top surface of the substrate 10 .
- the substrate 10 has an isolation layer formed thereon. The isolation layer covers lower portions of the fins FA and exposes upper portions of the fins FA.
- the isolation layer is a shallow trench isolation (STI) structure.
- STI shallow trench isolation
- the substrate 10 has a plurality of gate stacks G formed thereon, source/drain (S/D) regions 14 formed therein, an etching stop layer 16 and a dielectric layer 17 formed thereon.
- S/D source/drain
- the gate stack G may include a gate dielectric layer 11 , a gate electrode 12 and spacers 13 .
- the gate dielectric layer 11 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials, or combinations thereof.
- the high-k material may have a dielectric constant greater than about 4 or 10.
- the high-k material includes metal oxide, such as ZrO 2 , Gd 2 O 3 , HfO 2 , BaTiO 3 , Al 2 O 3 , LaO 2 , TiO 2 , Ta 2 O 5 , Y 2 O 3 , STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO, a combination thereof, or a suitable material.
- the gate dielectric layer 11 may optionally include a silicate such as HfSiO, LaSiO, AlSiO, a combination thereof, or a suitable material.
- the gate dielectric layer 11 may be formed by a suitable technique such as a thermal oxidation process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or combinations thereof.
- the gate dielectric layer 11 is formed between the gate electrode 12 and the substrate 10 , but the disclosure is not limited thereto.
- the gate dielectric layer 11 may be formed between the gate electrode 12 and the substrate 10 , and between the gate electrode 12 and the spacers 13 to surround the sidewalls and bottom of the gate electrode 12 .
- an interfacial layer such as a silicon oxide layer may further be formed between the gate dielectric layer 11 and the substrate 10 .
- the gate electrode 12 may include doped polysilicon, undoped polysilicon, or metal-containing conductive material.
- the gate electrode G includes a work function metal layer and a fill metal layer on the work function metal layer.
- the work function metal layer is an N-type work function metal layer or a P-type work function metal layer.
- the N-type work function metal layer includes TiAl, TiAlN, or TaCN, conductive metal oxide, and/or a suitable material.
- the P-type work function metal layer includes TiN, WN, TaN, conductive metal oxide, and/or a suitable material.
- the fill metal layer includes copper, aluminum, tungsten, or other suitable materials.
- the gate electrode 12 may further include a liner layer, an interface layer, a seed layer, an adhesion layer, a barrier layer, a combination thereof or the like.
- the gate electrode 12 may be formed by formed by suitable processes such as ALD, CVD, physical vapor depositon (PVD), plating process, or combinations thereof.
- the spacers 13 are disposed on sidewalls of the gate dielectric layer 11 and the gate electrode 12 .
- the spacer 13 may be a single layer structure or a multi-layer structure.
- the spacers 13 may be formed by the following processes: a spacer material layer is formed on the substrate 10 covering the gate electrodes 12 , the spacer material layer includes SiO 2 , SiN, SiCN, SiOCN, SiOR (wherein R is an alkyl group such as CH 3 , C 2 H 5 or C 3 H 7 ), SiC, SiOC, SiON, combinations thereof or the like, and may be formed by a suitable deposition process such as CVD, ALD or the like. Thereafter, an etching process such as an anisotropic etching process is performed to remove a portion of the spacer material layer, and the spacers 13 on sidewalls of the gate electrodes 12 and gate dielectric layer 11 are remained.
- the S/D regions 14 are formed in the substrate 10 beside the gate stacks G.
- the S/D regions 14 are doped regions configured for a PMOS device or P-type FinFET and include p-type dopants, such as boron, BF 2 + , and/or a combination thereof.
- the S/D regions 14 are doped regions configured for a NMOS device or N-type FinFET, and include n-type dopants, such as phosphorus, arsenic, and/or a combination thereof.
- the S/D regions 14 may be formed by an ion implanting process with the gate stack G as a mask. However, the disclosure is not limited thereto.
- the S/D regions 14 are strained layers formed by epitaxial growing process such as selective epitaxial growing process.
- recesses are formed in the substrate 10 on sides of the gate stack G, and the strained layers are formed by selectively growing epitaxy layers from the recesses.
- the strained layers 14 include silicon germanium (SiGe), SiGeB, Ge, InSb, GaSb, InGaSb or combinations thereof for a P-type MOS or FinFET device.
- the strained layers 16 include silicon carbon (SiC), silicon phosphate (SiP), SiCP, InP, GaAs, AlAs, InAs, InAlAs, InGaAs or a SiC/SiP multi-layer structure, or combinations thereof for an N-type MOS or FinFET device.
- the strained layers 14 may be optionally implanted with an N-type dopant or a P-type dopant as needed.
- the top surfaces of the S/D regions 14 are substantially coplanar with the top surface of the substrate 10 , but the disclosure is not limited thereto.
- the S/D regions 14 may further extend upwardly along the sidewalls of the corresponding spacers 13 , and thus have top surfaces higher than the top surface of the substrate 10 .
- the depth of the S/D region 14 ranges from 3 nm to 30 nm, for example, but the disclosure is not limited thereto.
- the cross-sectional shape of the S/D region 14 shown in FIG. 1A is merely for illustration, and the disclosure is not limited thereto.
- the S/D region 14 may have any suitable shape as needed.
- the substrate 10 may further include lightly doped regions formed therein. For example, lightly doped drain (LDD) regions may be formed adjacent to the S/D regions 14 in the substrate 10 .
- LDD lightly doped drain
- the silicide layers 15 include nickel silicide (NiSi), cobalt silicide (CoSi), titanium silicide (TiSi), tungsten silicide (WSi), molybdenum silicide (MoSi), platinum silicide (PtSi), palladium silicide (PdSi), CoSi, NiCoSi, NiPtSi, Ir, PtIrSi, ErSi, Yb Si, PdSi, RhSi, or NbSi, or combinations thereof.
- the silicide layers 15 are formed by performing a self-aligned silicide (salicide) process including following steps.
- a metal layer is formed to at least cover the S/D regions 14 .
- the material of the metal layer may include Ti, Co, Ni, NiCo, Pt, Ni(Pt), Ir, Pt(Ir), Er, Yb, Pd, Rh, Nb, TiSiN, or combinations thereof.
- an annealing process is carried out such that the metal layer is reacted with the S/D regions 14 , so as to form the silicide layers 15 .
- the unreacted metal layer is then removed.
- the thickness of the silicide layer 15 ranges from 2 nm to l 0 nm, for example, but the disclosure is not limited thereto.
- the etching stop layer 16 and the dielectric layer 17 are formed on the substrate 10 and laterally aside the gate stacks G.
- the etching stop layer 16 may also be referred to as a contact etch stop layer (CESL), and is disposed between the substrate 10 and the dielectric layer 17 and between the gate stack G and the dielectric layer 17 .
- the etching stop layer 16 includes SiN, SiC, SiOC, SiON, SiCN, SiOCN, or the like, or combinations thereof.
- the etching stop layer 16 may be formed by CVD, plasma-enhanced CVD (PECVD), flowable CVD (FCVD), ALD or the like.
- the dielectric layer 17 includes a material different from that of the etching stop layer 16 .
- the dielectric layer 17 may also be referred to as an interlayer dielectric layer (ILD).
- the dielectric layer 17 includes silicon oxide, carbon-containing oxide such as silicon oxycarbide (SiOC), silicate glass, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorine-doped silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), combinations thereof and/or other suitable dielectric materials.
- SiOC silicon oxycarbide
- TEOS tetraethylorthosilicate
- BPSG borophosphosilicate glass
- FSG fluorine-doped silica glass
- PSG phosphosilicate glass
- BSG boron doped silicon glass
- the dielectric layer 17 may include low-k dielectric material with a dielectric constant lower than 4, extreme low-k (ELK) dielectric material with a dielectric constant lower than 2.5 and may further include a small amount of high-k material with a dielectric constant higher than 4.
- the low-k material includes a polymer based material, such as benzocyclobutene (BCB), FLARE®, or SILK®; or a silicon dioxide based material, such as hydrogen silsesquioxane (HSQ) or SiOF.
- the high-k dielectric material includes ZrO 2 , HfO 2 , for example.
- the dielectric layer 17 may be a single layer structure or a multi-layer structure.
- the dielectric layer 17 may be formed by CVD, PECVD, FCVD, spin coating or the like.
- the etching stop layer 16 and the dielectric layer 17 may be formed by forming etching stop material layer and dielectric material layer over the substrate 10 and the gate stacks G, and a planarization process is then performed, such that the top surfaces of the gate stacks G are exposed.
- the top surface of the etching stop layer 16 , the top surface of the dielectric layer 17 and the top surfaces of the gate stacks G are substantially coplanar with each other, but the disclosure is not limited thereto.
- the gate electrode 12 may be formed by a gate first process which is formed before forming the spacers 13 , or formed by a gate last process which is formed after the dielectric layer 17 is formed.
- a dielectric layer 18 is formed over the substrate 10 to cover the top surfaces of the gate stacks G, the etching stop layer 16 and the dielectric layer 17 .
- the dielectric layer 18 may also be referred to as an interlayer dielectric layer (ILD).
- the material of the dielectric layer 18 includes dielectric materials similar to, and may be the same as or different from those of the dielectric layer 17 , which are not described again.
- the dielectric layer 18 may be formed by CVD, PECVD, FCVD, spin coating or the like.
- the thickness of the dielectric layer 18 ranges from 1 nm to 10 nm, for example, but the disclosure is not limited thereto.
- a contact 22 is formed penetrating through the dielectric layer 18 , the dielectric layer 17 and the etching stop layer 16 to electrically connect to the S/D regions 14 .
- the contact 22 may be formed by the following processes.
- the dielectric layer 18 , the dielectric layer 17 and the etching stop layer 16 are patterned to form openings 19 (or called “contact holes”) corresponding to the S/D regions 14 .
- the patterning method includes photolithograph and one or more etching processes.
- a patterned mask layer with openings is formed on the dielectric layer 18 .
- the openings of the patterned mask layer correspond to the intended locations of the subsequently formed contact holes.
- the patterned mask layer is a patterned photoresist, for example.
- portions of the dielectric layer 18 , the dielectric layer 17 and the etching stop layer 16 are removed by etching process (es) using the patterned mask layer as an etch mask, so as to form the openings 19 .
- the opening 19 penetrates through the dielectric layer 18 , the dielectric layer 17 and the etching stop layer 16 to expose the corresponding S/D region 14 or the silicide layer 15 on the S/D region 14 .
- the opening 19 has substantially vertical sidewalls, as shown in FIG. 1B , but the disclosure is not limited thereto. In alternative embodiments, the opening 19 have inclined sidewalls.
- the cross-sectional shape of the opening 19 may be square, rectangular, trapezoid or any other suitable shape as needed, and the disclosure is not limited thereto.
- the contact 22 is formed on the S/D region 14 within the opening 19 .
- the contact 22 includes a barrier layer 20 and a conductive layer (or referred to as conductive feature) 21 .
- the barrier layer 20 may include titanium, tantalum, titanium nitride, tantalum nitride, manganese nitride or a combination thereof.
- the conductive layer 21 may include metal, such as tungsten (W), copper (Cu), Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof or any metal material with suitable resistance and gap-fill capability.
- the height of the contact 22 may range from 0.5 nm to 90 nm, but the disclosure is not limited thereto.
- a barrier material layer and a metal material layer are formed on the substrate 100 by sputtering, CVD, PVD, electrochemical plating (ECP), electrodeposition (ELD), ALD, or combinations thereof or the like.
- the metal material layer is formed by a CVD process, during which the process temperature ranges from 50° C. to 500° C.
- the carrier gas may include Ar or N 2 with a flow rate ranging from 10-500 sccm, but the disclosure is not limited thereto.
- the barrier material layer and the metal material layer fill in the opening 19 and cover the top surface of the dielectric layer 18 .
- a planarization step such as CMP is then performed to remove portions of the metal material layer and the barrier material layer over the dielectric layer 18 , such that the top surface of the dielectric layer 18 is exposed.
- a planarization step such as CMP is then performed to remove portions of the metal material layer and the barrier material layer over the dielectric layer 18 , such that the top surface of the dielectric layer 18 is exposed.
- the top surfaces of the barrier layer 20 and the conductive layer 21 are substantially coplanar with the top surface of the dielectric layer 18 .
- the barrier layer 20 surrounds sidewalls and bottom surface of the conductive layer 21 .
- the barrier layer 20 is located between the conductive layer 21 and the S/D region 14 , and between the conductive layer 21 and the dielectric layer 18 /the dielectric layer 17 /the etching stop layer 15 .
- the barrier layer 20 serves as a diffusion barrier to prevent the diffusion of the metal atoms of the conductive layer 21 .
- an etching stop layer 23 and a dielectric layer 24 are sequentially formed over the substrate 10 by CVD, PECVD, FCVD, spin coating or the like.
- the dielectric layer 24 may also be referred to as an interlayer dielectric layer (ILD).
- the materials of the etching stop layer 23 and the dielectric layer 24 may be selected from the same candidate materials of the etching stop layer 16 and the dielectric layer 17 , respectively.
- the material of the etching stop layer 23 is different from the material of the dielectric layer 24 and the material of dielectric layer 18 .
- the etching stop layer 23 may be thinner than the dielectric layers 18 and 24 .
- the thickness of the etching stop layer 23 ranges from lnm to 10 nm, for example, but the disclosure is not limited thereto.
- the thickness of the dielectric layer 24 may be the same as or different that of the dielectric layer 18 .
- a via hole 25 is then formed in the dielectric layer 24 and the etching stop layer 23 to expose the contact 22 .
- the via hole 25 may also be a via trench.
- the via hole 25 may be formed by a photolithograph and one or more etching processes.
- a patterned mask layer such as a patterned photoresist is formed on the dielectric layer 24 .
- the patterned mask layer has openings correspond to the intended locations of the subsequently formed via hole 25 .
- portions of the dielectric layer 24 and the etching stop layer 23 are removed by using the patterned mask layer as an etch mask, so as to form the via hole 25 .
- the sidewalls of the via hole 25 may be inclined, and the cross-sectional shape of the via hole may be trapezoid.
- the sidewalls of the via hole 25 may be substantially vertical, and the cross-sectional shape of the via hole may be square, rectangular, or the like.
- the disclosure is not limited thereto.
- the via hole 25 exposes a top surface of the contact 22 , and may further expose a portion of the top surface of the dielectric layer 18 .
- the width W 2 (such as, bottom width) of the via hole 25 may be larger than the width W 1 (such as, top width) of the contact 22 , but the disclosure is not limited thereto.
- an inhibitor layer 26 is formed on the contact 22 exposed by the via hole 25 .
- the inhibitor layer 26 is a self-assembled monolayer (SAM) 26 .
- the molecule of SAM 26 has a head group R 1 showing a specific affinity for the material of the contact 22 .
- the head group R 1 refers to one end group of the molecule and may also be called as a terminal group.
- the head group R 1 is connected to an alkyl chain.
- the alkyl chain may include a liner alkyl chain or a branched alkyl chain.
- the carbon chain length (C-C)n of the alkyl chain may be adjustable to define critical dimension of the SAM 26 , for example, to increase or decrease a thickness of the SAM 26 .
- the head group R 1 may include thiol (—SH), disulfide, dialkyl sulfide, —CN, —NH2, —P, —PO, —PO 3 , —SeH, —SeSe, for example.
- the SAM 26 may include din-alkyl sulfide, di-n-alkyl disulfide, 3-thiophenol, mercaptopyridine, mercaptoaniline, thiophene, cysteine, xanthate, thiocarbaminate, thiocarbamate, thiourea, mercaptoimidazole, alkanethiol (such as CH 3 (CH 2 ) 15 SH), alkaneselenol, combinations thereof or the like.
- the SAM 26 may be formed by a vapor deposition process or a liquid deposition process.
- the SAM 26 is created by chemisorption of the hydrophilic head groups onto the contact 22 , followed by a slow two-dimensional organization of hydrophobic head groups.
- SAM 26 adsorption may occur from solution by immersion of the structure shown in FIG. 1C into a dilute solution of, in one embodiment, an alkane thiol in ethanol.
- SAM 26 adsorption may also occur from a vapor phase.
- the adsorbed molecules initially form a disordered mass of molecules, and instantaneously begin to form crystalline or semicrystalline structures on the contact 22 in a monolayer.
- the SAM 26 is selectively deposited on the contact 22 , forming a metal complex in some embodiment.
- the SAM 26 may be deposited via spin-on coating from a solution of, for example, an alkane thiol in ethanol.
- the un-reacted portions of the SAM material on the surfaces of the dielectric layers 18 / 24 and etching stop layer 23 may be rinsed off using suitable solvent based rinse, remaining a layer of SAM 26 on the surfaces of the contact 22 .
- a thickness of the SAM layer left on the contact 22 may be adjusted by adjusting the carbon chain length of the alkyl chain of the SAM.
- the inhibitor layer (SAM) 26 is formed both on the conductive layer 21 and the barrier layer 20 of the contact 22 , but the disclosure is not limited thereto. In alternative embodiments, the inhibitor layer 26 may be formed on the conductive layer 21 and not formed on the barrier layer 20 .
- an adhesion promoter layer 29 is formed on the exposed dielectric layer 18 , etching stop layer 23 and the dielectric layer 24 through a selective deposition process.
- the material of the adhesion promoter layer 29 is different from the material of the barrier layer 20 .
- the material of the adhesion promoter layer 29 includes oxide or nitride, such as metal oxide, metal nitride, or combinations thereof.
- the material of the adhesion promoter layer 29 may be a conductive material such as conductive metal oxide or a non-conductive material such as a dielectric material.
- the dielectric material may be low-k dielectric material, or high-k dielectric material.
- the metal oxide includes RuO, (such as RuO 2 ), WO x , IrO 2 , NiO x , TiO x , ReO 3 , SrRuO 3 , La o.3 Sr 0.5 CoO 3 , or combinations thereof, for example.
- the low-k dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.
- the high-k dielectric material may include ZrO 2 , HfO 2 or the like or a combination thereof.
- the thickness of the adhesion promoter layer 29 ranges from 0.5 nm to 1 nm, for example, but the disclosure is not limited thereto.
- the adhesion promoter layer 29 is formed by a selective deposition process such as a selective CVD or selective ALD process.
- the precursor or/and reaction gas of the selective deposition process may adsorb on the dielectric layers 18 / 24 and etching stop layer 23 and conduct a reaction to form the adhesion promoter layer 29 , and the precursor or/and the reaction gas would not absorb on the inhibitor layer 26 .
- the reaction mechanism of the selective deposition process and the property of the inhibitor layer 26 makes the adhesion promoter layer 29 only deposit on the surfaces of the dielectric layers 18 / 24 and the etching stop layer 23 , and not deposit on the inhibitor layer 26 over the contact 22 .
- the molecules of the inhibitor layer (SAM) 26 include specially designed functional groups to inhibit the adhesion promoter layer 29 deposition thereon.
- the specially designed functional groups (such as terminal groups R 2 shown in FIG. 1D ) of the SAM may have hydrophobic properties, for example, the terminal groups R 2 may include methyl (—CH 3 ), phenyl, pyrrole, tolyl, the like, or combinations thereof, which would not react with or adsorb the precursor or/and reaction gas used in the deposition process of the adhesion promoter layer 29 , so as to inhibit the adhesion promoter layer 29 depositing on the inhibitor layer 26 over the contact 22 .
- the terminal group R 2 is also referred to as tail group.
- the inhibitor layer 26 is removed by an etching process, such as wet etching, dry etching, or the like, or a combination thereof.
- an etching process such as wet etching, dry etching, or the like, or a combination thereof.
- the top surface of the contact 22 is exposed.
- a conductive material layer 30 ′ is formed over the substrate 10 .
- the conductive material layer 30 ′ fills in the via hole 25 and covers the top surface of the adhesion promoter layer, and is electrically connected to the contact 22 .
- the conductive material layer 30 ′ includes metal or metal alloy, such as Co, Cu, Ru, Ni, Al, Pt, Mo, W, Al, Ir, Os, alloy thereof, or combinations thereof.
- the forming method of the conductive material layer 30 ′ may include CVD, ALD, PVD, ECP, ELD, or the like or combinations thereof.
- the conductive material layer 30 ′ is formed by a CVD process, during which the process temperature ranges from 50° C. to 500° C., the carrier gas may include Ar or N2 with a flow rate ranging from 10-500 sccm, but the disclosure is not limited thereto.
- the material of the adhesion promoter layer 29 is selected depending on the material of the conductive material layer 30 ′.
- the adhesion promoter layer 29 includes a metal oxide correspond to the metal of the conductive material layer 30 ′, but the disclosure is not limited thereto.
- the conductive material layer 30 ′ including Ru correspond to the adhesion promoter layer 29 including RuO 2 , IrO 2 , NiOx, TiO x , ReO3, SrRuO 3 .
- the conductive material layer 30 ′ including W correspond to the adhesion promoter layer 29 including WOx.
- the conductive material layer 30 ′ including Co correspond to the adhesion promoter layer 29 including La 0.5 Sr 0.5 CoO 3 .
- the disclosure is not limited thereto.
- a planarization process (such as chemical mechanical polishing, CMP) is then performed to remove a portion of the conductive material layer 30 ′ over the top surface of the dielectric layer 24 .
- the planarization process is performed until the top surface of the dielectric layer 24 is exposed, that is, the adhesion promoter layer 29 over the top surface of the dielectric layer 24 is also removed by the planarization process.
- a adhesion promoter layer 29 a and a conductive layer 30 are remained in the via hole 25 .
- the top surface of the adhesion promoter layer 29 a and the top surface of the conductive layer 30 are substantially coplanar with the top surface of the dielectric layer 24 .
- the disclosure is not limited thereto.
- the adhesion promoter layer 29 a and the conductive layer 30 constitute a via 32 .
- the via 32 is located in the via hole 25 to electrically connect to the contact 22 .
- the height of the via 32 may range from 0.5 nm to 60 nm, but the disclosure is not limited thereto.
- the semiconductor device 50 a includes the substrate 10 , the gate stack G, the S/D regions 14 , the etching stop layer 16 , the dielectric layer 17 , the dielectric layer 18 , the etching stop layer 23 , the dielectric layer 24 , the contact 22 and the via 32 .
- the S/D regions 14 are located in the substrate 10 and beside the gate stack G.
- the S/D regions 14 include the silicide layers 15 formed thereon.
- the etching stop layer 16 and the dielectric layer 17 are located on the substrate 10 and laterally aside the gate stacks G.
- the dielectric layer 18 , the etching stop layer 23 and the dielectric layer 24 are located over the gate stacks G and the dielectric layer 17 .
- the contact 22 penetrates through the dielectric layer 18 , the dielectric layer 17 and the etching stop layer 16 to electrically connect to the S/D regions 14 .
- the contact 22 is landing on the silicide layer 15 of the S/D region 14 .
- the contact 22 includes a barrier layer 20 and a conductive layer 21 .
- the barrier layer 20 surrounds sidewalls and bottom of the conductive layer 21 to serve as a diffusion barrier.
- the via 32 penetrates through the dielectric layer 24 and the etching stop layer 23 to electrically connect to the contact 22 .
- the cross sectional shape of the contact 22 and the via 32 may respectively be square, rectangular, trapezoid or any other suitable shape as needed, and the disclosure is not limited thereto.
- the via 32 includes the adhesion promoter layer 29 a and the conductive layer 30 .
- the conductive layer 30 is located on the electrically connect to the contact 22 .
- the bottom surface of the conductive layer 30 is in physical and electric contact with the top surfaces of the barrier layer 20 and the conductive layer 21 of the contact 22 .
- the adhesion promoter layer 29 a surrounds sidewalls of the conductive layer 30 and is laterally between the conductive layer 30 and the dielectric layer 24 , and between the conductive layer 30 and the etching stop layer 23 .
- the bottom surface of the adhesion promoter layer 29 a is in physical contact with the top surface of the dielectric layer 18 .
- the bottom surface of the conductive layer 30 and the bottom surface of the adhesion promoter layer 29 a are substantially coplanar with the bottom surface of the etching stop layer 23 .
- the adhesion promoter layer 29 a is not in contact with the contact 22 , and is separated from the contact 22 by the conductive layer 30 .
- the adhesion promoter layer 29 a may be electrically connected to the contact 22 through the conductive layer 30 .
- the conductive layer 30 penetrates through the dielectric layer 24 , the etching stop layer 23 and the adhesion promoter layer 29 a to contact with the top surface of the contact 22 .
- the adhesion promoter layer 29 a may help to improve the adhesion between the conductive layer 30 and the dielectric layer 24 and between the conductive layer 30 and the etching stop layer 23 , and may also serve as diffusion barrier for preventing the metal atoms of the conductive layer 30 from diffusing to the adjacent dielectric layer 24 or/and the etching stop layer 23 .
- the contact 22 is with barrier layer, while the via 32 is free of a conventional barrier layer (that is, barrierless), but the disclosure. In some other embodiments, both the contact 22 and the via 32 are barrierless.
- FIG. 2A to FIG. 2C are schematic cross-sectional views illustrating a method of forming a semiconductor device according to a second embodiment of the disclosure.
- the second embodiment differs from the first embodiment in that no inhibitor layer is formed, and the selective deposition of the adhesion promoter layer is implemented through the different properties of the contact 22 and the dielectric layers 18 / 24 and the etching stop layer 23 .
- processes similar to FIG. 1C is performed to form a via hole 25 in the etching stop layer 23 and the dielectric layer 24 .
- the via hole 25 expose the top surface of the contact 22 , a portion of a top surface of the dielectric layer 18 , and sidewalls of the dielectric layer 24 and the etching stop layer 23 .
- the materials of the dielectric layers 18 / 24 , the etching stop layer 23 and the contact 22 are substantially the same as those described in the first embodiment, which are not described again.
- a selective deposition process is performed to form an adhesion promoter layer 129 on the top surface of the dielectric layer 18 , the sidewalls of the etching stop layer 23 , the sidewalls of the dielectric layer 24 exposed by the via hole 25 , and on the top surface of the dielectric layer 24 , and the selective deposition process is performed without forming an inhibitor layer on the contact 22 .
- the selective deposition process includes a pulsed mode ALD or CVD, for example. The selective deposition process may be performed by using a precursor and a reaction gas to react to form the adhesion promoter layer 129 .
- the reaction gas adsorbs on the exposed surface of the dielectric layer 18 , etching stop layer 23 and the dielectric layer 24 and does not adsorb on the exposed surface of the contact 22 , due to the different properties of the dielectric layer 18 /etching stop layer 23 /the dielectric layer 24 and the contact 22 .
- the oxygen or ammonia absorbs on the exposed dielectric layer 18 , etching stop layer 23 and dielectric layer 24 due to the hydrophilic properties thereof, and does not absorb on the contact 22 because the contact 22 have weaker hydrophilic property or does not have the hydrophilic property.
- the precursor reacts with the reaction gas absorbed on the dielectric layer 18 , etching stop layer 23 and dielectric layer 24 , and the adhesion promoter layer 129 is thus formed.
- the adhesion promoter layer 129 is selectively formed on the top surface of the dielectric layer 18 , the sidewalls of the etching stop layer 23 and the dielectric layer 24 without forming on the top surface of the contact 22 .
- the precursor of the selective deposition process for forming the adhesion promoter layer 129 may include TiCl 4 , TDMAT, TDEAT, TEMAT, and the reaction gas includes O 2 , wherein O 2 adsorbs on the exposed dielectric layer 18 , etching stop layer 23 and dielectric layer 24 without adsorbing on the contact 22 .
- the precursor of the selective deposition process may include HfCl 4 , [(CH 2 CH 3 ) 2 N] 4 Hf or the like, and the reaction gas includes O 2 , wherein O 2 adsorbs on the exposed dielectric layer 18 , etching stop layer 23 and dielectric layer 24 without adsorbing on the contact 22 .
- the precursor of the selective deposition process may include [Ru(tfa) 3 ], cyclo hexdiene or carbonyl based Ru precursors like Ru(CO)x or [Ru(CO) 3 C 6 H 8 ] 7 , [Ru(acac) 3 ], [Ru(CO) 2 (hfac) 2 ] or the like or combinations thereof, and the reaction gas include O 2 , wherein O 2 adsorbs on the exposed dielectric layer 18 , etching stop layer 23 and dielectric layer 24 without adsorbing on the contact 22 .
- the selective deposition process uses ammonia (NH 3 ) as the reaction gas, and the selective deposition process is performed in a way similar to that described above.
- NH 3 ammonia
- a conductive material layer 30 ′ is formed over the substrate 10 by CVD, ALD, PVD, ECP, ELD, or the like.
- the material of the conductive material layer 30 ′ is similar to, the same as or different from those described in the first embodiment.
- the conductive material layer 30 ′ and the adhesion promoter layer 129 may be in-situ formed.
- the conductive material layer 30 ′ includes a metal (such as W), and the adhesion promoter layer 129 includes a metal oxide (such as WO x ) correspond to the metal of the conductive material layer 30 ′, the conductive material layer 30 ′ and the adhesion promoter layer 129 may be formed in a same chamber of the a deposition machine by the following process.
- process gases such as WF 6 and O 2 are introduced into the deposition chamber to form the metal oxide WO x of the adhesion promoter layer 129 , thereafter, O 2 source gas is closed to stop introducing O 2 into the chamber, and keep introducing the precursor WF 6 to form the metal W of the conductive material layer 30 ′.
- FIG. 3A to FIG. 3D are schematic cross-sectional view illustrating a method of forming a semiconductor device according to a third embodiment of the disclosure.
- the third embodiment differs from the foregoing embodiments in that the adhesion promoter layer is formed by a blanket deposition process and an etching back process.
- an adhesion promoter layer 229 is blanket deposited over the substrate 10 .
- the deposition process includes CVD, ALD, or the like or combinations thereof.
- the adhesion promoter layer 229 covers the top surface of the dielectric layer 24 and fills in the via hole 25 to cover the inner surface of the via hole 25 .
- the top surface of the contact 22 , a portion of the top surface of the dielectric layer 18 , the sidewalls of the etching stop layer 23 , the sidewalls and the top surface of the dielectric layer 24 are covered by the adhesion promoter layer 229 .
- a portion of the adhesion promoter layer 229 is removed by an etching process (such as anisotropic etching process) to form an adhesion promoter layer 229 a.
- the adhesion promoter layer 229 is etched back, such that the horizontal portions thereof are removed, that is, the portions of the adhesion promoter layer 229 on the top surface of the dielectric layer 24 and at the bottom of the via hole 25 are removed, and the portion of the adhesion promoter layer 229 on sidewalls of the via hole 25 remain.
- the adhesion promoter layer 229 a is disposed on sidewalls of the via hole 25 , the top surface of the adhesion promoter layer 229 a may be substantially coplanar with the top surface of the dielectric layer 24 .
- the adhesion promoter layer 229 a covers a portion of the top surface of the dielectric layer 18 , and may or may not cover the top surface of the contact 22 . In other words, the top surface of the contact 22 is at least partially exposed by the adhesion promoter layer 229 a.
- the adhesion promoter layer 229 a is not in contact with the top surface of the contact 22 , and the top surface of the contact 22 is completely exposed by the adhesion promoter layer 229 a. In some other embodiments, a small portion of the top surface of the contact 22 may be covered by the adhesion promoter layer 229 a.
- a conductive material layer 30 ′ is formed over the substrate 10 .
- the conductive material layer 30 ′ covers the top surface of the dielectric layer 24 and fills into the via hole 25 .
- the conductive material layer 30 ′ is in contact with the top surface of the dielectric layer 24 .
- a planarization process is performed to remove a portion of the conductive material layer 30 ′ over the top surface of the dielectric layer 24 , and a conductive layer 30 in the via hole 25 is remained.
- the conductive layer 30 and the adhesion promoter layer 229 a constitute a via 232 .
- a semiconductor device 50 c is thus formed.
- the semiconductor device 50 c is similar to the semiconductor device 50 a, expect that the forming method of the adhesion promoter layer 229 a is different from that of the adhesion promoter layer 29 a, and the adhesion promoter layer 229 a may be in contact with the contact 22 in some embodiments.
- FIG. 4 and FIG. 5 are schematic cross-sectional views illustrating semiconductor devices according to some embodiments of the disclosure.
- the adhesion promoter layer 29 / 129 over the top surfaces of dielectric layer 24 / 124 are removed during the planarization process, but the disclosure is not limited thereto.
- the adhesion material layer 29 is made of a dielectric layer
- a planarization process is performed to remove the conductive material layer 30 ′ over the top surface of the adhesion promoter layer 29 , so as to form a conductive layer 30 a.
- the planarization process may include a CMP process, and the adhesion promoter layer 29 may serve as a CMP stop layer during the CMP process.
- the top surface of the conductive layer 30 a is substantially coplanar with the top surface of the adhesion promoter layer 29 .
- the semiconductor device 50 d includes the substrate 10 , the gate stack G, the S/D regions 14 , the etching stop layer 16 , the dielectric layer 17 , the dielectric layer 18 , the etching stop layer 23 , the dielectric layer 24 , the contact 22 , the conductive layer 30 a and the adhesion promoter layer 29 .
- the conductive layer 30 a is in electrically contact with the contact 22 .
- the adhesion promoter layer 29 is electrically isolated from the conductive layer 30 a and the contact 22 .
- the adhesion promoter layer 29 and the conductive layer 30 a are located in the via hole 25 and protrude from the top surface of the dielectric layer 24 .
- the top surface of the dielectric layer 24 is covered by the adhesion promoter layer 29 .
- the top surface of the conductive layer 30 a is coplanar with the top surface of the adhesion promoter layer 29 and higher than the top surface of the dielectric layer 24 .
- the adhesion promoter layer 29 surrounds the sidewalls of the conductive layer 30 a and further extends to cover the top surface of the dielectric layer 24 .
- the adhesion promoter layer 29 includes a first portion FP and a second portion SP connected to each other.
- the first portion FP is located in the via hole 25 and protrudes from the top surface of the dielectric layer 24 , surrounding the sidewalls of the conductive layer 30 a.
- the first portion FP is located between the conductive layer 30 a and the etching stop layer 23 , between the conductive layer 30 a and the dielectric layer 24 , and between the conductive layer 30 a and the second portion SP.
- the conductive layer 30 a and the first portion FP of the adhesion promoter layer 29 constitute a via 32 a.
- the top surface of the via 32 a protrudes from the top surface of the dielectric layer 24 .
- the second portion SP is located on the top surface of the dielectric layer 24 and laterally aside the via 30 a, extending in a direction parallel with the top surface of the substrate 10 .
- the first portion FP and the second portion SP are comprised in the same layer of the adhesion promoter layer 29 , no interface is existed between the first portion FP and the second portion SP, that is, no interface is existed between the via 32 a and the second portion SP.
- the planarization process may be stopped at the top surface of the adhesion promoter layer 29 , as shown in FIG. 4 , and may also be stopped at the top surface of the dielectric layer 24 , as shown in FIG. 1H . That is, the adhesion promoter layer 29 over the top surface of the dielectric layer 24 may or may not be removed during the planarization process. In the embodiments in which the adhesion promoter layer 29 is made of conductive material, the planarization process will remove the adhesion promoter layer 29 over the top surface of the dielectric layer 24 .
- the planarization process may remove the conductive material layer 30 ′ over the top surface of the adhesion promoter layer 129 and not remove the adhesion promoter layer 129 .
- the silicide layer 15 is formed after the spacer 13 is formed, as shown in FIG. 1H , FIG. 2 C, FIG. 3D and FIG. 4 , the silicide layer 15 covers a portion of the top surface of the S/D region 14 .
- the top surface of the silicide layer 15 is covered by the etching stop layer 16 and the contact 22 , the sidewalls of the silicide layer 15 is in contact with the spacer 13 of the gate stack G.
- a portion of the silicide layer 15 is located between the etching stop layer 16 and the S/D region 14 .
- the disclosure is not limited thereto.
- FIG. 5 illustrates a semiconductor device 50 e according to some other embodiments of the disclosure.
- a silicide layer 115 may be formed on the S/D region 14 after the contact hole 19 ( FIG. 1B ) is formed.
- the sidewalls of the silicide layer 115 is aligned with the sidewalls of the contact 22 .
- the silicide layer 115 is not in contact with the spacer 13 of the gate stack G, and is separated from the spacer 13 by the etching stop layer 16 therebetween.
- the top surface of the silicide layer 115 is covered by the contact 22 , and the sidewalls of the silicide layer 115 are covered by the etching stop layer 16 .
- a portion of the top surface of the S/D region 14 is covered by the silicide layer 115 and the etching stop layer 16 .
- the semiconductor devices 50 a - 50 e may be planar transistors, FinFETs, gate-all-around transistors, nanowire transistors, multiple-gate transistors, or the like, and the disclosure is not limited thereto.
- the semiconductor device 50 a - 50 e may be further subjected to variety of processes, such that a plurality of (multi-layers of) metal lines and vias and dielectric layers are formed over the via 32 / 32 a / 132 / 232 and the dielectric layer 24 / 124 , so as to form an interconnection structure over the substrate 10 .
- the metal lines are extending on top surfaces of the dielectric layers in a horizontal direction parallel with a top surface of the substrate 10 , for example.
- the vias vertically penetrates through the dielectric layers to connect the metal lines in different layers.
- the via are formed without barrier layer surrounding the conductive layer, and the adhesion promoter layer is formed on sidewalls of the conductive layer.
- the resistivity of barrierless via of the disclosure is lower than a conventional via having barrier layer.
- the via is free of barrier layer (that is, barrierless), while the contact includes a barrier layer, but the disclosure is not limited thereto.
- the barrierless process may also be applied to the contact.
- a semiconductor device 50 f may include a contact 122 and a via 32 , both the contact 122 and the via 32 are free of a barrier layer.
- the contact 122 includes an adhesion promoter layer 120 and a conductive layer 121 .
- the adhesion promoter layer 120 and the conductive layer 121 may be formed by similar processes of the adhesion promoter layer and conductive layer of the via as described above.
- the conductive layer 121 is in direct contact with the silicide layer 15 on the S/D region 14 .
- the adhesion promoter layer 120 is located on sidewalls of the conductive layer 121 .
- the barrierless process of the disclosure may be applied to contact, via or/and the other metal lines or vias of the interconnection structure to be formed over the substrate 10 .
- all of the metal features (metal lines, vias, and contacts) of the interconnection structure are barrierless.
- some of the metal features of the interconnection structure are barrierless, and others are formed with barrier layer.
- At least the via is formed free of barrier layer, and the adhesion promoter layer is selectively formed at least between the conductive layer and the adjacent dielectric layers.
- the adhesion promoter layer help to improve the adhesion between the conductive layer and the adjacent dielectric features, thus avoiding metal peeling issue.
- the adhesion promoter layer may also present the metal diffusion of the conductive layer. As a result, the performance and the yield of the semiconductor device are improved, and defects thereof are reduced.
- a semiconductor device includes a substrate, a gate stack and a first dielectric layer over the substrate, a source/drain (S/D) region, a contact, and a via.
- the first dielectric layer is laterally aside and over the gate stack.
- the S/D region is located in the substrate on sides of the gate stack.
- the contact penetrates through the first dielectric layer to electrically connect to the S/D region.
- the via penetrates through a second dielectric layer to connect to the contact.
- the via includes a conductive layer and an adhesion promoter layer on sidewalls of the conductive layer.
- the conductive layer is in contact with the contact.
- a semiconductor device includes a substrate, a gate stack and a first dielectric layer over the substrate, a contact, and a conductive layer.
- the first dielectric layer is laterally aside and over the gate stack.
- the contact penetrates through the first dielectric layer to electrically connect to the substrate.
- the conductive layer penetrates through a second dielectric layer and an adhesion promoter layer to connect to the contact.
- the adhesion promoter layer is laterally between the conductive layer and the second dielectric layer.
- a method of manufacturing a semiconductor device includes the following processes.
- a substrate having a gate stack formed thereon is provided.
- a first dielectric layer is formed aside and over the gate stack.
- a contact is formed to penetrate through the first dielectric layer to connect to the substrate.
- a second dielectric layer is formed over the first dielectric layer.
- the second dielectric layer is patterned to form a via hole to expose a top surface of the contact and a portion of a top surface of the first dielectric layer.
- An adhesion promoter layer is selectively deposited on the portion of the top surface of the first dielectric layer and sidewalls of the second dielectric layer exposed by the via hole.
- a conductive layer is formed within the via hole to electrically contact with the contact.
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Abstract
Description
- The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that may be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
- Such scaling down has also increased the complexity of manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1A toFIG. 1H are schematic cross-sectional views illustrating a method of forming a semiconductor device according to a first embodiment of the disclosure. -
FIG. 2A toFIG. 2C are schematic cross-sectional views illustrating a method of forming a semiconductor device according to a second embodiment of the disclosure. -
FIG. 3A toFIG. 3D are schematic cross-sectional views illustrating a method of forming a semiconductor device according to a third embodiment of the disclosure. -
FIG. 4 toFIG. 6 schematic cross-sectional views respectively illustrating a semiconductor device according to some embodiments of the disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “over”, “overlying”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the FIG.s. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIG.s. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- In some embodiments in which the semiconductor device is FinFET device, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.
-
FIG. 1A toFIG. 1H are schematic cross-sectional views illustrating a method of forming a semiconductor device according to a first embodiment of the disclosure. - Referring to
FIG. 1A , asubstrate 10 is provided. In some embodiments, thesubstrate 10 is a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. Thesubstrate 10 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material (such as silicon) formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of thesubstrate 10 may include silicon; germanium; a compound semiconductor including silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. - Depending on the requirements of design, the
substrate 10 may be a P-type substrate, an N-type substrate or a combination thereof and may have doped regions therein. Thesubstrate 10 may be configured for an NMOS device, a PMOS device, an N-type FinFET device, a P-type FinFET device, other kinds of devices (such as, multiple-gate transistors, gate-all-around transistors or nanowire transistors) or combinations thereof. In some embodiments, thesubstrate 10 for NMOS device or N-type FinFET device may include Si, SiP, SiC, SiPC, InP, GaAs, AlAs, InAs, InAlAs, InGaAs or combinations thereof. Thesubstrate 10 for PMOS device or P-type FinFET device may include Si, SiGe, SiGeB, Ge, InSb, GaSb, InGaSb or combinations thereof. - In some embodiments in which the
substrate 10 is configured for a FinFET device, thesubstrate 10 may include a plurality of fins FA, as shown the portion above the dashed line inFIG. 1A (for the sake of brevity, fins FA are merely illustrated inFIG. 1A and not shown in the following figures). The fins FA protrude from a top surface of thesubstrate 10. In some embodiments, thesubstrate 10 has an isolation layer formed thereon. The isolation layer covers lower portions of the fins FA and exposes upper portions of the fins FA. In some embodiments, the isolation layer is a shallow trench isolation (STI) structure. - In some embodiments, the
substrate 10 has a plurality of gate stacks G formed thereon, source/drain (S/D)regions 14 formed therein, anetching stop layer 16 and adielectric layer 17 formed thereon. - Still referring to
FIG. 1A , the gate stack G may include a gatedielectric layer 11, agate electrode 12 andspacers 13. The gatedielectric layer 11 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials, or combinations thereof. The high-k material may have a dielectric constant greater than about 4 or 10. In some embodiments, the high-k material includes metal oxide, such as ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2O5, Y2O3, STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO, a combination thereof, or a suitable material. In alternative embodiments, thegate dielectric layer 11 may optionally include a silicate such as HfSiO, LaSiO, AlSiO, a combination thereof, or a suitable material. - The
gate dielectric layer 11 may be formed by a suitable technique such as a thermal oxidation process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or combinations thereof. In some embodiments, thegate dielectric layer 11 is formed between thegate electrode 12 and thesubstrate 10, but the disclosure is not limited thereto. In some other embodiment, thegate dielectric layer 11 may be formed between thegate electrode 12 and thesubstrate 10, and between thegate electrode 12 and thespacers 13 to surround the sidewalls and bottom of thegate electrode 12. In some embodiments, an interfacial layer such as a silicon oxide layer may further be formed between thegate dielectric layer 11 and thesubstrate 10. - The
gate electrode 12 may include doped polysilicon, undoped polysilicon, or metal-containing conductive material. In some embodiments, the gate electrode G includes a work function metal layer and a fill metal layer on the work function metal layer. The work function metal layer is an N-type work function metal layer or a P-type work function metal layer. In some embodiments, the N-type work function metal layer includes TiAl, TiAlN, or TaCN, conductive metal oxide, and/or a suitable material. In alternative embodiments, the P-type work function metal layer includes TiN, WN, TaN, conductive metal oxide, and/or a suitable material. The fill metal layer includes copper, aluminum, tungsten, or other suitable materials. In some embodiments, thegate electrode 12 may further include a liner layer, an interface layer, a seed layer, an adhesion layer, a barrier layer, a combination thereof or the like. Thegate electrode 12 may be formed by formed by suitable processes such as ALD, CVD, physical vapor depositon (PVD), plating process, or combinations thereof. - The
spacers 13 are disposed on sidewalls of thegate dielectric layer 11 and thegate electrode 12. Thespacer 13 may be a single layer structure or a multi-layer structure. In some embodiments, thespacers 13 may be formed by the following processes: a spacer material layer is formed on thesubstrate 10 covering thegate electrodes 12, the spacer material layer includes SiO2, SiN, SiCN, SiOCN, SiOR (wherein R is an alkyl group such as CH3, C2H5 or C3H7), SiC, SiOC, SiON, combinations thereof or the like, and may be formed by a suitable deposition process such as CVD, ALD or the like. Thereafter, an etching process such as an anisotropic etching process is performed to remove a portion of the spacer material layer, and thespacers 13 on sidewalls of thegate electrodes 12 andgate dielectric layer 11 are remained. - S/
D regions 14 are formed in thesubstrate 10 beside the gate stacks G. In some embodiments, the S/D regions 14 are doped regions configured for a PMOS device or P-type FinFET and include p-type dopants, such as boron, BF2 +, and/or a combination thereof. In alternative embodiments, the S/D regions 14 are doped regions configured for a NMOS device or N-type FinFET, and include n-type dopants, such as phosphorus, arsenic, and/or a combination thereof. The S/D regions 14 may be formed by an ion implanting process with the gate stack G as a mask. However, the disclosure is not limited thereto. - In some other embodiments, the S/
D regions 14 are strained layers formed by epitaxial growing process such as selective epitaxial growing process. In some embodiments, recesses are formed in thesubstrate 10 on sides of the gate stack G, and the strained layers are formed by selectively growing epitaxy layers from the recesses. In some embodiments, thestrained layers 14 include silicon germanium (SiGe), SiGeB, Ge, InSb, GaSb, InGaSb or combinations thereof for a P-type MOS or FinFET device. In alternative embodiments, thestrained layers 16 include silicon carbon (SiC), silicon phosphate (SiP), SiCP, InP, GaAs, AlAs, InAs, InAlAs, InGaAs or a SiC/SiP multi-layer structure, or combinations thereof for an N-type MOS or FinFET device. In some embodiments, thestrained layers 14 may be optionally implanted with an N-type dopant or a P-type dopant as needed. - In some embodiments, the top surfaces of the S/
D regions 14 are substantially coplanar with the top surface of thesubstrate 10, but the disclosure is not limited thereto. In some other embodiments, the S/D regions 14 may further extend upwardly along the sidewalls of the correspondingspacers 13, and thus have top surfaces higher than the top surface of thesubstrate 10. In some embodiments, the depth of the S/D region 14 ranges from 3nm to 30nm, for example, but the disclosure is not limited thereto. The cross-sectional shape of the S/D region 14 shown inFIG. 1A is merely for illustration, and the disclosure is not limited thereto. The S/D region 14 may have any suitable shape as needed. In some embodiments, thesubstrate 10 may further include lightly doped regions formed therein. For example, lightly doped drain (LDD) regions may be formed adjacent to the S/D regions 14 in thesubstrate 10. - Still referring to
FIG. 1A , in some embodiments, after the S/D regions 14 are formed and before forming theetching stop layer 16, a plurality ofsilicide layers 15 may be formed on the S/D regions 14. In some embodiments, the silicide layers 15 include nickel silicide (NiSi), cobalt silicide (CoSi), titanium silicide (TiSi), tungsten silicide (WSi), molybdenum silicide (MoSi), platinum silicide (PtSi), palladium silicide (PdSi), CoSi, NiCoSi, NiPtSi, Ir, PtIrSi, ErSi, Yb Si, PdSi, RhSi, or NbSi, or combinations thereof. - In some embodiments, the silicide layers 15 are formed by performing a self-aligned silicide (salicide) process including following steps. A metal layer is formed to at least cover the S/
D regions 14. The material of the metal layer may include Ti, Co, Ni, NiCo, Pt, Ni(Pt), Ir, Pt(Ir), Er, Yb, Pd, Rh, Nb, TiSiN, or combinations thereof. Thereafter, an annealing process is carried out such that the metal layer is reacted with the S/D regions 14, so as to form the silicide layers 15. The unreacted metal layer is then removed. In some embodiments, the thickness of thesilicide layer 15 ranges from 2nm to l0nm, for example, but the disclosure is not limited thereto. - Still referring to
FIG. 1A , theetching stop layer 16 and thedielectric layer 17 are formed on thesubstrate 10 and laterally aside the gate stacks G. Theetching stop layer 16 may also be referred to as a contact etch stop layer (CESL), and is disposed between thesubstrate 10 and thedielectric layer 17 and between the gate stack G and thedielectric layer 17. In some embodiments, theetching stop layer 16 includes SiN, SiC, SiOC, SiON, SiCN, SiOCN, or the like, or combinations thereof. Theetching stop layer 16 may be formed by CVD, plasma-enhanced CVD (PECVD), flowable CVD (FCVD), ALD or the like. - The
dielectric layer 17 includes a material different from that of theetching stop layer 16. In some embodiments, thedielectric layer 17 may also be referred to as an interlayer dielectric layer (ILD). In some embodiments, thedielectric layer 17 includes silicon oxide, carbon-containing oxide such as silicon oxycarbide (SiOC), silicate glass, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorine-doped silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), combinations thereof and/or other suitable dielectric materials. In some embodiments, thedielectric layer 17 may include low-k dielectric material with a dielectric constant lower than 4, extreme low-k (ELK) dielectric material with a dielectric constant lower than 2.5 and may further include a small amount of high-k material with a dielectric constant higher than 4. In some embodiments, the low-k material includes a polymer based material, such as benzocyclobutene (BCB), FLARE®, or SILK®; or a silicon dioxide based material, such as hydrogen silsesquioxane (HSQ) or SiOF. The high-k dielectric material includes ZrO2, HfO2, for example. Thedielectric layer 17 may be a single layer structure or a multi-layer structure. Thedielectric layer 17 may be formed by CVD, PECVD, FCVD, spin coating or the like. - In some embodiments, the
etching stop layer 16 and thedielectric layer 17 may be formed by forming etching stop material layer and dielectric material layer over thesubstrate 10 and the gate stacks G, and a planarization process is then performed, such that the top surfaces of the gate stacks G are exposed. In some embodiments, the top surface of theetching stop layer 16, the top surface of thedielectric layer 17 and the top surfaces of the gate stacks G are substantially coplanar with each other, but the disclosure is not limited thereto. - It is noted that, the
gate electrode 12 may be formed by a gate first process which is formed before forming thespacers 13, or formed by a gate last process which is formed after thedielectric layer 17 is formed. - Referring to
FIG. 1B , adielectric layer 18 is formed over thesubstrate 10 to cover the top surfaces of the gate stacks G, theetching stop layer 16 and thedielectric layer 17. In some embodiments, thedielectric layer 18 may also be referred to as an interlayer dielectric layer (ILD). In some embodiments, the material of thedielectric layer 18 includes dielectric materials similar to, and may be the same as or different from those of thedielectric layer 17, which are not described again. Thedielectric layer 18 may be formed by CVD, PECVD, FCVD, spin coating or the like. In some embodiments, the thickness of thedielectric layer 18 ranges from 1 nm to 10 nm, for example, but the disclosure is not limited thereto. - In some embodiments, a
contact 22 is formed penetrating through thedielectric layer 18, thedielectric layer 17 and theetching stop layer 16 to electrically connect to the S/D regions 14. Thecontact 22 may be formed by the following processes. In some embodiments, thedielectric layer 18, thedielectric layer 17 and theetching stop layer 16 are patterned to form openings 19 (or called “contact holes”) corresponding to the S/D regions 14. In some embodiments, the patterning method includes photolithograph and one or more etching processes. - In some embodiments, after the
dielectric layer 18 is formed, a patterned mask layer with openings is formed on thedielectric layer 18. The openings of the patterned mask layer correspond to the intended locations of the subsequently formed contact holes. The patterned mask layer is a patterned photoresist, for example. Thereafter, portions of thedielectric layer 18, thedielectric layer 17 and theetching stop layer 16 are removed by etching process (es) using the patterned mask layer as an etch mask, so as to form theopenings 19. - In some embodiments, the
opening 19 penetrates through thedielectric layer 18, thedielectric layer 17 and theetching stop layer 16 to expose the corresponding S/D region 14 or thesilicide layer 15 on the S/D region 14. In some embodiments, theopening 19 has substantially vertical sidewalls, as shown inFIG. 1B , but the disclosure is not limited thereto. In alternative embodiments, theopening 19 have inclined sidewalls. Besides, the cross-sectional shape of theopening 19 may be square, rectangular, trapezoid or any other suitable shape as needed, and the disclosure is not limited thereto. - Still referring to
FIG. 1B , thecontact 22 is formed on the S/D region 14 within theopening 19. In some embodiments, thecontact 22 includes abarrier layer 20 and a conductive layer (or referred to as conductive feature) 21. Thebarrier layer 20 may include titanium, tantalum, titanium nitride, tantalum nitride, manganese nitride or a combination thereof. Theconductive layer 21 may include metal, such as tungsten (W), copper (Cu), Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof or any metal material with suitable resistance and gap-fill capability. In some embodiments, the height of thecontact 22 may range from 0.5 nm to 90 nm, but the disclosure is not limited thereto. - In some embodiments, a barrier material layer and a metal material layer are formed on the substrate 100 by sputtering, CVD, PVD, electrochemical plating (ECP), electrodeposition (ELD), ALD, or combinations thereof or the like. In some embodiments, the metal material layer is formed by a CVD process, during which the process temperature ranges from 50° C. to 500° C., the carrier gas may include Ar or N2 with a flow rate ranging from 10-500 sccm, but the disclosure is not limited thereto. The barrier material layer and the metal material layer fill in the
opening 19 and cover the top surface of thedielectric layer 18. Thereafter, a planarization step such as CMP is then performed to remove portions of the metal material layer and the barrier material layer over thedielectric layer 18, such that the top surface of thedielectric layer 18 is exposed. In some embodiments, the top surfaces of thebarrier layer 20 and theconductive layer 21 are substantially coplanar with the top surface of thedielectric layer 18. - Still referring to
FIG. 1B , in some embodiments, thebarrier layer 20 surrounds sidewalls and bottom surface of theconductive layer 21. In other words, thebarrier layer 20 is located between theconductive layer 21 and the S/D region 14, and between theconductive layer 21 and thedielectric layer 18/thedielectric layer 17/theetching stop layer 15. Thebarrier layer 20 serves as a diffusion barrier to prevent the diffusion of the metal atoms of theconductive layer 21. - Referring to
FIG. 1C , anetching stop layer 23 and adielectric layer 24 are sequentially formed over thesubstrate 10 by CVD, PECVD, FCVD, spin coating or the like. In some embodiments, thedielectric layer 24 may also be referred to as an interlayer dielectric layer (ILD). The materials of theetching stop layer 23 and thedielectric layer 24 may be selected from the same candidate materials of theetching stop layer 16 and thedielectric layer 17, respectively. The material of theetching stop layer 23 is different from the material of thedielectric layer 24 and the material ofdielectric layer 18. In some embodiments, theetching stop layer 23 may be thinner than thedielectric layers etching stop layer 23 ranges from lnm to 10 nm, for example, but the disclosure is not limited thereto. The thickness of thedielectric layer 24 may be the same as or different that of thedielectric layer 18. - An opening such as a via
hole 25 is then formed in thedielectric layer 24 and theetching stop layer 23 to expose thecontact 22. In some embodiments, the viahole 25 may also be a via trench. The viahole 25 may be formed by a photolithograph and one or more etching processes. In some embodiments, after theetching stop layer 23 and thedielectric layer 24 are formed, a patterned mask layer such as a patterned photoresist is formed on thedielectric layer 24. The patterned mask layer has openings correspond to the intended locations of the subsequently formed viahole 25. Thereafter, portions of thedielectric layer 24 and theetching stop layer 23 are removed by using the patterned mask layer as an etch mask, so as to form the viahole 25. - Still referring to
FIG. 1C , in some embodiments, the sidewalls of the viahole 25 may be inclined, and the cross-sectional shape of the via hole may be trapezoid. In alternative embodiments, the sidewalls of the viahole 25 may be substantially vertical, and the cross-sectional shape of the via hole may be square, rectangular, or the like. However, the disclosure is not limited thereto. - In some embodiments, the via
hole 25 exposes a top surface of thecontact 22, and may further expose a portion of the top surface of thedielectric layer 18. In other words, the width W2 (such as, bottom width) of the viahole 25 may be larger than the width W1 (such as, top width) of thecontact 22, but the disclosure is not limited thereto. - Referring to
FIG. 1D , aninhibitor layer 26 is formed on thecontact 22 exposed by the viahole 25. In some embodiments, theinhibitor layer 26 is a self-assembled monolayer (SAM) 26. The molecule ofSAM 26 has a head group R1 showing a specific affinity for the material of thecontact 22. The head group R1 refers to one end group of the molecule and may also be called as a terminal group. In some embodiments, the head group R1 is connected to an alkyl chain. The alkyl chain may include a liner alkyl chain or a branched alkyl chain. The carbon chain length (C-C)n of the alkyl chain may be adjustable to define critical dimension of theSAM 26, for example, to increase or decrease a thickness of theSAM 26. - Selection of the head group R1 is depending on the application of the SAM, and the material of the
contact 22. In some embodiments, the head group R1 may include thiol (—SH), disulfide, dialkyl sulfide, —CN, —NH2, —P, —PO, —PO3, —SeH, —SeSe, for example. In some embodiments, theSAM 26 may include din-alkyl sulfide, di-n-alkyl disulfide, 3-thiophenol, mercaptopyridine, mercaptoaniline, thiophene, cysteine, xanthate, thiocarbaminate, thiocarbamate, thiourea, mercaptoimidazole, alkanethiol (such as CH3(CH2)15SH), alkaneselenol, combinations thereof or the like. - The
SAM 26 may be formed by a vapor deposition process or a liquid deposition process. TheSAM 26 is created by chemisorption of the hydrophilic head groups onto thecontact 22, followed by a slow two-dimensional organization of hydrophobic head groups.SAM 26 adsorption may occur from solution by immersion of the structure shown inFIG. 1C into a dilute solution of, in one embodiment, an alkane thiol in ethanol.SAM 26 adsorption may also occur from a vapor phase. The adsorbed molecules initially form a disordered mass of molecules, and instantaneously begin to form crystalline or semicrystalline structures on thecontact 22 in a monolayer. Owing to the specific affinity of the head group R1 of theSAM 26 to the material of thecontact 22, and the SAM material will not react with the exposeddielectric layer 18,etching stop layer 23 anddielectric layer 24, theSAM 26 is selectively deposited on thecontact 22, forming a metal complex in some embodiment. TheSAM 26 may be deposited via spin-on coating from a solution of, for example, an alkane thiol in ethanol. The un-reacted portions of the SAM material on the surfaces of thedielectric layers 18/24 andetching stop layer 23 may be rinsed off using suitable solvent based rinse, remaining a layer ofSAM 26 on the surfaces of thecontact 22. It will be understood that a thickness of the SAM layer left on thecontact 22 may be adjusted by adjusting the carbon chain length of the alkyl chain of the SAM. In some embodiments, the inhibitor layer (SAM) 26 is formed both on theconductive layer 21 and thebarrier layer 20 of thecontact 22, but the disclosure is not limited thereto. In alternative embodiments, theinhibitor layer 26 may be formed on theconductive layer 21 and not formed on thebarrier layer 20. - Referring to
FIG. 1E , anadhesion promoter layer 29 is formed on the exposeddielectric layer 18,etching stop layer 23 and thedielectric layer 24 through a selective deposition process. The material of theadhesion promoter layer 29 is different from the material of thebarrier layer 20. In some embodiments, the material of theadhesion promoter layer 29 includes oxide or nitride, such as metal oxide, metal nitride, or combinations thereof. In some embodiments, the material of theadhesion promoter layer 29 may be a conductive material such as conductive metal oxide or a non-conductive material such as a dielectric material. The dielectric material may be low-k dielectric material, or high-k dielectric material. In some embodiments, the metal oxide includes RuO, (such as RuO2), WOx, IrO2, NiOx, TiOx, ReO3, SrRuO3, Lao.3Sr0.5CoO3, or combinations thereof, for example. The low-k dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The high-k dielectric material may include ZrO2, HfO2 or the like or a combination thereof. In some embodiments, the thickness of theadhesion promoter layer 29 ranges from 0.5 nm to 1 nm, for example, but the disclosure is not limited thereto. - The
adhesion promoter layer 29 is formed by a selective deposition process such as a selective CVD or selective ALD process. In some embodiments, the precursor or/and reaction gas of the selective deposition process may adsorb on thedielectric layers 18/24 andetching stop layer 23 and conduct a reaction to form theadhesion promoter layer 29, and the precursor or/and the reaction gas would not absorb on theinhibitor layer 26. In some embodiments, the reaction mechanism of the selective deposition process and the property of theinhibitor layer 26 makes theadhesion promoter layer 29 only deposit on the surfaces of thedielectric layers 18/24 and theetching stop layer 23, and not deposit on theinhibitor layer 26 over thecontact 22. - In some embodiments, the molecules of the inhibitor layer (SAM) 26 include specially designed functional groups to inhibit the
adhesion promoter layer 29 deposition thereon. For example, the specially designed functional groups (such as terminal groups R2 shown inFIG. 1D ) of the SAM may have hydrophobic properties, for example, the terminal groups R2 may include methyl (—CH3), phenyl, pyrrole, tolyl, the like, or combinations thereof, which would not react with or adsorb the precursor or/and reaction gas used in the deposition process of theadhesion promoter layer 29, so as to inhibit theadhesion promoter layer 29 depositing on theinhibitor layer 26 over thecontact 22. In some embodiments, the terminal group R2 is also referred to as tail group. - Referring to
FIG. 1E toFIG. 1F , thereafter, theinhibitor layer 26 is removed by an etching process, such as wet etching, dry etching, or the like, or a combination thereof. The top surface of thecontact 22 is exposed. - Referring to
FIG. 1G , aconductive material layer 30′ is formed over thesubstrate 10. Theconductive material layer 30′ fills in the viahole 25 and covers the top surface of the adhesion promoter layer, and is electrically connected to thecontact 22. In some embodiments, theconductive material layer 30′ includes metal or metal alloy, such as Co, Cu, Ru, Ni, Al, Pt, Mo, W, Al, Ir, Os, alloy thereof, or combinations thereof. The forming method of theconductive material layer 30′ may include CVD, ALD, PVD, ECP, ELD, or the like or combinations thereof. In some embodiments, theconductive material layer 30′ is formed by a CVD process, during which the process temperature ranges from 50° C. to 500° C., the carrier gas may include Ar or N2 with a flow rate ranging from 10-500 sccm, but the disclosure is not limited thereto. - In some embodiments, the material of the
adhesion promoter layer 29 is selected depending on the material of theconductive material layer 30′. In some embodiments, theadhesion promoter layer 29 includes a metal oxide correspond to the metal of theconductive material layer 30′, but the disclosure is not limited thereto. For example, theconductive material layer 30′ including Ru correspond to theadhesion promoter layer 29 including RuO2, IrO2, NiOx, TiOx, ReO3, SrRuO3. Theconductive material layer 30′ including W correspond to theadhesion promoter layer 29 including WOx. Theconductive material layer 30′ including Co correspond to theadhesion promoter layer 29 including La0.5Sr0.5CoO3. However, the disclosure is not limited thereto. - Referring to
FIG. 1G toFIG. 1H , a planarization process (such as chemical mechanical polishing, CMP) is then performed to remove a portion of theconductive material layer 30′ over the top surface of thedielectric layer 24. In some embodiments in which theadhesion promoter layer 29 is a conductive layer, the planarization process is performed until the top surface of thedielectric layer 24 is exposed, that is, theadhesion promoter layer 29 over the top surface of thedielectric layer 24 is also removed by the planarization process. In some embodiments, after the planarization process, aadhesion promoter layer 29 a and aconductive layer 30 are remained in the viahole 25. The top surface of theadhesion promoter layer 29 a and the top surface of theconductive layer 30 are substantially coplanar with the top surface of thedielectric layer 24. However, the disclosure is not limited thereto. - Referring to
FIG. 1H , in some embodiments, theadhesion promoter layer 29 a and theconductive layer 30 constitute a via 32. The via 32 is located in the viahole 25 to electrically connect to thecontact 22. In some embodiments, the height of the via 32 may range from 0.5 nm to 60 nm, but the disclosure is not limited thereto. - Still referring to
FIG. 1H , asemiconductor device 50 a is thus formed, thesemiconductor device 50 a includes thesubstrate 10, the gate stack G, the S/D regions 14, theetching stop layer 16, thedielectric layer 17, thedielectric layer 18, theetching stop layer 23, thedielectric layer 24, thecontact 22 and the via 32. The S/D regions 14 are located in thesubstrate 10 and beside the gate stack G. In some embodiments, the S/D regions 14 include the silicide layers 15 formed thereon. Theetching stop layer 16 and thedielectric layer 17 are located on thesubstrate 10 and laterally aside the gate stacks G. Thedielectric layer 18, theetching stop layer 23 and thedielectric layer 24 are located over the gate stacks G and thedielectric layer 17. - The
contact 22 penetrates through thedielectric layer 18, thedielectric layer 17 and theetching stop layer 16 to electrically connect to the S/D regions 14. In some embodiments, thecontact 22 is landing on thesilicide layer 15 of the S/D region 14. In some embodiments, thecontact 22 includes abarrier layer 20 and aconductive layer 21. Thebarrier layer 20 surrounds sidewalls and bottom of theconductive layer 21 to serve as a diffusion barrier. The via 32 penetrates through thedielectric layer 24 and theetching stop layer 23 to electrically connect to thecontact 22. In some embodiments, the cross sectional shape of thecontact 22 and the via 32 may respectively be square, rectangular, trapezoid or any other suitable shape as needed, and the disclosure is not limited thereto. - In some embodiments, the via 32 includes the
adhesion promoter layer 29 a and theconductive layer 30. Theconductive layer 30 is located on the electrically connect to thecontact 22. In some embodiments, the bottom surface of theconductive layer 30 is in physical and electric contact with the top surfaces of thebarrier layer 20 and theconductive layer 21 of thecontact 22. Theadhesion promoter layer 29 a surrounds sidewalls of theconductive layer 30 and is laterally between theconductive layer 30 and thedielectric layer 24, and between theconductive layer 30 and theetching stop layer 23. The bottom surface of theadhesion promoter layer 29 a is in physical contact with the top surface of thedielectric layer 18. In some embodiments, the bottom surface of theconductive layer 30 and the bottom surface of theadhesion promoter layer 29 a are substantially coplanar with the bottom surface of theetching stop layer 23. - In some embodiments, the
adhesion promoter layer 29 a is not in contact with thecontact 22, and is separated from thecontact 22 by theconductive layer 30. Theadhesion promoter layer 29 a may be electrically connected to thecontact 22 through theconductive layer 30. In other word, theconductive layer 30 penetrates through thedielectric layer 24, theetching stop layer 23 and theadhesion promoter layer 29 a to contact with the top surface of thecontact 22. - The
adhesion promoter layer 29 a may help to improve the adhesion between theconductive layer 30 and thedielectric layer 24 and between theconductive layer 30 and theetching stop layer 23, and may also serve as diffusion barrier for preventing the metal atoms of theconductive layer 30 from diffusing to theadjacent dielectric layer 24 or/and theetching stop layer 23. - Still referring to
FIG. 1H , in the first embodiment, thecontact 22 is with barrier layer, while the via 32 is free of a conventional barrier layer (that is, barrierless), but the disclosure. In some other embodiments, both thecontact 22 and the via 32 are barrierless. -
FIG. 2A toFIG. 2C are schematic cross-sectional views illustrating a method of forming a semiconductor device according to a second embodiment of the disclosure. The second embodiment differs from the first embodiment in that no inhibitor layer is formed, and the selective deposition of the adhesion promoter layer is implemented through the different properties of thecontact 22 and thedielectric layers 18/24 and theetching stop layer 23. - Referring to
FIG. 1C andFIG. 2A , processes similar toFIG. 1C is performed to form a viahole 25 in theetching stop layer 23 and thedielectric layer 24. The viahole 25 expose the top surface of thecontact 22, a portion of a top surface of thedielectric layer 18, and sidewalls of thedielectric layer 24 and theetching stop layer 23. The materials of thedielectric layers 18/24, the etching stop layer23 and thecontact 22 are substantially the same as those described in the first embodiment, which are not described again. - In some embodiments, after the via
hole 25 is formed, a selective deposition process is performed to form anadhesion promoter layer 129 on the top surface of thedielectric layer 18, the sidewalls of theetching stop layer 23, the sidewalls of thedielectric layer 24 exposed by the viahole 25, and on the top surface of thedielectric layer 24, and the selective deposition process is performed without forming an inhibitor layer on thecontact 22. In some embodiments, the selective deposition process includes a pulsed mode ALD or CVD, for example. The selective deposition process may be performed by using a precursor and a reaction gas to react to form theadhesion promoter layer 129. In some embodiments, the reaction gas adsorbs on the exposed surface of thedielectric layer 18,etching stop layer 23 and thedielectric layer 24 and does not adsorb on the exposed surface of thecontact 22, due to the different properties of thedielectric layer 18/etching stop layer 23/thedielectric layer 24 and thecontact 22. - For example, the materials of the
dielectric layer 18, theetching stop layer 23 and thedielectric layer 24 have hydrophilic property, on which the reaction gas is easy to adsorb. The materials of thecontact 22 have a weaker hydrophilic property than that of thedielectric layers 18/24 and theetching stop layer 23, or the materials of thecontact 22 do not have hydrophilic properties, such as have hydrophobic properties. In some embodiments, the reaction gas may include oxygen (O2) or ammonia (NH3). The oxygen or ammonia absorbs on the exposeddielectric layer 18,etching stop layer 23 anddielectric layer 24 due to the hydrophilic properties thereof, and does not absorb on thecontact 22 because thecontact 22 have weaker hydrophilic property or does not have the hydrophilic property. As such, the precursor reacts with the reaction gas absorbed on thedielectric layer 18,etching stop layer 23 anddielectric layer 24, and theadhesion promoter layer 129 is thus formed. Since the reaction gas is merely absorbed on thedielectric layer 18, theetching stop layer 23 and thedielectric layer 24 without absorbing on thecontact 22, theadhesion promoter layer 129 is selectively formed on the top surface of thedielectric layer 18, the sidewalls of theetching stop layer 23 and thedielectric layer 24 without forming on the top surface of thecontact 22. - In some embodiments in which the
adhesion promoter layer 129 includes TiO2, the precursor of the selective deposition process for forming theadhesion promoter layer 129 may include TiCl4, TDMAT, TDEAT, TEMAT, and the reaction gas includes O2, wherein O2 adsorbs on the exposeddielectric layer 18,etching stop layer 23 anddielectric layer 24 without adsorbing on thecontact 22. - In some embodiments in which the
adhesion promoter layer 129 includes HfO2, the precursor of the selective deposition process may include HfCl4, [(CH2CH3)2N]4Hf or the like, and the reaction gas includes O2, wherein O2 adsorbs on the exposeddielectric layer 18,etching stop layer 23 anddielectric layer 24 without adsorbing on thecontact 22. - In some embodiments in which the
adhesion promoter layer 129 includes RuO2, the precursor of the selective deposition process may include [Ru(tfa)3], cyclo hexdiene or carbonyl based Ru precursors like Ru(CO)x or [Ru(CO)3C6H8]7, [Ru(acac)3], [Ru(CO)2 (hfac)2] or the like or combinations thereof, and the reaction gas include O2, wherein O2 adsorbs on the exposeddielectric layer 18,etching stop layer 23 anddielectric layer 24 without adsorbing on thecontact 22. - In some embodiments in which the
adhesion promoter layer 129 includes other metal oxide such as Al2O3, WOx, Y2O3, La2O3, MgOx, LiOx, V2O5, Yb2O3, MoOx, GdOx, the selective deposition process is similar to that described above using oxygen as the reaction gas. - In some embodiments in which the
adhesion promoter layer 129 includes a nitride, the selective deposition process uses ammonia (NH3) as the reaction gas, and the selective deposition process is performed in a way similar to that described above. - Referring to
FIG. 2B , aconductive material layer 30′ is formed over thesubstrate 10 by CVD, ALD, PVD, ECP, ELD, or the like. The material of theconductive material layer 30′ is similar to, the same as or different from those described in the first embodiment. In some embodiments, theconductive material layer 30′ and theadhesion promoter layer 129 may be in-situ formed. For example, theconductive material layer 30′ includes a metal (such as W), and theadhesion promoter layer 129 includes a metal oxide (such as WOx) correspond to the metal of theconductive material layer 30′, theconductive material layer 30′ and theadhesion promoter layer 129 may be formed in a same chamber of the a deposition machine by the following process. In one embodiment, process gases (precursor) such as WF6 and O2 are introduced into the deposition chamber to form the metal oxide WOx of theadhesion promoter layer 129, thereafter, O2 source gas is closed to stop introducing O2 into the chamber, and keep introducing the precursor WF6 to form the metal W of theconductive material layer 30′. - Referring to
FIG. 2B toFIG. 2C , thereafter, a planarization process is performed to remove theconductive material layer 30′ and theadhesion promoter layer 129 over the top surface of thedielectric layer 24 in some embodiments. Anadhesion promoter layer 129 and aconductive layer 30 remain in the viahole 25 to constitute a via 132. Asemiconductor device 50 b is thus completed. Thesemiconductor device 50 b is similar to thesemiconductor device 50 a, except that the forming method of theadhesion promoter layer 129 a is different from theadhesion promoter layer 29 a. The other features of thesemiconductor device 50 b are substantially the same as those of thesemiconductor device 50 a, which are not described again. -
FIG. 3A toFIG. 3D are schematic cross-sectional view illustrating a method of forming a semiconductor device according to a third embodiment of the disclosure. The third embodiment differs from the foregoing embodiments in that the adhesion promoter layer is formed by a blanket deposition process and an etching back process. - Referring to
FIG. 3A , in some embodiments, after the viahole 25 is formed, anadhesion promoter layer 229 is blanket deposited over thesubstrate 10. The deposition process includes CVD, ALD, or the like or combinations thereof. Theadhesion promoter layer 229 covers the top surface of thedielectric layer 24 and fills in the viahole 25 to cover the inner surface of the viahole 25. In other words, the top surface of thecontact 22, a portion of the top surface of thedielectric layer 18, the sidewalls of theetching stop layer 23, the sidewalls and the top surface of thedielectric layer 24 are covered by theadhesion promoter layer 229. - Referring to
FIG. 3A toFIG. 3B , a portion of theadhesion promoter layer 229 is removed by an etching process (such as anisotropic etching process) to form anadhesion promoter layer 229 a. In some embodiments, theadhesion promoter layer 229 is etched back, such that the horizontal portions thereof are removed, that is, the portions of theadhesion promoter layer 229 on the top surface of thedielectric layer 24 and at the bottom of the viahole 25 are removed, and the portion of theadhesion promoter layer 229 on sidewalls of the viahole 25 remain. - Referring to
FIG. 3B , in some embodiments, theadhesion promoter layer 229 a is disposed on sidewalls of the viahole 25, the top surface of theadhesion promoter layer 229 a may be substantially coplanar with the top surface of thedielectric layer 24. Theadhesion promoter layer 229 a covers a portion of the top surface of thedielectric layer 18, and may or may not cover the top surface of thecontact 22. In other words, the top surface of thecontact 22 is at least partially exposed by theadhesion promoter layer 229 a. In some embodiments, theadhesion promoter layer 229 a is not in contact with the top surface of thecontact 22, and the top surface of thecontact 22 is completely exposed by theadhesion promoter layer 229 a. In some other embodiments, a small portion of the top surface of thecontact 22 may be covered by theadhesion promoter layer 229 a. - Referring to
FIG. 3C andFIG. 3D , processes similar to those fromFIG. 1G toFIG. 1H are performed, aconductive material layer 30′ is formed over thesubstrate 10. Theconductive material layer 30′ covers the top surface of thedielectric layer 24 and fills into the viahole 25. In this embodiment, theconductive material layer 30′ is in contact with the top surface of thedielectric layer 24. Thereafter, a planarization process is performed to remove a portion of theconductive material layer 30′ over the top surface of thedielectric layer 24, and aconductive layer 30 in the viahole 25 is remained. Theconductive layer 30 and theadhesion promoter layer 229 a constitute a via 232. Asemiconductor device 50 c is thus formed. Thesemiconductor device 50 c is similar to thesemiconductor device 50 a, expect that the forming method of theadhesion promoter layer 229 a is different from that of theadhesion promoter layer 29 a, and theadhesion promoter layer 229 a may be in contact with thecontact 22 in some embodiments. -
FIG. 4 andFIG. 5 are schematic cross-sectional views illustrating semiconductor devices according to some embodiments of the disclosure. - In the forgoing first and second embodiments, the
adhesion promoter layer 29/129 over the top surfaces ofdielectric layer 24/124 are removed during the planarization process, but the disclosure is not limited thereto. - Referring to
FIG. 1G andFIG. 4 , in some embodiments in which theadhesion material layer 29 is made of a dielectric layer, after theconductive material layer 30′ is formed, a planarization process is performed to remove theconductive material layer 30′ over the top surface of theadhesion promoter layer 29, so as to form aconductive layer 30 a. The planarization process may include a CMP process, and theadhesion promoter layer 29 may serve as a CMP stop layer during the CMP process. In some embodiments, the top surface of theconductive layer 30 a is substantially coplanar with the top surface of theadhesion promoter layer 29. - Referring to
FIG. 4 , asemiconductor device 50 d is thus formed. Thesemiconductor device 50 d includes thesubstrate 10, the gate stack G, the S/D regions 14, theetching stop layer 16, thedielectric layer 17, thedielectric layer 18, theetching stop layer 23, thedielectric layer 24, thecontact 22, theconductive layer 30 a and theadhesion promoter layer 29. Theconductive layer 30 a is in electrically contact with thecontact 22. Theadhesion promoter layer 29 is electrically isolated from theconductive layer 30 a and thecontact 22. - In some embodiments, the
adhesion promoter layer 29 and theconductive layer 30 a are located in the viahole 25 and protrude from the top surface of thedielectric layer 24. In some embodiments, the top surface of thedielectric layer 24 is covered by theadhesion promoter layer 29. The top surface of theconductive layer 30 a is coplanar with the top surface of theadhesion promoter layer 29 and higher than the top surface of thedielectric layer 24. In other words, theadhesion promoter layer 29 surrounds the sidewalls of theconductive layer 30 a and further extends to cover the top surface of thedielectric layer 24. - From another point of view, the
adhesion promoter layer 29 includes a first portion FP and a second portion SP connected to each other. The first portion FP is located in the viahole 25 and protrudes from the top surface of thedielectric layer 24, surrounding the sidewalls of theconductive layer 30 a. The first portion FP is located between theconductive layer 30 a and theetching stop layer 23, between theconductive layer 30 a and thedielectric layer 24, and between theconductive layer 30 a and the second portion SP. In some embodiments, theconductive layer 30 a and the first portion FP of theadhesion promoter layer 29 constitute a via 32 a. The top surface of the via 32 a protrudes from the top surface of thedielectric layer 24. - The second portion SP is located on the top surface of the
dielectric layer 24 and laterally aside the via 30 a, extending in a direction parallel with the top surface of thesubstrate 10. In some embodiments, since the first portion FP and the second portion SP are comprised in the same layer of theadhesion promoter layer 29, no interface is existed between the first portion FP and the second portion SP, that is, no interface is existed between the via 32 a and the second portion SP. - It is noted that, in the embodiments in which the
adhesion promoter layer 29 is made of dielectric material, the planarization process may be stopped at the top surface of theadhesion promoter layer 29, as shown inFIG. 4 , and may also be stopped at the top surface of thedielectric layer 24, as shown inFIG. 1H . That is, theadhesion promoter layer 29 over the top surface of thedielectric layer 24 may or may not be removed during the planarization process. In the embodiments in which theadhesion promoter layer 29 is made of conductive material, the planarization process will remove theadhesion promoter layer 29 over the top surface of thedielectric layer 24. - The concept of the embodiment shown in
FIG. 4 may also be applied to the second embodiment. Referring toFIG. 2B , in the second embodiment, after theconductive material layer 30′ is formed, the planarization process may remove theconductive material layer 30′ over the top surface of theadhesion promoter layer 129 and not remove theadhesion promoter layer 129. - In the foregoing embodiments, the
silicide layer 15 is formed after thespacer 13 is formed, as shown inFIG. 1H , FIG.2C,FIG. 3D andFIG. 4 , thesilicide layer 15 covers a portion of the top surface of the S/D region 14. The top surface of thesilicide layer 15 is covered by theetching stop layer 16 and thecontact 22, the sidewalls of thesilicide layer 15 is in contact with thespacer 13 of the gate stack G. A portion of thesilicide layer 15 is located between theetching stop layer 16 and the S/D region 14. However, the disclosure is not limited thereto. -
FIG. 5 illustrates asemiconductor device 50 e according to some other embodiments of the disclosure. In some embodiments, asilicide layer 115 may be formed on the S/D region 14 after the contact hole 19 (FIG. 1B ) is formed. Referring toFIG. 5 , in some embodiments, the sidewalls of thesilicide layer 115 is aligned with the sidewalls of thecontact 22. Thesilicide layer 115 is not in contact with thespacer 13 of the gate stack G, and is separated from thespacer 13 by theetching stop layer 16 therebetween. The top surface of thesilicide layer 115 is covered by thecontact 22, and the sidewalls of thesilicide layer 115 are covered by theetching stop layer 16. A portion of the top surface of the S/D region 14 is covered by thesilicide layer 115 and theetching stop layer 16. - In the embodiments of the disclosure, the semiconductor devices 50 a-50 e may be planar transistors, FinFETs, gate-all-around transistors, nanowire transistors, multiple-gate transistors, or the like, and the disclosure is not limited thereto. The semiconductor device 50 a-50 e may be further subjected to variety of processes, such that a plurality of (multi-layers of) metal lines and vias and dielectric layers are formed over the via 32/32 a/132/232 and the
dielectric layer 24/124, so as to form an interconnection structure over thesubstrate 10. In some embodiments, the metal lines are extending on top surfaces of the dielectric layers in a horizontal direction parallel with a top surface of thesubstrate 10, for example. The vias vertically penetrates through the dielectric layers to connect the metal lines in different layers. - In the foregoing embodiments, the via are formed without barrier layer surrounding the conductive layer, and the adhesion promoter layer is formed on sidewalls of the conductive layer. In some embodiment, the resistivity of barrierless via of the disclosure is lower than a conventional via having barrier layer. In the illustrated embodiments, the via is free of barrier layer (that is, barrierless), while the contact includes a barrier layer, but the disclosure is not limited thereto. The barrierless process may also be applied to the contact. As shown in
FIG. 6 , in some embodiments, asemiconductor device 50f may include acontact 122 and a via 32, both thecontact 122 and the via 32 are free of a barrier layer. In some embodiments, thecontact 122 includes an adhesion promoter layer 120 and aconductive layer 121. The adhesion promoter layer 120 and theconductive layer 121 may be formed by similar processes of the adhesion promoter layer and conductive layer of the via as described above. In this embodiment, theconductive layer 121 is in direct contact with thesilicide layer 15 on the S/D region 14. The adhesion promoter layer 120 is located on sidewalls of theconductive layer 121. - It is noted that, the barrierless process of the disclosure may be applied to contact, via or/and the other metal lines or vias of the interconnection structure to be formed over the
substrate 10. In some embodiments, all of the metal features (metal lines, vias, and contacts) of the interconnection structure are barrierless. In some embodiments, some of the metal features of the interconnection structure are barrierless, and others are formed with barrier layer. - In some embodiments of the disclosure, at least the via is formed free of barrier layer, and the adhesion promoter layer is selectively formed at least between the conductive layer and the adjacent dielectric layers. As such, the resistivity of the metal features included in the interconnections of the semiconductor device is reduced. At the same time, the adhesion promoter layer help to improve the adhesion between the conductive layer and the adjacent dielectric features, thus avoiding metal peeling issue. In addition, the adhesion promoter layer may also present the metal diffusion of the conductive layer. As a result, the performance and the yield of the semiconductor device are improved, and defects thereof are reduced.
- In accordance with some embodiments of the disclosure, a semiconductor device includes a substrate, a gate stack and a first dielectric layer over the substrate, a source/drain (S/D) region, a contact, and a via. The first dielectric layer is laterally aside and over the gate stack. The S/D region is located in the substrate on sides of the gate stack. The contact penetrates through the first dielectric layer to electrically connect to the S/D region. The via penetrates through a second dielectric layer to connect to the contact. the via includes a conductive layer and an adhesion promoter layer on sidewalls of the conductive layer. The conductive layer is in contact with the contact.
- In accordance with alternative embodiments of the disclosure, a semiconductor device includes a substrate, a gate stack and a first dielectric layer over the substrate, a contact, and a conductive layer. The first dielectric layer is laterally aside and over the gate stack. The contact penetrates through the first dielectric layer to electrically connect to the substrate. The conductive layer penetrates through a second dielectric layer and an adhesion promoter layer to connect to the contact. The adhesion promoter layer is laterally between the conductive layer and the second dielectric layer.
- In accordance with some embodiments of the disclosure, a method of manufacturing a semiconductor device includes the following processes. A substrate having a gate stack formed thereon is provided. A first dielectric layer is formed aside and over the gate stack. A contact is formed to penetrate through the first dielectric layer to connect to the substrate. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is patterned to form a via hole to expose a top surface of the contact and a portion of a top surface of the first dielectric layer. An adhesion promoter layer is selectively deposited on the portion of the top surface of the first dielectric layer and sidewalls of the second dielectric layer exposed by the via hole. A conductive layer is formed within the via hole to electrically contact with the contact.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
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