US20200243522A1 - Methods of fabricating semiconductor devices having gate-all-around structure with oxygen blocking layers - Google Patents
Methods of fabricating semiconductor devices having gate-all-around structure with oxygen blocking layers Download PDFInfo
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- US20200243522A1 US20200243522A1 US16/258,004 US201916258004A US2020243522A1 US 20200243522 A1 US20200243522 A1 US 20200243522A1 US 201916258004 A US201916258004 A US 201916258004A US 2020243522 A1 US2020243522 A1 US 2020243522A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Definitions
- FinFET devices typically include semiconductor fins with high aspect ratios and in the fin channel and source/drain regions are formed.
- a gate structure is formed over and along the sides of the fin (e.g., wrapping) utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices.
- device feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. There are still various challenges in the fabrication of FinFET devices.
- FIG. 1 shows a plane view of an intermediate structure at one stage of an exemplary method for fabricating a semiconductor device, in accordance with some embodiments.
- FIG. 2 shows a perspective view of an intermediate structure at one stage of an exemplary method for fabricating a semiconductor device, in accordance with some embodiments.
- FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L and 3M show cross-sectional views of respective structures at various stages of an exemplary method for fabricating a semiconductor device taken along line I-I′ in FIG. 1 , in accordance with some embodiments.
- FIG. 4 shows a plane view of a semiconductor device in accordance with some embodiments.
- FIG. 5 shows a cross-sectional view of a portion of a semiconductor device taken along line II-II′ in FIG. 4 , in accordance with some embodiments.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- the gate all around (GAA) transistor structures described below may be patterned by any suitable method.
- the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes.
- double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
- a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.
- nMOSFET n-type metal-oxide-semiconductor Field Effect Transistor
- nWF work function
- FinFET Fin Field Effect Transistor
- N3 3 nm
- An ultra-thin nWF layer is easy formed in the space between nano-sheets and may also be easy oxidized to cause the work function of n-type metal gate shift to p-type work function which induces higher Vt in the nMOSFET.
- Embodiments disclosed herein relate generally to fabricating semiconductor devices having a GAA structure with oxygen blocking layers.
- the oxygen blocking layers in the GAA structure can protect an ultra-thin n-type work function (nWF) layer for ultra-low Vt tuning of nMOSFET.
- the semiconductor devices are for example FinFET devices having different GAA structures in n-type MOS (nMOS) and p-type MOS (pMOS) regions.
- the oxygen blocking layers and the ultra-thin nWF layer of the GAA structure in the nMOS region are formed using four steps in-situ processes to prevent oxidation of the ultra-thin nWF layer. Therefore, the semiconductor devices of the embodiments of the disclosure can achieve ultra-low nMOS Vt tuning with an ultra-thin nWF layer in the GAA structure.
- a first oxygen blocking layer is formed under an ultra-thin n-type work function (nWF) layer, and a second oxygen blocking layer is formed on the ultra-thin nWF layer.
- the native oxide on the first oxygen blocking layer is removed using a dry etching process in a process chamber before forming the ultra-thin nWF layer.
- the ultra-thin nWF layer is in-situ deposited on the first oxygen blocking layer in the process chamber.
- the second oxygen blocking layer is in-situ formed on the ultra-thin nWF layer in the process chamber.
- the first and second oxygen blocking layers and the ultra-thin nWF layer are in-situ formed in the same process chamber.
- the ultra-thin nWF layer is prevented from oxidation to achieve ultra-low nMOS threshold voltage (Vt) for the semiconductor devices.
- the first and second oxygen blocking layers are thin enough to fill in the spaces between nano-sheets and do not adversely affect the process window of forming metal gate of the GAA structure.
- Some embodiments described herein are described in the context of FinFET devices, and more particularly, in the context of forming a GAA structure of the FinFET devices.
- the GAA structure includes an ultra-thin nWF layer sandwiched between oxygen blocking layers.
- the oxygen blocking layers and the ultra-thin nWF layer are in-situ formed in the same process chamber to prevent oxidation of the ultra-thin nWF layer.
- FIG. 1 illustrates a plane view of an intermediate structure at one stage of an exemplary method for fabricating a semiconductor device 100 such as a FinFET device, in accordance with some embodiments.
- the semiconductor device 100 includes multiple dummy gate structures 120 formed on and across multiple fin structures 106 in an nMOS region 100 A, and multiple dummy gate structures 130 formed on and across multiple fin structures 108 in a pMOS region 100 B.
- the fin structures 106 and 108 are separated from each other by isolation structures 104 .
- the fin structures 106 and 108 , the dummy gate structures 120 and 130 , and the isolation structures 104 are formed on a substrate 102 .
- Other aspects not illustrated in or described with respect to FIG. 1 may become apparent from the following figures and description.
- the structure in FIG. 1 may be electrically connected or coupled in a manner to operate one or more transistors, for example eight transistors in each of the nMOS and pMOS regions.
- FIG. 2 illustrates a perspective (three-dimensional) view of an intermediate structure at one stage of an exemplary method for fabricating a semiconductor device, in accordance with some embodiments.
- the structure of FIG. 2 illustrates a portion of the semiconductor device 100 of FIG. 1 in the nMOS region 100 A.
- a portion of the semiconductor device 100 of FIG. 1 in the pMOS region 100 B may also have the same perspective view as shown in FIG. 2 .
- multiple fin structures 106 protruding from a substrate 102 .
- Each of the fin structures 106 includes a fin 102 F and a stack of alternating semiconductor layers 110 and 112 on the fin 102 F.
- the total number of layers in the stack of semiconductor layers 110 and 112 is between three and ten.
- the total thickness of the stacked semiconductor layers 110 and 112 is in a range from about 60 nm to about 80 nm.
- the substrate 102 may be a bulk semiconductor substrate, or a semiconductor-on-insulator (SOI) substrate, which may be doped (e.g., with a p-type or an n-type dopant) to form various well regions or doped regions therein, or undoped.
- SOI substrate includes a layer of a semiconductor material formed on an insulator layer.
- the insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like.
- the insulator layer is provided on a silicon or glass substrate.
- the substrate 102 may be made of silicon or another semiconductor material.
- the substrate 102 is a silicon wafer.
- the substrate 102 is made of a compound semiconductor such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (InAs), or indium phosphide (InP).
- the substrate 102 is made of an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP.
- the semiconductor layers 110 and 112 are made of different materials such as silicon, germanium, silicon germanium (SiGe), gallium arsenic (GaAs), indium arsenide (InAs), silicon carbide (SiC), or InGaAs.
- the semiconductor layers 110 are made of SiGe
- the semiconductor layers 112 are made of Si.
- the semiconductor layer 110 or the semiconductor layer 112 may be firstly formed on the substrate 102 .
- the semiconductor layers 110 and 112 are blanketly formed on the substrate 102 independently by epitaxial growth process.
- the substrate 102 and the blanketly formed stacked semiconductor layers 110 and 112 are patterned together using photolithography and etching processes to form multiple trenches in the substrate 102 and in the stacked semiconductor layers 110 and 112 .
- a patterned hard mask (not shown) is formed on the stacked semiconductor layers 110 and 112 to serve as an etching mask for forming the fin structures 106 .
- Each of the trenches is between neighboring pairs of fin structures 106 .
- the fin structure 106 includes a fin 102 F and a fin stack 102 S on the fin 102 F.
- the fin 102 F is formed from the substrate 102 .
- the fin stack 102 S is formed from the stacked semiconductor layers 110 and 112 .
- the etching process may include a reactive ion etch (RIE), neutral beam etch (NBE), inductive coupled plasma (ICP) etch, or a combination thereof.
- RIE reactive ion etch
- NBE neutral beam etch
- ICP inductive coupled plasma
- isolation structures 104 are formed in the trenches between the fins 102 F and on the substrate 102 , in accordance with some embodiments. Each of the fins 102 F may protrude above the isolation structures 104 .
- the isolation structure 104 is, for example a shallow-trench-isolation (STI) structure, which surrounds the bottom portion of the fin 102 F.
- the isolation structure 104 is formed by filling the trenches with an insulating material and then the filled insulating material is recessed by an etching process.
- the insulating material is such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or another low dielectric constant (low-k) dielectric material.
- the trenches may be filled with the insulating material using a deposition process, such as chemical vapor deposition (CVD), flowable CVD (FCVD), a spin-on-glass (SOG) process, or another applicable process.
- CVD chemical vapor deposition
- FCVD flowable CVD
- SOG spin-on-glass
- a liner 103 may be formed between the isolation structures 104 and the substrate 102 , and also between the isolation structures 104 and the fins 102 F.
- a liner material layer for forming the liner 103 is conformally deposited on the sidewalls of the fin structures 106 , and on the top surfaces of the fin stacks 102 S and the substrate 102 before filling the trenches with the insulating material.
- the material of the liner 103 may be silicon oxide, silicon nitride or silicon oxynitride.
- the liner material layer may be deposited using CVD, physical vapor deposition (PVD) or atomic layer deposition (ALD) process.
- the liner material layer is recessed together with the filled insulating material of the isolation structures 104 by an etching process to form the liner 103 .
- the etching process includes RIE, NBE or another suitable etching process.
- the top surfaces of the isolation structure 104 and the liner 103 are lower than or at the same level with the top surfaces of the fins 102 F.
- the dummy gate structure 120 is formed across the fin structures 106 , along the sidewalls and over the top surfaces of the fin structures 106 , in accordance with some embodiments.
- the dummy gate structure 120 is also formed on the isolation structures 104 .
- the longitudinal direction of the dummy gate structure 120 is perpendicular to the longitudinal direction of the fin structures 106 .
- each of the dummy gate structures 120 will be replaced with a replacement gate structure in a gate-last process to form a gate-all-around (GAA) structure in the nMOS region 100 A.
- GAA gate-all-around
- the dummy gate structure 130 is also formed across the fin structures 108 , along the sidewalls and over the top surfaces of the fin structures 108 .
- the dummy gate structure 130 is also formed on the isolation structures 104 .
- the longitudinal direction of the dummy gate structure 130 is perpendicular to the longitudinal direction of the fin structures 108 .
- each of the dummy gate structures 130 will be replaced with a replacement gate structure in a gate-last process to form a GAA structure in the pMOS region 100 B.
- the materials and processes of forming the GAA structures in the nMOS region 100 A and the pMOS region 100 B would be described with reference to FIGS. 3A to 3M .
- Each of the dummy gate structures 120 and 130 includes a dummy gate dielectric layer 108 and a dummy gate electrode layer 109 on the dummy gate dielectric layer 108 .
- the dummy gate electrode layer 109 is made of poly-silicon.
- the dummy gate dielectric layer 108 may be made of silicon oxide, silicon nitride, silicon oxynitride or another low dielectric constant (low-k) dielectric material.
- the dummy gate dielectric layer 108 and the dummy gate electrode layer 109 are deposited independently and then may be patterned together using photolithography and etching processes to from the dummy gate structures 120 and 130 .
- the deposition processes for the dummy gate dielectric layer 108 and the dummy gate electrode layer 109 may include CVD, PVD, ALD, high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), or plasma enhanced CVD (PECVD) process.
- the etching processes for forming the dummy gate structures 120 and 130 may include RIE, NBE or another suitable etching process.
- a first hard mask 117 and a second hard mask 118 are patterned and formed on the dummy gate electrode layer 109 to serve as an etching mask for forming the dummy gate structures 120 and 130 .
- the first hard mask 117 is made of silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN) or silicon nitride (SiN or Si 3 N 4 ).
- the second hard mask 118 may be made of silicon oxide (SiO 2 ). The first hard mask 117 and the second hard mask 118 are formed using deposition, photolithography and etching processes.
- FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L and 3M show cross-sectional views of respective structures at various stages of an exemplary method for fabricating a semiconductor device 100 taken along line I-I′ in FIG. 1 , in accordance with some embodiments.
- Line I-I′ is on a plane that is perpendicular to the dummy gate structures 120 and 130 , and along the fin structures 106 and 108 .
- the dummy gate structure 120 is formed on the fin structure 106
- the dummy gate structure 130 is formed on the fin structure 108 , in accordance with some embodiments.
- the various features as shown in FIG. 3A are the same as or similar to those described with respect to FIGS. 1 and 2 .
- gate spacers 140 are formed along the sidewalls of the dummy gate structures 120 and 130 , in accordance with some embodiments.
- the gate spacers 140 are also formed on the sidewalls of the etched semiconductor layers 110 .
- the semiconductor layers 110 at source and drain regions are etched using the dummy gate structures 120 and 130 as etching mask.
- the semiconductor layers 110 are etched by an etching process such as plasma etching, RIE or another dry etching process.
- the gate spacers 140 may be formed by conformally depositing one or more spacer layers on the dummy gate structures 120 and 130 , along the sidewalls of the etched semiconductor layers 110 , and on the isolation structures 104 .
- the spacer layers may be made of different materials and have different thicknesses than each other.
- the one or more spacer layers may include silicon oxide (SiO 2 ), silicon nitride (SiN or Si 3 N 4 ), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or a combination thereof, and may be deposited by CVD, ALD or another deposition process.
- the spacer layers are then anisotropically etched to form the gate spacers 140 .
- the etching process may include a RIE, NBE, or another etching process.
- the semiconductor layers 112 of the fin structure 106 at source and drain regions are etched using the dummy gate structure 120 and the gate spacers 140 as etching mask to form recesses.
- the semiconductor layers 112 of the fin structure 108 at source and drain regions are etched using the dummy gate structure 130 and the gate spacers 140 as etching mask to form recesses.
- the recesses may be formed using an isotropic etching process such as plasma etching, RIE or another dry etching process.
- the isotropic etching process may be a wet etching process that uses an etching solution such as ammonium hydroxide-peroxide water mixture (APM), tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or another etchant.
- APM ammonium hydroxide-peroxide water mixture
- TMAH tetramethylammonium hydroxide
- NH 4 OH ammonium hydroxide
- the bottom surfaces of the recesses may be lower than the top surface of the fins 102 F.
- source and drain structures 122 are formed in the recesses and on opposite sides of the dummy gate structure 120 in the nMOS region 100 A, in accordance with some embodiments.
- source and drain structures 132 are formed in the recesses and on opposite sides of the dummy gate structure 130 in the pMOS region 100 B.
- the top surfaces of the epitaxial source and drain structures 122 and 132 may be higher than or at the same level with the top surfaces of the fin structures 106 and 108 .
- the source and drain structures 122 in the nMOS region 100 A and the source and drain structures 132 in the pMOS region 100 B may be made of different epitaxial semiconductor materials.
- the epitaxial semiconductor materials include silicon germanium (SiGe1-x, where x can be between approximately 0 and 1), silicon carbide (SiC), silicon phosphorus, germanium, an III-V compound semiconductor, an II-VI compound semiconductor, or another epitaxial semiconductor.
- the materials of an III-V compound semiconductor may include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP or GaP.
- the source and drain structures 122 in the nMOS region 100 A are made of SiC
- the source and drain structures 132 in the pMOS region 100 B are made of SiGe.
- the source and drain structures 122 and the source and drain structures 132 may be independently formed by metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or a combination thereof.
- MOCVD metal-organic CVD
- MBE molecular beam epitaxy
- LPE liquid phase epitaxy
- VPE vapor phase epitaxy
- SEG selective epitaxial growth
- the source and drain structures 122 and the source and drain structures 132 may be independently doped by in-situ doping during the epitaxial growth and/or by implantation after the epitaxial growth.
- some source and drain structures 122 in the nMOS region 100 A may be shared between two neighboring transistors, such as through coalescing the structures by epitaxial growth.
- some source and drain structures 132 in the pMOS region 100 B may be shared between two neighboring transistors, such as through coalescing the structures by epitaxial growth.
- the neighboring FinFETs with the shared source and drain structures may be implemented as two functional transistors. Other configurations in other examples may implement other numbers of functional transistors.
- a contact etch stop layer (CESL) 142 and an interlayer dielectric (ILD) layer 144 are formed on the source and drain structures 122 , the source and drain structures 132 and on the isolation structure 104 , in accordance with some embodiments.
- the CESL 142 is conformally deposited on the dummy gate structures 120 and 130 , the gate spacers 140 , the source and drain structures 122 , the source and drain structures 132 , and the isolation structure 104 .
- the ILD layer 144 is deposited on the CESL 142 .
- the CESL 142 can provide a mechanism to stop an etching process when forming via contacts to the source and drain structures 122 and 132 .
- the CESL 142 may be formed of a dielectric material having a different etch selectivity from the adjacent ILD layer 144 .
- the material of the CESL 142 may include silicon nitride (SiN or Si 3 N 4 ), silicon carbon nitride (SiCN) or a combination thereof, and may be deposited by CVD, PECVD, ALD, or another deposition process.
- the CESL 142 has a thickness in a range from about 2 nm to about 5 nm.
- the material of the ILD layer 144 may include silicon dioxide or a low-k dielectric material (e.g., a material having a dielectric constant (k-value) lower than the k-value (about 3.9) of silicon dioxide).
- the low-k dielectric material may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiOxCy), Spin-On-Glass (SOG) or a combination thereof.
- the ILD layer 144 may be deposited by spin-on coating, CVD, Flowable CVD (FCVD), PECVD, PVD, or another deposition process.
- a planarization process for example a chemical mechanical polishing (CMP) process, is performed on the ILD layer 144 and the CESL 142 .
- CMP chemical mechanical polishing
- the first hard masks 117 , the second hard masks 118 and portions of the gate spacers 140 are also removed in the planarization process.
- the dummy gate electrode layers 109 are exposed.
- the top surfaces of the ILD layer 144 and the CESL 142 may be coplanar with the top surfaces of the dummy gate electrode layers 109 and the gate spacers 140 .
- the dummy gate electrode layers 109 , the dummy gate dielectric layers 108 and the semiconductor layers 110 are removed using one or more etching processes, in accordance with some embodiments.
- a trench 124 is formed between the gate spacers 140 and multiple spaces 126 are formed between the gate spacers 140 .
- Each of the space 126 is between the semiconductor layers 112 .
- a trench 134 is formed between the gate spacers 140 and multiple spaces 136 are formed between the gate spacers 140 .
- Each of the space 136 is between the semiconductor layers 112 .
- each of the spaces 126 and 136 between the neighboring semiconductor layers 112 has a height d 1 that is in a range from about 8 nm to about 10 nm.
- the semiconductor layers 112 are separated from each other by a distance that is in a range from about 8 nm to about 10 nm.
- Each of the semiconductor layers 112 has a thickness that is in a range from about 8 nm to about 10 nm.
- the semiconductor layers 112 may be referred to as nanosheets or nanowires.
- the spaces 126 and 136 may also be referred to as sheet-sheet spacing.
- the semiconductor layers 112 serve as channel layers of the semiconductor device 100 .
- FIGS. 3E to 3M show cross-sectional views of a portion of respective structures at various stages of an exemplary method for fabricating the semiconductor device 100 taken along line I-I′ in FIG. 1 , in accordance with some embodiments.
- the dimensions of various features may not be drawn to scale and may be arbitrarily increased or reduced for clarity of illustration.
- an interfacial layer (IL) 127 is formed on and around the semiconductor layers 112 in the trenches 124 and 134 and in the spaces 126 and 136 , in accordance with some embodiments.
- the interfacial layer 127 may be silicon oxide and formed by deposition, chemical oxidation or thermal oxidation process.
- the interfacial layer 127 is silicon oxide which is formed using ozone (O 3 ) with standard clean 1 (SC1) and standard clean 2 (SC2) processes.
- SC1 standard clean 1
- SC2 standard clean 2
- the interfacial layer 127 has a thickness that may be in a range from about 5 ⁇ to about 15 ⁇ .
- a gate dielectric layer 128 is conformally deposited on the ILD layer 144 , the CESL 142 , the gate spacers 140 and the interfacial layer (IL) 127 , in the trenches 124 and 134 and in the spaces 126 and 136 .
- the gate dielectric layer 128 also surrounds the semiconductor layers 112 .
- the gate dielectric layer 128 includes silicon oxide, silicon nitride, a high-k dielectric material, multilayers thereof, or other dielectric material.
- the high-k dielectric material may have a k-value greater than about 7.0.
- the high-k dielectric material may include a metal oxide of or a metal silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof.
- the gate dielectric layer 128 may be deposited by ALD, PECVD, molecular-beam deposition (MBD), or another deposition process.
- the gate dielectric layer 128 may be a high-k gate dielectric layer.
- the gate dielectric layer 128 is HfO 2 that is deposited by ALD process using HfCl 4 and H 2 O as precursor.
- the gate dielectric layer 128 has a thickness that is in a range from about 10 ⁇ to about 20 ⁇ .
- a capping layer 129 is conformally deposited on the gate dielectric layer 128 in the trenches 124 and 134 and in the spaces 126 and 136 .
- the capping layer 129 is TiSiN that is deposited by ALD process using TiCl 4 , SiH 4 and NH 3 as precursor.
- the capping layer 129 has a thickness that may be in a range from about 10 ⁇ to about 20 ⁇ .
- an in-situ post-metal anneal (iPMA) process is performed on the capping layer 129 in the nMOS region 100 A and the pMOS region 100 B to reduce oxygen vacancy in the gate dielectric layer 128 .
- the iPMA process may be performed at a temperature in a range from about 850° C. to about 950° C. with spike annealing in an N 2 ambient.
- the capping layer 131 is Si that is deposited by CVD process using Si 2 H 6 and H 2 as precursor at a temperature in a range from about 350° C. to about 450° C.
- the capping layer 131 has a thickness that may be in a range from about 20 ⁇ to about 50 ⁇ .
- an post-cap anneal (PCA) process is performed on the capping layer 131 in the nMOS region 100 A and the pMOS region 100 B to enhance the film quality of the gate dielectric layer 128 .
- the PCA process may be performed at a temperature in a range from about 900° C. to about 950° C. with spike annealing in an N 2 ambient.
- the capping layer 131 is removed and then the capping layer 129 is also removed, in accordance with some embodiments.
- the capping layers 131 and 129 may be removed using different etching processes. The removal of the capping layers 131 and 129 can increase the filling space for a subsequently forming metal gate.
- a post-deposition anneal (PDA) process is performed in the nMOS region 100 A and the pMOS region 100 B to further improve the film quality of the gate dielectric layer 128 .
- the PDA process may be performed at a temperature in a range from about 850° C. to about 950° C., for example 890° C., with spike annealing in an NH 3 ambient.
- a blocking layer 150 is conformally deposited on the gate dielectric layer 128 in the trenches 124 and 134 and in the spaces 126 and 136 , in accordance with some embodiments.
- the blocking layer 150 also surrounds the semiconductor layers 112 .
- the blocking layer 150 includes TaN, TiN, TaAlN, TiAlN, TaSiN, TiSiN or AlN.
- the blocking layer 150 is TaN that is deposited by ALD process using pentakis (dimethylamino) tantalum (PDMAT) and NH 3 as precursor and is performed at a temperature in a range from about 225° C. to about 325° C.
- the deposited blocking layer 150 has a thickness that is in a range from about 7 ⁇ to about 10 ⁇ .
- the deposited blocking layer 150 is etched back to be a thin blocking layer 150 ′, in accordance with some embodiments.
- the blocking layer 150 is TaN.
- the partial removal of the blocking layer 150 is performed using WCl 5 as etching gas at a temperature in a range from about 300° C. to about 500° C.
- the thin blocking layer 150 ′ has a thickness that is in a range from about 5 ⁇ to about 6 ⁇ . The partial removal of the blocking layer 150 can increase the filling space of a metal gate.
- native oxide may form on the thin blocking layer 150 ′.
- the native oxide may be removed from the thin blocking layer 150 ′ using a dry etching process in a process chamber before forming an n-type work function layer.
- the thin blocking layer 150 ′ is TaN and the native oxide of TaN is TaON.
- the TaON may be removed using WCl 5 or TaCl 5 as etching gas at a temperature in a range from about 300° C. to about 500° C. and at a total pressure in a range from about 5 torr to about 15 torr.
- the thin blocking layer 150 ′ after the native oxide is removed, has a thickness from about 1 ⁇ to about 2 ⁇ .
- the thin blocking layer 150 ′ is also referred to as a first oxygen blocking layer that can prevent a subsequently forming n-type work function layer from oxidation.
- an n-type work function (nWF) layer 152 is conformally deposited on the thin blocking layer 150 ′ in the trenches 124 and 134 and in the spaces 126 and 136 , in accordance with some embodiments.
- the nWF layer 152 also surrounds the semiconductor layers 112 .
- the nWF layer 152 includes TiAlC, TiAl, TaAlC or TaC, and serves the Vt tuning of nMOS.
- the nWF layer 152 is in-situ deposited by ALD process that is performed in the same process chamber as the removal of the native oxide from the thin blocking layer 150 ′.
- the nWF layer 152 is TiAlC that is deposited by ALD process using TiCl 4 and triethyl aluminium (TEAL) as precursor and is performed at a temperature in a range from about 350° C. to about 450° C., or from about 350° C. to about 425° C.
- the nWF layer 152 has a thickness in a range from about 10 ⁇ to about 20 ⁇ . The thickness of the nWF layer 152 can be adjusted by varying the number of cycles in the ALD process.
- a capping layer 153 is conformally deposited on the nWF layer 152 in the trenches 124 and 134 and in the spaces 126 and 136 , in accordance with some embodiments.
- the capping layer 153 also surrounds the semiconductor layers 112 .
- the capping layer 153 is in-situ deposited by ALD process performed in the same process chamber as the deposition of the nWF layer 152 .
- the capping layer 153 includes TiN, TaN, TiAlN, TaAlN, TiSiN, TaSiN or AlN.
- the capping layer 153 is TiN that is deposited by ALD process using TiCl 4 and NH 3 as precursor and is performed at a temperature in a range from about 350° C. to about 450° C., or from about 400° C. to about 450° C. In some examples, the capping layer 153 has a thickness that is in a range from about 5 ⁇ to about 15 ⁇ . The thickness of the capping layer 153 can be adjusted by varying the number of cycles in the ALD process.
- a capping film 154 is conformally formed on the capping layer 153 in the trenches 124 and 134 and in the spaces 126 and 136 , in accordance with some embodiments.
- the capping film 154 also surrounds the semiconductor layers 112 .
- the capping film 154 is in-situ formed by a soaking process performed in the same process chamber as the deposition of the capping layer 153 .
- the capping film 154 includes Al, Mo, Ru, Mn, Zr or Si.
- the capping film 154 is Al that is formed by triethyl aluminium (TEAL) soaking on the capping layer 153 at a temperature in a range from about 350° C. to about 425° C.
- TEAL triethyl aluminium
- the capping film 154 has a thickness in a range from about 5 ⁇ to about 10 ⁇ .
- the thickness of the capping film 154 can be adjusted by varying the soaking time of the soaking process. In some instances, the soaking time is in a range from about 60 seconds to about 180 seconds.
- the capping layer 153 and the capping film 154 are together referred to as a second oxygen blocking layer that can prevent the nWF layer 152 from oxidation.
- the capping film 154 , the capping layer 153 , the nWF layer 152 and the thin blocking layer 150 ′ in the pMOS region 100 B are removed, in accordance with some embodiments.
- a patterned mask (not shown) such as a patterned photoresist is formed on the capping film 154 in the nMOS region 100 A to serve as an etching mask.
- the capping film 154 , the capping layer 153 and the nWF layer 152 in the pMOS region 100 B are removed by a dry etching process, a wet etching process or a combination thereof.
- the thin blocking layer 150 ′ in the pMOS region 100 B is removed by a pre-clean process using WCl 5 as an etching gas in a process chamber. Thereafter, the gate dielectric layer 128 in the pMOS region 100 B is exposed, and then the patterned mask such as the patterned photoresist in the nMOS region 100 A is removed in an ashing process.
- a p-type work function (pWF) layer 156 is conformally deposited on the capping film 154 in the trench 124 and the spaces 126 , and is also conformally deposited on the gate dielectric layer 128 in the trench 134 and the spaces 136 , in accordance with some embodiments.
- the pWF layer 156 also surrounds the semiconductor layers 112 .
- the pWF layer 156 includes TiN, TaN, TiSiN, TaSiN, TaSi 2 , Ru, RuO 2 , Mo, MoN, MoSi 2 , ZrSi 2 , NiSi 2 , WN or WCN, and serves the Vt tuning of pMOS.
- the pWF layer 156 is in-situ deposited by ALD process that is performed in the same process chamber as the pre-clean process of the thin blocking layer 150 ′ of the pMOS region 100 B.
- the pWF layer 156 is TiN that is deposited by ALD process using TiCl 4 and NH 3 as precursor and is performed at a temperature in a range from about 350° C. to about 450° C.
- the pWF layer 156 has a thickness that is in a range from about 10 ⁇ to about 30 ⁇ .
- the pWF layer 156 has thickness uniformity less than 2% and step coverage over 99%.
- the respective spaces 126 and 136 between the semiconductor layers 112 has the height d 1 of about 8 nm, and the thickness of the pWF layer 156 is about 15 ⁇ to full fill the spaces 126 and 136 . In some instances, the respective spaces 126 and 136 between the semiconductor layers 112 has the height d 1 of about 10 nm, and there may be some gaps in the spaces 126 and 136 for filling a metal gate fill material.
- a first portion 158 - 1 of a metal gate fill material is formed on the pWF layer 156 at the bottoms of the trenches 124 and 134 , and may also be in the spaces 126 and 136 , in accordance with some embodiments.
- the first portion 158 - 1 is in-situ deposited by PVD process that is performed in the same process chamber as the deposition of the pWF layer 156 .
- the metal gate fill material includes Co, W, Al, Ru, Cu, another suitable metal material or a combination thereof.
- the first portion 158 - 1 is Co that is deposited using PVD process to fill at the bottoms of the trenches 124 and 134 due to the directional deposition of PVD process.
- a second portion 158 - 2 of the metal gate fill material is conformally deposited on the pWF layer 156 and along the sidewalls of the trenches 124 and 134 , and may also be in the spaces 126 and 136 (not shown), in accordance with some embodiments.
- the second portion 158 - 2 is in-situ deposited by CVD process that is performed in the same process chamber as the deposition of the first portion 158 - 1 .
- the second portion 158 - 2 is Co that is deposited using CVD process to be along the sidewalls of the trenches 124 and 134 .
- the second portion 158 - 2 can serve as a seed layer used in a subsequent electrochemical plating (ECP) process to form the metal gate fill material.
- ECP electrochemical plating
- a third portion 158 - 3 of the metal gate fill material is formed on the second portion 158 - 2 and the first portion 158 - 1 to full fill the trenches 124 and 134 , and may also be in the spaces 126 and 136 (not shown), in accordance with some embodiments.
- the third portion 158 - 3 is Co that is formed using an ECP process.
- the ECP process is a bottom-up approach which has good fill capability to full fill the trenches 124 and 134 with the metal gate fill material.
- the first portion 158 - 1 , the second portion 158 - 2 and third portion 158 - 3 are together referred to as the metal gate fill material 158 .
- an anneal process is performed on the metal gate fill material 158 in the nMOS region 100 A and the pMOS region 100 B, in accordance with some embodiments.
- the anneal process is performed using H 2 at a high temperature in a range from about 300° C. to about 600° C.
- the anneal process can densify the metal gate fill material 158 to enhance the conductivity thereof.
- the metal gate fill material 158 can be formed with void free.
- a GAA structure 160 A is formed in the nMOS region 100 A, and another GAA structure 160 B is formed in the pMOS region 100 B, as shown in FIG. 3M in accordance with some embodiments.
- the top surface of the GAA structures 160 A and 160 B may be coplanar with the top surfaces of the ILD layer 144 , the CESL 142 and the gate spacers 140 .
- the GAA structures 160 A and 160 B are formed in a gate-last process with replacement gate structures to surround the semiconductor layers 112 that serve as channel regions of the semiconductor device 100 .
- FIG. 4 shows a plane view of a semiconductor device 100 in accordance with some embodiments.
- the semiconductor device 100 includes multiple GAA structures 160 A in the nMOS region 100 A, and multiple GAA structures 160 B in the pMOS region 100 B.
- Each of the GAA structures 160 A and 160 B is independently surrounded by the gate spacers 140 .
- the GAA structures 160 A and 160 B surround the channel regions of respective FinFETs.
- the source and drain structures 122 are disposed on opposite sides of the GAA structure 160 A.
- the source and drain structures 132 are disposed on opposite sides of the GAA structure 160 B.
- the neighboring epitaxial source or drain structures 122 of different FinFETs in the nMOS region 100 A may be merged together.
- the neighboring epitaxial source or drain structures 132 of different FinFETs in the pMOS region 100 B may be merged together.
- the neighboring epitaxial source or drain structures 122 of different FinFETs in the nMOS region 100 A may be separated from each other.
- the neighboring epitaxial source or drain structures 132 of different FinFETs in the pMOS region 100 B may be separated from each other.
- Multiple FinFETs of the nMOS region 100 A are isolated from multiple FinFETs of the pMOS region 100 B by the isolation structures 104 on the substrate 102 .
- some components or features for example, the CESL 142 and the ILD layer 144 ) illustrated in the above mentioned figures are omitted to avoid obscuring other components or features.
- FIG. 5 shows a cross-sectional view of a portion of the semiconductor device 100 taken along line II-II′ in FIG. 4 , in accordance with some embodiments.
- Line II-II′ is on a plane that is along the GAA structure 160 A in the nMOS region 100 A and the GAA structure 160 B in the pMOS region 100 B.
- the GAA structure 160 A is separated from the GAA structure 160 B by the isolation structure 104 which is illustrated with a demarcation line in FIG. 5 .
- the interfacial layer (IL) 127 is conformally formed on the fins 102 F and to surround the semiconductor layers (also referred to as nanosheets) 112 in the nMOS region 100 A and the pMOS region 100 B.
- the gate dielectric layer 128 is conformally formed on the IL 127 and the isolation structure 104 , and to surround the semiconductor layers 112 in the nMOS region 100 A and the pMOS region 100 B.
- the GAA structure 160 A includes the nWF layer 152 sandwiched between the thin blocking layer 150 ′ and the capping layer 153 .
- the nWF layer 152 is directly deposited on the thin blocking layer 150 ′ after the native oxide is removed from the thin blocking layer 150 ′.
- the capping film 154 is formed on the capping layer 153 .
- Each of the thin blocking layer 150 ′, the nWF layer 152 , the capping layer 153 and the capping film 154 surround the semiconductor layers 112 in the nMOS region 100 A.
- the nWF layer 152 is thin enough for filling in the spaces 126 between the semiconductor layers 112 at the technology nodes of N3 and below.
- the thin blocking layer 150 ′ can serve as a first oxygen blocking layer to prevent the thin nWF layer 152 from oxidation.
- the capping layer 153 and the capping film 154 can together serve as a second oxygen blocking layer to prevent the thin nWF layer 152 from oxidation more efficiently.
- the oxidation of the nWF layer will cause the work function of n-type metal gate shift to p-type work function which induces higher threshold voltage (Vt) of nMOS.
- Vt threshold voltage
- the native oxide removal of the thin blocking layer 150 ′, and the formations of the nWF layer 152 , the capping layer 153 and the capping film 154 are in-situ performed in the same process chamber to avoid oxidation of the thin nWF layer 152 more efficiently. Therefore, the semiconductor device 100 can achieve ultra-low Vt of nMOS with ultra-thin nWF layer in GAA structure.
- the pWF layer 156 is conformally formed on and in direct contact with the gate dielectric layer 128 in the pMOS region 100 B.
- the pWF layer 156 is directly deposited on the gate dielectric layer 128 without the thin blocking layer 150 ′ in the pMOS region 100 B.
- the pWF layer 156 is also conformally formed on the capping film 154 in the nMOS region 100 A.
- the pWF layer 156 surrounds the semiconductor layers 112 in the nMOS region 100 A and the pMOS region 100 B.
- the metal gate fill material 158 is formed in the nMOS region 100 A and the pMOS region 100 B to surround the semiconductor layers 112 , and is also formed on the fins 102 F and the isolation structures 104 .
- the top surface of the metal gate fill material 158 of the GAA structure 160 A is at the same level with the metal gate fill material 158 of the GAA structure 160 B.
- via contacts (not shown) to the source and drain structures 122 and the source and drain structures 132 are formed in the ILD layer 144 .
- the via contacts are formed to pass through the CESL layer 142 and to be in contact with the respective source and drain structures 122 and the respective source and drain structures 132 .
- the via contacts are formed by forming contact holes in the ILD layer 144 and the CESL layer 142 using photolithography and etching processes. The source and drain structures 122 and the source and drain structures 132 are exposed through the contact holes.
- the contact holes are filled with a conductive material using a deposition process.
- a liner may be conformally deposited on the sidewalls and the bottom surface of the contact hole before filling the contact hole with the conductive material.
- the liner may be used as a diffusion barrier layer, an adhesion layer, or a combination thereof.
- the material of the liner may include Ti, TiN, Ta, TaN, or the like.
- the liner may be deposited by ALD, PECVD, MBD, PVD, or another deposition technique.
- an anneal process may be performed to facilitate a reaction between some portions of the liner and the source and drain structures 122 and the source and drain structures 132 to form silicide regions at the respective source and drain structures 122 and the respective source and drain structures 132 .
- the conductive material of the via contacts includes a metal, such as Co, W, Cu, Al, Au, Ag, alloys thereof, or a combination thereof, and may be deposited by CVD, ALD, PVD, or another deposition technique.
- a metal such as Co, W, Cu, Al, Au, Ag, alloys thereof, or a combination thereof
- CVD chemical vapor deposition
- ALD atomic layer deposition
- PVD physical vapor deposition
- excess portion of the conductive material over the ILD layer 144 is removed in a planarization process, such as a CMP process, to form the via contacts.
- an additional ILD layer (not shown) is formed on the ILD layer 144 and the GAA structures 160 A and 160 B. Contacts to the GAA structures 160 A and 160 B are formed in and pass through the additional ILD layer.
- the materials and the processes for forming the contacts to the GAA structures 160 A and 160 B may be the same as or similar to those described above with respect to the via contacts to the source and drain structures 122 and the source and drain structures 132 .
- the GAA structure 160 A in the nMOS region 100 A includes the gate dielectric layer 128 , the thin blocking layer 150 ′, the n-type work function layer 152 , the capping layer 153 , the capping film 154 and the p-type work function layer 156 to surround the semiconductor layers (also referred to as nanosheets) 112 in sequence.
- the GAA structure 160 B in the pMOS region 100 B includes the gate dielectric layer 128 and the p-type work function layer 156 to surround the semiconductor layers (also referred to as nanosheets) 112 in sequence.
- the GAA structures 160 A and 160 B further include the metal gate fill material 158 to full fill the trenches 124 and 134 between the gate spacers 140 .
- the metal gate fill material 158 may also be in the spaces 126 and 136 between the semiconductor layers 112 .
- the n-type work function layer 152 is thin enough for easy filling in the spaces 126 between the semiconductor layers 112 at the technology nodes of N3 and below.
- each of the spaces 126 between the semiconductor layers 112 has the height d 1 that is in a range from about 8 nm to about 10 nm.
- the thickness of the n-type work function layer 152 is in a range from about 10 ⁇ to about 20 ⁇ .
- a thin n-type work function layer may be easy oxidized to cause the work function of n-type metal gate shift to p-type work function which induces higher threshold voltage (Vt) of nMOS.
- the thin blocking layer 150 ′ can serve as a first oxygen blocking layer to prevent the thin n-type work function layer 152 from oxidation.
- the capping layer 153 and the capping film 154 can together serve as a second oxygen blocking layer to prevent the thin n-type work function layer 152 from oxidation more efficiently.
- the native oxide removal of the thin blocking layer 150 ′, and the formations of the n-type work function layer 152 , the capping layer 153 and the capping film 154 are in-situ performed in the same process chamber to avoid the oxidation of the thin n-type work function layer 152 more efficiently. Therefore, the semiconductor device 100 can achieve ultra-low threshold voltage (Vt) of nMOS with ultra-thin n-type work function layer for GAA structure.
- Vt ultra-low threshold voltage
- the embodiments of the disclosure are suitable for semiconductor devices with GAA structure at multiple technology nodes of 20 nm (N20), N16, N10, N7, N5, N3 and beyond.
- the GAA structures of the semiconductor devices use ultra-thin n-type work function layer and thin oxygen blocking layers to fill the spaces between nanosheets and the trenches between the gate spacers. Therefore, the process window of filling metal gates can be enlarged. Moreover, the thin oxygen blocking layers can reduce gate resistance for device performance improvement.
- the four steps in-situ processes of forming the ultra-thin n-type work function layer sandwiched between the oxygen blocking layers can efficiently prevent oxidation of the ultra-thin n-type work function layer. Therefore, ultra-low Vt tuning of nMOS for the semiconductor devices beyond N3 technology node with ultra-thin n-type work function layer in the GAA structure can be achieved to gain device performance.
- a method of fabricating a semiconductor device includes forming a fin structure on a substrate.
- the fin structure comprises a stack of alternating first semiconductor layers and second semiconductor layers.
- the method also includes removing the first semiconductor layers to form spaces between the second semiconductor layers, and depositing a gate dielectric layer to surround the second semiconductor layers.
- the method further includes depositing a first oxygen blocking layer on the gate dielectric layer to surround the second semiconductor layers, and removing the native oxide from the first oxygen blocking layer in a process chamber.
- the method includes depositing an n-type work function layer on the first oxygen blocking layer to surround the second semiconductor layers in the process chamber.
- the method also includes forming a second oxygen blocking layer on the n-type work function layer to surround the second semiconductor layers in the process chamber.
- the second oxygen blocking layer includes a capping layer and a capping film on the capping layer.
- the method further includes forming a metal gate fill material on the capping film to form a gate-all-around structure.
- a method of fabricating a semiconductor device includes forming a plurality of semiconductor nanosheets over a substrate in a p-type device region and an n-type device region. The semiconductor nanosheets are separated from each other. The method also includes depositing a gate dielectric layer to surround the semiconductor nanosheets in both the p-type device region and the n-type device region. The method further includes depositing a first oxygen blocking layer on the gate dielectric layer to surround the semiconductor nanosheets in the n-type device region, and removing the native oxide from the first oxygen blocking layer in a process chamber. In addition, the method includes depositing an n-type work function layer on the first oxygen blocking layer to surround the semiconductor nanosheets in the process chamber.
- the method also includes forming a second oxygen blocking layer on the n-type work function layer to surround the semiconductor nanosheets in the process chamber.
- the second oxygen blocking layer includes a capping layer and a capping film on the capping layer.
- the method further includes depositing a p-type work function layer directly on the gate dielectric layer to surround the semiconductor nanosheets in the p-type device region and on the second oxygen blocking layer in the n-type device region in the process chamber.
- the method includes depositing a metal gate fill material on the p-type work function layer to form a first gate-all-around structure in the n-type device region and to form a second gate-all-around structure in the p-type device region.
- a semiconductor device in some embodiments, includes a fin protruding from a semiconductor substrate, and a plurality of semiconductor nanosheets separated from each other and disposed over the fin.
- the semiconductor device also includes a first gate-all-around (GAA) structure surrounding the semiconductor nanosheets in an n-type device region.
- the first GAA structure includes an n-type work function layer sandwiched between a first oxygen blocking layer and a second oxygen blocking layer.
- the semiconductor device further includes a second GAA structure surrounding the semiconductor nanosheets in a p-type device region.
- the second GAA structure includes a p-type work function layer directly on a gate dielectric layer.
- the semiconductor device includes first source and drain structures disposed on opposite sides of the first GAA structure.
- the semiconductor device also includes second source and drain structures disposed on opposite sides of the second GAA structure.
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Abstract
Description
- The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and designs have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. As the semiconductor IC industry has progressed into nanometer process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a Fin Field Effect Transistor (FinFET).
- FinFET devices typically include semiconductor fins with high aspect ratios and in the fin channel and source/drain regions are formed. A gate structure is formed over and along the sides of the fin (e.g., wrapping) utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices. However, since device feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. There are still various challenges in the fabrication of FinFET devices.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 shows a plane view of an intermediate structure at one stage of an exemplary method for fabricating a semiconductor device, in accordance with some embodiments. -
FIG. 2 shows a perspective view of an intermediate structure at one stage of an exemplary method for fabricating a semiconductor device, in accordance with some embodiments. -
FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L and 3M show cross-sectional views of respective structures at various stages of an exemplary method for fabricating a semiconductor device taken along line I-I′ inFIG. 1 , in accordance with some embodiments. -
FIG. 4 shows a plane view of a semiconductor device in accordance with some embodiments. -
FIG. 5 shows a cross-sectional view of a portion of a semiconductor device taken along line II-II′ inFIG. 4 , in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- The gate all around (GAA) transistor structures described below may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.
- For advanced technology of semiconductor devices, the most common way to get ultra-low threshold voltage (Vt) of n-type metal-oxide-semiconductor Field Effect Transistor (nMOSFET) is to increase the thickness of n-type work function (nWF) layer. However, for Fin Field Effect Transistor (FinFET) devices with GAA structures at technology nodes of 3 nm (N3) and below, the space between nano-sheets (also referred to as sheet-sheet spacing) is not large enough for a thick nWF layer of large than about 40 Å in the sheet-sheet spacing. An ultra-thin nWF layer is easy formed in the space between nano-sheets and may also be easy oxidized to cause the work function of n-type metal gate shift to p-type work function which induces higher Vt in the nMOSFET.
- Embodiments disclosed herein relate generally to fabricating semiconductor devices having a GAA structure with oxygen blocking layers. The oxygen blocking layers in the GAA structure can protect an ultra-thin n-type work function (nWF) layer for ultra-low Vt tuning of nMOSFET. The semiconductor devices are for example FinFET devices having different GAA structures in n-type MOS (nMOS) and p-type MOS (pMOS) regions. The oxygen blocking layers and the ultra-thin nWF layer of the GAA structure in the nMOS region are formed using four steps in-situ processes to prevent oxidation of the ultra-thin nWF layer. Therefore, the semiconductor devices of the embodiments of the disclosure can achieve ultra-low nMOS Vt tuning with an ultra-thin nWF layer in the GAA structure.
- According to embodiments of the disclosure, a first oxygen blocking layer is formed under an ultra-thin n-type work function (nWF) layer, and a second oxygen blocking layer is formed on the ultra-thin nWF layer. The native oxide on the first oxygen blocking layer is removed using a dry etching process in a process chamber before forming the ultra-thin nWF layer. Next, the ultra-thin nWF layer is in-situ deposited on the first oxygen blocking layer in the process chamber. Afterward, the second oxygen blocking layer is in-situ formed on the ultra-thin nWF layer in the process chamber. The first and second oxygen blocking layers and the ultra-thin nWF layer are in-situ formed in the same process chamber. Therefore, the ultra-thin nWF layer is prevented from oxidation to achieve ultra-low nMOS threshold voltage (Vt) for the semiconductor devices. Moreover, the first and second oxygen blocking layers are thin enough to fill in the spaces between nano-sheets and do not adversely affect the process window of forming metal gate of the GAA structure.
- The foregoing broadly outlines some aspects of the embodiments described herein. Some embodiments described herein are described in the context of FinFET devices, and more particularly, in the context of forming a GAA structure of the FinFET devices. The GAA structure includes an ultra-thin nWF layer sandwiched between oxygen blocking layers. The oxygen blocking layers and the ultra-thin nWF layer are in-situ formed in the same process chamber to prevent oxidation of the ultra-thin nWF layer. Some variations of the exemplary methods and structures are described. A person having ordinary skill in the art will readily understand other modifications may be made that are contemplated within the scope of other embodiments. Implementations of some aspects of the present disclosure may be used in other processes and/or in other devices. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although embodiments of the method may be described in a particular order, various other embodiments of the method may be performed in any logical order and may include fewer or more steps than what is described herein.
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FIG. 1 illustrates a plane view of an intermediate structure at one stage of an exemplary method for fabricating asemiconductor device 100 such as a FinFET device, in accordance with some embodiments. Thesemiconductor device 100 includes multipledummy gate structures 120 formed on and acrossmultiple fin structures 106 in annMOS region 100A, and multipledummy gate structures 130 formed on and acrossmultiple fin structures 108 in apMOS region 100B. Thefin structures isolation structures 104. Thefin structures dummy gate structures isolation structures 104 are formed on asubstrate 102. Other aspects not illustrated in or described with respect toFIG. 1 may become apparent from the following figures and description. The structure inFIG. 1 may be electrically connected or coupled in a manner to operate one or more transistors, for example eight transistors in each of the nMOS and pMOS regions. -
FIG. 2 illustrates a perspective (three-dimensional) view of an intermediate structure at one stage of an exemplary method for fabricating a semiconductor device, in accordance with some embodiments. The structure ofFIG. 2 illustrates a portion of thesemiconductor device 100 ofFIG. 1 in thenMOS region 100A. A portion of thesemiconductor device 100 ofFIG. 1 in thepMOS region 100B may also have the same perspective view as shown inFIG. 2 . In some embodiments,multiple fin structures 106 protruding from asubstrate 102. Each of thefin structures 106 includes afin 102F and a stack of alternatingsemiconductor layers fin 102F. In some examples, the total number of layers in the stack ofsemiconductor layers semiconductor layers - The
substrate 102 may be a bulk semiconductor substrate, or a semiconductor-on-insulator (SOI) substrate, which may be doped (e.g., with a p-type or an n-type dopant) to form various well regions or doped regions therein, or undoped. Generally, an SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a silicon or glass substrate. Thesubstrate 102 may be made of silicon or another semiconductor material. For example, thesubstrate 102 is a silicon wafer. In some examples, thesubstrate 102 is made of a compound semiconductor such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some examples, thesubstrate 102 is made of an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP. - The semiconductor layers 110 and 112 are made of different materials such as silicon, germanium, silicon germanium (SiGe), gallium arsenic (GaAs), indium arsenide (InAs), silicon carbide (SiC), or InGaAs. In some embodiments, the semiconductor layers 110 are made of SiGe, and the semiconductor layers 112 are made of Si. The
semiconductor layer 110 or thesemiconductor layer 112 may be firstly formed on thesubstrate 102. The semiconductor layers 110 and 112 are blanketly formed on thesubstrate 102 independently by epitaxial growth process. - The
substrate 102 and the blanketly formed stackedsemiconductor layers substrate 102 and in the stackedsemiconductor layers semiconductor layers fin structures 106. Each of the trenches is between neighboring pairs offin structures 106. Thefin structure 106 includes afin 102F and afin stack 102S on thefin 102F. Thefin 102F is formed from thesubstrate 102. Thefin stack 102S is formed from the stackedsemiconductor layers - Still referring to
FIG. 2 ,multiple isolation structures 104 are formed in the trenches between thefins 102F and on thesubstrate 102, in accordance with some embodiments. Each of thefins 102F may protrude above theisolation structures 104. Theisolation structure 104 is, for example a shallow-trench-isolation (STI) structure, which surrounds the bottom portion of thefin 102F. Theisolation structure 104 is formed by filling the trenches with an insulating material and then the filled insulating material is recessed by an etching process. The insulating material is such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or another low dielectric constant (low-k) dielectric material. The trenches may be filled with the insulating material using a deposition process, such as chemical vapor deposition (CVD), flowable CVD (FCVD), a spin-on-glass (SOG) process, or another applicable process. - In addition, a
liner 103 may be formed between theisolation structures 104 and thesubstrate 102, and also between theisolation structures 104 and thefins 102F. A liner material layer for forming theliner 103 is conformally deposited on the sidewalls of thefin structures 106, and on the top surfaces of the fin stacks 102S and thesubstrate 102 before filling the trenches with the insulating material. The material of theliner 103 may be silicon oxide, silicon nitride or silicon oxynitride. The liner material layer may be deposited using CVD, physical vapor deposition (PVD) or atomic layer deposition (ALD) process. Next, the liner material layer is recessed together with the filled insulating material of theisolation structures 104 by an etching process to form theliner 103. The etching process includes RIE, NBE or another suitable etching process. In some instances, the top surfaces of theisolation structure 104 and theliner 103 are lower than or at the same level with the top surfaces of thefins 102F. - Still referring to
FIG. 2 , thedummy gate structure 120 is formed across thefin structures 106, along the sidewalls and over the top surfaces of thefin structures 106, in accordance with some embodiments. Thedummy gate structure 120 is also formed on theisolation structures 104. The longitudinal direction of thedummy gate structure 120 is perpendicular to the longitudinal direction of thefin structures 106. In some embodiments of the disclosure, each of thedummy gate structures 120 will be replaced with a replacement gate structure in a gate-last process to form a gate-all-around (GAA) structure in thenMOS region 100A. - The
dummy gate structure 130 is also formed across thefin structures 108, along the sidewalls and over the top surfaces of thefin structures 108. Thedummy gate structure 130 is also formed on theisolation structures 104. The longitudinal direction of thedummy gate structure 130 is perpendicular to the longitudinal direction of thefin structures 108. In some embodiments of the disclosure, each of thedummy gate structures 130 will be replaced with a replacement gate structure in a gate-last process to form a GAA structure in thepMOS region 100B. The materials and processes of forming the GAA structures in thenMOS region 100A and thepMOS region 100B would be described with reference toFIGS. 3A to 3M . - Each of the
dummy gate structures gate dielectric layer 108 and a dummygate electrode layer 109 on the dummygate dielectric layer 108. In some embodiments, the dummygate electrode layer 109 is made of poly-silicon. The dummygate dielectric layer 108 may be made of silicon oxide, silicon nitride, silicon oxynitride or another low dielectric constant (low-k) dielectric material. The dummygate dielectric layer 108 and the dummygate electrode layer 109 are deposited independently and then may be patterned together using photolithography and etching processes to from thedummy gate structures gate dielectric layer 108 and the dummygate electrode layer 109 may include CVD, PVD, ALD, high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), or plasma enhanced CVD (PECVD) process. The etching processes for forming thedummy gate structures - A first
hard mask 117 and a secondhard mask 118 are patterned and formed on the dummygate electrode layer 109 to serve as an etching mask for forming thedummy gate structures hard mask 117 is made of silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN) or silicon nitride (SiN or Si3N4). The secondhard mask 118 may be made of silicon oxide (SiO2). The firsthard mask 117 and the secondhard mask 118 are formed using deposition, photolithography and etching processes. -
FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L and 3M show cross-sectional views of respective structures at various stages of an exemplary method for fabricating asemiconductor device 100 taken along line I-I′ inFIG. 1 , in accordance with some embodiments. Line I-I′ is on a plane that is perpendicular to thedummy gate structures fin structures FIG. 3A , thedummy gate structure 120 is formed on thefin structure 106, and thedummy gate structure 130 is formed on thefin structure 108, in accordance with some embodiments. The various features as shown inFIG. 3A are the same as or similar to those described with respect toFIGS. 1 and 2 . - Next, referring to
FIG. 3B ,gate spacers 140 are formed along the sidewalls of thedummy gate structures gate spacers 140 are also formed on the sidewalls of the etched semiconductor layers 110. In some embodiments, the semiconductor layers 110 at source and drain regions are etched using thedummy gate structures dummy gate structures isolation structures 104. The spacer layers may be made of different materials and have different thicknesses than each other. The one or more spacer layers may include silicon oxide (SiO2), silicon nitride (SiN or Si3N4), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or a combination thereof, and may be deposited by CVD, ALD or another deposition process. The spacer layers are then anisotropically etched to form thegate spacers 140. The etching process may include a RIE, NBE, or another etching process. - Afterwards, the semiconductor layers 112 of the
fin structure 106 at source and drain regions are etched using thedummy gate structure 120 and thegate spacers 140 as etching mask to form recesses. Also, the semiconductor layers 112 of thefin structure 108 at source and drain regions are etched using thedummy gate structure 130 and thegate spacers 140 as etching mask to form recesses. The recesses may be formed using an isotropic etching process such as plasma etching, RIE or another dry etching process. Alternatively, the isotropic etching process may be a wet etching process that uses an etching solution such as ammonium hydroxide-peroxide water mixture (APM), tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or another etchant. The bottom surfaces of the recesses may be lower than the top surface of thefins 102F. - Next, still referring to
FIG. 3B , source and drainstructures 122 are formed in the recesses and on opposite sides of thedummy gate structure 120 in thenMOS region 100A, in accordance with some embodiments. Also, source and drainstructures 132 are formed in the recesses and on opposite sides of thedummy gate structure 130 in thepMOS region 100B. In some instances, the top surfaces of the epitaxial source and drainstructures fin structures - The source and drain
structures 122 in thenMOS region 100A and the source and drainstructures 132 in thepMOS region 100B may be made of different epitaxial semiconductor materials. The epitaxial semiconductor materials include silicon germanium (SiGe1-x, where x can be between approximately 0 and 1), silicon carbide (SiC), silicon phosphorus, germanium, an III-V compound semiconductor, an II-VI compound semiconductor, or another epitaxial semiconductor. The materials of an III-V compound semiconductor may include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP or GaP. In some examples, the source and drainstructures 122 in thenMOS region 100A are made of SiC, and the source and drainstructures 132 in thepMOS region 100B are made of SiGe. The source and drainstructures 122 and the source and drainstructures 132 may be independently formed by metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or a combination thereof. In addition, the source and drainstructures 122 and the source and drainstructures 132 may be independently doped by in-situ doping during the epitaxial growth and/or by implantation after the epitaxial growth. - Moreover, some source and drain
structures 122 in thenMOS region 100A may be shared between two neighboring transistors, such as through coalescing the structures by epitaxial growth. Also, some source and drainstructures 132 in thepMOS region 100B may be shared between two neighboring transistors, such as through coalescing the structures by epitaxial growth. For example, the neighboring FinFETs with the shared source and drain structures may be implemented as two functional transistors. Other configurations in other examples may implement other numbers of functional transistors. - Next, referring to
FIG. 3C , a contact etch stop layer (CESL) 142 and an interlayer dielectric (ILD)layer 144 are formed on the source and drainstructures 122, the source and drainstructures 132 and on theisolation structure 104, in accordance with some embodiments. TheCESL 142 is conformally deposited on thedummy gate structures gate spacers 140, the source and drainstructures 122, the source and drainstructures 132, and theisolation structure 104. TheILD layer 144 is deposited on theCESL 142. - Generally, the
CESL 142 can provide a mechanism to stop an etching process when forming via contacts to the source and drainstructures CESL 142 may be formed of a dielectric material having a different etch selectivity from theadjacent ILD layer 144. The material of theCESL 142 may include silicon nitride (SiN or Si3N4), silicon carbon nitride (SiCN) or a combination thereof, and may be deposited by CVD, PECVD, ALD, or another deposition process. In some examples, theCESL 142 has a thickness in a range from about 2 nm to about 5 nm. The material of theILD layer 144 may include silicon dioxide or a low-k dielectric material (e.g., a material having a dielectric constant (k-value) lower than the k-value (about 3.9) of silicon dioxide). The low-k dielectric material may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiOxCy), Spin-On-Glass (SOG) or a combination thereof. TheILD layer 144 may be deposited by spin-on coating, CVD, Flowable CVD (FCVD), PECVD, PVD, or another deposition process. - Afterwards, a planarization process, for example a chemical mechanical polishing (CMP) process, is performed on the
ILD layer 144 and theCESL 142. The firsthard masks 117, the secondhard masks 118 and portions of thegate spacers 140 are also removed in the planarization process. After the planarization process, the dummy gate electrode layers 109 are exposed. The top surfaces of theILD layer 144 and theCESL 142 may be coplanar with the top surfaces of the dummy gate electrode layers 109 and thegate spacers 140. - Referring to
FIG. 3D , the dummy gate electrode layers 109, the dummy gatedielectric layers 108 and the semiconductor layers 110 (FIG. 3C ) are removed using one or more etching processes, in accordance with some embodiments. Thereafter, in thenMOS region 100A, atrench 124 is formed between thegate spacers 140 andmultiple spaces 126 are formed between thegate spacers 140. Each of thespace 126 is between the semiconductor layers 112. Also, in thepMOS region 100B, atrench 134 is formed between thegate spacers 140 andmultiple spaces 136 are formed between thegate spacers 140. Each of thespace 136 is between the semiconductor layers 112. In some embodiments, each of thespaces spaces semiconductor device 100. - Next,
FIGS. 3E to 3M show cross-sectional views of a portion of respective structures at various stages of an exemplary method for fabricating thesemiconductor device 100 taken along line I-I′ inFIG. 1 , in accordance with some embodiments. In the cross-sectional views ofFIGS. 3E to 3M , the dimensions of various features may not be drawn to scale and may be arbitrarily increased or reduced for clarity of illustration. - Referring to
FIG. 3E , an interfacial layer (IL) 127 is formed on and around the semiconductor layers 112 in thetrenches spaces interfacial layer 127 may be silicon oxide and formed by deposition, chemical oxidation or thermal oxidation process. In some examples, theinterfacial layer 127 is silicon oxide which is formed using ozone (O3) with standard clean 1 (SC1) and standard clean 2 (SC2) processes. Theinterfacial layer 127 has a thickness that may be in a range from about 5 Å to about 15 Å. - Next, a
gate dielectric layer 128 is conformally deposited on theILD layer 144, theCESL 142, thegate spacers 140 and the interfacial layer (IL) 127, in thetrenches spaces gate dielectric layer 128 also surrounds the semiconductor layers 112. Thegate dielectric layer 128 includes silicon oxide, silicon nitride, a high-k dielectric material, multilayers thereof, or other dielectric material. The high-k dielectric material may have a k-value greater than about 7.0. The high-k dielectric material may include a metal oxide of or a metal silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof. Thegate dielectric layer 128 may be deposited by ALD, PECVD, molecular-beam deposition (MBD), or another deposition process. Thegate dielectric layer 128 may be a high-k gate dielectric layer. For example, thegate dielectric layer 128 is HfO2 that is deposited by ALD process using HfCl4 and H2O as precursor. In some examples, thegate dielectric layer 128 has a thickness that is in a range from about 10 Å to about 20 Å. - Next, a
capping layer 129 is conformally deposited on thegate dielectric layer 128 in thetrenches spaces capping layer 129 is TiSiN that is deposited by ALD process using TiCl4, SiH4 and NH3 as precursor. Thecapping layer 129 has a thickness that may be in a range from about 10 Å to about 20 Å. Afterwards, an in-situ post-metal anneal (iPMA) process is performed on thecapping layer 129 in thenMOS region 100A and thepMOS region 100B to reduce oxygen vacancy in thegate dielectric layer 128. The iPMA process may be performed at a temperature in a range from about 850° C. to about 950° C. with spike annealing in an N2 ambient. - Next, another
capping layer 131 is conformally deposited on thecapping layer 129 in thetrenches spaces capping layer 131 is Si that is deposited by CVD process using Si2H6 and H2 as precursor at a temperature in a range from about 350° C. to about 450° C. Thecapping layer 131 has a thickness that may be in a range from about 20 Å to about 50 Å. Afterwards, an post-cap anneal (PCA) process is performed on thecapping layer 131 in thenMOS region 100A and thepMOS region 100B to enhance the film quality of thegate dielectric layer 128. The PCA process may be performed at a temperature in a range from about 900° C. to about 950° C. with spike annealing in an N2 ambient. - Afterwards, referring to
FIG. 3F , thecapping layer 131 is removed and then thecapping layer 129 is also removed, in accordance with some embodiments. The capping layers 131 and 129 may be removed using different etching processes. The removal of the capping layers 131 and 129 can increase the filling space for a subsequently forming metal gate. After the capping layers 131 and 129 are removed, a post-deposition anneal (PDA) process is performed in thenMOS region 100A and thepMOS region 100B to further improve the film quality of thegate dielectric layer 128. The PDA process may be performed at a temperature in a range from about 850° C. to about 950° C., for example 890° C., with spike annealing in an NH3 ambient. - Next, referring to
FIG. 3G , ablocking layer 150 is conformally deposited on thegate dielectric layer 128 in thetrenches spaces blocking layer 150 also surrounds the semiconductor layers 112. Theblocking layer 150 includes TaN, TiN, TaAlN, TiAlN, TaSiN, TiSiN or AlN. In some embodiments, theblocking layer 150 is TaN that is deposited by ALD process using pentakis (dimethylamino) tantalum (PDMAT) and NH3 as precursor and is performed at a temperature in a range from about 225° C. to about 325° C. In some examples, the depositedblocking layer 150 has a thickness that is in a range from about 7 Å to about 10 Å. - Afterwards, referring to
FIG. 3H , the depositedblocking layer 150 is etched back to be athin blocking layer 150′, in accordance with some embodiments. In some embodiments, theblocking layer 150 is TaN. The partial removal of theblocking layer 150 is performed using WCl5 as etching gas at a temperature in a range from about 300° C. to about 500° C. In some examples, after the etch-back process, thethin blocking layer 150′ has a thickness that is in a range from about 5 Å to about 6 Å. The partial removal of theblocking layer 150 can increase the filling space of a metal gate. - During the fabrication processes, native oxide may form on the
thin blocking layer 150′. According to embodiments of the disclosure, the native oxide may be removed from thethin blocking layer 150′ using a dry etching process in a process chamber before forming an n-type work function layer. In some embodiments, thethin blocking layer 150′ is TaN and the native oxide of TaN is TaON. The TaON may be removed using WCl5 or TaCl5 as etching gas at a temperature in a range from about 300° C. to about 500° C. and at a total pressure in a range from about 5 torr to about 15 torr. In some examples, after the native oxide is removed, thethin blocking layer 150′ has a thickness from about 1 Å to about 2 Å. Thethin blocking layer 150′ is also referred to as a first oxygen blocking layer that can prevent a subsequently forming n-type work function layer from oxidation. - Next, referring to
FIG. 3I , an n-type work function (nWF)layer 152 is conformally deposited on thethin blocking layer 150′ in thetrenches spaces nWF layer 152 also surrounds the semiconductor layers 112. ThenWF layer 152 includes TiAlC, TiAl, TaAlC or TaC, and serves the Vt tuning of nMOS. ThenWF layer 152 is in-situ deposited by ALD process that is performed in the same process chamber as the removal of the native oxide from thethin blocking layer 150′. In some embodiments, thenWF layer 152 is TiAlC that is deposited by ALD process using TiCl4 and triethyl aluminium (TEAL) as precursor and is performed at a temperature in a range from about 350° C. to about 450° C., or from about 350° C. to about 425° C. In some examples, thenWF layer 152 has a thickness in a range from about 10 Å to about 20 Å. The thickness of thenWF layer 152 can be adjusted by varying the number of cycles in the ALD process. - Still referring to
FIG. 3I , acapping layer 153 is conformally deposited on thenWF layer 152 in thetrenches spaces capping layer 153 also surrounds the semiconductor layers 112. Thecapping layer 153 is in-situ deposited by ALD process performed in the same process chamber as the deposition of thenWF layer 152. Thecapping layer 153 includes TiN, TaN, TiAlN, TaAlN, TiSiN, TaSiN or AlN. In some embodiments, thecapping layer 153 is TiN that is deposited by ALD process using TiCl4 and NH3 as precursor and is performed at a temperature in a range from about 350° C. to about 450° C., or from about 400° C. to about 450° C. In some examples, thecapping layer 153 has a thickness that is in a range from about 5 Å to about 15 Å. The thickness of thecapping layer 153 can be adjusted by varying the number of cycles in the ALD process. - Still referring to
FIG. 3I , acapping film 154 is conformally formed on thecapping layer 153 in thetrenches spaces capping film 154 also surrounds the semiconductor layers 112. Thecapping film 154 is in-situ formed by a soaking process performed in the same process chamber as the deposition of thecapping layer 153. Thecapping film 154 includes Al, Mo, Ru, Mn, Zr or Si. In some embodiments, thecapping film 154 is Al that is formed by triethyl aluminium (TEAL) soaking on thecapping layer 153 at a temperature in a range from about 350° C. to about 425° C. In some examples, thecapping film 154 has a thickness in a range from about 5 Å to about 10 Å. The thickness of thecapping film 154 can be adjusted by varying the soaking time of the soaking process. In some instances, the soaking time is in a range from about 60 seconds to about 180 seconds. Thecapping layer 153 and thecapping film 154 are together referred to as a second oxygen blocking layer that can prevent thenWF layer 152 from oxidation. - Next, referring to
FIG. 3J , thecapping film 154, thecapping layer 153, thenWF layer 152 and thethin blocking layer 150′ in thepMOS region 100B are removed, in accordance with some embodiments. A patterned mask (not shown) such as a patterned photoresist is formed on thecapping film 154 in thenMOS region 100A to serve as an etching mask. Thecapping film 154, thecapping layer 153 and thenWF layer 152 in thepMOS region 100B are removed by a dry etching process, a wet etching process or a combination thereof. Next, thethin blocking layer 150′ in thepMOS region 100B is removed by a pre-clean process using WCl5 as an etching gas in a process chamber. Thereafter, thegate dielectric layer 128 in thepMOS region 100B is exposed, and then the patterned mask such as the patterned photoresist in thenMOS region 100A is removed in an ashing process. - Next, referring to
FIG. 3K , a p-type work function (pWF)layer 156 is conformally deposited on thecapping film 154 in thetrench 124 and thespaces 126, and is also conformally deposited on thegate dielectric layer 128 in thetrench 134 and thespaces 136, in accordance with some embodiments. ThepWF layer 156 also surrounds the semiconductor layers 112. ThepWF layer 156 includes TiN, TaN, TiSiN, TaSiN, TaSi2, Ru, RuO2, Mo, MoN, MoSi2, ZrSi2, NiSi2, WN or WCN, and serves the Vt tuning of pMOS. ThepWF layer 156 is in-situ deposited by ALD process that is performed in the same process chamber as the pre-clean process of thethin blocking layer 150′ of thepMOS region 100B. In some embodiments, thepWF layer 156 is TiN that is deposited by ALD process using TiCl4 and NH3 as precursor and is performed at a temperature in a range from about 350° C. to about 450° C. In some examples, thepWF layer 156 has a thickness that is in a range from about 10 Å to about 30 Å. ThepWF layer 156 has thickness uniformity less than 2% and step coverage over 99%. In some instances, therespective spaces pWF layer 156 is about 15 Å to full fill thespaces respective spaces spaces - Still referring to
FIG. 3K , a first portion 158-1 of a metal gate fill material is formed on thepWF layer 156 at the bottoms of thetrenches spaces pWF layer 156. The metal gate fill material includes Co, W, Al, Ru, Cu, another suitable metal material or a combination thereof. In some embodiments, the first portion 158-1 is Co that is deposited using PVD process to fill at the bottoms of thetrenches - Afterwards, still referring to
FIG. 3K , a second portion 158-2 of the metal gate fill material is conformally deposited on thepWF layer 156 and along the sidewalls of thetrenches spaces 126 and 136 (not shown), in accordance with some embodiments. The second portion 158-2 is in-situ deposited by CVD process that is performed in the same process chamber as the deposition of the first portion 158-1. In some embodiments, the second portion 158-2 is Co that is deposited using CVD process to be along the sidewalls of thetrenches - Referring to
FIG. 3L , a third portion 158-3 of the metal gate fill material is formed on the second portion 158-2 and the first portion 158-1 to full fill thetrenches spaces 126 and 136 (not shown), in accordance with some embodiments. In some embodiments, the third portion 158-3 is Co that is formed using an ECP process. The ECP process is a bottom-up approach which has good fill capability to full fill thetrenches gate fill material 158. - Afterwards, still referring to
FIG. 3L , an anneal process is performed on the metalgate fill material 158 in thenMOS region 100A and thepMOS region 100B, in accordance with some embodiments. In some embodiments, the anneal process is performed using H2 at a high temperature in a range from about 300° C. to about 600° C. The anneal process can densify the metalgate fill material 158 to enhance the conductivity thereof. According the embodiments of the disclosure, the metalgate fill material 158 can be formed with void free. - Next, excess portions of the
gate dielectric layer 128 and the above mentioned various layers for a gate electrode layer deposited on the top surfaces of theILD layer 144, theCESL 142 and thegate spacers 140 as shown inFIG. 3L are removed in a planarization process, such as a CMP process. Thereafter, aGAA structure 160A is formed in thenMOS region 100A, and anotherGAA structure 160B is formed in thepMOS region 100B, as shown inFIG. 3M in accordance with some embodiments. The top surface of theGAA structures ILD layer 144, theCESL 142 and thegate spacers 140. TheGAA structures semiconductor device 100. -
FIG. 4 shows a plane view of asemiconductor device 100 in accordance with some embodiments. Thesemiconductor device 100 includesmultiple GAA structures 160A in thenMOS region 100A, andmultiple GAA structures 160B in thepMOS region 100B. Each of theGAA structures gate spacers 140. Moreover, theGAA structures structures 122 are disposed on opposite sides of theGAA structure 160A. Also, the source and drainstructures 132 are disposed on opposite sides of theGAA structure 160B. In some embodiments, the neighboring epitaxial source or drainstructures 122 of different FinFETs in thenMOS region 100A may be merged together. Also, the neighboring epitaxial source or drainstructures 132 of different FinFETs in thepMOS region 100B may be merged together. In some other embodiments, the neighboring epitaxial source or drainstructures 122 of different FinFETs in thenMOS region 100A may be separated from each other. Also, the neighboring epitaxial source or drainstructures 132 of different FinFETs in thepMOS region 100B may be separated from each other. Multiple FinFETs of thenMOS region 100A are isolated from multiple FinFETs of thepMOS region 100B by theisolation structures 104 on thesubstrate 102. InFIG. 4 , for ease of depicting the figure, some components or features (for example, theCESL 142 and the ILD layer 144) illustrated in the above mentioned figures are omitted to avoid obscuring other components or features. -
FIG. 5 shows a cross-sectional view of a portion of thesemiconductor device 100 taken along line II-II′ inFIG. 4 , in accordance with some embodiments. Line II-II′ is on a plane that is along theGAA structure 160A in thenMOS region 100A and theGAA structure 160B in thepMOS region 100B. In fact, theGAA structure 160A is separated from theGAA structure 160B by theisolation structure 104 which is illustrated with a demarcation line inFIG. 5 . The interfacial layer (IL) 127 is conformally formed on thefins 102F and to surround the semiconductor layers (also referred to as nanosheets) 112 in thenMOS region 100A and thepMOS region 100B. Thegate dielectric layer 128 is conformally formed on theIL 127 and theisolation structure 104, and to surround the semiconductor layers 112 in thenMOS region 100A and thepMOS region 100B. - In the
nMOS region 100A, theGAA structure 160A includes thenWF layer 152 sandwiched between thethin blocking layer 150′ and thecapping layer 153. ThenWF layer 152 is directly deposited on thethin blocking layer 150′ after the native oxide is removed from thethin blocking layer 150′. Thecapping film 154 is formed on thecapping layer 153. Each of thethin blocking layer 150′, thenWF layer 152, thecapping layer 153 and thecapping film 154 surround the semiconductor layers 112 in thenMOS region 100A. According to some embodiments of the disclosure, thenWF layer 152 is thin enough for filling in thespaces 126 between the semiconductor layers 112 at the technology nodes of N3 and below. Thethin blocking layer 150′ can serve as a first oxygen blocking layer to prevent thethin nWF layer 152 from oxidation. In addition, thecapping layer 153 and thecapping film 154 can together serve as a second oxygen blocking layer to prevent thethin nWF layer 152 from oxidation more efficiently. - The oxidation of the nWF layer will cause the work function of n-type metal gate shift to p-type work function which induces higher threshold voltage (Vt) of nMOS. According to the embodiments of the disclosure, the native oxide removal of the
thin blocking layer 150′, and the formations of thenWF layer 152, thecapping layer 153 and thecapping film 154 are in-situ performed in the same process chamber to avoid oxidation of thethin nWF layer 152 more efficiently. Therefore, thesemiconductor device 100 can achieve ultra-low Vt of nMOS with ultra-thin nWF layer in GAA structure. - In addition, the
pWF layer 156 is conformally formed on and in direct contact with thegate dielectric layer 128 in thepMOS region 100B. In theGAA structure 160B, thepWF layer 156 is directly deposited on thegate dielectric layer 128 without thethin blocking layer 150′ in thepMOS region 100B. ThepWF layer 156 is also conformally formed on thecapping film 154 in thenMOS region 100A. ThepWF layer 156 surrounds the semiconductor layers 112 in thenMOS region 100A and thepMOS region 100B. The metalgate fill material 158 is formed in thenMOS region 100A and thepMOS region 100B to surround the semiconductor layers 112, and is also formed on thefins 102F and theisolation structures 104. The top surface of the metalgate fill material 158 of theGAA structure 160A is at the same level with the metalgate fill material 158 of theGAA structure 160B. - Afterwards, via contacts (not shown) to the source and drain
structures 122 and the source and drainstructures 132 are formed in theILD layer 144. The via contacts are formed to pass through theCESL layer 142 and to be in contact with the respective source and drainstructures 122 and the respective source and drainstructures 132. The via contacts are formed by forming contact holes in theILD layer 144 and theCESL layer 142 using photolithography and etching processes. The source and drainstructures 122 and the source and drainstructures 132 are exposed through the contact holes. - Thereafter, the contact holes are filled with a conductive material using a deposition process. Moreover, in each of the contact holes, a liner may be conformally deposited on the sidewalls and the bottom surface of the contact hole before filling the contact hole with the conductive material. The liner may be used as a diffusion barrier layer, an adhesion layer, or a combination thereof. The material of the liner may include Ti, TiN, Ta, TaN, or the like. The liner may be deposited by ALD, PECVD, MBD, PVD, or another deposition technique. In addition, an anneal process may be performed to facilitate a reaction between some portions of the liner and the source and drain
structures 122 and the source and drainstructures 132 to form silicide regions at the respective source and drainstructures 122 and the respective source and drainstructures 132. - The conductive material of the via contacts includes a metal, such as Co, W, Cu, Al, Au, Ag, alloys thereof, or a combination thereof, and may be deposited by CVD, ALD, PVD, or another deposition technique. Next, excess portion of the conductive material over the
ILD layer 144 is removed in a planarization process, such as a CMP process, to form the via contacts. - Afterwards, an additional ILD layer (not shown) is formed on the
ILD layer 144 and theGAA structures GAA structures GAA structures structures 122 and the source and drainstructures 132. - According to the embodiments of the disclosure, methods for fabricating the
semiconductor devices 100 such as FinFET devices with theGAA structures GAA structure 160A in thenMOS region 100A includes thegate dielectric layer 128, thethin blocking layer 150′, the n-typework function layer 152, thecapping layer 153, thecapping film 154 and the p-typework function layer 156 to surround the semiconductor layers (also referred to as nanosheets) 112 in sequence. TheGAA structure 160B in thepMOS region 100B includes thegate dielectric layer 128 and the p-typework function layer 156 to surround the semiconductor layers (also referred to as nanosheets) 112 in sequence. TheGAA structures gate fill material 158 to full fill thetrenches gate spacers 140. The metalgate fill material 158 may also be in thespaces - In some embodiments of the disclosure, the n-type
work function layer 152 is thin enough for easy filling in thespaces 126 between the semiconductor layers 112 at the technology nodes of N3 and below. In some embodiments, each of thespaces 126 between the semiconductor layers 112 has the height d1 that is in a range from about 8 nm to about 10 nm. The thickness of the n-typework function layer 152 is in a range from about 10 Å to about 20 Å. A thin n-type work function layer may be easy oxidized to cause the work function of n-type metal gate shift to p-type work function which induces higher threshold voltage (Vt) of nMOS. According to the embodiments of the disclosure, thethin blocking layer 150′ can serve as a first oxygen blocking layer to prevent the thin n-typework function layer 152 from oxidation. Moreover, thecapping layer 153 and thecapping film 154 can together serve as a second oxygen blocking layer to prevent the thin n-typework function layer 152 from oxidation more efficiently. - In addition, according to the embodiments of the disclosure, the native oxide removal of the
thin blocking layer 150′, and the formations of the n-typework function layer 152, thecapping layer 153 and thecapping film 154 are in-situ performed in the same process chamber to avoid the oxidation of the thin n-typework function layer 152 more efficiently. Therefore, thesemiconductor device 100 can achieve ultra-low threshold voltage (Vt) of nMOS with ultra-thin n-type work function layer for GAA structure. - According to the benefits mentioned above, the embodiments of the disclosure are suitable for semiconductor devices with GAA structure at multiple technology nodes of 20 nm (N20), N16, N10, N7, N5, N3 and beyond. The GAA structures of the semiconductor devices use ultra-thin n-type work function layer and thin oxygen blocking layers to fill the spaces between nanosheets and the trenches between the gate spacers. Therefore, the process window of filling metal gates can be enlarged. Moreover, the thin oxygen blocking layers can reduce gate resistance for device performance improvement.
- Furthermore, according to the embodiments of the disclosure, the four steps in-situ processes of forming the ultra-thin n-type work function layer sandwiched between the oxygen blocking layers can efficiently prevent oxidation of the ultra-thin n-type work function layer. Therefore, ultra-low Vt tuning of nMOS for the semiconductor devices beyond N3 technology node with ultra-thin n-type work function layer in the GAA structure can be achieved to gain device performance.
- In some embodiments, a method of fabricating a semiconductor device is provided. The method includes forming a fin structure on a substrate. The fin structure comprises a stack of alternating first semiconductor layers and second semiconductor layers. The method also includes removing the first semiconductor layers to form spaces between the second semiconductor layers, and depositing a gate dielectric layer to surround the second semiconductor layers. The method further includes depositing a first oxygen blocking layer on the gate dielectric layer to surround the second semiconductor layers, and removing the native oxide from the first oxygen blocking layer in a process chamber. In addition, the method includes depositing an n-type work function layer on the first oxygen blocking layer to surround the second semiconductor layers in the process chamber. The method also includes forming a second oxygen blocking layer on the n-type work function layer to surround the second semiconductor layers in the process chamber. The second oxygen blocking layer includes a capping layer and a capping film on the capping layer. The method further includes forming a metal gate fill material on the capping film to form a gate-all-around structure.
- In some embodiments, a method of fabricating a semiconductor device is provided. The method includes forming a plurality of semiconductor nanosheets over a substrate in a p-type device region and an n-type device region. The semiconductor nanosheets are separated from each other. The method also includes depositing a gate dielectric layer to surround the semiconductor nanosheets in both the p-type device region and the n-type device region. The method further includes depositing a first oxygen blocking layer on the gate dielectric layer to surround the semiconductor nanosheets in the n-type device region, and removing the native oxide from the first oxygen blocking layer in a process chamber. In addition, the method includes depositing an n-type work function layer on the first oxygen blocking layer to surround the semiconductor nanosheets in the process chamber. The method also includes forming a second oxygen blocking layer on the n-type work function layer to surround the semiconductor nanosheets in the process chamber. The second oxygen blocking layer includes a capping layer and a capping film on the capping layer. The method further includes depositing a p-type work function layer directly on the gate dielectric layer to surround the semiconductor nanosheets in the p-type device region and on the second oxygen blocking layer in the n-type device region in the process chamber. In addition, the method includes depositing a metal gate fill material on the p-type work function layer to form a first gate-all-around structure in the n-type device region and to form a second gate-all-around structure in the p-type device region.
- In some embodiments, a semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate, and a plurality of semiconductor nanosheets separated from each other and disposed over the fin. The semiconductor device also includes a first gate-all-around (GAA) structure surrounding the semiconductor nanosheets in an n-type device region. The first GAA structure includes an n-type work function layer sandwiched between a first oxygen blocking layer and a second oxygen blocking layer. The semiconductor device further includes a second GAA structure surrounding the semiconductor nanosheets in a p-type device region. The second GAA structure includes a p-type work function layer directly on a gate dielectric layer. In addition, the semiconductor device includes first source and drain structures disposed on opposite sides of the first GAA structure. The semiconductor device also includes second source and drain structures disposed on opposite sides of the second GAA structure.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
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