US20200098849A1 - On-die capacitor for a vlsi chip with backside metal plates - Google Patents
On-die capacitor for a vlsi chip with backside metal plates Download PDFInfo
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- US20200098849A1 US20200098849A1 US16/142,792 US201816142792A US2020098849A1 US 20200098849 A1 US20200098849 A1 US 20200098849A1 US 201816142792 A US201816142792 A US 201816142792A US 2020098849 A1 US2020098849 A1 US 2020098849A1
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- 238000000034 method Methods 0.000 claims abstract description 33
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
Definitions
- the present invention relates to through vias, and more specifically, to forming one or more capacitors for a die using through-substrate vias.
- 3D-IC integrated circuit
- TSVs through substrate vias
- Efficient use of TSVs permits superior electrical connection throughout a 3D-IC, and can offer other benefits for 3D-ICs. As such, there is a need to more effectively use TSVs for 3D-ICs.
- a method includes: providing a substrate, providing at least one device layer over the substrate, providing a first plurality of metal layers over the at least one device layer on a first side of the substrate, where the first plurality of metal layers are connected to devices in the device layer, forming a second plurality of metal layers on a second side of the substrate opposite the first side, where the second plurality of metal layers form at least one capacitor, connecting the plurality of first metal layers to the second plurality of metal layers using a plurality of through-substrate-vias (TSVs).
- TSVs through-substrate-vias
- a structure includes: The structure includes: a substrate, a device layer over the substrate, a first plurality of metal layers connected to the device layer, where the device layer and the first plurality of metal layers are disposed on a first side of the substrate, and a second plurality of metal layers disposed on a second side of the substrate opposite the first side, where the second plurality of metal layers form at least one capacitor and where a plurality of through-substrate vias (TSVs) extend between the first plurality of metal layers and the second plurality of metal layers.
- TSVs through-substrate vias
- FIG. 1 illustrates a semiconductor structure with backside plates forming one or more capacitors in accordance with an embodiment of the present disclosure.
- FIG. 2A illustrates backside plates for a semiconductor structure in accordance with an embodiment of the present disclosure.
- FIG. 2B illustrates backside plates for a semiconductor structure in accordance with an embodiment of the present disclosure.
- FIG. 3A illustrates a semiconductor structure with backside plates forming one or more capacitors in accordance with an embodiment of the present disclosure.
- FIG. 3B illustrates a semiconductor structure with backside plates forming one or more capacitors in accordance with an embodiment of the present disclosure.
- FIG. 4A illustrates a top backside plate configuration for forming one or more capacitors in accordance with an embodiment of the present disclosure.
- FIG. 4B illustrates a top backside plate configuration for forming one or more capacitors in accordance with an embodiment of the present disclosure.
- FIG. 4C illustrates a top backside plate configuration for forming one or more capacitors in accordance with an embodiment of the present disclosure.
- FIG. 4D illustrates a top backside plate configuration for forming one or more capacitors in accordance with an embodiment of the present disclosure.
- FIG. 5 illustrates a flow for forming a semiconductor structure in accordance with at least one embodiment of the present disclosure.
- VLSI circuits can be fabricated on a thin silicon wafer or other suitable material. At least one benefit of the present disclosure is providing for one or more embodiments that utilize both sides of a silicon wafer (or other suitable material or wafer). One side forms a connection for the device layers, and the other side, e.g. the back side, has two or more metal plates for forming capacitors on the back side of the structure. The capacitors are connected to the entire structure by through-substrate vias (TSVs) and the contact of the TSVs through and on the two or more metal plates form the capacitors on the back side of the structure.
- TSVs through-substrate vias
- Utilizing the backside of the structure is an efficient use of space for building large scale solutions, and having the capacitors on the back of the substrate allows for direct connection to components, such as transistors, located on a device layer(s) of the structure, which in turn provides for more efficient device use by minimizing current leakage.
- FIG. 1 illustrates a semiconductor structure 100 with one or more on-die capacitors (discussed below) formed on the back (as shown in FIG. 3 ) of a substrate 110 (or other supportive material) by multiple through-substrates via (TSV) connections 135 .
- the substrate 110 can be any suitable material or wafer, including but not limited to a silicon (Si) wafer or a Si substrate 110 .
- the structure 100 can include one or more device layers 120 over the substrate 110 (also referred to as active regions), where the one or more device layers 120 can include one or more transistors, conductors, insulating materials and layers, or any other suitable semiconductor devices thereon, collectively device layer components 122 as shown in FIG. 3 .
- the device layers 120 can be formed using any suitable semiconductor process or processes, including one or more steps that employ CVD and PVD techniques.
- the structure can also include one or more metal layers 130 over the device layer 120 , where the metal layers 130 can be any suitable conductive materials, e.g. tungsten or copper, and can be deposited using any suitable deposition or plating techniques.
- the device 100 is interconnected using multiple TSV connections 135 .
- a set 140 of two or more metal plates is deposited on the back of the device 100 , e.g. the back or unused side 110 a of substrate 110 using any suitable plating or deposition process.
- the plates forming the set 140 are discussed in greater detail with reference to FIG. 2A , FIG. 2B , FIG. 4A , and FIG. 4B .
- One plate has holes formed there-through to enable the TSVs 135 to connect through one plate and into another plate.
- the interconnection forms the one or more capacitors (discussed below). Any suitable back end of the line (BEOL) technique can be employed to form the TSVs 135 and interconnection throughout the device 100 .
- BEOL back end of the line
- FIG. 2A illustrates a configuration for back plates 150 a and 150 b where the TSVs are micro-TSVs 135 a .
- the length of the TSVs 135 are generally a little longer than the wafer thickness and the width or diameter of the TSVs 135 may depend on what the fabrication technique being used (e.g., 65 nm, 22 nm, 7 nm, etc.).
- FIG. 2B illustrates a configuration for back plates (e.g. any suitable conductive plates, including but not limited to copper, tungsten, gold, silver, etc.) 150 c and 150 d , where the TSVs 135 are standard TSVs 135 , e.g. 20 nm to 25 nm in length.
- holes 170 a are formed on plate 150 a using any suitable etching or laser technique, where the holes 170 a can accommodate micro-TSVs.
- holes 170 b are formed on plate 150 b using any suitable etching or laser technique, where the holes 170 b can accommodate standard TSVs.
- the template for holes 170 a and/or 170 b is based on the nature of the BEOL connection or wiring scheme used to interconnect the substrate 110 , the device layers 120 , and the metal layers 130 .
- the holes 170 a and 170 b can be formed on the applicable plates in light of the wiring scheme using any suitable laser or etching technique.
- FIG. 3A shows a cross-section of structure 100 when backsides 150 a , 150 b are used to form the one or more capacitors 140 a .
- one or more dielectric layers 121 are formed over the substrate 110 and in contact with one or both of the substrate 110 and the device layers 120 .
- TSVs e.g. micro TSVs 135 a
- the direct connection to the transistors 122 enhances the overall power transfer and storage of the device 100 by providing a shorter distance of power transfer between the transistors 122 and the to-be-formed capacitors 140 a , in addition to providing a direct connection thereto.
- a dielectric layer 124 is deposited on semiconductor plate 150 a , followed by patterning the holes 170 a (shown in detail in FIG. 2A ) through semiconductor substrate 110 after the TSVs 135 a interconnect the structure. Any suitable etching or laser technique can be used to make the holes 170 a .
- the holes 170 a may have inner sidewalls and inner bottom surface covered with a conformal dielectric liner (not shown), such as SiO 2 or Si 3 N 4 .
- the holes 170 a are filled with micro-TSV structures 135 a that can be composed of any suitable conductive material, such as copper or tungsten, and which interconnect the device 100 .
- the plurality of TSVs 135 a are micro-TSVs, and the back plates 150 a , 150 b of FIG. 2A are used. In another embodiment, although not shown, back plates 150 c , 150 d of FIG. 2B are employed, and the TSVs 135 a are standard TSVs.
- FIG. 3B illustrates the configuration of FIG. 3A with additional plates 150 e and 150 f at the back end of the structure to form a stacked structure with multiple layers of capacitance at the back—i.e., capacitor 140 a and 140 b .
- multiple plates including but not limited to 150 a , 150 b , 150 e , and 150 f (with dielectric layer 124 c between 150 e and 150 f and dielectric layer 124 b separating the two capacitors 140 a and 140 b ) can be formed in the z direction (the same can be done with the configuration of FIG. 2B ).
- the holes 170 a can be formed in any direction including laterally across, up or down, through the center, and on the periphery of 150 b (and 150 f if multiple sets are used). Since the holes 170 a can be formed in any direction, the one or more capacitors 140 formed on the backside of the structure 100 can be in any direction, including the x and y direction, as well as in the z-direction. In one embodiment, the partitioning to form the one or more capacitors 140 is more clearly shown in FIG. 4A (and with reference to the surface of plate 150 b ) discussed below. In one embodiment, metal plates 150 a and 150 b (and by extension metal plates 150 e and 150 f ) can be substantially the same thickness and/or have substantially the same resistivity.
- the multilayers e.g. the additional plates 150 e , 150 f
- the connection between plates 150 a and 150 b can be formed such that a single capacitor is formed and in one embodiment more than one capacitor is formed.
- plates 150 a , 150 e are VSS plates and plates 150 b , 150 f are VDD plates.
- 150 c can be a VSS plate and 150 d can be a VDD plate.
- one or more capacitors 140 a can be formed by adjusting the dielectric material (not shown) (during initial deposition) between the plates 150 a , 150 b or 150 c , 150 d , by adjusting the interconnection of the vias through the holes 170 a or 170 b , e.g. the larger the area between via connections, the larger the capacitor, and/or by partitioning the plate (See FIG. 4C in reference to plate 150 d , but applicable to plate 150 b as well) using any suitable lasering, soldering, or other suitable partitioning technique.
- the one or more schemes are shown with reference to the surface of back plate 150 b ( FIG. 4A and FIG. 4B ) and back plate 150 d ( FIG. 4C and FIG. 4D ), with the complete wiring being accomplished as discussed with reference to the above discussion(s) or any other suitable technique.
- FIG. 4A illustrates the metal plate 150 b in more detail to illustrate partitioning and forming a capacitor 140 a
- FIG. 4A is with reference to a single back plate, and it is understood that the completed structure is ascertained with reference to FIG. 3 ).
- a micro-TSV scheme is used, and via connections to the back plate 150 a (not shown) can be in any direction, e.g. through the center and the periphery of 150 b .
- the back plate 150 b as show in FIG. 4A illustrates one or more embodiments for one or more capacitors 140 a of FIG. 3 .
- the vias connect to the periphery only, e.g. sections 153 a , 153 b , 153 c , and 153 d , thus creating a single large capacitor 140 a.
- FIG. 4B illustrates the metal plate 150 b in more detail to illustrate partitioning and forming one or more capacitors 140 a
- FIG. 4B is with reference to a single back plate, and it is understood that the completed structure is ascertained with reference to FIG. 3 ).
- a micro-TSV scheme is used, and via connections to the back plate 150 a (not shown) can be in any direction, e.g. through the center and the periphery of 150 b .
- a single capacitor 140 a can be formed as in FIG. 4A , but an additional capacitor 140 b is formed by connecting vias through holes 170 a to the plate 150 a (not shown) in the bounded area 441 while the remaining portion of the plate is part of a different capacitor 140 a.
- FIG. 4C illustrates the metal plate 150 d (as stated above, FIG. 4C is with reference to a single back plate, and it is understood that the completed structure is ascertained with reference to FIG. 3 ) in more detail to illustrate partitioning and forming the capacitor 140 a .
- a standard-TSV scheme is used, via connections to the back plate 150 c (not shown) can go along and through the periphery of 150 d , which is not partitioned and which has a substantially uniform dielectric material (not shown) between 150 d and 150 c.
- FIG. 4D illustrates the metal plate 150 d in more detail to illustrate one or more embodiments of the present disclosure related to partitioning and forming more than one capacitor 140 a .
- via connections to the back plate 150 c can go along and through the periphery of 150 d , where 150 d is partitioned into sections 152 a , 152 b , 152 c , and 152 d , and where a substantially uniform dielectric material (not shown) is between 150 d and 150 c .
- Each partitioned region 152 a , 152 b , 152 c , and 152 d corresponds to a section of back plate 150 d and back plate 150 c (not shown) and constitutes a single capacitor, for a total of four capacitors as shown in FIG. 4D ???, although other schemes are possible in accordance with the techniques described herein.
- FIG. 5 illustrates a flow 500 for forming one or more back plate capacitors 140 a in accordance with at least one embodiment of the present disclosure.
- Block 510 provides any suitable semiconductor substrate 110 or supporting material, e.g. silicon.
- Block 520 provides a device layer 120 that contains one or more semiconductor structures, including transistors, over the substrate, where the device layer 120 can be formed using any combination of suitable semiconductor deposition or formation techniques.
- Block 530 provides a first set of metal layers 130 over the device layer 120 using any suitable deposition or plating technique.
- Block 540 interconnects the layers 130 , 120 , and 110 using one or more TSV connections 135 and using any suitable BEOL technique.
- the TSV connections are composed of micro TSVs 135 a and in one embodiment the TSV connections are composed of standards TSVs.
- a second set of metal layers e.g. back plates 150 a , 150 b
- the TSV connection 135 used to connect layers 110 , 120 , and 130 will serve as the template for the holes 170 a .
- both the first set of metal layers 130 and the second set of metal layers, e.g. 150 a , 150 b are made of any suitable conducting material, including tungsten, copper, gold, and silver.
- a suitable dielectric material is deposited in between the back metal plates 150 a , 150 b , and in conjunction with the TSV connections, forms one or more capacitors 140 a .
- the number and size of the capacitors is adjustable by the manner in which the TSVs 135 are connected, where in one embodiment micro TSVs 135 a can go through holes that cover periphery and center of a back plate and where in one embodiment TSVs 135 are standard TSVs that can connect along the periphery of a back plate. In one embodiment, the TSVs 135 a connect directly to devices in the device layer 120 .
- the one back plate is a VSS plate and one plate is a VDD plate, and both plates have substantially the same thickness.
- more than one set of back plates 150 a , 150 b are deposited on the backside of the substrate 110 in order to form multiple layers of capacitors.
- aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.”
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Abstract
Description
- The present invention relates to through vias, and more specifically, to forming one or more capacitors for a die using through-substrate vias.
- Many methods have been suggested in semiconductor manufacturing technology to form 3D-ICs. 3D-IC technology typically demands very thin chips of tens of microns to achieve high density integration. The thin chips are stacked and electrically connected by through substrate vias (TSVs). Efficient use of TSVs permits superior electrical connection throughout a 3D-IC, and can offer other benefits for 3D-ICs. As such, there is a need to more effectively use TSVs for 3D-ICs.
- According to one embodiment of the present disclosure, a method is provided. The method includes: providing a substrate, providing at least one device layer over the substrate, providing a first plurality of metal layers over the at least one device layer on a first side of the substrate, where the first plurality of metal layers are connected to devices in the device layer, forming a second plurality of metal layers on a second side of the substrate opposite the first side, where the second plurality of metal layers form at least one capacitor, connecting the plurality of first metal layers to the second plurality of metal layers using a plurality of through-substrate-vias (TSVs).
- According to another embodiment of the present disclosure, a structure is provided. The structure includes: The structure includes: a substrate, a device layer over the substrate, a first plurality of metal layers connected to the device layer, where the device layer and the first plurality of metal layers are disposed on a first side of the substrate, and a second plurality of metal layers disposed on a second side of the substrate opposite the first side, where the second plurality of metal layers form at least one capacitor and where a plurality of through-substrate vias (TSVs) extend between the first plurality of metal layers and the second plurality of metal layers.
-
FIG. 1 illustrates a semiconductor structure with backside plates forming one or more capacitors in accordance with an embodiment of the present disclosure. -
FIG. 2A illustrates backside plates for a semiconductor structure in accordance with an embodiment of the present disclosure. -
FIG. 2B illustrates backside plates for a semiconductor structure in accordance with an embodiment of the present disclosure. -
FIG. 3A illustrates a semiconductor structure with backside plates forming one or more capacitors in accordance with an embodiment of the present disclosure. -
FIG. 3B illustrates a semiconductor structure with backside plates forming one or more capacitors in accordance with an embodiment of the present disclosure. -
FIG. 4A illustrates a top backside plate configuration for forming one or more capacitors in accordance with an embodiment of the present disclosure. -
FIG. 4B illustrates a top backside plate configuration for forming one or more capacitors in accordance with an embodiment of the present disclosure. -
FIG. 4C illustrates a top backside plate configuration for forming one or more capacitors in accordance with an embodiment of the present disclosure. -
FIG. 4D illustrates a top backside plate configuration for forming one or more capacitors in accordance with an embodiment of the present disclosure. -
FIG. 5 illustrates a flow for forming a semiconductor structure in accordance with at least one embodiment of the present disclosure. - It is noted that the drawings of the present application are provided for illustrative purposes and, as such, they are not drawn to scale. In the drawings and the description that follows, like materials are referred to by like reference numerals. For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the components, layers and/or materials as oriented in the drawing figures which accompany the present application.
- In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present disclosure. However, it will be appreciated by one of ordinary skill in the art that the present disclosure may be practiced with viable alternative process options without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the various embodiments of the present disclosure.
- Very-large-scale-integrated circuits (“VLSI circuits”) can be fabricated on a thin silicon wafer or other suitable material. At least one benefit of the present disclosure is providing for one or more embodiments that utilize both sides of a silicon wafer (or other suitable material or wafer). One side forms a connection for the device layers, and the other side, e.g. the back side, has two or more metal plates for forming capacitors on the back side of the structure. The capacitors are connected to the entire structure by through-substrate vias (TSVs) and the contact of the TSVs through and on the two or more metal plates form the capacitors on the back side of the structure. Utilizing the backside of the structure is an efficient use of space for building large scale solutions, and having the capacitors on the back of the substrate allows for direct connection to components, such as transistors, located on a device layer(s) of the structure, which in turn provides for more efficient device use by minimizing current leakage.
-
FIG. 1 illustrates asemiconductor structure 100 with one or more on-die capacitors (discussed below) formed on the back (as shown inFIG. 3 ) of a substrate 110 (or other supportive material) by multiple through-substrates via (TSV)connections 135. Thesubstrate 110 can be any suitable material or wafer, including but not limited to a silicon (Si) wafer or aSi substrate 110. Thestructure 100 can include one ormore device layers 120 over the substrate 110 (also referred to as active regions), where the one ormore device layers 120 can include one or more transistors, conductors, insulating materials and layers, or any other suitable semiconductor devices thereon, collectively device layer components 122 as shown inFIG. 3 . Thedevice layers 120 can be formed using any suitable semiconductor process or processes, including one or more steps that employ CVD and PVD techniques. The structure can also include one ormore metal layers 130 over thedevice layer 120, where themetal layers 130 can be any suitable conductive materials, e.g. tungsten or copper, and can be deposited using any suitable deposition or plating techniques. - The
device 100 is interconnected usingmultiple TSV connections 135. In one embodiment, aset 140 of two or more metal plates is deposited on the back of thedevice 100, e.g. the back orunused side 110 a ofsubstrate 110 using any suitable plating or deposition process. The plates forming theset 140 are discussed in greater detail with reference toFIG. 2A ,FIG. 2B ,FIG. 4A , andFIG. 4B . One plate has holes formed there-through to enable the TSVs 135 to connect through one plate and into another plate. The interconnection forms the one or more capacitors (discussed below). Any suitable back end of the line (BEOL) technique can be employed to form theTSVs 135 and interconnection throughout thedevice 100. -
FIG. 2A illustrates a configuration forback plates TSVs 135 are generally a little longer than the wafer thickness and the width or diameter of theTSVs 135 may depend on what the fabrication technique being used (e.g., 65 nm, 22 nm, 7 nm, etc.).FIG. 2B illustrates a configuration for back plates (e.g. any suitable conductive plates, including but not limited to copper, tungsten, gold, silver, etc.) 150 c and 150 d, where theTSVs 135 arestandard TSVs 135, e.g. 20 nm to 25 nm in length. - In
FIG. 2A ,holes 170 a are formed onplate 150 a using any suitable etching or laser technique, where theholes 170 a can accommodate micro-TSVs. InFIG. 2B , holes 170 b are formed onplate 150 b using any suitable etching or laser technique, where theholes 170 b can accommodate standard TSVs. - In one embodiment, whether the configuration of
FIG. 2A orFIG. 2B is employed, the template forholes 170 a and/or 170 b is based on the nature of the BEOL connection or wiring scheme used to interconnect thesubstrate 110, the device layers 120, and the metal layers 130. Theholes -
FIG. 3A shows a cross-section ofstructure 100 whenbacksides more capacitors 140 a. In one embodiment, one or moredielectric layers 121 are formed over thesubstrate 110 and in contact with one or both of thesubstrate 110 and the device layers 120. In one embodiment, as stated, prior to depositing theback plates micro TSVs 135 a, can connect directly to transistors 122 (or any othersuitable device layer 120 component) using any suitable BEOL connection and wiring technique. The direct connection to the transistors 122 enhances the overall power transfer and storage of thedevice 100 by providing a shorter distance of power transfer between the transistors 122 and the to-be-formed capacitors 140 a, in addition to providing a direct connection thereto. - In one embodiment, a
dielectric layer 124 is deposited onsemiconductor plate 150 a, followed by patterning theholes 170 a (shown in detail inFIG. 2A ) throughsemiconductor substrate 110 after theTSVs 135 a interconnect the structure. Any suitable etching or laser technique can be used to make theholes 170 a. Theholes 170 a may have inner sidewalls and inner bottom surface covered with a conformal dielectric liner (not shown), such as SiO2 or Si3N4. Theholes 170 a are filled withmicro-TSV structures 135 a that can be composed of any suitable conductive material, such as copper or tungsten, and which interconnect thedevice 100. (In one embodiment, air can be used as a dielectric material and one or both of dielectric material and inner liners can be omitted). In one embodiment, as shown, the plurality ofTSVs 135 a are micro-TSVs, and theback plates FIG. 2A are used. In another embodiment, although not shown, backplates FIG. 2B are employed, and theTSVs 135 a are standard TSVs. -
FIG. 3B illustrates the configuration ofFIG. 3A withadditional plates capacitor FIG. 3B , which as shown uses the scheme ofFIG. 2A in one embodiment, multiple plates, including but not limited to 150 a, 150 b, 150 e, and 150 f (withdielectric layer 124 c between 150 e and 150 f anddielectric layer 124 b separating the twocapacitors FIG. 2B ). In the scheme that employs the back plate configuration ofFIG. 2A , theholes 170 a can be formed in any direction including laterally across, up or down, through the center, and on the periphery of 150 b (and 150 f if multiple sets are used). Since theholes 170 a can be formed in any direction, the one ormore capacitors 140 formed on the backside of thestructure 100 can be in any direction, including the x and y direction, as well as in the z-direction. In one embodiment, the partitioning to form the one ormore capacitors 140 is more clearly shown inFIG. 4A (and with reference to the surface ofplate 150 b) discussed below. In one embodiment,metal plates extension metal plates - As shown in
FIG. 3B , in one embodiment, since theholes 170 a can be formed in any direction, the multilayers, e.g. theadditional plates holes 170 a (seeFIG. 4A ). In one embodiment (seeFIG. 4A andFIG. 4B ), the connection betweenplates plates plates - With respect to
FIGS. 4A, 4B, 4C, and 4D , one ormore capacitors 140 a can be formed by adjusting the dielectric material (not shown) (during initial deposition) between theplates holes FIG. 4C in reference toplate 150 d, but applicable toplate 150 b as well) using any suitable lasering, soldering, or other suitable partitioning technique. It is to be appreciated that the one or more schemes are shown with reference to the surface ofback plate 150 b (FIG. 4A andFIG. 4B ) andback plate 150 d (FIG. 4C andFIG. 4D ), with the complete wiring being accomplished as discussed with reference to the above discussion(s) or any other suitable technique. -
FIG. 4A illustrates themetal plate 150 b in more detail to illustrate partitioning and forming acapacitor 140 a (as stated above,FIG. 4A is with reference to a single back plate, and it is understood that the completed structure is ascertained with reference toFIG. 3 ). In one embodiment, a micro-TSV scheme is used, and via connections to theback plate 150 a (not shown) can be in any direction, e.g. through the center and the periphery of 150 b. Theback plate 150 b as show inFIG. 4A illustrates one or more embodiments for one ormore capacitors 140 a ofFIG. 3 . In one embodiment, the vias connect to the periphery only,e.g. sections large capacitor 140 a. -
FIG. 4B illustrates themetal plate 150 b in more detail to illustrate partitioning and forming one ormore capacitors 140 a (as stated above,FIG. 4B is with reference to a single back plate, and it is understood that the completed structure is ascertained with reference toFIG. 3 ). In one embodiment, a micro-TSV scheme is used, and via connections to theback plate 150 a (not shown) can be in any direction, e.g. through the center and the periphery of 150 b. Asingle capacitor 140 a can be formed as inFIG. 4A , but anadditional capacitor 140 b is formed by connecting vias throughholes 170 a to theplate 150 a (not shown) in the boundedarea 441 while the remaining portion of the plate is part of adifferent capacitor 140 a. -
FIG. 4C illustrates themetal plate 150 d (as stated above,FIG. 4C is with reference to a single back plate, and it is understood that the completed structure is ascertained with reference toFIG. 3 ) in more detail to illustrate partitioning and forming thecapacitor 140 a. In one embodiment, a standard-TSV scheme is used, via connections to theback plate 150 c (not shown) can go along and through the periphery of 150 d, which is not partitioned and which has a substantially uniform dielectric material (not shown) between 150 d and 150 c. -
FIG. 4D (as stated above,FIG. 4D is with reference to a single back plate, and it is understood that the completed structure is ascertained with reference toFIG. 3 ) illustrates themetal plate 150 d in more detail to illustrate one or more embodiments of the present disclosure related to partitioning and forming more than onecapacitor 140 a. In one embodiment, where a standard-TSV scheme is used, via connections to theback plate 150 c (not shown) can go along and through the periphery of 150 d, where 150 d is partitioned intosections region back plate 150 d and backplate 150 c (not shown) and constitutes a single capacitor, for a total of four capacitors as shown inFIG. 4D ???, although other schemes are possible in accordance with the techniques described herein. -
FIG. 5 illustrates a flow 500 for forming one or moreback plate capacitors 140 a in accordance with at least one embodiment of the present disclosure. Each one of the blocks of the flow can be executed by one or more suitable semiconductor tools and using one or more suitable semiconductor steps.Block 510 provides anysuitable semiconductor substrate 110 or supporting material, e.g. silicon.Block 520 provides adevice layer 120 that contains one or more semiconductor structures, including transistors, over the substrate, where thedevice layer 120 can be formed using any combination of suitable semiconductor deposition or formation techniques.Block 530 provides a first set ofmetal layers 130 over thedevice layer 120 using any suitable deposition or plating technique. Block 540 interconnects thelayers more TSV connections 135 and using any suitable BEOL technique. In one embodiment, the TSV connections are composed ofmicro TSVs 135 a and in one embodiment the TSV connections are composed of standards TSVs. Inblock 550, a second set of metal layers, e.g. backplates substrate 110, where at least one of theback plates TSV connection 135 used to connectlayers holes 170 a. In one embodiment, both the first set ofmetal layers 130 and the second set of metal layers, e.g. 150 a, 150 b, are made of any suitable conducting material, including tungsten, copper, gold, and silver. - In one embodiment, per
block 560, a suitable dielectric material is deposited in between theback metal plates more capacitors 140 a. Per block 570, the number and size of the capacitors is adjustable by the manner in which theTSVs 135 are connected, where in one embodimentmicro TSVs 135 a can go through holes that cover periphery and center of a back plate and where in oneembodiment TSVs 135 are standard TSVs that can connect along the periphery of a back plate. In one embodiment, theTSVs 135 a connect directly to devices in thedevice layer 120. In one embodiment, the one back plate is a VSS plate and one plate is a VDD plate, and both plates have substantially the same thickness. In one embodiment, more than one set ofback plates substrate 110 in order to form multiple layers of capacitors. The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. - In the following, reference is made to embodiments presented in this disclosure. However, the scope of the present disclosure is not limited to specific described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice contemplated embodiments. Furthermore, although embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the scope of the present disclosure. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
- Aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.”
- While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (20)
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US11404534B2 (en) * | 2019-06-28 | 2022-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside capacitor techniques |
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US6236103B1 (en) | 1999-03-31 | 2001-05-22 | International Business Machines Corp. | Integrated high-performance decoupling capacitor and heat sink |
US6492244B1 (en) | 2001-11-21 | 2002-12-10 | International Business Machines Corporation | Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices |
US6819543B2 (en) | 2002-12-31 | 2004-11-16 | Intel Corporation | Multilayer capacitor with multiple plates per layer |
US7473979B2 (en) | 2006-05-30 | 2009-01-06 | International Business Machines Corporation | Semiconductor integrated circuit devices having high-Q wafer back-side capacitors |
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TWI400731B (en) | 2008-08-29 | 2013-07-01 | Ind Tech Res Inst | Capacitor device and method for manufacturing the same |
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US11205620B2 (en) * | 2018-09-18 | 2021-12-21 | International Business Machines Corporation | Method and apparatus for supplying power to VLSI silicon chips |
US11404534B2 (en) * | 2019-06-28 | 2022-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside capacitor techniques |
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