US20200075508A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20200075508A1 US20200075508A1 US16/254,646 US201916254646A US2020075508A1 US 20200075508 A1 US20200075508 A1 US 20200075508A1 US 201916254646 A US201916254646 A US 201916254646A US 2020075508 A1 US2020075508 A1 US 2020075508A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
Definitions
- the embodiments of the present invention relate to a semiconductor device.
- a material film may be peeled off from a substrate in a dicing region at an end of a semiconductor chip. Such peeling-off of the material film causes a failure in the semiconductor chip when the peeling-off propagates from the dicing region to a device region.
- FIG. 1 is a schematic plan view showing an example of a semiconductor wafer in accordance with a first embodiment
- FIG. 2 is an illustration showing an example of a dicing method according to the first embodiment
- FIG. 3 is an illustration showing the example of the dicing method, following to FIG. 2 ;
- FIG. 4 is an illustration showing the example of the dicing method, following to FIG. 2 ;
- FIG. 5 is an illustration showing the example of the dicing method, following to FIG. 2 ;
- FIG. 6 is an illustration showing the example of the dicing method, following to FIG. 3 ;
- FIG. 7 is an illustration showing the example of the dicing method, following to FIG. 3 ;
- FIG. 8 is an illustration showing the example of the dicing method, following to FIG. 6 ;
- FIG. 9 is a schematic plan view showing a configuration example of one semiconductor chip after diced.
- FIG. 10 is a sectional view taken on line 10 - 10 of FIG. 9 ;
- FIG. 11 is an illustration showing the state of propagation of a crack that has reached a trench.
- FIG. 12 is a sectional view showing the state of a semiconductor device after packaged.
- an upper direction or “a lower direction” refers to a relative direction when a direction of a surface perpendicular to a semiconductor substrate on which semiconductor elements are provided is assumed as “an upper direction”. Therefore, the term “upper direction” or “lower direction” occasionally differs from an upper direction or a lower direction based on a gravitational acceleration direction.
- elements identical to those described in the foregoing drawings are denoted by like reference characters and detailed explanations thereof are omitted as appropriate.
- a semiconductor device includes a substrate having a first region provided with a semiconductor element and a second region provided from the first region to an end.
- a material film is provided above the first and second regions.
- a first metal film is provided on the material film in the second region or on the material film between the first region and the second region.
- FIG. 1 is a schematic plan view showing an example of a semiconductor wafer in accordance with a first embodiment.
- a semiconductor wafer W is provided with a plurality of device regions Rdev and a plurality of dicing regions Rdic.
- the device regions Rdev and the dicing regions Rdic are regions on the front surface of the semiconductor wafer W.
- a semiconductor element such as a transistor and a memory cell array
- the semiconductor element is formed on the semiconductor wafer W through a semiconductor manufacturing process.
- the semiconductor element may, for example, be a memory cell array of NAND flash memories or its control circuit.
- the memory cell array may, for example, be a three-dimensional memory cell array of three-dimensionally arranged memory cells. It is a matter of course that the present embodiment is also applicable to LSI (Large Scale Integration) other than the semiconductor memories.
- Each dicing region Rdic is a line-like region between device regions Rdev adjacent to each other, which is a region to be cut by dicing.
- the dicing region Rdic is also referred to as a dicing line.
- a laser beam is emitted to a substrate 10 to form a modified portion LM (see FIG. 4 ) inside the substrate 10 in the dicing region Rdic, and then the semiconductor wafer W is cleaved at the modified portion LM as a starting point.
- the semiconductor wafer W is chipped per device region Rdev into semiconductor chips.
- Silicon is an example of semiconductor, however, another semiconductor, other than silicon, may also be used.
- the semiconductor wafer W is cut with a laser dicing method using a laser beam.
- a laser dicing method for example, a through-transmission laser in the infrared region is used.
- another dicing method such as a blade dicing method, may be used.
- FIGS. 2 to 8 are illustrations showing an example of the dicing method according to the first embodiment.
- Semiconductor elements formed on the semiconductor wafer W are omitted in the illustrations.
- a material film 20 formed above the substrate 10 and the semiconductor elements is schematically illustrated. The configuration of the material film 20 will be explained later with reference to FIG. 10 .
- a protective tape 110 for dicing is stuck on the front surface of the semiconductor wafer W.
- the protective tape 110 protects the semiconductor elements, the material film 20 , etc. at the time of laser dicing.
- the semiconductor wafer W and the protective tape 110 are turned upside down, and, as shown in FIGS. 3 and 4 , using a laser oscillator 120 , a laser beam 121 is emitted to the portions which correspond to the dicing regions Rdic from the rear surface of the semiconductor wafer W.
- a modified portion (amorphous layer or polysilicon layer) LM is formed inside the semiconductor wafer W.
- the modified portion LM is formed inside the semiconductor wafer W in each dicing region Rdic.
- FIG. 5 is a perspective view showing the state of emitting the laser beam 121 .
- the laser oscillator 120 while moving in a Y-direction as shown by an arrow A, emits the laser beam 121 in the form of pulses.
- modified portions LM are formed intermittently in the Y-direction and formed roughly in parallel along the dicing region Rdic. Although being formed intermittently, the modified portions LM are connected in the Y-direction roughly in the form of a layer.
- the modified portions LM may be in the form of a single layer or a plurality of layers formed at different positions (heights) in a Z-direction.
- the rear surface of the semiconductor wafer W is polished by CMP (Chemical Mechanical Polishing). Being polished with a sharpening stone 130 , the semiconductor wafer W is thinned, and not only that, as shown in FIG. 7 , a cleavage 131 spreads in the Z-direction from each modified portion LM due to vibration by polishing. The semiconductor wafer W is polished until the modified portions LM are removed.
- CMP Chemical Mechanical Polishing
- the rear surface of the semiconductor wafer W is stuck on a dicing tape 136 having an adhesive layer and then the dicing tape 136 is fixed with a ring 135 .
- the dicing tape 136 is pushed up with a push-up member 140 to be pulled (expanded).
- the semiconductor wafer W is pulled outwardly.
- the semiconductor wafer W is cleaved further along the modified portions LM, which are the starting points, (in other words, along the dicing lines), to be chipped into a plurality of semiconductor chips.
- the rear surface of the semiconductor wafer W is polished after being irradiated with a laser beam.
- the semiconductor wafer W may be irradiated with the laser beam after being polished at its rear surface.
- another dicing method such as a blade dicing method, may be used.
- the blade dicing method vibrates the semiconductor wafer W much more than the laser dicing method, to cut the material film 20 , the substrate 10 , etc. directly with a blade, so that a crack CR shown in FIG. 10 is easily generated. Therefore, the effects of the present embodiment will be exhibited further by applying the present embodiment to the blade dicing method.
- each semiconductor chip is picked up and mounted on a resin substrate (not shown).
- the semiconductor chip is bonded to the resin substrate by metal wiring and sealed with resin, thereby a semiconductor package is completed.
- FIG. 9 is a schematic plan view showing a configuration example of one semiconductor chip 1 after diced.
- the semiconductor chip 1 has a device region Rdev and a dicing region Rdic on its front surface.
- the device region Rdev as a first region, is a region in which a semiconductor element is provided, on the front surface of the substrate 10 (see FIG. 10 ).
- the dicing region Rdic is a region from the device region Rdev to an end of the substrate 10 , on the front surface of the substrate 10 , which is a region to be used for cutting in a dicing process.
- the dicing region Rdic is provided with a first metal film 40 e and a protruding portion 70 .
- the first metal film 40 e and the protruding portion 70 are arranged at a position apart from the device region Rdev so as to surround the device region Rdev.
- the first metal film 40 e and the protruding portion 70 will be explained later in detail with reference to FIG. 10 .
- the dicing region Rdic, the first metal film 40 e , and the protruding portion 70 may be completely removed in the dicing process, however, in general, at least partially remain in the periphery of the device region Rdev as shown in FIG. 9 .
- FIG. 10 is a sectional view taken on line 10 - 10 of FIG. 9 .
- the semiconductor chip 1 as a semiconductor device, is provided with a substrate 10 , element isolation portions 12 , a metal compound layer 15 , a semiconductor element 17 , a material film 20 , crack stoppers 30 , metal films 40 , and a passivation film 50 .
- the substrate 10 is, as described above, a semiconductor substrate such as a silicon substrate.
- the semiconductor element 17 provided in the device region Rdev of the substrate 10 may, for example, be a memory cell array or a CMOS circuit.
- the metal compound layer 15 is provided on the substrate 10 , used for a gate electrode (not shown) of a transistor in the device region Rdev.
- a conductive metal compound such as tungsten silicide (WSi) or tungsten nitride (WN), is used.
- WSi tungsten silicide
- WN tungsten nitride
- the metal compound layer 15 is not provided as a component of the semiconductor element 17 .
- the metal compound layer 15 is provided for maintaining the flatness of the front surface of the substrate 10 and for easy positioning in a lithography process.
- the element isolation portions 12 define active areas in the device region Rdev, provided for electrically isolating the active areas from each other.
- the element isolation portions 12 are also referred to as STI (Shallow Trench Isolation).
- the element isolation portions 12 are also provided between the device region Rdev and the dicing region Rdic.
- an element isolation portion 12 e nearest to the perimeter of the semiconductor chip 1 is provided between the device region Rdev and the dicing region Rdic and provided so as to divide the metal compound layer 15 .
- the element isolation portion 12 e may be provided in the dicing region Rdic.
- the element isolation portion 12 e is provided so as to surround the entire periphery of the device region Rdev along the perimeter of the semiconductor chip 1 of FIG. 9 (along the dicing region Rdic).
- the element isolation portion 12 e has a function to restrict the propagation of a crack CR or change the direction of the crack CR when the crack CR is generated between the metal compound layer 15 and the material film 20 .
- the element isolation portion 12 e may also have a function to separate a test pattern present in the dicing region Rdic.
- the material film 20 is provided on the device region Rdev and also on the dicing region Rdic.
- the material film 20 in the dicing region Rdic is, for example, a stacked film (also referred to as an ONON film, hereinafter) of a plurality of silicon oxide films (SiO 2 ) and a plurality of silicon nitride films (SiN) alternately stacked, or a stacked film (also referred to as an OWOW film, hereinafter) of a plurality of silicon oxide films (SiO 2 ) and a plurality of second metal films (for example, tungsten films (W)) alternately stacked.
- a stacked film also referred to as an ONON film, hereinafter
- SiN silicon nitride films
- a stacked film also referred to as an OWOW film, hereinafter
- the ONON film is a stacked film to be used in a memory cell array forming process.
- the silicon nitride films of the ONON film are replaced with the second metal films (for example, tungsten films), so that the ONON film changes to be the OWOW film.
- the OWOW film is used as one component of the memory cell array.
- the second metal films function as word lines of the memory cell array.
- the material film 20 may either be the ONON film or the OWOW film.
- the material film 20 in the dicing region Rdic may be an interlayer insulating film to cover the CMOS transistor.
- the material film 20 in the dicing region Rdic may be a single-layer film of a silicon oxide film such as a TEOS film.
- the crack stoppers 30 are provided inside the material film 20 on the perimeter of the device region Rdev and extend in the Z-direction toward the substrate 10 from the surface of the material film 20 .
- the crack stoppers 30 have, for example, a metal such as tungsten embedded therein.
- the crack stoppers 30 are provided so as to surround the periphery of the device region Rdev. Accordingly, the crack stoppers 30 restrict the propagation of the crack CR into the device region Rdev.
- the crack stoppers 30 are also referred to as a guard ring.
- the metal films 40 are, for example, used as a bonding-pad forming material.
- a conductive metal such as tungsten is used.
- the first metal film 40 e nearest to the perimeter of the semiconductor chip 1 is provided on the material film 20 in the dicing region Rdic or on the material film 20 between the device region Rdev and the dicing region Rdic, provided at a position apart from the device region Rdev.
- the first metal film 40 e functions as a mask in an etching process to expose bonding pads and is provided for forming a trench TR. In the etching process, the protruding portion 70 made of the material film 20 is formed under the first metal film 40 e .
- the protruding portion 70 is also disposed so as to surround the device region Rdev at a position apart from the device region Rdev. Accordingly, the trench TR is formed between the device region Rdev and the protruding portion 70 .
- the passivation film 50 covers the material film 20 in the device region Rdev and protects the semiconductor element 17 , the material film 20 , etc.
- the passivation film 50 is, for example, polyimide.
- the trench TR is provided between the device region Rdev and the dicing region Rdic, and provided near to the device region Rdev than the element isolation portions 12 .
- the trench TR caves in toward the substrate 10 from the surface of the material film 20 in the device region Rdev and also from the surface of the material film 20 under the first metal film 40 e . In other words, the trench TR caves in to a position lower than the surface of the material film 20 around the trench TR.
- the material film 20 has been etched in the same manner as the trench TR in the dicing region Rdic outside the first metal film 40 e . However, the material film 20 may not have been etched in the dicing region Rdic outside the first metal film 40 e.
- the trench TR may be provided to surround the entire periphery of the device region Rdev.
- the trench TR may be partially provided at a location where the material film 20 is easily peeled off and the crack CR is easily generated.
- the trench TR may have a flat, curved or pointed bottom.
- the material film 20 is easily peeled off from the metal compound layer 15 at an end of the semiconductor chip 1 , due to an impact in the dicing process, stress in TCT (Thermal Cycle Test), etc.
- TCT Thermal Cycle Test
- the crack CR propagates between the material film 20 and the metal compound layer 15 , toward the element isolation portion 12 e . In other words, the crack CR propagates toward the device region Rdev from the end of the semiconductor chip 1 .
- the propagation of the crack CR may stop when it reaches the element isolation portion 12 e .
- the material film 20 is thinner than the substrate 10 and vulnerable to mechanical stress, when the crack CR propagates further, it propagates inside the material film 20 .
- the crack CR tries to propagate toward the upper surface of the element isolation portion 12 e (in the Z-direction apart from the substrate 10 ). Therefore, force directed toward the device region Rdev from the end of the semiconductor chip 1 and force directed upward (in the Z-direction) from the element isolation portion 12 e are applied to the material film 20 . Accordingly, the crack CR propagates inside the material film 20 diagonally upward from the element isolation portion 12 e toward the device region Rdev.
- the trench TR is provided on the surface of the material film 20 between the device region Rdev and the dicing region Rdic, and provided nearer to the device region Rdev than the element isolation portion 12 e . Therefore, the trench TR is positioned above the element isolation portion 12 e in a diagonally upward direction, so that the crack CR can easily propagate toward the trench TR and, when the crack CR reaches the trench TR, the propagation completes. Accordingly, the trench TR has a function to induce the crack CR and terminate the crack CR with no propagation to the device region Rdev.
- the trench TR is preferably a cavity with no another material being embedded therein.
- the trench TR is preferably a cavity from the moment of formation of the trench TR to the moment of installation of the semiconductor chip 1 (for example, in the dicing and TCT processes). It is not problematic that a thin film is attached to the inner surface of the trench TR.
- the trench TR may be filled with sealing resin. In this case, although a crack induction effect of the trench TR is reduced a little bit, it is still effective.
- FIG. 11 is an illustration showing the state of propagation of the crack CR that has reached the trench TR.
- the crack CR When the crack CR has spread from the end of the semiconductor chip 1 and reached the element isolation portion 12 e , the crack CR propagates in a diagonally upward direction toward the trench TR. When the crack CR has reached the trench TR, it does not propagate anymore.
- the material film 20 at the end of the semiconductor chip 1 may be brown off to be removed without remaining there. However, since the material film 20 is not required in the dicing region Rdic, there is no problem even if it is removed. Of course it is not problematic even if the material film 20 remains at the end of the semiconductor chip 1 .
- the position of the trench TR that easily induces the crack CR depends on the conditions such as the film thickness of the material film 20 , and hence it cannot be said definitely.
- the material film 20 is an ONON film having a film thickness of about 5 ⁇ m to 15 ⁇ m
- the first metal film 40 e may be disposed directly above the element isolation portion 12 e .
- the first metal film 40 e may be disposed at roughly the same position as the element isolation portion 12 e . Accordingly, the trench TR is disposed nearer to the device region Rdev than the element isolation portion 12 e in a self-alignment manner.
- FIG. 12 is a sectional view showing the state of a semiconductor device after packaged. After being diced, the semiconductor chip 1 is mounted on a substrate (not shown) and then sealed with resin 60 as a resin portion.
- the resin 60 is provided above both of the dicing region Rdic and the device region Rdev.
- the resin 60 covers the material film 20 , the first metal film 40 e , the protruding portion 70 , and the passivation film 50 , and has a contact with these components.
- the trench TR is filled with the resin 60 .
- the trench TR is provided on the surface of the material film 20 between the device region Rdev and the dicing region Rdic, and provided nearer to the device region Rdev than the element isolation portions 12 . Accordingly, the trench TR can induce the crack CR that is generated between the material film 20 and the metal compound layer 15 , and terminate the propagation of the crack CR. In other words, the trench TR can restrict the propagation of the peeling-off of the material film 20 to the device region Rdev.
Abstract
A semiconductor device according to the present embedment includes a substrate having a first region provided with a semiconductor element and a second region provided from the first region to an end. A material film is provided above the first and second regions. A first metal film is provided on the material film in the second region or on the material film between the first region and the second region. A trench, which caves in toward the substrate from a surface of the material film in the first region and from a surface of the material film under the first metal film, is provided in the material film between the first metal film and the first region.
Description
- This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2018-160575, filed on Aug. 29, 2018 and No. 2018-218600, filed on Nov. 21, 2018, the entire contents of which are incorporated herein by reference.
- The embodiments of the present invention relate to a semiconductor device.
- When a semiconductor wafer is chipped by dicing into semiconductor chips or after being chipped, a material film may be peeled off from a substrate in a dicing region at an end of a semiconductor chip. Such peeling-off of the material film causes a failure in the semiconductor chip when the peeling-off propagates from the dicing region to a device region.
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FIG. 1 is a schematic plan view showing an example of a semiconductor wafer in accordance with a first embodiment; -
FIG. 2 is an illustration showing an example of a dicing method according to the first embodiment; -
FIG. 3 is an illustration showing the example of the dicing method, following toFIG. 2 ; -
FIG. 4 is an illustration showing the example of the dicing method, following toFIG. 2 ; -
FIG. 5 is an illustration showing the example of the dicing method, following toFIG. 2 ; -
FIG. 6 is an illustration showing the example of the dicing method, following toFIG. 3 ; -
FIG. 7 is an illustration showing the example of the dicing method, following toFIG. 3 ; -
FIG. 8 is an illustration showing the example of the dicing method, following toFIG. 6 ; -
FIG. 9 is a schematic plan view showing a configuration example of one semiconductor chip after diced; -
FIG. 10 is a sectional view taken on line 10-10 ofFIG. 9 ; -
FIG. 11 is an illustration showing the state of propagation of a crack that has reached a trench; and -
FIG. 12 is a sectional view showing the state of a semiconductor device after packaged. - Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments. In the embodiments, “an upper direction” or “a lower direction” refers to a relative direction when a direction of a surface perpendicular to a semiconductor substrate on which semiconductor elements are provided is assumed as “an upper direction”. Therefore, the term “upper direction” or “lower direction” occasionally differs from an upper direction or a lower direction based on a gravitational acceleration direction. In the present specification and the drawings, elements identical to those described in the foregoing drawings are denoted by like reference characters and detailed explanations thereof are omitted as appropriate.
- A semiconductor device according to the present embedment includes a substrate having a first region provided with a semiconductor element and a second region provided from the first region to an end. A material film is provided above the first and second regions. A first metal film is provided on the material film in the second region or on the material film between the first region and the second region. A trench, which caves in toward the substrate from a surface of the material film in the first region and from a surface of the material film under the first metal film, is provided in the material film between the first metal film and the first region.
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FIG. 1 is a schematic plan view showing an example of a semiconductor wafer in accordance with a first embodiment. A semiconductor wafer W is provided with a plurality of device regions Rdev and a plurality of dicing regions Rdic. The device regions Rdev and the dicing regions Rdic are regions on the front surface of the semiconductor wafer W. - In each device region Rdev as a first region, a semiconductor element (not shown), such as a transistor and a memory cell array, is provided. The semiconductor element is formed on the semiconductor wafer W through a semiconductor manufacturing process. The semiconductor element may, for example, be a memory cell array of NAND flash memories or its control circuit. The memory cell array may, for example, be a three-dimensional memory cell array of three-dimensionally arranged memory cells. It is a matter of course that the present embodiment is also applicable to LSI (Large Scale Integration) other than the semiconductor memories.
- Each dicing region Rdic, as a second region, is a line-like region between device regions Rdev adjacent to each other, which is a region to be cut by dicing. The dicing region Rdic is also referred to as a dicing line. According to the present embodiment, a laser beam is emitted to a
substrate 10 to form a modified portion LM (seeFIG. 4 ) inside thesubstrate 10 in the dicing region Rdic, and then the semiconductor wafer W is cleaved at the modified portion LM as a starting point. In this way, the semiconductor wafer W is chipped per device region Rdev into semiconductor chips. Silicon is an example of semiconductor, however, another semiconductor, other than silicon, may also be used. - A dicing method for the semiconductor wafer W will be explained next. In the present embodiment, the semiconductor wafer W is cut with a laser dicing method using a laser beam. As for the laser beam, for example, a through-transmission laser in the infrared region is used. Instead of the laser dicing method, another dicing method, such as a blade dicing method, may be used.
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FIGS. 2 to 8 are illustrations showing an example of the dicing method according to the first embodiment. Semiconductor elements formed on the semiconductor wafer W are omitted in the illustrations. Amaterial film 20 formed above thesubstrate 10 and the semiconductor elements is schematically illustrated. The configuration of thematerial film 20 will be explained later with reference toFIG. 10 . - At first, as shown in
FIG. 2 , aprotective tape 110 for dicing is stuck on the front surface of the semiconductor wafer W. Theprotective tape 110 protects the semiconductor elements, thematerial film 20, etc. at the time of laser dicing. - Subsequently, the semiconductor wafer W and the
protective tape 110 are turned upside down, and, as shown inFIGS. 3 and 4 , using alaser oscillator 120, alaser beam 121 is emitted to the portions which correspond to the dicing regions Rdic from the rear surface of the semiconductor wafer W. In this way, as shown inFIG. 4 , a modified portion (amorphous layer or polysilicon layer) LM is formed inside the semiconductor wafer W. The modified portion LM is formed inside the semiconductor wafer W in each dicing region Rdic. -
FIG. 5 is a perspective view showing the state of emitting thelaser beam 121. Thelaser oscillator 120, while moving in a Y-direction as shown by an arrow A, emits thelaser beam 121 in the form of pulses. In this way, modified portions LM are formed intermittently in the Y-direction and formed roughly in parallel along the dicing region Rdic. Although being formed intermittently, the modified portions LM are connected in the Y-direction roughly in the form of a layer. The modified portions LM may be in the form of a single layer or a plurality of layers formed at different positions (heights) in a Z-direction. - Subsequently, as shown in
FIG. 6 , the rear surface of the semiconductor wafer W is polished by CMP (Chemical Mechanical Polishing). Being polished with a sharpeningstone 130, the semiconductor wafer W is thinned, and not only that, as shown inFIG. 7 , acleavage 131 spreads in the Z-direction from each modified portion LM due to vibration by polishing. The semiconductor wafer W is polished until the modified portions LM are removed. - Subsequently, the rear surface of the semiconductor wafer W is stuck on a
dicing tape 136 having an adhesive layer and then thedicing tape 136 is fixed with aring 135. Subsequently, as shown inFIG. 8 , the dicingtape 136 is pushed up with a push-upmember 140 to be pulled (expanded). In this way, together with the dicingtape 136, the semiconductor wafer W is pulled outwardly. At this time, the semiconductor wafer W is cleaved further along the modified portions LM, which are the starting points, (in other words, along the dicing lines), to be chipped into a plurality of semiconductor chips. - In the above example, the rear surface of the semiconductor wafer W is polished after being irradiated with a laser beam. However, the semiconductor wafer W may be irradiated with the laser beam after being polished at its rear surface. Moreover, in the present embodiment, although the laser dicing method is explained, another dicing method, such as a blade dicing method, may be used. The blade dicing method vibrates the semiconductor wafer W much more than the laser dicing method, to cut the
material film 20, thesubstrate 10, etc. directly with a blade, so that a crack CR shown inFIG. 10 is easily generated. Therefore, the effects of the present embodiment will be exhibited further by applying the present embodiment to the blade dicing method. - Thereafter, each semiconductor chip is picked up and mounted on a resin substrate (not shown). The semiconductor chip is bonded to the resin substrate by metal wiring and sealed with resin, thereby a semiconductor package is completed.
-
FIG. 9 is a schematic plan view showing a configuration example of onesemiconductor chip 1 after diced. Thesemiconductor chip 1 has a device region Rdev and a dicing region Rdic on its front surface. The device region Rdev, as a first region, is a region in which a semiconductor element is provided, on the front surface of the substrate 10 (seeFIG. 10 ). The dicing region Rdic is a region from the device region Rdev to an end of thesubstrate 10, on the front surface of thesubstrate 10, which is a region to be used for cutting in a dicing process. The dicing region Rdic is provided with afirst metal film 40 e and a protrudingportion 70. Thefirst metal film 40 e and the protrudingportion 70 are arranged at a position apart from the device region Rdev so as to surround the device region Rdev. Thefirst metal film 40 e and the protrudingportion 70 will be explained later in detail with reference toFIG. 10 . The dicing region Rdic, thefirst metal film 40 e, and the protrudingportion 70 may be completely removed in the dicing process, however, in general, at least partially remain in the periphery of the device region Rdev as shown inFIG. 9 . -
FIG. 10 is a sectional view taken on line 10-10 ofFIG. 9 . Thesemiconductor chip 1, as a semiconductor device, is provided with asubstrate 10,element isolation portions 12, ametal compound layer 15, asemiconductor element 17, amaterial film 20,crack stoppers 30,metal films 40, and apassivation film 50. - The
substrate 10 is, as described above, a semiconductor substrate such as a silicon substrate. Thesemiconductor element 17 provided in the device region Rdev of thesubstrate 10 may, for example, be a memory cell array or a CMOS circuit. - The
metal compound layer 15 is provided on thesubstrate 10, used for a gate electrode (not shown) of a transistor in the device region Rdev. As for themetal compound layer 15, a conductive metal compound, such as tungsten silicide (WSi) or tungsten nitride (WN), is used. Although remaining in the dicing region Rdic, themetal compound layer 15 is not provided as a component of thesemiconductor element 17. In the dicing region Rdic, themetal compound layer 15 is provided for maintaining the flatness of the front surface of thesubstrate 10 and for easy positioning in a lithography process. - The
element isolation portions 12 define active areas in the device region Rdev, provided for electrically isolating the active areas from each other. Theelement isolation portions 12 are also referred to as STI (Shallow Trench Isolation). Theelement isolation portions 12 are also provided between the device region Rdev and the dicing region Rdic. For example, among theelement isolation portions 12, anelement isolation portion 12 e nearest to the perimeter of thesemiconductor chip 1 is provided between the device region Rdev and the dicing region Rdic and provided so as to divide themetal compound layer 15. Although being provided between the device region Rdev and the dicing region Rdic, theelement isolation portion 12 e may be provided in the dicing region Rdic. Moreover, in the planar layout, theelement isolation portion 12 e is provided so as to surround the entire periphery of the device region Rdev along the perimeter of thesemiconductor chip 1 ofFIG. 9 (along the dicing region Rdic). Theelement isolation portion 12 e has a function to restrict the propagation of a crack CR or change the direction of the crack CR when the crack CR is generated between themetal compound layer 15 and thematerial film 20. Theelement isolation portion 12 e may also have a function to separate a test pattern present in the dicing region Rdic. - The
material film 20 is provided on the device region Rdev and also on the dicing region Rdic. When thesemiconductor element 17 is a memory cell array, thematerial film 20 in the dicing region Rdic is, for example, a stacked film (also referred to as an ONON film, hereinafter) of a plurality of silicon oxide films (SiO2) and a plurality of silicon nitride films (SiN) alternately stacked, or a stacked film (also referred to as an OWOW film, hereinafter) of a plurality of silicon oxide films (SiO2) and a plurality of second metal films (for example, tungsten films (W)) alternately stacked. The ONON film is a stacked film to be used in a memory cell array forming process. In the memory cell array forming process, the silicon nitride films of the ONON film are replaced with the second metal films (for example, tungsten films), so that the ONON film changes to be the OWOW film. The OWOW film is used as one component of the memory cell array. In this case, the second metal films function as word lines of the memory cell array. Thematerial film 20 may either be the ONON film or the OWOW film. - When the
semiconductor element 17 is a CMOS transistor of an LSI, thematerial film 20 in the dicing region Rdic may be an interlayer insulating film to cover the CMOS transistor. For example, thematerial film 20 in the dicing region Rdic may be a single-layer film of a silicon oxide film such as a TEOS film. - The
crack stoppers 30 are provided inside thematerial film 20 on the perimeter of the device region Rdev and extend in the Z-direction toward thesubstrate 10 from the surface of thematerial film 20. Thecrack stoppers 30 have, for example, a metal such as tungsten embedded therein. Thecrack stoppers 30 are provided so as to surround the periphery of the device region Rdev. Accordingly, thecrack stoppers 30 restrict the propagation of the crack CR into the device region Rdev. Thecrack stoppers 30 are also referred to as a guard ring. - The
metal films 40 are, for example, used as a bonding-pad forming material. As for themetal films 40, a conductive metal such as tungsten is used. Among themetal films 40, thefirst metal film 40 e nearest to the perimeter of thesemiconductor chip 1 is provided on thematerial film 20 in the dicing region Rdic or on thematerial film 20 between the device region Rdev and the dicing region Rdic, provided at a position apart from the device region Rdev. Thefirst metal film 40 e functions as a mask in an etching process to expose bonding pads and is provided for forming a trench TR. In the etching process, the protrudingportion 70 made of thematerial film 20 is formed under thefirst metal film 40 e. In the same manner as thefirst metal film 40 e, the protrudingportion 70 is also disposed so as to surround the device region Rdev at a position apart from the device region Rdev. Accordingly, the trench TR is formed between the device region Rdev and the protrudingportion 70. - The
passivation film 50 covers thematerial film 20 in the device region Rdev and protects thesemiconductor element 17, thematerial film 20, etc. Thepassivation film 50 is, for example, polyimide. - The trench TR is provided between the device region Rdev and the dicing region Rdic, and provided near to the device region Rdev than the
element isolation portions 12. The trench TR caves in toward thesubstrate 10 from the surface of thematerial film 20 in the device region Rdev and also from the surface of thematerial film 20 under thefirst metal film 40 e. In other words, the trench TR caves in to a position lower than the surface of thematerial film 20 around the trench TR. Thematerial film 20 has been etched in the same manner as the trench TR in the dicing region Rdic outside thefirst metal film 40 e. However, thematerial film 20 may not have been etched in the dicing region Rdic outside thefirst metal film 40 e. - It is preferable for the trench TR to be provided to surround the entire periphery of the device region Rdev. However, the trench TR may be partially provided at a location where the
material film 20 is easily peeled off and the crack CR is easily generated. Moreover, the trench TR may have a flat, curved or pointed bottom. - When the
metal compound layer 15 is provided between thesubstrate 10 and thematerial film 20 in the dicing region Rdic, thematerial film 20 is easily peeled off from themetal compound layer 15 at an end of thesemiconductor chip 1, due to an impact in the dicing process, stress in TCT (Thermal Cycle Test), etc. When thematerial film 20 is peeled off from themetal compound layer 15, the crack CR propagates between thematerial film 20 and themetal compound layer 15, toward theelement isolation portion 12 e. In other words, the crack CR propagates toward the device region Rdev from the end of thesemiconductor chip 1. - Since the
element isolation portion 12 e divides themetal compound layer 15, the propagation of the crack CR may stop when it reaches theelement isolation portion 12 e. However, since thematerial film 20 is thinner than thesubstrate 10 and vulnerable to mechanical stress, when the crack CR propagates further, it propagates inside thematerial film 20. In other words, the crack CR tries to propagate toward the upper surface of theelement isolation portion 12 e (in the Z-direction apart from the substrate 10). Therefore, force directed toward the device region Rdev from the end of thesemiconductor chip 1 and force directed upward (in the Z-direction) from theelement isolation portion 12 e are applied to thematerial film 20. Accordingly, the crack CR propagates inside thematerial film 20 diagonally upward from theelement isolation portion 12 e toward the device region Rdev. - The trench TR is provided on the surface of the
material film 20 between the device region Rdev and the dicing region Rdic, and provided nearer to the device region Rdev than theelement isolation portion 12 e. Therefore, the trench TR is positioned above theelement isolation portion 12 e in a diagonally upward direction, so that the crack CR can easily propagate toward the trench TR and, when the crack CR reaches the trench TR, the propagation completes. Accordingly, the trench TR has a function to induce the crack CR and terminate the crack CR with no propagation to the device region Rdev. - In order for the trench TR to effectively induce the crack CR, the trench TR is preferably a cavity with no another material being embedded therein. Specifically, the trench TR is preferably a cavity from the moment of formation of the trench TR to the moment of installation of the semiconductor chip 1 (for example, in the dicing and TCT processes). It is not problematic that a thin film is attached to the inner surface of the trench TR. In the TCT process, the trench TR may be filled with sealing resin. In this case, although a crack induction effect of the trench TR is reduced a little bit, it is still effective.
-
FIG. 11 is an illustration showing the state of propagation of the crack CR that has reached the trench TR. When the crack CR has spread from the end of thesemiconductor chip 1 and reached theelement isolation portion 12 e, the crack CR propagates in a diagonally upward direction toward the trench TR. When the crack CR has reached the trench TR, it does not propagate anymore. Thematerial film 20 at the end of thesemiconductor chip 1 may be brown off to be removed without remaining there. However, since thematerial film 20 is not required in the dicing region Rdic, there is no problem even if it is removed. Of course it is not problematic even if thematerial film 20 remains at the end of thesemiconductor chip 1. - The position of the trench TR that easily induces the crack CR depends on the conditions such as the film thickness of the
material film 20, and hence it cannot be said definitely. However, for example, in the case where thematerial film 20 is an ONON film having a film thickness of about 5 μm to 15 μm, it is preferable, in the planer layout viewed from above the front surface of thesubstrate 10, to provide the trench TR at a position near to the device region Rdev by about 5 μm from theelement isolation portion 12 e. - In order to dispose the trench TR nearer to the device region Rdev than the
element isolation portion 12 e, thefirst metal film 40 e may be disposed directly above theelement isolation portion 12 e. In other words, in the planer layout viewed from above the front surface of thesubstrate 10, thefirst metal film 40 e may be disposed at roughly the same position as theelement isolation portion 12 e. Accordingly, the trench TR is disposed nearer to the device region Rdev than theelement isolation portion 12 e in a self-alignment manner. -
FIG. 12 is a sectional view showing the state of a semiconductor device after packaged. After being diced, thesemiconductor chip 1 is mounted on a substrate (not shown) and then sealed withresin 60 as a resin portion. Theresin 60 is provided above both of the dicing region Rdic and the device region Rdev. Moreover, as shown inFIG. 12 , in the case where thefirst metal film 40 e and the protrudingportion 70 are still present, theresin 60 covers thematerial film 20, thefirst metal film 40 e, the protrudingportion 70, and thepassivation film 50, and has a contact with these components. The trench TR is filled with theresin 60. - As described above, according to the present embodiment, the trench TR is provided on the surface of the
material film 20 between the device region Rdev and the dicing region Rdic, and provided nearer to the device region Rdev than theelement isolation portions 12. Accordingly, the trench TR can induce the crack CR that is generated between thematerial film 20 and themetal compound layer 15, and terminate the propagation of the crack CR. In other words, the trench TR can restrict the propagation of the peeling-off of thematerial film 20 to the device region Rdev. - While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Claims (20)
1. A semiconductor device comprising:
a substrate having a first region provided with a semiconductor element and a second region provided from the first region to an end;
a material film provided above the first and second regions; and
a first metal film provided on the material film in the second region or on the material film between the first region and the second region,
wherein a trench, which caves in toward the substrate from a surface of the material film in the first region and from a surface of the material film under the first metal film, is provided in the material film between the first metal film and the first region.
2. The semiconductor device according to claim 1 further comprising an element isolation portion provided on a surface of the substrate between the first region and the second region,
wherein the trench is provided nearer to the first region than the element isolation portion.
3. The semiconductor device according to claim 2 , wherein the first metal film is provided directly above the element isolation portion.
4. The semiconductor device according to claim 2 , wherein the material film has a crack that extends from the element isolation portion to the trench.
5. The semiconductor device according to claim 3 , wherein the material film has a crack that extends from the element isolation portion to the trench.
6. The semiconductor device according to claim 1 further comprising a crack stopper provided in the material film at a perimeter of the first region and extending toward the substrate from a surface of the material film.
7. The semiconductor device according to claim 2 further comprising a crack stopper provided in the material film at a perimeter of the first region and extending toward the substrate from a surface of the material film.
8. The semiconductor device according to claim 3 further comprising a crack stopper provided in the material film at a perimeter of the first region and extending toward the substrate from a surface of the material film.
9. The semiconductor device according to claim 4 further comprising a crack stopper provided in the material film at a perimeter of the first region and extending toward the substrate from a surface of the material film.
10. The semiconductor device according to claim 1 , wherein the trench is provided so as to surround an entire periphery of the first region.
11. The semiconductor device according to claim 1 , wherein the trench is provided at part of a periphery of the first region.
12. The semiconductor device according to claim 2 further comprising a metal compound layer provided between the substrate and the material film,
wherein a crack is present between the material film and the metal compound layer from an end of the material film to the element isolation portion, the crack extending from the element isolation portion to the trench.
13. The semiconductor device according to claim 12 , wherein the material film is a stacked film of a plurality of silicon oxide films and a plurality of silicon nitride films alternately stacked or of the plurality of silicon oxide films and a plurality of second metal films alternately stacked, or is a single layer of an insulating film,
wherein the metal compound layer is tungsten silicide (WSi) or tungsten nitride (WN).
14. The semiconductor device according to claim 12 , wherein the element isolation portion divides the metal compound layer.
15. The semiconductor device according to claim 1 , wherein a surface of the material film in the second region is located closer to the substrate than the surface of the material film under the first metal film, and
the first metal film is not provided on the surface of the material film in the second region.
16. The semiconductor device according to claim 2 , wherein a surface of the material film in the second region is located closer to the substrate than the surface of the material film under the first metal film, and
the first metal film is not provided on the surface of the material film in the second region.
17. The semiconductor device according to claim 3 , wherein a surface of the material film in the second region is located closer to the substrate than the surface of the material film under the first metal film, and
the first metal film is not provided on the surface of the material film in the second region.
18. The semiconductor device according to claim 4 , wherein a surface of the material film in the second region is located closer to the substrate than the surface of the material film under the first metal film, and
the first metal film is not provided on the surface of the material film in the second region.
19. The semiconductor device according to claim 1 , wherein the trench is not filled before installation of the semiconductor device.
20. The semiconductor device according to claim 1 further comprising a resin provided above the first and second regions, the resin having a contact with the first metal film and being embedded in the trench.
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US17/513,212 US11610852B2 (en) | 2018-08-29 | 2021-10-28 | Semiconductor device |
US18/171,954 US20230197641A1 (en) | 2018-08-29 | 2023-02-21 | Semiconductor device |
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Citations (2)
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US20050026397A1 (en) * | 2003-07-28 | 2005-02-03 | International Business Machines Corporation | Crack stop for low k dielectrics |
US20090243044A1 (en) * | 2008-03-28 | 2009-10-01 | Nec Electronics Corporation | Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor device |
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US5789302A (en) | 1997-03-24 | 1998-08-04 | Siemens Aktiengesellschaft | Crack stops |
US6492247B1 (en) | 2000-11-21 | 2002-12-10 | International Business Machines Corporation | Method for eliminating crack damage induced by delaminating gate conductor interfaces in integrated circuits |
JP4489345B2 (en) * | 2002-12-13 | 2010-06-23 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
JP4813778B2 (en) * | 2004-06-30 | 2011-11-09 | 富士通セミコンダクター株式会社 | Semiconductor device |
JP4869664B2 (en) * | 2005-08-26 | 2012-02-08 | 本田技研工業株式会社 | Manufacturing method of semiconductor device |
US8847400B2 (en) * | 2010-09-15 | 2014-09-30 | Ps4 Luxco S.A.R.L. | Semiconductor device, method for manufacturing the same, and data processing device |
US8970008B2 (en) | 2013-03-14 | 2015-03-03 | Infineon Technologies Ag | Wafer and integrated circuit chip having a crack stop structure |
JP6292049B2 (en) * | 2013-09-02 | 2018-03-14 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
US10811334B2 (en) * | 2016-11-26 | 2020-10-20 | Texas Instruments Incorporated | Integrated circuit nanoparticle thermal routing structure in interconnect region |
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2019
- 2019-01-23 US US16/254,646 patent/US20200075508A1/en not_active Abandoned
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US20050026397A1 (en) * | 2003-07-28 | 2005-02-03 | International Business Machines Corporation | Crack stop for low k dielectrics |
US20090243044A1 (en) * | 2008-03-28 | 2009-10-01 | Nec Electronics Corporation | Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor device |
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