US20190363039A1

US20190363039A1 - Semiconductor package and manufacturing process

Info

Publication number: US20190363039A1
Application number: US15/986,636
Authority: US
Inventors: Bernd Karl Appelt; You-Lung Yen; Kay Stefan ESSIG
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2018-05-22
Filing date: 2018-05-22
Publication date: 2019-11-28
Also published as: US20210225746A1; US11574856B2; CN110518001B; CN110518001A

Abstract

A semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.

Description

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to a semiconductor package and a manufacturing method, and to a semiconductor package including a substrate having a capture land and a method for manufacturing the substrate and the semiconductor package.

2. Description of the Related Art

Castellated packages have been used in the auto-vehicle (ATV) field. The castellated packages historically have castellated side surfaces based on sawn copper (Cu) plated through holes (PTHs). During assembly to the motherboard, solder wicks up the sidewalls of the PTHs and forms a solder fillet which can be inspected for joint quality. That is, the side surfaces of the castellated package are solder wettable flanks that can be used for inspection to insure the joint quality between the castellated packages and the motherboard. However, the castellated packages are typically not over molded because the molding compound would penetrate the PTHs and prevent the solder from wetting onto the sidewalls of the PTHs. In addition, during a saw singulation process of the castellated packages, the Cu layer on the sidewall of the PTH may be ripped from the substrate base (e.g., an interposer). This results in defective castellation PTHs in the opposing singulated packages. That is, extra Cu pieces remain on the sidewall of one PTH-half of a castellated package, and Cu-voids form on the sidewall of the opposing PTH-halves of the opposing castellated package.

SUMMARY

In some embodiments, a semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.
In some embodiments, a semiconductor package includes a substrate, a semiconductor chip and an encapsulant. The substrate includes a base material, an indentation structure, a capture land and an interconnection structure. The base material has a top surface and an outer side surface connected to the top surface. The indentation structure is recessed from the outer side surface of the base material, and has a first width. The capture land is disposed in or on the base material and is disposed adjacent to the indentation structure. The capture land has a third width that is greater than the first width of the indentation structure. The interconnection structure is disposed in the indentation structure and connected to the capture land. The semiconductor chip is disposed adjacent to the top surface of the base material. The encapsulant covers the semiconductor chip and the substrate.
In some embodiments, a manufacturing process includes: (a) providing a substrate, wherein the substrate includes a base material and a capture land disposed in or on the base material, and the capture land extends across a singulation line of the substrate; and (b) forming a recess structure at the singulation line, wherein a position of the recess structure corresponds to a position of the capture land.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of some embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that various structures may not be drawn to scale, and dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

FIG. 2 illustrates an enlarged view of an area “A” shown in FIG. 1, wherein an interconnection structure is omitted for the purpose of the clear explanation.

FIG. 3 illustrates a perspective view of a portion of the semiconductor package of FIG. 1.

FIG. 4 illustrates a top view of the portion of the semiconductor package of FIG. 3.

FIG. 5 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

FIG. 6 illustrates a perspective view of a portion of the semiconductor package of FIG. 5.

FIG. 7 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

FIG. 8 illustrates a perspective view of a portion of the semiconductor package of FIG. 7.

FIG. 9 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

FIG. 10 illustrates a perspective view of a portion of the semiconductor package of FIG. 9.

FIG. 11 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

FIG. 12 illustrates a perspective view of a portion of the semiconductor package of FIG. 11.

FIG. 13 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

FIG. 14 illustrates a perspective view of a portion of the semiconductor package of FIG. 13.

FIG. 15 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

FIG. 16 illustrates a cross-sectional view of an assembly of the semiconductor package and a motherboard according to some embodiments of the present disclosure.

FIG. 17 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 18 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 19 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 20 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 21 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 22 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 23 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 24 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 25 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 26 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 27 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 28 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 29 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 30 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 31 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 32 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 33 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 34 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 35 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 36 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 37 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 38 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 39 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 40 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 41 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 42 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

FIG. 43 illustrates one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

DETAILED DESCRIPTION

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
At least some embodiments of the present disclosure provide for a semiconductor package including a substrate having a capture land and an interconnection structure, wherein an outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. At least some embodiments of the present disclosure provide for techniques for manufacturing the substrate and the semiconductor package.
In a comparative castellated package, a plurality of package units are mounted to a substrate base (e.g., an interposer) individually. Since each of the package units may represent different assembly process so that the manufacturing process is complicated. Besides, each comparative castellated package may include the substrate base (e.g., the interposer) on which the package unit is mounted to, so that the substrate base (e.g., the interposer) is another additional cost. Further, another issue is that the comparative castellated package are typically not over molded because the molding compound would penetrate the PTHs and prevent the solder from wetting onto the sidewalls of the PTHs. Thus, when the comparative castellated package is attached to the motherboard by using, for example, surface mounting technique (SMT), the yield rate and the soldering reliability of the surface mounting technique (SMT) are low.
The present disclosure provides for a semiconductor package including a substrate having a capture land and an interconnection structure to address at least the above concerns. In some embodiments, the capture land is disposed to cover a hole of the substrate. The interconnection structure may be formed on the sidewall of the hole, and then be cut. The capture land can prevent the molding compound from entering the hole.
FIG. 1 illustrates a cross-sectional view of a semiconductor package 1 according to some embodiments of the present disclosure. FIG. 2 illustrates an enlarged view of an area “A” shown in FIG. 1, wherein an interconnection structure is omitted for the purpose of the clear explanation. The semiconductor package 1 includes a substrate 2, at least one semiconductor chip 14, at least one passive device 16 and an encapsulant 18.
The substrate 2 may be a package substrate or an interposer used for carrying the semiconductor chip 14 and the passive device 16, and may include a base material 20, a capture land 30, an interconnection structure 32, an indentation structure 4, a first protection layer 28 and a second protection layer 29. The base material 20 has a bottom surface 201, a top surface 202, an outer side surface 203 (FIG. 3) and an inner lateral surface 204. The top surface 202 is opposite to the bottom surface 201. The outer side surface 203 extends between the bottom surface 201 and the top surface 202, that is, the outer side surface 203 may be connected to the top surface 202 and/or the bottom surface 201. The inner lateral surface 204 is recessed form the outer side surface 203. As shown in FIG. 1, the inner lateral surface 204 extends between the bottom surface 201 and the top surface 202, that is, the inner lateral surface 204 is a curved surface formed from a through hole extending through the base material 20, and is connected to the top surface 202 and the bottom surface 201. However, in another embodiment, the inner lateral surface 204 may be formed from a blind hole that does not extend through the base material 20, and may be connected to the bottom surface 201. That is, the inner lateral surface 204 may not be connected to the top surface 202. In some embodiments, the inner lateral surface 204 of the base material 20 is inclined with respect to the top surface 202 of the base material 20. That is, the inner lateral surface 204 is not perpendicular to the top surface 202 and the bottom surface 201 of the base material 20. As shown in FIG. 1, an inclination angle between the inner lateral surface 204 and the top surface 202 of the base material 20 is less than 90 degrees, and an inclination angle between the inner lateral surface 204 and the bottom surface 201 of the base material 20 is greater than 90 degrees.
The base material 20 includes a first circuitry structure 21, a first dielectric structure 22, a first via structure 221, a second circuitry structure 23, a second dielectric structure 24, a second via structure 241, a third circuitry structure 25, a third dielectric structure 26, a third via structure 261 and a fourth circuitry structure 27. Each of the first dielectric structure 22, the second dielectric structure 24 and the third dielectric structure 26 may be a dielectric layer or a passivation layer and may include, or be formed from, a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material such as a polyamide (PA), an Ajinomoto build-up film (ABF), a bismaleimide-triazine (BT), a polyimide (PI), epoxy or polybenzoxazole (PBO), or a combination of two or more thereof. In one or more embodiments, each of the first dielectric structure 22, the second dielectric structure 24 and the third dielectric structure 26 may include, or be formed from a dry film type material that includes a resin and a plurality of fillers. In another embodiment, each of the first dielectric structure 22, the second dielectric structure 24 and the third dielectric structure 26 may include, or be formed from a liquid type material that includes a homogeneous resin without fillers. In some embodiments, the material of each of the first dielectric structure 22, the second dielectric structure 24 and the third dielectric structure 26 may include inorganic material (e.g., SiO_x, SiN_x, TaO_x), a glass, glass fabric, glass fibers, silicon, or a ceramic.
The first circuitry structure 21 may be a patterned circuit layer. As shown in FIG. 1, the first circuitry structure 21 may be a redistribution layer (RDL), and is disposed on the bottom surface of the first dielectric structure 22 (e.g., the bottom surface 201 of the base material 20). For example, the first circuitry structure 21 may include a first metal layer 211 and a second metal layer 212 disposed in that order on the first dielectric structure 22. The first metal layer 211 may be a seed layer including, for example, titanium and/or copper, another metal, or an alloy, and may be formed or disposed by sputtering. Alternatively, the first metal layer 211 may be a portion of a copper foil. The second metal layer 212 may include, for example, copper, or another metal or combination of metals, and may be formed or disposed by electroplating. In some embodiments, the first circuitry structure 21 may include a plurality of conductive traces and/or a plurality of bonding pads.
The second circuitry structure 23 may be a patterned circuit layer. As shown in FIG. 1, the second circuitry structure 23 may be a redistribution layer (RDL), and is disposed on the top surface of the first dielectric structure 22. The first via structure 221 is disposed in the first dielectric structure 22, and is electrically connected to the first circuitry structure 21 and the second circuitry structure 23. In some embodiments, the first via structure 221 and the second metal layer 212 of the first circuitry structure 21 are formed integrally and concurrently. However, in another embodiment, the first via structure 221 and the second circuitry structure 23 are formed integrally and concurrently.
The second dielectric structure 24 covers and contacts the second circuitry structure 23 and the top surface of the first dielectric structure 22. The third circuitry structure 25 may be a patterned circuit layer. As shown in FIG. 1, the third circuitry structure 25 may be a redistribution layer (RDL), and is disposed on the top surface of the second dielectric structure 24. The second via structure 241 is disposed in the second dielectric structure 24, and is electrically connected to the second circuitry structure 23 and the third circuitry structure 25. In some embodiments, the second via structure 241 and the third circuitry structure 25 are formed integrally and concurrently. However, in another embodiment, the second via structure 241 and the second circuitry structure 23 are formed integrally and concurrently.
The third dielectric structure 26 covers and contacts the third circuitry structure 25 and the top surface of the second dielectric structure 24. The fourth circuitry structure 27 may be a patterned circuit layer. As shown in FIG. 1, the fourth circuitry structure 27 may be a redistribution layer (RDL), and is disposed on the top surface of the third dielectric structure 26. For example, the fourth circuitry structure 27 may include a first metal layer 271 and a second metal layer 272 disposed in that order on the third dielectric structure 26. The first metal layer 271 may be a seed layer including, for example, titanium and/or copper, another metal, or an alloy, and may be formed or disposed by sputtering. Alternatively, the first metal layer 271 may be a portion of a copper foil. The second metal layer 272 may include, for example, copper, or another metal or combination of metals, and may be formed or disposed by electroplating. In some embodiments, the fourth circuitry structure 27 may include a plurality of conductive traces and/or a plurality of bonding pads. In one or more embodiments, a line width/line space (L/S) of the fourth circuitry structure 27 may be equal to or less than about 3 micrometers (m)/about 3 m, equal to or less than about 2 m/about 2 μm (such as, for example, about 1.8 μm/about 1.8 μm or less, about 1.6 μm/about 1.6 μm or less, or about 1.4 μm/about 1.4 μm or less), equal to or less than about 1 μm/about 1 μm, or equal to or less than about 0.5 μm/about 0.5 μm. An L/S of each of the first circuitry structure 21, the second circuitry structure 23 and the third circuitry structure 25 may be greater than the L/S of the fourth circuitry structure 27.
The third via structure 261 is disposed in the third dielectric structure 26, and is electrically connected to the third circuitry structure 25 and the fourth circuitry structure 27. In some embodiments, the third via structure 261 and the second metal layer 272 of the fourth circuitry structure 27 are formed integrally and concurrently. However, in another embodiment, the third via structure 261 and the third circuitry structure 25 are formed integrally and concurrently.
The first protection layer 28 covers and contacts the bottom surface of the first dielectric structure 22 and at least a portion of the first circuitry structure 21. The first protection layer 28 may define at least one opening to expose a portion of the first circuitry structure 21. The first protection layer 28 may include a solder resist material, such as, for example, epoxy acrylate, benzocyclobutene (BCB) or polyimide. The second protection layer 29 covers and contacts the top surface of the third dielectric structure 26 and at least a portion of the fourth circuitry structure 27. The second protection layer 29 may define at least one opening to expose a portion of the fourth circuitry structure 27. The second protection layer 29 may include a solder resist material, such as, for example, epoxy, acrylate, benzocyclobutene (BCB) or polyimide.
The capture land 30 is disposed in or on the base material 20, and has an outer side surface 303 (e.g., a periphery surface at the exposed end) and a bottom surface 304. In the embodiment illustrated in FIG. 1, the capture land 30 is disposed on the base material 20 and covers a space defined by the inner lateral surface 204 of the base material 20. Thus, a portion of the capture land 30 may cover and contact the top surface 202 of the base material 20. In some embodiments, the capture land 30 is a via stop structure. For example, the via stop structure may be a laser drilling stop structure during a laser drilling process or an etching stop structure during an etching process. In one or more embodiments, the capture land 30 may include a first metal layer 301 and a second metal layer 302 disposed in that order on the third dielectric structure 26. The first metal layer 301 may be a seed layer including, for example, titanium and/or copper, another metal, or an alloy, and may be formed or disposed by sputtering. Alternatively, the first metal layer 301 may be a portion of a copper foil. The second metal layer 302 may include, for example, copper, or another metal or combination of metals, and may be formed or disposed by electroplating. In some embodiments, the capture land 30 is a portion of the fourth circuitry structure 27, or the capture land 30 and the fourth circuitry structure 27 are formed integrally and concurrently. That is, the first metal layer 301 of the capture land 30 and the first metal layer 271 of the fourth circuitry structure 27 are the same layer, and are formed integrally and concurrently. In addition, the second metal layer 302 of the capture land 30 and the second metal layer 272 of the fourth circuitry structure 27 are the same layer, and are formed integrally and concurrently.
Referring to FIG. 2, the indentation structure 4 is the space defined by the inner lateral surface 204 of the base material 20 and the bottom surface 304 of the capture land 30. That is, the inner lateral surface 204 of the base material 20 is the sidewall of the indentation structure 4, and the top of the indentation structure 4 is covered by the capture land 30. The indentation structure 4 is recessed from the outer side surface 203 of the base material 20, and the capture land 30 is disposed adjacent to the indentation structure 4. In some embodiments, the indentation structure 4 includes a first portion (e.g., top portion) 41 and a second portion (e.g., bottom portion) 42. The first portion 41 is disposed adjacent to the capture land 30 and corresponds to the top point P₁of the inner lateral surface 204. The second portion 42 is disposed away from the capture land 30 and corresponds to the bottom point P₂of the inner lateral surface 204. A second width W₂of the second portion 42 is greater than a first width W₁of the first portion 41 (e.g., may be about 1.1 or more times greater, about 1.3 or more times greater, about 1.5 or more times greater, or about 1.7 or more times greater). That is, the indentation structure 4 is tapered from the second portion (bottom portion) 42 to the first portion (top portion) 41. This is because that the inner lateral surface 204 of the base material 20 is formed from a hole that is formed by laser drilling. In addition, the capture land 30 has a third width W₃that is greater than the first width W₁of the first portion 41 of the indentation structure 4 (e.g., may be about 1.3 or more times greater, about 1.5 or more times greater, about 1.7 or more times greater, or about 2.0 or more times greater). The third width W₃of the capture land 30 may be greater than or less than the second width W₂of the second portion 42 of the indentation structure 4.
Referring to FIG. 1, the interconnection structure 32 is disposed along and on the inner lateral surface 204 of the base material 20 in the indentation structure 4, that is, at least a portion of the interconnection structure 32 is disposed within the indentation structure 4. A material of the interconnection structure 32 may include copper, and the interconnection structure 32 may be formed by electroplating. As shown in FIG. 1, the interconnection structure 32 includes a first end 321 and a second end 322. The first end 321 is disposed on and contacts the capture land 30, so that the interconnection structure 32 is connected to the capture land 30. The first end 321 of the interconnection structure 32 has an outer side surface 323 (e.g., an exposed periphery surface). The second end 322 extends to the bottom surface 201 of the base material 20. In some embodiments, the second end 322 is a portion of the first circuitry structure 21, That is, the second end 322 of the interconnection structure 32 includes two metal layers that are the same as the first circuitry structure 21. In some embodiments, the interconnection structure 32 and the second metal layer 212 of the first circuitry structure 21 are the same layer, and are formed integrally and concurrently. As shown in FIG. 1, the outer side surface 323 of the interconnection structure 32 is substantially coplanar with the outer side surface 303 of the capture land 30 since they are formed concurrently after a cutting process.
The semiconductor chip 14 and the passive device 16 are disposed adjacent to the top surface 202 of the base material 20. As shown in FIG. 1, the semiconductor chip 14 and the passive device 16 are disposed on and electrically connected the fourth circuitry structure 27 on the top surface 202 of the base material 20. For example, the semiconductor chip 14 is bonded to the base material 20 by flip chip bonding, and the passive device 16 is bonded to the base material 20 by surface mounting technique (SMT).
The encapsulant 18, for example, molding compound, is disposed adjacent to the top surface 202 of the base material 20 to cover the semiconductor chip 14, the passive device 16 and the substrate 2. As shown in FIG. 1, the encapsulant 18 covers and contacts the semiconductor chip 14, the passive device 16, the second protection layer 29 and the capture land 30. The encapsulant 18 has an outer side surface 183 (e.g., a periphery lateral surface). The outer side surface 183 of the encapsulant 18 is substantially coplanar with the outer side surface 323 of the interconnection structure 32 and the outer side surface 303 of the capture land 30 since they are formed concurrently after a cutting process.
FIG. 3 illustrates a perspective view of a portion of the semiconductor package 1 of FIG. 1. The interconnection structure 32 defines a recess portion 5 recessed from the outer side surface 203 of the base material 20. That is, the interconnection structure 32 does not fill the indentation structure 4. The recess portion 5 is conformal with the indentation structure 4 or the inner lateral surface 204 of the base material 20. As shown in FIG. 3, an outer side surface 200 of the substrate 2 includes the outer side surface 203 of the base material 20, an outer side surface 283 of the first protection layer 28, an outer side surface 293 of the second protection layer 29, the outer side surface 323 of the interconnection structure 32 and the outer side surface 303 of the capture land 30 that are coplanar with each other since they are formed concurrently after a cutting process. In addition, an outer side surface 13 of the semiconductor package 1 includes the outer side surface 183 of the encapsulant 18 and the outer side surface 200 of the substrate 2 (e.g., including the outer side surface 203 of the base material 20, the outer side surface 283 of the first protection layer 28, the outer side surface 293 of the second protection layer 29, the outer side surface 323 of the interconnection structure 32 and the outer side surface 303 of the capture land 30) that are coplanar with each other since they are formed concurrently after a cutting process.
FIG. 4 illustrates a top view of the portion of the semiconductor package 1 of FIG. 3. The shapes of the capture land 30, first portion 41 of the indentation structure 4 and the second portion 42 of the indentation structure 4 may be semi-circular or semi-elliptical, and may be concentric with respect to each other. As shown in FIG. 4, the third width W₃of the capture land 30 is greater than the second width W₂of the second portion 42 of the indentation structure 4, and the second width W₂of the second portion 42 of the indentation structure 4 is greater than the first width W₁of the first portion 41 of the indentation structure 4.
In the illustrated embodiment of the semiconductor package 1 shown in FIG. 1 through FIG. 4, the semiconductor package 1 may be a castellated package, and can be over molded because the capture land 30 can prevent the encapsulant 18 from entering the indentation structure 4 or the recess portion 5 during a molding process. Thus, when the semiconductor package 1 is attached to a motherboard by using, for example, surface mounting technique (SMT), solder can wick up the interconnection structure 32 and form a solder fillet which can be inspected for joint quality, and the yield rate and the soldering reliability of the surface mounting technique (SMT) are improved. Further, during a singulation process, the interconnection structure 32 is covered by the capture land 30 and the encapsulant 18, thus the interconnection structure 32 will not be ripped from the base material 20. In addition, the semiconductor package 1 includes the substrate 2, thus, additional interposer is not necessary, and the cost of semiconductor package 1 can be reduced. In addition, the substrate 2 includes four metal layers (e.g., the first circuitry structure 21, the second circuitry structure 23, the third circuitry structure 25 and the fourth circuitry structure 27). However, in other embodiments, the substrate 2 may include any number of metal layers greater than two.
FIG. 5 illustrates a cross-sectional view of a semiconductor package 1 a according to some embodiments of the present disclosure. FIG. 6 illustrates a perspective view of a portion of the semiconductor package 1 a of FIG. 5. The semiconductor package 1 a is similar to the semiconductor package 1 shown in FIG. 1 through FIG. 4, except for the structure of the interconnection structure 32 a of the substrate 2 a. The interconnection structure 32 a of the substrate 2 a of the semiconductor package 1 a fills the indentation structure 4. Thus, the recess portion 5 of FIG. 3 will not occur. As shown in FIG. 5, the interconnection structure 32 a is tapered from its bottom end (corresponding to the second portion 42 of the indentation structure 4) to its top end (corresponding to the first portion 41 of the indentation structure 4). As shown in FIG. 6, an outer side surface 324 of the interconnection structure 32 a is substantially coplanar with the outer side surface 203 of the base material 20, the outer side surface 283 of the first protection layer 28, the outer side surface 293 of the second protection layer 29, the outer side surface 303 of the capture land 30 and the outer side surface 183 of the encapsulant 18 since they are formed concurrently after a cutting process.
FIG. 7 illustrates a cross-sectional view of a semiconductor package 1 b according to some embodiments of the present disclosure. FIG. 8 illustrates a perspective view of a portion of the semiconductor package 1 b of FIG. 7. The semiconductor package 1 b is similar to the semiconductor package 1 shown in FIG. 1 through FIG. 4, except for the structure of the substrate 2 b. The substrate 2 b includes a base material 20 b, and the base material 20 b includes a first sub-base material 20′ and a second sub-base material 20″. The first sub-base material 20′ includes the first circuitry structure 21, the first dielectric structure 22 and the first via structure 221, and has an inner lateral surface 204 a recessed from the outer side surface 203 of the base material 20 b. The second sub-base material 20″ includes the second circuitry structure 23, the second dielectric structure 24, the second via structure 241, the third circuitry structure 25, the third dielectric structure 26, the third via structure 261 and the fourth circuitry structure 27.
The capture land 30 a is disposed on the first dielectric structure 22 of the first sub-base material 20′, and is embedded in the second dielectric structure 24 of the second sub-base material 20″. The capture land 30 a has an outer side surface 303 a (e.g., a periphery surface at the exposed end) and a bottom surface 304 a. In the embodiment illustrated in FIG. 7, the capture land 30 a covers a space defined by the inner lateral surface 204 a of the first sub-base material 20′. In some embodiments, the capture land 30 a is a portion of the second circuitry structure 23, or the capture land 30 a and the second circuitry structure 23 are formed integrally and concurrently.
Referring to FIG. 7, the indentation structure 4 a is the space defined by the inner lateral surface 204 a of the first sub-base material 20′ and the bottom surface 304 a of the capture land 30 a. That is, the inner lateral surface 204 a of the first sub-base material 20′ is the sidewall of the indentation structure 4 a, and the top of the indentation structure 4 a is covered by the capture land 30 a. The indentation structure 4 a selectively extends through the first sub-base material 20′, and does not extend through the base material 20 b. The indentation structure 4 a is recessed from the outer side surface 203 of the base material 20 b, and the indentation structure 4 a is tapered from its bottom portion to its top portion.
Referring to FIG. 7, the interconnection structure 32 b is disposed along and on the inner lateral surface 204 a of the first sub-base material 20′ in the indentation structure 4 a. The first end 321 b of the interconnection structure 32 b is disposed on and contacts the capture land 30 a, so that the interconnection structure 32 b is connected to the capture land 30 a. The second end 322 b of the interconnection structure 32 b extends to the bottom surface 201 of the base material 20 b. In some embodiments, the second end 322 b is a portion of the first circuitry structure 21. In some embodiments, the interconnection structure 32 b and the second metal layer 212 of the first circuitry structure 21 are the same layer, and are formed integrally and concurrently. As shown in FIG. 7, the outer side surface 323 b of the interconnection structure 32 b is substantially coplanar with the outer side surface 303 a of the capture land 30 a since they are formed concurrently after a cutting process. In addition, a portion of the second dielectric structure 24, a portion of the third dielectric structure 26, a portion of the fourth circuitry structure 27 and a via structure 205 are disposed above the indentation structure 4 a and the capture land 30 a. The via structure 205 connects the fourth circuit layer 27 and the capture land 30 a. As shown in FIG. 7, the indentation structure 4 a extends from the first circuitry structure 21 to the second circuitry structure 23 for simplicity sake. However, in other embodiments, the indentation structure 4 a may also extend to the third circuitry structure 25 in a four-layered substrate or any intermediate circuit layer in a higher circuit layer count substrate.
FIG. 9 illustrates a cross-sectional view of a semiconductor package 1 c according to some embodiments of the present disclosure. FIG. 10 illustrates a perspective view of a portion of the semiconductor package 1 c of FIG. 9. The semiconductor package 1 c is similar to the semiconductor package 1 b shown in FIG. 7 through FIG. 8, except for the structure of the indentation structure 4 b of the substrate 2 c. As shown FIG. 9, the inner lateral surface 204 b of the first sub-base material 20′ is substantially perpendicular to the bottom surface 201 of the base material 20 c and the bottom surface 304 a of the capture land 30 a. This is because that the inner lateral surface 204 b of the first sub-base material 20′ is formed from a hole that is formed by blade sawing, exposure and development, or laser drilling.
FIG. 11 illustrates a cross-sectional view of a semiconductor package 1 d according to some embodiments of the present disclosure. FIG. 12 illustrates a perspective view of a portion of the semiconductor package 1 d of FIG. 12. The semiconductor package 1 d is similar to the semiconductor package 1 a shown in FIG. 5 through FIG. 6, except for the structures of the interconnection structures 32 c, 32 d of the substrate 2 d. As shown in FIG. 11 and FIG. 12, the substrate 2 d includes a base material 20 d, at least one lower interconnection structure 32 c and at least one upper interconnection structure 32 d. The lower interconnection structure 32 c is tapered from its bottom end to its top end, and the top end of the lower interconnection structure 32 c connects a bottom surface of a capture land 30 b. The upper interconnection structure 32 d is tapered from its top end to its bottom end, and the bottom end of the upper interconnection structure 32 d connects a top surface of the capture land 30 b. The capture land 30 b is a portion of the third circuitry structure 25. The upper interconnection structure 32 d is disposed right above the lower interconnection structure 32 c. In some embodiments, the lower interconnection structure 32 c and the first circuitry structure 21 are formed integrally and concurrently, and the upper interconnection structure 32 d and the fourth circuitry structure 27 are formed integrally and concurrently. As shown FIG. 12, an outer side surface 325 of the lower interconnection structure 32 c, an outer side surface 303 b of the capture land 30 b, an outer side surface 326 of the upper interconnection structure 32 d, the outer side surface 203 of the base material 20 d, the outer side surface 283 of the first protection layer 28, the outer side surface 293 of the second protection layer 29 and the outer side surface 183 of the encapsulant 18 are substantially coplanar with each other since they are formed concurrently after a cutting process. In other embodiments, the center of the capture land 30 b may be drilled through. The resultant central opening in the capture land 30 b will be filled with copper during a simultaneous plating of the lower interconnection structure 32 c and the upper interconnection structure 32 d.
FIG. 13 illustrates a cross-sectional view of a semiconductor package 1 e according to some embodiments of the present disclosure. FIG. 14 illustrates a perspective view of a portion of the semiconductor package 1 e of FIG. 13. The semiconductor package 1 e includes a substrate 2 e, at least one semiconductor chip 14 a and an encapsulant 18 a. The substrate 2 e is used for carrying the semiconductor chip 14 a, and may include a base material 20 e, a capture land 30 c, an interconnection structure 32 e and an indentation structure 4 c. The base material 20 e has a bottom surface 201, a top surface 202, an outer side surface 203 (FIG. 14) and an inner lateral surface 204 e. The top surface 202 is opposite to the bottom surface 201. The outer side surface 203 extends between the bottom surface 201 and the top surface 202. The inner lateral surface 204 e is recessed form the outer side surface 203.
The base material 20 e includes a first circuitry structure 21 a, a first dielectric structure 22 a and a first via structure 221 a. The first dielectric structure 22 a may be a molding compound, a dielectric layer or a passivation layer and may include, or be formed from, a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material such as a polyamide (PA), an Ajinomoto build-up film (ABF), a bismaleimide-triazine (BT), a polyimide (PI), epoxy or polybenzoxazole (PBO), or a combination of two or more thereof. In one or more embodiments, the first dielectric structure 22 a may include, or be formed from a dry film type material that includes a resin and a plurality of fillers. In another embodiment, the first dielectric structure 22 a may include, or be formed from a liquid type material that includes a homogeneous resin without fillers.
The first circuitry structure 21 a may be a patterned circuit layer. As shown in FIG. 13, the first circuitry structure 21 a may be a redistribution layer (RDL), and is embedded in the first dielectric structure 22 a and exposed from the top surface of the first dielectric structure 22 a (e.g., the top surface 202 of the base material 20 e). In some embodiments, the first circuitry structure 21 a may include a plurality of conductive traces and/or a plurality of bonding pads. In one or more embodiments, a line width/line space (L/S) of the first circuitry structure 21 a may be equal to or less than about 3 micrometers (m)/about 3 m, equal to or less than about 2 m/about 2 μm (such as, for example, about 1.8 μm/about 1.8 μm or less, about 1.6 μm/about 1.6 μm or less, or about 1.4 μm/about 1.4 μm or less), equal to or less than about 1 μm/about 1 μm, or equal to or less than about 0.5 μm/about 0.5 μm.
The first via structure 221 a is disposed in the first dielectric structure 22 a. One end of the first via structure 221 a connects the first circuitry structure 21 a, and the other end of the first via structure 221 a is exposed from the bottom surface of the first dielectric structure 22 a (e.g., the bottom surface 201 of the base material 20 e).
The capture land 30 c is disposed in the base material 20, and has an outer side surface 303 c (e.g., a periphery surface at the exposed end) and a bottom surface 304 c. In the embodiment illustrated in FIG. 13, the top surface of the capture land 30 c is coplanar with the top surface of the first dielectric structure 22 a (e.g., the top surface 202 of the base material 20 e). The capture land 30 c covers a space defined by the inner lateral surface 204 e of the base material 20 e. In some embodiments, the capture land 30 c is a portion of the first circuitry structure 21 a, or the capture land 30 c and the first circuitry structure 21 a are formed integrally and concurrently.
The indentation structure 4 c is the space defined by the inner lateral surface 204 e of the base material 20 e and the bottom surface 304 c of the capture land 30 c. That is, the inner lateral surface 204 e of the base material 20 e is the sidewall of the indentation structure 4 c, and the top of the indentation structure 4 c is covered by the capture land 30 c. The indentation structure 4 c is recessed from the outer side surface 203 of the base material 20 e.
The interconnection structure 32 e is disposed along and on the inner lateral surface 204 e of the base material 20 e in the indentation structure 4 c. The interconnection structure 32 e may be formed by etching. The interconnection structure 32 e has an outer side surface 323 e (e.g., an exposed periphery surface). In some embodiments, the first via structure 221 a and the solid portion of the interconnection structure 32 e are formed integrally and concurrently. As shown in FIG. 14, the outer side surface 323 e of the interconnection structure 32 e is substantially coplanar with the outer side surface 303 c of the capture land 30 c since they are formed concurrently after a cutting process.
The semiconductor chip 14 a is disposed adjacent to the top surface 202 of the base material 20 e. As shown in FIG. 13, the semiconductor chip 14 a is disposed on and electrically connected the first circuitry structure 21 a by, for example, flip chip bonding. The encapsulant 18 a, for example, molding compound, is disposed adjacent to the top surface 202 of the base material 20 e to cover the semiconductor chip 14 a and the substrate 2 e. As shown in FIG. 13, the encapsulant 18 a covers and contacts the semiconductor chip 14 a, the base material 20 e and the capture land 30 c. The encapsulant 18 a has an outer side surface 183 a (e.g., a periphery lateral surface). The outer side surface 183 a of the encapsulant 18 a is substantially coplanar with the outer side surface 323 e of the interconnection structure 32 e and the outer side surface 303 c of the capture land 30 c since they are formed concurrently after a cutting process. For simplicity sake, one chip (e.g., the semiconductor chip 14 a) is shown although it is contemplated that as for any System-in-Package, additional chips and or passive device may be added on the top side.
Referring to FIG. 14, the interconnection structure 32 e defines a recess portion 5 a recessed from the outer side surface 203 of the base material 20 e. That is, the interconnection structure 32 e does not full the indentation structure 4 c.
FIG. 15 illustrates a cross-sectional view of a semiconductor package if according to some embodiments of the present disclosure. The semiconductor package if is similar to the semiconductor package 1 e shown in FIG. 13 through FIG. 14, except that the semiconductor package if further includes a second circuitry structure 23 a and a first protection layer 28 a. The second circuitry structure 23 a may be a patterned circuit layer. As shown in FIG. 15, the second circuitry structure 23 a may be a redistribution layer (RDL), and is disposed on the bottom surface 201 of the base material 20 f. Thus, the second circuitry structure 23 a is electrically connected to the first circuitry structure 21 a through the first via structure 221 a. In addition, the second circuitry structure 23 a is electrically connected to the capture land 30 c through the interconnection structure 32 f. In some embodiments, the second circuitry structure 23 a may include a plurality of conductive traces and/or a plurality of bonding pads. In one or more embodiments, an L/S of the second circuitry structure 23 a may be greater than the L/S of the first circuitry structure 21 a.
The first protection layer 28 a covers and contacts the bottom surface of the first dielectric structure 22 a (e.g., the bottom surface 201 of the base material 20 f) and at least a portion of the second circuitry structure 23 a. The first protection layer 28 a may include a solder resist material, such as, for example, benzocyclobutene (BCB) or polyimide. In some embodiments, the first protection layer 28 a may define a plurality of openings to expose portions of the second circuitry structure 23 a. For simplicity sake, a two layered-substrate has been illustrated here. However, multi-layered substrates of the same external structure may be employed as applicable.
FIG. 16 illustrates a cross-sectional view of an assembly 80 of the semiconductor package 1 and a motherboard 82 according to some embodiments of the present disclosure. The semiconductor package 1 of the assembly 80 is the same as the semiconductor package 1 of FIG. 1 to FIG. 4, and is bonded to the motherboard 82 through the solder 84. As shown in FIG. 16, when the semiconductor package 1 is attached to the motherboard 82 by using, for example, surface mounting technique (SMT), the solder 84 can wick up the interconnection structure 32 and form a solder fillet which can be inspected for joint quality, and the yield rate and the soldering reliability of the surface mounting technique (SMT) are improved. That is, the side surfaces of the semiconductor package 1 are solder wettable flanks.
FIG. 17 through FIG. 24 illustrate a method for manufacturing a semiconductor package according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a semiconductor package such as the semiconductor package 1 shown in FIG. 1 to FIG. 4.
Referring to FIG. 17, a base material 20 is provided. The base material 20 has a bottom surface 201, a top surface 202 opposite to the bottom surface 201 and a plurality of singulation lines 51. The base material 20 includes a first metal layer 211, a first dielectric structure 22, a second circuitry structure 23, a second dielectric structure 24, a second via structure 241, a third circuitry structure 25, a third dielectric structure 26 and a first metal layer 271. The first dielectric structure 22, the second circuitry structure 23, the second dielectric structure 24, the second via structure 241, the third circuitry structure 25 and the third dielectric structure 26 may be the same as the first dielectric structure 22, the second circuitry structure 23, the second dielectric structure 24, the second via structure 241, the third circuitry structure 25 and the third dielectric structure 26 as stated above, respectively. In some embodiments, the first metal layer 211 may be a copper foil or a seed layer, and may be formed or disposed on the bottom surface 201 of the base material 20 by pressing or adhesion. Similarly, the first metal layer 271 may be a copper foil or a seed layer, and may be formed or disposed on the top surface 202 of the base material 20 by pressing or adhesion. The singulation lines 51 are the paths of the sawing blade or the laser during a singulation process.
Referring to FIG. 18, at least one first hole 52, at least one second hole 54 and at least one third hole 56 are formed by, for example, laser drilling. The first hole 52 extends through the first metal layer 211 and the first dielectric structure 22, and is stopped by the second circuitry structure 23 so as to expose a portion of the second circuitry structure 23. As shown in FIG. 18, the first hole 52 is tapered from its bottom end to its top end. The second hole 54 extends through the first dielectric structure 22, the second dielectric structure 24, the third circuitry structure 25 and the third dielectric structure 26, and is stopped by the first metal layer 271 so as to expose a portion of the first metal layer 271. As shown in FIG. 18, the second hole 54 is tapered from its bottom end to its top end. The third hole 56 extends through the first metal layer 271 and the third dielectric structure 26, and is stopped by the third circuitry structure 25 so as to expose a portion of the third circuitry structure 25. As shown in FIG. 18, the third hole 56 is tapered from its top end to its bottom end. It is understood that the first hole 52, the second hole 54 and the third hole 56 are blind holes. The second hole 54 is disposed on the singulation lines 51. That is, the second hole 54 may across the singulation line 51, and the central axis of the second hole 54 may be disposed at the singulation line 51. The second hole 54 is a recess structure at the singulation line 51, and a position of the recess structure (e.g., the second hole 54) corresponds to a position of a portion of the first metal layer 271 of the capture land 30 (FIG. 20). That is, a portion of the base material 20 is removed to form the recess structure (e.g., the second hole 54) to expose the portion of the first metal layer 271 of capture land 30 (FIG. 20).
Referring to FIG. 19, a bottom metal layer 58 and a top metal layer 60 are formed on the bottom side and the top side of the base material 20, respectively. In some embodiments, the bottom metal layer 58 and the top metal layer 60 may be formed concurrently by electroplating. As shown in FIG. 19, the bottom metal layer 58 covers and contacts the first metal layer 211 and the sidewalls of the first hole 52 and the second hole 54. The bottom metal layer 58 may fill the first hole 52 to form a first via structure 221, and may not fill the second hole 54. In addition, the top metal layer 60 covers and contacts the first metal layer 271 and the sidewall of the third hole 56. The top metal layer 60 may fill the third hole 56 to form a third via structure 261. It is noted that the first hole 52 and third hole 56 may be filled.
Referring to FIG. 20, the bottom metal layer 58 on the first metal layer 211 is patterned by subtractive etching to form the second metal layer 212. The top metal layer 60 on the first metal layer 271 is patterned by subtractive etching to form the second metal layer 272. Then, portions of the first metal layer 211 that are not covered by the second metal layer 212 are removed by, for example, flash etching, so as to form a first circuitry structure 21. Portions of the first metal layer 271 that are not covered by the second metal layer 272 are removed by, for example, flash etching, so as to form a fourth circuitry structure 27 and a capture land 30 on the second hole 54. Meanwhile, a portion of the first metal layer 271 on the second hole 54 is the first metal layer 301, and a portion of the second metal layer 272 on the first metal layer 301 is the second metal layer 302. The capture land 30 includes the first metal layer 301 and the second metal layer 302. Thus, the capture land 30 is a portion of the fourth circuitry structure 27, and the capture land 30 and the fourth circuitry structure 27 are formed concurrently. The capture land 30 is disposed in or on the base material 20, and the capture land 30 extends across the singulation line 51. In addition, a portion of the bottom metal layer 58 disposed in the second hole 54 is the interconnection structure 32. A portion of the interconnection structure 32 is disposed on and contacts the capture land 30, and another portion of the interconnection structure 32 extends to the bottom surface 201 of the base material 20. That is, the interconnection structure 32 is a conductive patterned structure formed along an inner lateral surface of the recess structure (e.g., the second hole 54) to connect to the capture land 30. In some embodiments, the interconnection structure 32 and the second metal layer 212 of the first circuitry structure 21 are the same layer, and are formed integrally and concurrently. Instead of a subtractive process to form the external circuit patterns, an additive process like pattern plating may be used to form the circuit pattern.
Referring to FIG. 21, a first protection layer 28 is formed or disposed to cover and contact the bottom surface of the first dielectric structure 22 and at least a portion of the first circuitry structure 21. The first protection layer 28 may define at least one opening to expose a portion of the first circuitry structure 21. The first protection layer 28 may include a solder resist material, such as, for example, benzocyclobutene (BCB), epoxy, acrylate or polyimide. A second protection layer 29 is formed or disposed to cover and contact the top surface of the third dielectric structure 26 and at least a portion of the fourth circuitry structure 27. The second protection layer 29 may define at least one opening to expose a portion of the fourth circuitry structure 27. The second protection layer 29 may include a solder resist material, such as, for example, benzocyclobutene (BCB), epoxy, acrylate or polyimide. Meanwhile, a substrate 2 is formed. The substrate 2 includes the base material 20, the capture land 30, the interconnection structure 32, the first protection layer 28 and the second protection layer 29.
Referring to FIG. 22, at least one semiconductor chip 14 and at least one passive device 16 are disposed adjacent to the top surface 202 of the base material 20. As shown in FIG. 22, the semiconductor chip 14 and the passive device 16 are disposed on and electrically connected the fourth circuitry structure 27 on the top surface 202 of the base material 20 of the substrate 2. For example, the semiconductor chip 14 is bonded to the base material 20 by flip chip bonding, and the passive device 16 is bonded to the base material 20 by surface mounting technique (SMT).
Referring to FIG. 23, an encapsulant 18, for example, molding compound, is formed or disposed adjacent to the top surface 202 of the base material 20 to cover the semiconductor chip 14, the passive device 16 and the substrate 2. As shown in FIG. 23, the encapsulant 18 covers and contacts the semiconductor chip 14, the passive device 16, the second protection layer 29 and the capture land 30. Since the top end of the interconnection structure 32 is formed on the capture land 30, the encapsulant 18 can be formed by molding process. In other words, the capture land 30 and the top end of the interconnection structure 32 can prevent the encapsulant 18 from entering the second hole 54 during the molding process.
Referring to FIG. 24, a singulation process is conducted form a plurality of semiconductor packages 1 as shown in FIG. 1 to FIG. 4. The encapsulant 18 and the substrate 2 are singulated along the singulation line 51 by a saw blade or a laser beam. During the singulation process, the interconnection structure 32 is covered by the capture land 30 and the encapsulant 18, thus the interconnection structure 32 will not be ripped from the base material 20. Thus, the yield rate of the semiconductor package 1 can be improved.
FIG. 25 illustrates a method for manufacturing a semiconductor package according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a semiconductor package such as the semiconductor package 1 a shown in FIG. 5 to FIG. 6. The initial stages of the illustrated process are the same as, or similar to, the stages illustrated in FIG. 17 through FIG. 18. FIG. 25 depicts a stage subsequent to that depicted in FIG. 18.
Referring to FIG. 25, the bottom metal layer 58 fills the second hole 54.
The stages subsequent to that shown in FIG. 25 of the illustrated process are similar to the stages illustrated in FIG. 20 through FIG. 24, thus forming the semiconductor package 1 a shown in FIG. 5 and FIG. 6.
FIG. 26 illustrates a method for manufacturing a semiconductor package according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a semiconductor package such as the semiconductor package 1 b shown in FIG. 7 to FIG. 8. The initial stage of the illustrated process is the same as, or similar to, the stage illustrated in FIG. 17. FIG. 26 depicts a stage subsequent to that depicted in FIG. 17.
Referring to FIG. 26, the first hole 52, at least one second hole 54 a and the third hole 56 are formed by, for example, laser drilling. The first hole 52 and the second hole 54 a extend through the first metal layer 211 and the first dielectric structure 22, and are stopped by the second circuitry structure 23 so as to expose a portion of the second circuitry structure 23. As shown in FIG. 26, the first hole 52 is tapered from its bottom end to its top end, and the second hole 54 a is also tapered from its bottom end to its top end. The third hole 56 extends through the first metal layer 271 and the third dielectric structure 26, and is stopped by the third circuitry structure 25 so as to expose a portion of the third circuitry structure 25. As shown in FIG. 26, the third hole 56 is tapered from its top end to its bottom end. It is understood that the first hole 52, the second hole 54 and the third hole 56 are blind holes. The second hole 54 a is disposed on the singulation lines 51. That is, the second hole 54 a may across the singulation line 51, and the central axis of the second hole 54 a may be disposed at the singulation line 51. The second hole 54 a is a recess structure at the singulation line 51, and a position of the recess structure (e.g., the second hole 54 a) corresponds to a position of a portion of the second circuitry structure 23 of the capture land 30 a (FIG. 7). It is noted that the second hole 54 a may also be extended to the third circuitry structure 25 to connect to an appropriate pad there as an alternative structure.
The stages subsequent to that shown in FIG. 26 of the illustrated process are similar to the stages illustrated in FIG. 19 through FIG. 24, thus forming the semiconductor package 1 b shown in FIG. 7 and FIG. 8. It is understood that, after the singulation process, the one-half of the second hole 54 a is the indentation structure 4 a of the substrate 2 b of FIG. 7, and the bottom metal layer 58 in the indentation structure 4 a is the interconnection structure 32 b of FIG. 7.
FIG. 27 through FIG. 29 illustrate a method for manufacturing a semiconductor package according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a semiconductor package such as the semiconductor package 1 c shown in FIG. 9 to FIG. 10. The initial stage of the illustrated process is the same as, or similar to, the stage illustrated in FIG. 17. FIG. 27 depicts a stage subsequent to that depicted in FIG. 17.
Referring to FIG. 27, the first hole 52 and the third hole 56 are formed by, for example, laser drilling. The first hole 52 extends through the first metal layer 211 and the first dielectric structure 22, and is stopped by the second circuitry structure 23 so as to expose a portion of the second circuitry structure 23. As shown in FIG. 27, the first hole 52 is tapered from its bottom end to its top end. The third hole 56 extends through the first metal layer 271 and the third dielectric structure 26, and is stopped by the third circuitry structure 25 so as to expose a portion of the third circuitry structure 25. As shown in FIG. 27, the third hole 56 is tapered from its top end to its bottom end. It is understood that the first hole 52 and the third hole 56 are blind holes.
Referring to FIG. 28, at least one second hole 54 c is formed by, for example, blade sawing, exposure and development, or laser drilling. The second hole 54 c extends through the first metal layer 211 and the first dielectric structure 22, and is stopped by the second circuitry structure 23 so as to expose a portion of the second circuitry structure 23. As shown in FIG. 28, the second hole 54 c is not a tapered structure. The sidewall of the second hole 54 c is substantially perpendicular to the bottom surface 201 of the base material 20 c and the bottom surface 304 a of the capture land 30 a. It is understood that the second hole 54 c is a blind hole. The second hole 54 c is disposed on the singulation lines 51. That is, the second hole 54 c may across the singulation line 51, and the central axis of the second hole 54 c may be disposed at the singulation line 51. The second hole 54 c is a recess structure at the singulation line 51, and a position of the recess structure (e.g., the second hole 54 c) corresponds to a position of a portion of the second circuitry structure 23 of the capture land 30 a.
Referring to FIG. 29, a bottom metal layer 58 and a top metal layer 60 are formed on the bottom side and the top side of the base material 20 c, respectively. In some embodiments, the bottom metal layer 58 and the top metal layer 60 may be formed concurrently by electroplating. As shown in FIG. 29, the bottom metal layer 58 covers and contacts the first metal layer 211 and the sidewalls of the first hole 52 and the second hole 54 c. The bottom metal layer 58 may full the first hole 52 to form a first via structure 221, and may not full the second hole 54 c. In addition, the top metal layer 60 covers and contacts the first metal layer 271 and the sidewall of the third hole 56. The top metal layer 60 may full the third hole 56 to form a third via structure 261. As an alternative, the second hole 54 c may be extended to an appropriate land of the third circuitry structure 25 to yield an alternative castellated substrate.
The stages subsequent to that shown in FIG. 29 of the illustrated process are similar to the stages illustrated in FIG. 20 through FIG. 24, thus forming the semiconductor package 1 c shown in FIG. 9 and FIG. 10.
It is understood that, after the singulation process, the one-half of the second hole 54 c is the indentation structure 4 b of the substrate 2 c of FIG. 9, and the bottom metal layer 58 in the indentation structure 4 b is the interconnection structure 32 b of FIG. 9.
FIG. 30 through FIG. 31 illustrate a method for manufacturing a semiconductor package according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a semiconductor package such as the semiconductor package 1 d shown in FIG. 11 to FIG. 12. The initial stage of the illustrated process is the same as, or similar to, the stage illustrated in FIG. 17. FIG. 30 depicts a stage subsequent to that depicted in FIG. 17.
Referring to FIG. 30, the first hole 52, at least one second lower hole 54 d, at least one second upper hole 54 e and the third hole 56, are formed by, for example, laser drilling. The first hole 52 extends through the first metal layer 211 and the first dielectric structure 22, and is stopped by the second circuitry structure 23 so as to expose a portion of the second circuitry structure 23. As shown in FIG. 30, the first hole 52 is tapered from its bottom end to its top end. The second lower hole 54 d extends through the first metal layer 211, the first dielectric structure 22 and the second dielectric structure 24, and is stopped by the third circuitry structure 25 (e.g., the capture land 30 b) so as to expose a bottom portion of the third circuitry structure 25. As shown in FIG. 30, the second lower hole 54 d is tapered from its bottom end to its top end. The second upper hole 54 e extends through the first metal layer 271 and the third dielectric structure 26, and is stopped by the third circuitry structure 25 (e.g., the capture land 30 b) so as to expose a top portion of the third circuitry structure 25 (e.g., the capture land 30 b). As shown in FIG. 30, the second upper hole 54 e is tapered from its top end to its bottom end. The third hole 56 extends through the first metal layer 271 and the third dielectric structure 26, and is stopped by the third circuitry structure 25 so as to expose a top portion of the third circuitry structure 25. As shown in FIG. 30, the third hole 56 is tapered from its top end to its bottom end. It is understood that the first hole 52, the second lower hole 54 d, the second upper hole 54 e and the third hole 56 are blind holes. The second upper hole 54 e is disposed right above the second lower hole 54 d.
Referring to FIG. 31, a bottom metal layer 58 and a top metal layer 60 are formed on the bottom side and the top side of the base material 20 d, respectively. In some embodiments, the bottom metal layer 58 and the top metal layer 60 may be formed concurrently by electroplating. As shown in FIG. 31, the bottom metal layer 58 covers and contacts the first metal layer 211 and the sidewalls of the first hole 52 and the second lower hole 54 d. The bottom metal layer 58 may full the first hole 52 to form a first via structure 221, and may also fill the second lower hole 54 d to form a lower interconnection structure 32 c. In addition, the top metal layer 60 covers and contacts the first metal layer 271 and the sidewalls of the second upper hole 54 e and the third hole 56. The top metal layer 60 may fill the third hole 56 to form a third via structure 261, and may also fill the second upper hole 54 e to form an upper interconnection structure 32 d. Alternatively, the capture land 30 b may be drilled through and subsequently filled in simultaneously during plating as an alternative via structure, a so called x-via.
The stages subsequent to that shown in FIG. 31 of the illustrated process are similar to the stages illustrated in FIG. 20 through FIG. 24, thus forming the semiconductor package 1 d shown in FIG. 11 and FIG. 12.
It is understood that, after the singulation process, the one-half of the lower interconnection structure 32 c is the lower interconnection structure 32 c of FIG. 11, and the one-half of the upper interconnection structure 32 d is the upper interconnection structure 32 d of FIG. 11.
FIG. 32 through FIG. 39 illustrate a method for manufacturing a semiconductor package according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a semiconductor package such as the semiconductor package 1 e shown in FIG. 13 to FIG. 14. Referring to FIG. 32, a carrier 62 with a metal layer 64 is provided. The carrier 62 may be, for example, a metal material, a ceramic material, a glass material, a substrate or a semiconductor wafer. In some embodiments, the metal layer 64 may be a copper foil that is formed or disposed on a surface of the carrier 62.
Referring to FIG. 33, a first circuitry structure 21 a and a capture land 30 c are formed or built up on the metal layer 64 on the carrier 62. In some embodiments, the capture land 30 c is a portion of the first circuitry structure 21 a, or the capture land 30 c and the first circuitry structure 21 a are formed integrally and concurrently. The first circuitry structure 21 a may be a redistribution layer (RDL), and may include a plurality of conductive traces and/or a plurality of bonding pads.
Referring to FIG. 34, at least one first via structure 221 a and at least one metal pillar 66 are formed or disposed on the first circuitry structure 21 a by, for example, electroplating. The first via structure 221 a is formed on the bonding pad of the first circuitry structure 21 a, and the metal pillar 66 is formed on the capture land 30 c.
Referring to FIG. 35, a first dielectric structure 22 a is formed or disposed to cover the metal layer 64, the first circuitry structure 21 a, the first via structure 221 a and the metal pillar 66 by, for example, molding or lamination. The first dielectric structure 22 a may be a molding compound, a dielectric layer or a passivation layer and may include, or be formed from, a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material such as a polyamide (PA), an Ajinomoto build-up film (ABF), a bismaleimide-triazine (BT), a polyimide (PI), epoxy or polybenzoxazole (PBO), or a combination of two or more thereof. In one or more embodiments, the first dielectric structure 22 a may include, or be formed from a dry film type material that includes a resin and a plurality of fillers. In another embodiment, the first dielectric structure 22 a may include, or be formed from a liquid type material that includes a homogeneous resin without fillers.
Referring to FIG. 36, a top portion of the first dielectric structure 22 a is removed by, for example, grinding. Thus, the first dielectric structure 22 a is thinned, and one end of the first via structure 221 a and one end of the metal pillar 66 are exposed from the bottom surface of the first dielectric structure 22 a.
Referring to FIG. 37, a dry film 68 is formed or disposed on the bottom surface of the first dielectric structure 22 a to cover the first via structure 221 a and the metal pillar 66. Then, at least one opening 681 is formed in the dry film 68 by, for example, photolithography process (e.g., including exposure and development) so as to expose the metal pillar 66. Then, a portion of the metal pillar 66 corresponding to the opening 681 is etched so as to form a recess structure 70.
Referring to FIG. 38, the dry film 68 is removed by, for example, stripping. Then, the carrier 62 is removed. Then, the metal layer 64 is removed by, for example, etching. Meanwhile, a substrate 2 e is obtained. The substrate 2 e has a plurality of singulation lines 51. The recess structure 70 is disposed at the singulation line 51, and the position of the recess structure 70 corresponds to the position of the capture land 30 c.
Referring to FIG. 39, at least one semiconductor chip 14 a is disposed on the substrate 2 e. As shown in FIG. 39, the semiconductor chip 14 a is disposed on and electrically connected the first circuitry structure 21 a by, for example, flip chip bonding. An encapsulant 18 a, for example, molding compound, is disposed adjacent to the top surface 202 of the base material 20 e of the substrate 2 e to cover the semiconductor chip 14 a and the substrate 2 e. Since the top end of the recess structure 70 is covered by the capture land 30 c, the encapsulant 18 a can be formed by molding process. In other words, the capture land 30 c can prevent the encapsulant 18 a from entering the recess structure 70 during the molding process.
Then, a singulation process is conducted form a plurality of semiconductor packages 1 e as shown in FIG. 13 to FIG. 14. The encapsulant 18 a and the substrate 2 e are singulated along the singulation lines 51 by a saw blade or a laser beam. After the singulation process, the one half of the recess structure 70 is the interconnection structure 32 e of FIG. 13. It is noted that, during the singulation process, the recess structure 70 is covered by the capture land 30 c and the encapsulant 18 a, thus the recess structure 70 will not be ripped from the base material 20 e. Thus, the yield rate of the semiconductor package 1 e can be improved.
FIG. 40 through FIG. 43 illustrate a method for manufacturing a semiconductor package according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a semiconductor package such as the semiconductor package if shown in FIG. 15. The initial stages of the illustrated process are the same as, or similar to, the stages illustrated in FIG. 32 to FIG. 36. FIG. 40 depicts a stage subsequent to that depicted in FIG. 36.
Referring to FIG. 40, a second circuitry structure 23 a is formed on the first dielectric structure 22 a to connect to the first via structure 221 a and the metal pillar 66 on the capture land 30 c. The second circuitry structure 23 a may be a patterned circuit layer. As shown in FIG. 40, the second circuitry structure 23 a may be a redistribution layer (RDL), and is disposed on the bottom surface of the first dielectric structure 22 a. Thus, the second circuitry structure 23 a is electrically connected to the first circuitry structure 21 a through the first via structure 221 a. In some embodiments, the second circuitry structure 23 a may include a plurality of conductive traces and/or a plurality of bonding pads. In one or more embodiments, an L/S of the second circuitry structure 23 a may be greater than the L/S of the first circuitry structure 21 a. Then, a first protection layer 28 a is formed or disposed to cover and contact the bottom surface of the first dielectric structure 22 a and at least a portion of the second circuitry structure 23 a. The first protection layer 28 a may include a solder resist material, such as, for example, benzocyclobutene (BCB) or polyimide. In some embodiments, the first protection layer 28 a may define a plurality of openings to expose portions of the second circuitry structure 23 a.
Referring to FIG. 41, a dry film 72 is formed or disposed on the first protection layer 28 a to cover the first protection layer 28 a and the exposed portions of the second circuitry structure 23 a. Then, at least one opening 721 is formed in the dry film 72 by, for example, photolithography process (e.g., including exposure and development) so as to expose a portion of the second circuitry structure 23 a on the metal pillar 66. Then, a portion of the second circuitry structure 23 a on the metal pillar 66 and a portion of the metal pillar 66 corresponding to the opening 721 are etched so as to form a recess structure 74.
Referring to FIG. 42, the dry film 72 is removed by, for example, stripping. Then, the carrier 62 is removed. Then, the metal layer 64 is removed by, for example, etching. Meanwhile, a substrate 2 f is obtained. The substrate 2 f has a plurality of singulation lines 51. The recess structure 74 is disposed at the singulation line 51, and the position of the recess structure 74 corresponds to the position of the capture land 30 c.
Referring to FIG. 43, at least one semiconductor chip 14 a is disposed on the substrate 2 f. As shown in FIG. 43, the semiconductor chip 14 a is disposed on and electrically connected the first circuitry structure 21 a by, for example, flip chip bonding. An encapsulant 18 a, for example, molding compound, is disposed adjacent to the top surface 202 of the base material 20 f of the substrate 2 f to cover the semiconductor chip 14 a and the substrate 2 f. Since the top end of the recess structure 74 is covered by the capture land 30 c, the encapsulant 18 a can be formed by molding process. In other words, the capture land 30 c can prevent the encapsulant 18 a from entering the recess structure 74 during the molding process.
Then, a singulation process is conducted form a plurality of semiconductor packages if as shown in FIG. 15. The encapsulant 18 a and the substrate 2 f are singulated along the singulation lines 51 by a saw blade or a laser beam. After the singulation process, the one half of the recess structure 74 is the interconnection structure 32 f of FIG. 15.
Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such an arrangement.
As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to +10% of that numerical value, such as less than or equal to +5%, less than or equal to +4%, less than or equal to +3%, less than or equal to +2%, less than or equal to +1%, less than or equal to +0.5%, less than or equal to +0.1%, or less than or equal to +0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to +10% of an average of the values, such as less than or equal to +5%, less than or equal to +4%, less than or equal to +3%, less than or equal to +2%, less than or equal to +1%, less than or equal to +0.5%, less than or equal to +0.1%, or less than or equal to +0.05%.
Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.
As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise.
As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 10⁴S/m, such as at least 10⁵S/m or at least 10⁶S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.

Claims

1. A semiconductor package, comprising:

a base material having a top surface and an inner lateral surface;

a capture land disposed in or on the base material, and having an outer side surface;

an interconnection structure disposed along the inner lateral surface of the base material, and on the capture land, wherein the interconnection structure has an outer side surface, and an outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure;

a semiconductor chip disposed on the top surface of the base material; and

an encapsulant disposed adjacent to the top surface of the base material, and covering the semiconductor chip.

2. The semiconductor package of claim 1, wherein the interconnection structure contacts the capture land, and the outer side surface of the interconnection structure is substantially coplanar with the outer side surface of the capture land.

3. The semiconductor package of claim 1, wherein the encapsulant has an outer side surface, and the outer side surface of the encapsulant is substantially coplanar with the outer side surface of the capture land.

4. The semiconductor package of claim 1, further comprising an indentation structure defined by the inner lateral surface of the base material and the capture land.

5. The semiconductor package of claim 4, wherein at least a portion of the interconnection structure is disposed within the indentation structure.

6. The semiconductor package of claim 4, wherein the inner lateral surface of the base material is inclined with respect to the top surface of the base material.

7. The semiconductor package of claim 4, wherein the base material includes a first sub-base material and a second sub-base material, the indentation structure is defined by an inner lateral surface of the first sub-dielectric layer and the capture land.

8. The semiconductor package of claim 4, wherein the indentation structure includes a first portion disposed adjacent to the capture land and a second portion disposed away from the capture land, and a width of the first portion is less than a width of the second portion.

9. The semiconductor package of claim 4, wherein a width of the capture land is greater than a width of the indentation structure.

10. The semiconductor package of claim 4, wherein the base material includes at least one dielectric structure and at least one circuitry structure, and a portion of the dielectric structure and a portion of the circuitry structure are disposed above the indentation structure.

11. The semiconductor package of claim 10, wherein the base material further includes a via structure disposed above the indentation structure, and the via structure connects the circuitry structure and the capture land.

12. The semiconductor package of claim 1, wherein the capture land is a via stop structure.

13. The semiconductor package of claim 12, wherein the via stop structure is a laser drilling stop structure or etching stop structure.

14. The semiconductor package of claim 1, wherein the base material includes at least one dielectric structure and at least one circuitry structure, and the capture land is a portion of a circuitry structure.

15. A semiconductor package, comprising

a substrate, including:

a base material having a top surface and an outer side surface connected to the top surface;

an indentation structure recessed from the outer side surface of the base material, and having a first width;

a capture land disposed in or on the base material and disposed adjacent to the indentation structure, wherein the capture land has a third width that is greater than the first width of the indentation structure; and

an interconnection structure disposed in the indentation structure and connected to the capture land;

a semiconductor chip disposed adjacent to the top surface of the base material; and

an encapsulant covering the semiconductor chip and the substrate.

16. The semiconductor package of claim 15, wherein the base material of the substrate includes a circuitry structure connected to the capture land by a via structure.

17. The semiconductor package of claim 15, wherein the encapsulant has an outer side surface, and the outer side surface of the encapsulant is substantially coplanar with the outer side surface of the base material of the substrate.

18. The semiconductor package of claim 15, wherein the base material further has an inner lateral surface, and the indentation structure is defined by the inner lateral surface of the base material and the capture land.

19. The semiconductor package of claim 15, wherein an outer side surface of the substrate includes the outer side surface of the base material, an outer side surface of the interconnection structure and an outer side surface of the capture land.

20. The semiconductor package of claim 15, wherein the capture land is a via stop structure.

21. The semiconductor package of claim 20, wherein the via stop structure is a laser drilling stop structure or etching stop structure.

22-27. (canceled)