US20190245082A1 - Laterally diffused mosfet on fully depleted soi - Google Patents
Laterally diffused mosfet on fully depleted soi Download PDFInfo
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- US20190245082A1 US20190245082A1 US16/389,315 US201916389315A US2019245082A1 US 20190245082 A1 US20190245082 A1 US 20190245082A1 US 201916389315 A US201916389315 A US 201916389315A US 2019245082 A1 US2019245082 A1 US 2019245082A1
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- semiconductor layer
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- shallow trench
- trench isolation
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- 238000002955 isolation Methods 0.000 claims abstract description 55
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- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
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- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
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- 238000005468 ion implantation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions
- the present description relates generally to integrated circuits, and more particularly, to laterally diffused MOSFETs on fully depleted silicon-on-insulator (SOI).
- SOI silicon-on-insulator
- LDMOS Laterally diffused MOSFET
- FDSOI fully depleted SOI
- LDD lightly doped drain
- the lightly doped drain (LDD) segment provides a voltage drop from the drain to edge of the gate that can help prevent gate dielectric breakdown.
- the LDMOS on FDSOI may support higher breakdown voltages compared to bulk LDMOS.
- the LDD segment also adds to the resistance of the LDMOS in on-state (on-resistance) which can be an issue in applications where fast turn on of the LDMOS is required. Therefore, providing an LDMOS on FDSOI with low resistance in on-state is highly desirable.
- FIG. 1 illustrates an example of an LDMOS on FDSOI, according to some aspects of the disclosure.
- FIG. 2 illustrates an example of an LDMOS on FDSOI, according to some aspects of the disclosure.
- FIG. 3 illustrates a flow diagram of an example method and concept for creating an LDMOS on FDSOI, according to some aspects of the disclosure.
- FDSOI may be used for high performance processors because it may provide ultra-low power consumption electronics with drastically reduced leakage power.
- a channel of an LDMOS on FDSOI may be very thin and thus may not need to be doped. Using an un-doped channel may minimize random fluctuations in LDMOS voltage. Additionally, there is no floating body effect in an LDMOS on FDSOI and consequently it is easier to control short-channel effects.
- an LDMOS on FDSOI may require smaller dimensions for the same voltage level.
- an LDMOS on FDSOI with reduced resistance in on-state is described.
- a drain region of the LDMOS on FDSOI may include a lightly doped segment.
- the lightly doped drain (LDD) segment may help prevent a gate dielectric breakdown and increase drain to source voltage, which the LDMOS can tolerate.
- the LDD segment may contribute to the on-state resistance of the LDMOS. The higher on-state resistance may become an issue when fast turn on of the LDMOS is required.
- the gate voltage may concurrently be applied at two locations of the LDMOS circuit. First, the gate voltage is applied to the channel to create an inversion layer in the channel.
- the gate voltage may be applied to a semiconductor well behind the buried oxide layer to create a back bias and thus enhance the drain to source current.
- the gate voltage may be applied to a semiconductor well behind the buried oxide layer to create a back bias and thus enhance the drain to source current.
- LDMOS on FDSOI with reduced on-state resistance can be detected during failure analysis and device characteristics measurements. Because a removal of SOI in certain areas may be performed without adding to the process steps, connecting the gate voltage to the semiconductor well does not require an extra mask or process step. Additionally, the formation of the LDD segment is similar to the process that adjusts the threshold voltage of a MOSFET and thus does not require an additional process step.
- FIG. 1 illustrates an example of an LDMOS on FDSOI, according to some aspects of the disclosure.
- LDMOS 100 includes substrate 102 and first semiconductor layer 104 where first semiconductor layer 104 is disposed on substrate 102 .
- first semiconductor layer 104 is an n-type diffusion layer such as an N well.
- LDMOS 100 includes buried oxide layer 106 (BOX layer) that is disposed on first semiconductor layer 104 and second semiconductor layer 108 that is disposed on top of buried oxide layer 106 .
- second semiconductor layer 108 is created by a process that begins with growing an oxide layer on top of an additional substrate. Then the additional substrate may be flipped and bonded to substrate 102 .
- substrate 102 includes semiconductor layer 104 .
- the grown oxide layer may attach to semiconductor layer 104 .
- a cut is made through a thickness of the additional substrate to create, on top of the grown oxide layer, a remaining semiconductor layer of the additional substrate.
- the remaining semiconductor layer of the additional substrate is second semiconductor layer 108 and the grown oxide layer is buried oxide layer 106 .
- Second semiconductor layer 108 may include first gate region 110 , drain region 112 , and source region 114 .
- First gate region 110 may be positioned between source region 114 and drain region 112 and may have a length of 100 nm to 400 nm.
- LDMOS 100 further includes first shallow trench isolation 116 that may be disposed between drain region 112 and first semiconductor layer 104 .
- First shallow trench isolation 116 may be positioned between first end 134 of second semiconductor layer 108 and first semiconductor layer 104 .
- First shallow trench isolation 116 may extend from second semiconductor layer 108 to first semiconductor layer 104 .
- second gate region 120 may be disposed on first semiconductor layer 104 away from second semiconductor layer 108 and between first shallow trench isolation 116 and second shallow trench isolation 118 .
- Second shallow trench isolation 118 may extend from second gate region 120 to first semiconductor layer 104 .
- gate node 130 may be coupled to first gate region 110 and second gate region 120 .
- Gate node 130 may apply a same gate voltage to first gate region 110 and second gate region 120 such that the gate voltage may also be applied to the first semiconductor layer 104 . Applying the gate voltage via second gate region 120 to first semiconductor layer 104 during an on-state of LDMOS 100 may create a back bias of first gate region 110 . In some examples, the gate voltage is between 0.6 volts to 1.8 volts.
- LDMOS 100 further includes third shallow trench isolation 122 that may be disposed between source region 114 and first semiconductor layer 104 .
- Third shallow trench isolation 122 may be positioned between second end 136 of second semiconductor layer 108 and first semiconductor layer 104 (N well). Third shallow trench isolation 122 may extend from second semiconductor layer 108 to first semiconductor layer 104 to isolate source region 114 from first semiconductor layer 104 .
- first shallow trench isolation 116 second shallow trench isolation 118 , and third shallow trench isolation 122 are made of a dielectric material such as silicon oxide. Shallow trench isolations 118 and 122 may prevent electric current leakage between adjacent components.
- second semiconductor layer 108 including first gate region 110 is very thin, e.g., between 20 nm and 35 nm.
- First gate region 110 is not doped and is fully depleted of mobile charges.
- buried oxide layer 106 is also very thin, e.g., between 10 nm and 30 nm.
- second semiconductor layer 108 may be created as an un-doped layer. Then in drain region 112 and source region 114 n-type dopants are deposited. In some embodiments, source region 114 is a highly doped n-type (N + ) semiconductor. In some embodiments, drain region 112 includes two adjacent n-type segments, first drain segment 112 A and second drain segment 112 B. First drain segment 112 A is a lightly doped n-type segment that may be called lightly doped drain (LDD). Second drain segment 112 B is N + , a highly doped n-type. First drain segment 112 A is in contact with first gate region 110 .
- LDD lightly doped drain
- LDD segment is positioned between second drain segment 112 B and first gate region 110 and may be used to provide a voltage drop from second drain segment 112 B to an edge of first gate region 110 .
- the voltage drop may reduce the electric field intensity in first gate region 110 .
- the N + second drain segment 112 B is used for creating an ohmic contact with a drain node (not shown).
- the N + source region 114 may also be used for creating an ohmic contact with a source node (not shown).
- second gate region 120 is also an N + region to create an ohmic contact with gate node 130 .
- first drain segment 112 A of drain region 112 that is lightly doped has a higher resistance than second drain segment 112 B that is highly doped. Therefore, first drain segment 112 A may contribute more than second drain segment 112 B to the resistance between drain region 112 and source region 114 of LDMOS 100 . Thus, lightly doped first drain segment 112 A may increase the resistance of LDMOS 100 in the on-state.
- substrate 102 is not doped and first semiconductor layer 104 is a deposited N well.
- substrate 102 is lightly doped p-type and first semiconductor layer 104 is an N well in the lightly doped p-type substrate.
- a positive threshold voltage of LDMOS 100 decreases. Decreasing the threshold voltage may cause a current between drain region 112 and source region 114 to increase.
- LDMOS 100 when LDMOS 100 is turned on a voltage of about 1.8 volts may be applied to the gate node and the source node may be grounded.
- gate node 130 of LDMOS 100 couples to first gate region 110 via high dielectric constant oxide layer 132 , tri-nitride layer 126 , and polysilicon layer 124 .
- low dielectric constant silicon Nitride layer 128 covers the coupling.
- a material of gate node 130 that couples first gate region 110 to second gate region 120 is a metal made of tungsten or cobalt.
- LDMOS 100 is forward biased and a gate voltage is applied between first gate region 110 and source region 114 . The gate voltage is a positive voltage above threshold voltage of LDMOS 100 . Then, an inversion layer is formed in first gate region 110 that cause a current to flow from drain region 112 to source region 114 .
- applying the positive bias to second gate region 120 of LDMOS 100 may act as a back bias and thus may increase the current from drain region 112 to source region 114 .
- LDMOS 100 is reverse biased and the gate voltage of first gate region 110 is zero or a negative voltage that is applied between first gate region 110 and source region 114 .
- applying the negative bias to second gate region 120 of LDMOS 100 does not affect a performance of LDMOS 100 when reversed biased.
- FIG. 2 illustrates an example of an LDMOS on FDSOI, according to some aspects of the disclosure.
- LDMOS 200 includes substrate 202 and first semiconductor layer 204 where first semiconductor layer 204 is disposed on substrate 202 .
- first semiconductor layer 204 is a p-type diffusion layer such as a P well.
- LDMOS 200 includes buried oxide layer 206 (BOX) that is disposed on first semiconductor layer 204 and second semiconductor layer 208 that is disposed on top of buried oxide layer 206 .
- second semiconductor layer 208 is disposed on top of buried oxide layer 206 by a same process described above for creating second semiconductor layer 108 .
- Second semiconductor layer 208 may include first gate region 210 , drain region 212 , and source region 214 .
- First gate region 210 may be positioned between source region 214 and drain region 212 .
- LDMOS 200 has a same structure as LDMOS 100 . Additionally, in LDMOS 200 source region 214 , drain region 212 , and second gate region 220 as well as first semiconductor layer 204 are p-type semiconductors. Also, source region 214 , second gate region 220 , and second drain segment 212 B are highly doped p-type (P + ) semiconductors. LDMOS 200 is described in more details with respect to method 300 of FIG. 3 .
- gate node 230 of LDMOS 200 couples to first gate region 210 via high dielectric constant oxide layer 232 , tri-nitride layer 226 , and polysilicon layer 224 .
- low dielectric constant silicon Nitride layer 228 covers the coupling.
- a material of gate node 230 that couples first gate region 210 to second gate region 220 is a metal made of tungsten or cobalt.
- LDMOS 200 is forward biased and a gate voltage is applied between first gate region 210 and source region 214 . The gate voltage is a negative voltage below a negative threshold voltage of LDMOS 200 .
- first gate region 210 that cause a current to flow between source region 214 and drain region 212 .
- applying the negative bias to second gate region 220 of LDMOS 200 may act as a back bias and thus may increase the current flow from source region 214 to drain region 212 .
- LDMOS 200 is reverse biased and the gate voltage of first gate region 210 is zero or a positive voltage that is applied between first gate region 210 and source region 214 .
- applying the positive bias to second gate region 220 of LDMOS 200 does not affect a performance of LDMOS 200 when reversed biased.
- the P well and the N well may have a dopant concentration of about 10 18 and the N + and the P + regions have a dopant concertation between 5 ⁇ 10 19 and 5 ⁇ 10 20 .
- Lightly doped first drain segments 212 A and 112 A may have a concentration of about 10 18 .
- FIG. 3 illustrates a flow diagram of an example method and concept for creating an LDMOS on FDSOI, according to some aspects of the disclosure. Notably, one or more steps of method 300 described herein may be omitted, performed in a different sequence, and/or combined with other methods for various types of applications contemplated herein. Method 300 can be performed for creating LDMOS 100 or 200 of FIGS. 1 or 2 .
- a first semiconductor layer is disposed on a substrate.
- a buried oxide layer is disposed on the first semiconductor layer.
- first semiconductor layer 104 N well
- first semiconductor layer 104 P well
- first semiconductor layer 204 P well
- buried oxide layer 206 may be disposed on top of first semiconductor layer 204 .
- first semiconductor layers 104 and 204 are diffused layers.
- buried oxide layers 106 and 206 are very thin oxide layers between 10 nm and 30 nm.
- a second semiconductor layer is disposed on the buried oxide layer.
- a first gate region, a drain region, and a source region are created in the second semiconductor layer.
- second semiconductor layer 108 is disposed on buried oxide layer 106 .
- source region 114 , first gate region 110 , and drain region 112 are created in second semiconductor layer 108 .
- first gate region 110 is not doped
- source region 114 is N +
- the n-type drain region 112 includes first drain segment 112 A that is lightly doped and second drain segment 112 B that is N + .
- second semiconductor layer 208 is disposed on buried oxide layer 206 .
- source region 214 , first gate region 210 , and drain region 212 are created in second semiconductor layer 208 .
- first gate region 210 is not doped
- source region 214 is P +
- the p-type drain region 212 includes first drain segment 212 A that is lightly doped and second drain segment 212 B that is P + .
- second semiconductor layers 108 and 208 are not doped when created. The dopants in the source and drain regions are then deposited and annealed.
- second drain segments 112 B and 212 B and source regions 114 and 214 are raised.
- buried oxide layers 106 and 206 may be created on the additional substrate and then flipped and disposed on substrates 102 and 202 .
- second semiconductor layers 108 and 208 may be disposed in a same process that creates buried oxide layers 106 and 206 .
- the source, gate, and drain regions of second semiconductor layers 108 and 208 are created by ion implantation. The source, gate, and drain regions are created in the additional substrate before the additional substrate is flipped and bonded to substrates 102 and 202 .
- a first shallow trench isolation is disposed between the drain region of the second semiconductor layer and the first semiconductor layer.
- first shallow trench isolation 116 is disposed at first end 134 of second semiconductor layer 108 .
- First shallow trench isolation 116 is disposed between drain region 112 of second semiconductor layer 108 and first semiconductor layer 104 .
- First shallow trench isolation 116 is extended from drain region 112 to first semiconductor layer 104 .
- first shallow trench isolation 216 is disposed at first end 234 of second semiconductor layer 208 .
- First shallow trench isolation 216 is disposed between drain region 212 of second semiconductor layer 208 and first semiconductor layer 204 .
- First shallow trench isolation 216 is extended from drain region 212 to first semiconductor layer 204 .
- shallow trench isolations 116 and 216 are made of silicon dioxide and have a depth of 100 nm to 200 nm.
- buried oxide layers 106 and 206 are respectively extended beyond second semiconductor layer 108 and 208 .
- shallow trench isolations 116 and 216 are created to isolate drain regions 112 and 212 from first semiconductor layers 104 (N well) and 204 (P well).
- shallow trench isolations 122 and 222 are similarly created at second ends 136 and 236 of second semiconductor layers 108 and 208 .
- Shallow trench isolations 122 and 222 may isolate source regions 114 and 214 from first semiconductor layers 104 (N well) and 204 (P well). Additionally, shallow trench isolations 122 and 222 also isolate LDMOS 100 and LDMOS 200 from other LDMOS devices on substrates 102 and 202 .
- a section of the buried oxide layer next to the first shallow trench isolation is etched to create an exposed region on the first semiconductor layer.
- buried oxide layers 106 and 206 are respectively extended beyond second semiconductor layer 108 and 208 .
- buried oxide layers 106 and 206 may be etched to create shallow trench isolations 116 and 216 .
- Buried oxide layers 106 and 206 may further be etched beyond shallow trench isolations 116 and 216 to create exposed second gate regions 120 and 220 on first semiconductor layers 104 and 204 .
- a second gate region is disposed on the exposed region between the first shallow trench isolation and a second shallow trench isolation.
- second gate regions 120 and 220 are created at exposed regions of first semiconductor layers 104 and 204 .
- Second gate regions 120 and 220 are respectively N + and P + .
- shallow trench isolations 118 and 218 are similarly created next to second gate regions 120 and 220 .
- shallow trench isolations 118 and 218 isolate LDMOS 100 and LDMOS 200 from other LDMOS devices in substrates 102 and 202 .
- a gate node is coupled to the first and second gate regions.
- gate node 130 may be coupled to first gate region 110 and second gate region 120 .
- gate node 130 may be coupled to second gate region 120 through an ohmic contact such that a positive gate voltage may be applied to first semiconductor layer 104 in an on-state of LDMOS 100 .
- the positive gate voltage may create a back bias for first gate region 110 in the on-state when the gate node is positively biased with respect to source region 114 .
- the back bias may increase a flow of current from drain region 112 to source region 114 when LDMOS 100 is forward biased. Equivalently, the back bias may decrease a resistance between the drain region and source region.
- gate node 230 may be coupled to first gate region 210 and second gate region 220 .
- Gate node 230 may be coupled to second gate region 220 through an ohmic contact such that a negative gate voltage may be applied to first semiconductor layer 204 in an on-state of LDMOS 200 .
- the negative gate voltage may create a back bias for first gate region 210 in the on-state when the gate node is negatively biased with respect to the source region 214 .
- the back bias may increase a flow of current from source region 214 to drain region 212 when LDMOS 200 is forward biased. Equivalently, the back bias may decrease a resistance between the drain region and source region. In some examples, by connecting the gate node to the second gate region, a resistance between the drain and source regions is reduced by 30%.
- a processor configured to monitor and control an operation or a component may also mean the processor being programmed to monitor and control the operation or the processor being operable to monitor and control the operation.
- a processor configured to execute code can be construed as a processor programmed to execute code or operable to execute code.
- a phrase such as an “aspect” does not imply that such aspect is essential to the subject technology or that such aspect applies to all configurations of the subject technology.
- a disclosure relating to an aspect may apply to all configurations, or one or more configurations.
- a phrase such as an aspect may refer to one or more aspects and vice versa.
- a phrase such as a “configuration” does not imply that such configuration is essential to the subject technology or that such configuration applies to all configurations of the subject technology.
- a disclosure relating to a configuration may apply to all configurations, or one or more configurations.
- a phrase such as a configuration may refer to one or more configurations and vice versa.
- example is used herein to mean “serving as an example or illustration.” Any aspect or design described herein as “example” is not necessarily to be construed as preferred or advantageous over other aspects or designs.
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Abstract
A semiconductor device includes a substrate and a first semiconductor layer disposed on the substrate. The semiconductor device also includes a buried oxide layer disposed on the first semiconductor layer. A second semiconductor layer that comprises a first gate region, a drain region, and a source region is disposed on the buried oxide layer. The first gate region is positioned between the source and drain regions. A first shallow trench isolation is disposed between the drain region and the first semiconductor layer. The first shallow trench isolation is extended from the second semiconductor layer to the first semiconductor layer. The semiconductor device further includes a second gate region.
Description
- The present application is a continuation of the U.S. patent application Ser. No. 15/887,932 entitled “LATERALLY DIFFUSED MOSFET ON FULLY DEPLETED SOI HAVING LOW ON-RESISTANCE,” filed on Feb. 2, 2018, the disclosures of which is hereby incorporated by reference in its entirety for all purposes.
- The present description relates generally to integrated circuits, and more particularly, to laterally diffused MOSFETs on fully depleted silicon-on-insulator (SOI).
- Laterally diffused MOSFET (LDMOS) on fully depleted SOI (FDSOI) is gaining increased attention in semiconductor industry because it requires smaller dimensions compared to bulk LDMOS. Designing an LDMOS on FDSOI may form a drain that includes a lightly doped segment. The lightly doped drain (LDD) segment provides a voltage drop from the drain to edge of the gate that can help prevent gate dielectric breakdown. Thus, the LDMOS on FDSOI may support higher breakdown voltages compared to bulk LDMOS. However, the LDD segment also adds to the resistance of the LDMOS in on-state (on-resistance) which can be an issue in applications where fast turn on of the LDMOS is required. Therefore, providing an LDMOS on FDSOI with low resistance in on-state is highly desirable.
- Certain features of the subject technology are set forth in the appended claims. However, for purpose of explanation, several embodiments of the subject technology are set forth in the following figures.
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FIG. 1 illustrates an example of an LDMOS on FDSOI, according to some aspects of the disclosure. -
FIG. 2 illustrates an example of an LDMOS on FDSOI, according to some aspects of the disclosure. -
FIG. 3 illustrates a flow diagram of an example method and concept for creating an LDMOS on FDSOI, according to some aspects of the disclosure. - The detailed description set forth below is intended as a description of various configurations of the subject technology and is not intended to represent the only configurations in which the subject technology may be practiced. The appended drawings are incorporated herein and constitute a part of the detailed description. The detailed description includes specific details for the purpose of providing a thorough understanding of the subject technology. However, the subject technology is not limited to the specific details set forth herein and may be practiced without one or more of the specific details. In some instances, structures and components are shown in block diagram form in order to avoid obscuring the concepts of the subject technology.
- In one or more aspects of the subject technology, systems and configurations are described for providing LDMOS on FDSOI. FDSOI may be used for high performance processors because it may provide ultra-low power consumption electronics with drastically reduced leakage power. A channel of an LDMOS on FDSOI may be very thin and thus may not need to be doped. Using an un-doped channel may minimize random fluctuations in LDMOS voltage. Additionally, there is no floating body effect in an LDMOS on FDSOI and consequently it is easier to control short-channel effects. In addition, compared to bulk LDMOS, an LDMOS on FDSOI may require smaller dimensions for the same voltage level.
- In one or more aspects of the subject technology, an LDMOS on FDSOI with reduced resistance in on-state is described. A drain region of the LDMOS on FDSOI may include a lightly doped segment. The lightly doped drain (LDD) segment may help prevent a gate dielectric breakdown and increase drain to source voltage, which the LDMOS can tolerate. However, the LDD segment may contribute to the on-state resistance of the LDMOS. The higher on-state resistance may become an issue when fast turn on of the LDMOS is required. To reduce the on-state resistance, or likewise, to increase the drain to source current in the on-state, the gate voltage may concurrently be applied at two locations of the LDMOS circuit. First, the gate voltage is applied to the channel to create an inversion layer in the channel. Second, the gate voltage may be applied to a semiconductor well behind the buried oxide layer to create a back bias and thus enhance the drain to source current. By enhancing the drain to source current in the on-state of the LDMOS, in effect the resistance between the drain and source in the on-state may be reduced up to 30%. Additionally, applying the gate voltage to the semiconductor well behind the buried oxide layer may have no effect on performance of the LDMOS in the off-state.
- An LDMOS on FDSOI with reduced on-state resistance can be detected during failure analysis and device characteristics measurements. Because a removal of SOI in certain areas may be performed without adding to the process steps, connecting the gate voltage to the semiconductor well does not require an extra mask or process step. Additionally, the formation of the LDD segment is similar to the process that adjusts the threshold voltage of a MOSFET and thus does not require an additional process step.
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FIG. 1 illustrates an example of an LDMOS on FDSOI, according to some aspects of the disclosure. LDMOS 100 includessubstrate 102 andfirst semiconductor layer 104 wherefirst semiconductor layer 104 is disposed onsubstrate 102. In some examples,first semiconductor layer 104 is an n-type diffusion layer such as an N well. LDMOS 100 includes buried oxide layer 106 (BOX layer) that is disposed onfirst semiconductor layer 104 andsecond semiconductor layer 108 that is disposed on top of buriedoxide layer 106. In some examples,second semiconductor layer 108 is created by a process that begins with growing an oxide layer on top of an additional substrate. Then the additional substrate may be flipped and bonded tosubstrate 102. As described,substrate 102 includessemiconductor layer 104. Thus, after bonding the grown oxide layer may attach tosemiconductor layer 104. A cut is made through a thickness of the additional substrate to create, on top of the grown oxide layer, a remaining semiconductor layer of the additional substrate. In some embodiments, the remaining semiconductor layer of the additional substrate issecond semiconductor layer 108 and the grown oxide layer is buriedoxide layer 106.Second semiconductor layer 108 may includefirst gate region 110, drainregion 112, andsource region 114.First gate region 110 may be positioned betweensource region 114 and drainregion 112 and may have a length of 100 nm to 400 nm. - LDMOS 100 further includes first
shallow trench isolation 116 that may be disposed betweendrain region 112 andfirst semiconductor layer 104. Firstshallow trench isolation 116 may be positioned betweenfirst end 134 ofsecond semiconductor layer 108 andfirst semiconductor layer 104. Firstshallow trench isolation 116 may extend fromsecond semiconductor layer 108 tofirst semiconductor layer 104. Also,second gate region 120 may be disposed onfirst semiconductor layer 104 away fromsecond semiconductor layer 108 and between firstshallow trench isolation 116 and secondshallow trench isolation 118. Secondshallow trench isolation 118 may extend fromsecond gate region 120 tofirst semiconductor layer 104. Additionally,gate node 130 may be coupled tofirst gate region 110 andsecond gate region 120.Gate node 130 may apply a same gate voltage tofirst gate region 110 andsecond gate region 120 such that the gate voltage may also be applied to thefirst semiconductor layer 104. Applying the gate voltage viasecond gate region 120 tofirst semiconductor layer 104 during an on-state ofLDMOS 100 may create a back bias offirst gate region 110. In some examples, the gate voltage is between 0.6 volts to 1.8 volts. - LDMOS 100 further includes third
shallow trench isolation 122 that may be disposed betweensource region 114 andfirst semiconductor layer 104. Thirdshallow trench isolation 122 may be positioned betweensecond end 136 ofsecond semiconductor layer 108 and first semiconductor layer 104 (N well). Thirdshallow trench isolation 122 may extend fromsecond semiconductor layer 108 tofirst semiconductor layer 104 to isolatesource region 114 fromfirst semiconductor layer 104. - In some examples, first
shallow trench isolation 116; secondshallow trench isolation 118, and thirdshallow trench isolation 122 are made of a dielectric material such as silicon oxide.Shallow trench isolations - In some embodiments,
second semiconductor layer 108 includingfirst gate region 110 is very thin, e.g., between 20 nm and 35 nm.First gate region 110 is not doped and is fully depleted of mobile charges. In some examples, buriedoxide layer 106 is also very thin, e.g., between 10 nm and 30 nm. - In some embodiments,
second semiconductor layer 108 may be created as an un-doped layer. Then indrain region 112 and source region 114 n-type dopants are deposited. In some embodiments,source region 114 is a highly doped n-type (N+) semiconductor. In some embodiments,drain region 112 includes two adjacent n-type segments,first drain segment 112A andsecond drain segment 112B.First drain segment 112A is a lightly doped n-type segment that may be called lightly doped drain (LDD).Second drain segment 112B is N+, a highly doped n-type.First drain segment 112A is in contact withfirst gate region 110. LDD segment is positioned betweensecond drain segment 112B andfirst gate region 110 and may be used to provide a voltage drop fromsecond drain segment 112B to an edge offirst gate region 110. The voltage drop may reduce the electric field intensity infirst gate region 110. By reducing the electric field intensity infirst gate region 110, a gate dielectric breakdown can be prevented. Also, the N+second drain segment 112B is used for creating an ohmic contact with a drain node (not shown). The N+ source region 114 may also be used for creating an ohmic contact with a source node (not shown). In some embodiments,second gate region 120 is also an N+ region to create an ohmic contact withgate node 130. - In some examples, when
LDMOS 100 is turned on,first drain segment 112A ofdrain region 112 that is lightly doped has a higher resistance thansecond drain segment 112B that is highly doped. Therefore,first drain segment 112A may contribute more thansecond drain segment 112B to the resistance betweendrain region 112 andsource region 114 ofLDMOS 100. Thus, lightly dopedfirst drain segment 112A may increase the resistance ofLDMOS 100 in the on-state. - In some embodiments,
substrate 102 is not doped andfirst semiconductor layer 104 is a deposited N well. In some examples,substrate 102 is lightly doped p-type andfirst semiconductor layer 104 is an N well in the lightly doped p-type substrate. - In some embodiments, when a positive bias is applied to
second gate region 120 ofLDMOS 100, a positive threshold voltage ofLDMOS 100 decreases. Decreasing the threshold voltage may cause a current betweendrain region 112 andsource region 114 to increase. In some examples, whenLDMOS 100 is turned on a voltage of about 1.8 volts may be applied to the gate node and the source node may be grounded. - In some embodiments,
gate node 130 ofLDMOS 100 couples tofirst gate region 110 via high dielectricconstant oxide layer 132,tri-nitride layer 126, andpolysilicon layer 124. In some embodiments, low dielectric constantsilicon Nitride layer 128 covers the coupling. In some examples, a material ofgate node 130 that couplesfirst gate region 110 tosecond gate region 120 is a metal made of tungsten or cobalt. In some examples,LDMOS 100 is forward biased and a gate voltage is applied betweenfirst gate region 110 andsource region 114. The gate voltage is a positive voltage above threshold voltage ofLDMOS 100. Then, an inversion layer is formed infirst gate region 110 that cause a current to flow fromdrain region 112 to sourceregion 114. As described, applying the positive bias tosecond gate region 120 ofLDMOS 100, may act as a back bias and thus may increase the current fromdrain region 112 to sourceregion 114. In some embodiments,LDMOS 100 is reverse biased and the gate voltage offirst gate region 110 is zero or a negative voltage that is applied betweenfirst gate region 110 andsource region 114. In some examples, applying the negative bias tosecond gate region 120 ofLDMOS 100 does not affect a performance ofLDMOS 100 when reversed biased. -
FIG. 2 illustrates an example of an LDMOS on FDSOI, according to some aspects of the disclosure.LDMOS 200 includessubstrate 202 and first semiconductor layer 204 where first semiconductor layer 204 is disposed onsubstrate 202. In some examples, first semiconductor layer 204 is a p-type diffusion layer such as a P well.LDMOS 200 includes buried oxide layer 206 (BOX) that is disposed on first semiconductor layer 204 andsecond semiconductor layer 208 that is disposed on top of buriedoxide layer 206. In some examples,second semiconductor layer 208 is disposed on top of buriedoxide layer 206 by a same process described above for creatingsecond semiconductor layer 108.Second semiconductor layer 208 may includefirst gate region 210,drain region 212, andsource region 214.First gate region 210 may be positioned betweensource region 214 and drainregion 212. - In some embodiments,
LDMOS 200 has a same structure asLDMOS 100. Additionally, inLDMOS 200source region 214,drain region 212, andsecond gate region 220 as well as first semiconductor layer 204 are p-type semiconductors. Also,source region 214,second gate region 220, andsecond drain segment 212B are highly doped p-type (P+) semiconductors.LDMOS 200 is described in more details with respect tomethod 300 ofFIG. 3 . - Additionally,
gate node 230 ofLDMOS 200 couples tofirst gate region 210 via high dielectricconstant oxide layer 232,tri-nitride layer 226, andpolysilicon layer 224. In some embodiments, low dielectric constant silicon Nitride layer 228 covers the coupling. In some examples, a material ofgate node 230 that couplesfirst gate region 210 tosecond gate region 220 is a metal made of tungsten or cobalt. In some embodiments,LDMOS 200 is forward biased and a gate voltage is applied betweenfirst gate region 210 andsource region 214. The gate voltage is a negative voltage below a negative threshold voltage ofLDMOS 200. Then, an inversion layer is formed infirst gate region 210 that cause a current to flow betweensource region 214 and drainregion 212. In some examples, applying the negative bias tosecond gate region 220 ofLDMOS 200, may act as a back bias and thus may increase the current flow fromsource region 214 to drainregion 212. In some embodiments,LDMOS 200 is reverse biased and the gate voltage offirst gate region 210 is zero or a positive voltage that is applied betweenfirst gate region 210 andsource region 214. In some examples, applying the positive bias tosecond gate region 220 ofLDMOS 200, does not affect a performance ofLDMOS 200 when reversed biased. - In some embodiments and returning back to
FIGS. 1 and 2 , the P well and the N well may have a dopant concentration of about 10 18 and the N+ and the P+ regions have a dopant concertation between 5×1019 and 5×1020. Lightly dopedfirst drain segments -
FIG. 3 illustrates a flow diagram of an example method and concept for creating an LDMOS on FDSOI, according to some aspects of the disclosure. Notably, one or more steps ofmethod 300 described herein may be omitted, performed in a different sequence, and/or combined with other methods for various types of applications contemplated herein.Method 300 can be performed for creatingLDMOS FIGS. 1 or 2 . - As show in
FIG. 3 , atstep 302, a first semiconductor layer is disposed on a substrate. In addition, a buried oxide layer is disposed on the first semiconductor layer. Referring toFIG. 1 , first semiconductor layer 104 (N well) may be disposed, e.g., created, onsubstrate 102 and buriedoxide layer 106 may be disposed on top offirst semiconductor layer 104. Referring toFIG. 2 , first semiconductor layer 204 (P well) may be disposed onsubstrate 202 and buriedoxide layer 206 may be disposed on top of first semiconductor layer 204. In some embodiments, first semiconductor layers 104 and 204 are diffused layers. In some examples, buriedoxide layers - At
step 304, a second semiconductor layer is disposed on the buried oxide layer. In addition, a first gate region, a drain region, and a source region are created in the second semiconductor layer. In some embodiments as shown inFIG. 1 ,second semiconductor layer 108 is disposed on buriedoxide layer 106. Then sourceregion 114,first gate region 110, and drainregion 112 are created insecond semiconductor layer 108. In some examples,first gate region 110 is not doped,source region 114 is N+, and the n-type drain region 112 includesfirst drain segment 112A that is lightly doped andsecond drain segment 112B that is N+. In some embodiments as shown inFIG. 2 ,second semiconductor layer 208 is disposed on buriedoxide layer 206. Then sourceregion 214,first gate region 210, and drainregion 212 are created insecond semiconductor layer 208. In some examples,first gate region 210 is not doped,source region 214 is P+, and the p-type drain region 212 includesfirst drain segment 212A that is lightly doped andsecond drain segment 212B that is P+. In some embodiments and referring toFIGS. 1 and 2 , second semiconductor layers 108 and 208 are not doped when created. The dopants in the source and drain regions are then deposited and annealed. In some examples,second drain segments source regions - As described,
buried oxide layers substrates oxide layers substrates - At
step 306, a first shallow trench isolation is disposed between the drain region of the second semiconductor layer and the first semiconductor layer. In some embodiments as shown inFIG. 1 , firstshallow trench isolation 116 is disposed atfirst end 134 ofsecond semiconductor layer 108. Firstshallow trench isolation 116 is disposed betweendrain region 112 ofsecond semiconductor layer 108 andfirst semiconductor layer 104. Firstshallow trench isolation 116 is extended fromdrain region 112 tofirst semiconductor layer 104. In some embodiments as shown inFIG. 2 , firstshallow trench isolation 216 is disposed atfirst end 234 ofsecond semiconductor layer 208. Firstshallow trench isolation 216 is disposed betweendrain region 212 ofsecond semiconductor layer 208 and first semiconductor layer 204. Firstshallow trench isolation 216 is extended fromdrain region 212 to first semiconductor layer 204. In some examples and referring toFIGS. 1 and 2 ,shallow trench isolations oxide layers second semiconductor layer oxide layers shallow trench isolations drain regions shallow trench isolations Shallow trench isolations source regions shallow trench isolations LDMOS 100 andLDMOS 200 from other LDMOS devices onsubstrates - At
step 308, a section of the buried oxide layer next to the first shallow trench isolation is etched to create an exposed region on the first semiconductor layer. As discussed above and referring toFIGS. 1 and 2 , buriedoxide layers second semiconductor layer oxide layers shallow trench isolations Buried oxide layers shallow trench isolations second gate regions - At
step 310, a second gate region is disposed on the exposed region between the first shallow trench isolation and a second shallow trench isolation. Referring toFIGS. 1 and 2 ,second gate regions Second gate regions shallow trench isolations second gate regions shallow trench isolations LDMOS 100 andLDMOS 200 from other LDMOS devices insubstrates - At
step 312, a gate node is coupled to the first and second gate regions. As shown inFIG. 1 ,gate node 130 may be coupled tofirst gate region 110 andsecond gate region 120. As discussed,gate node 130 may be coupled tosecond gate region 120 through an ohmic contact such that a positive gate voltage may be applied tofirst semiconductor layer 104 in an on-state ofLDMOS 100. The positive gate voltage may create a back bias forfirst gate region 110 in the on-state when the gate node is positively biased with respect to sourceregion 114. The back bias may increase a flow of current fromdrain region 112 to sourceregion 114 whenLDMOS 100 is forward biased. Equivalently, the back bias may decrease a resistance between the drain region and source region. - Similarly, as shown in
FIG. 2 ,gate node 230 may be coupled tofirst gate region 210 andsecond gate region 220.Gate node 230 may be coupled tosecond gate region 220 through an ohmic contact such that a negative gate voltage may be applied to first semiconductor layer 204 in an on-state ofLDMOS 200. The negative gate voltage may create a back bias forfirst gate region 210 in the on-state when the gate node is negatively biased with respect to thesource region 214. The back bias may increase a flow of current fromsource region 214 to drainregion 212 whenLDMOS 200 is forward biased. Equivalently, the back bias may decrease a resistance between the drain region and source region. In some examples, by connecting the gate node to the second gate region, a resistance between the drain and source regions is reduced by 30%. - The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. Pronouns in the masculine (e.g., his) include the feminine and neuter gender (e.g., her and its) and vice versa. Headings and subheadings, if any, are used for convenience only and do not limit the subject disclosure.
- The predicate words “configured to,” “operable to,” and “programmed to” do not imply any particular tangible or intangible modification of a subject, but, rather, are intended to be used interchangeably. For example, a processor configured to monitor and control an operation or a component may also mean the processor being programmed to monitor and control the operation or the processor being operable to monitor and control the operation. Likewise, a processor configured to execute code can be construed as a processor programmed to execute code or operable to execute code.
- A phrase such as an “aspect” does not imply that such aspect is essential to the subject technology or that such aspect applies to all configurations of the subject technology. A disclosure relating to an aspect may apply to all configurations, or one or more configurations. A phrase such as an aspect may refer to one or more aspects and vice versa. A phrase such as a “configuration” does not imply that such configuration is essential to the subject technology or that such configuration applies to all configurations of the subject technology. A disclosure relating to a configuration may apply to all configurations, or one or more configurations. A phrase such as a configuration may refer to one or more configurations and vice versa.
- The word “example” is used herein to mean “serving as an example or illustration.” Any aspect or design described herein as “example” is not necessarily to be construed as preferred or advantageous over other aspects or designs.
- All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. § 112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.” Furthermore, to the extent that the term “include,” “have,” or the like is used in the description or the claims, such term is intended to be inclusive in a manner similar to the term “comprise” as “comprise” is interpreted when employed as a transitional word in a claim.
Claims (20)
1. A semiconductor device, comprising:
a substrate;
a first semiconductor layer disposed on the substrate;
a buried oxide layer disposed on the first semiconductor layer;
a second semiconductor layer disposed on the buried oxide layer, wherein the second semiconductor layer comprises a first gate region, a drain region, and a source region, and wherein the first gate region is positioned between the source and the drain regions;
a first shallow trench isolation disposed between the drain region at a first end of the second semiconductor layer and the first semiconductor layer, wherein the first shallow trench isolation is extended from the second semiconductor layer to the first semiconductor layer; and
a second gate region.
2. The semiconductor device of claim 1 , wherein the second gate region is disposed on the first semiconductor layer away from the second semiconductor layer and between the first shallow trench isolation and a second shallow trench isolation.
3. The semiconductor device of claim 1 , wherein the drain region comprises a lightly doped segment and a highly doped segment of a same dopant type, wherein the highly doped segment comprises a larger dopant concentration compared to the lightly doped segment.
4. The semiconductor device of claim 3 , wherein the lightly doped segment of the drain region is formed between the first gate region and the highly doped segment of the drain region.
5. The semiconductor device of claim 1 , wherein the second semiconductor layer has a first side in contact with the buried oxide layer, and wherein a gate node, a source node, and a drain node are respectively coupled to the first gate region, the source region, and the drain region on a second side of the second semiconductor layer opposite to the first side of the second semiconductor layer.
6. The semiconductor device of claim 1 , further comprising:
a third shallow trench isolation extending from the second semiconductor layer to the first semiconductor layer and disposed between the source region at a second end of the second semiconductor layer and the first semiconductor layer.
7. The semiconductor device of claim 6 , wherein the first shallow trench isolation is configured to isolate the drain region from the first semiconductor layer, and wherein a second shallow trench isolation is extended from the second gate region to the first semiconductor layer, and the third shallow trench isolation is configured to isolate the source region from the first semiconductor layer.
8. The semiconductor device of claim 1 , wherein the first semiconductor layer is a doped well in the substrate.
9. The semiconductor device of claim 1 , further comprising applying a gate voltage to the second gate region to increase a magnitude of a drain to source current in an on-state.
10. The semiconductor device of claim 1 , wherein the source region, the drain region, the second gate region, and the first semiconductor layer are n-type doped, and wherein first gate region in not doped.
11. The semiconductor device of claim 1 , wherein the source region, the drain region, the second gate region, and the first semiconductor layer are p-type doped, and wherein first gate region in not doped.
12. The semiconductor device of claim 1 , wherein a gate node is coupled to the first gate region and the second gate region and is configured to apply a gate voltage to the first gate region and the second gate region.
13. An apparatus comprising:
a first semiconductor layer disposed on a first substrate;
a buried oxide layer disposed on the first semiconductor layer;
a second semiconductor layer disposed on the buried oxide layer;
a first gate region, a drain region, and a source region disposed in the second semiconductor layer, wherein the first gate region is positioned between the source and the drain regions;
a first shallow trench isolation disposed between the drain region at a first end of the second semiconductor layer and the first semiconductor layer; and
a second gate region formed on an etched region on the first semiconductor layer.
14. The apparatus of claim 13 , further comprising a gate node configured to apply a gate voltage to the first gate region and the second gate region, and wherein an etched section of the buried oxide layer is next to the first shallow trench isolation and farther from the drain region.
15. The apparatus of claim 13 , wherein the first shallow trench isolation is extended from the second semiconductor layer to the first semiconductor layer, and wherein the drain region is isolated from the first semiconductor layer by the first shallow trench isolation.
16. The apparatus of claim 13 , wherein the drain region comprises a lightly doped segment and a highly doped segment of a same dopant type, wherein the highly doped segment comprises a larger dopant concentration compared to the lightly doped segment, and wherein the lightly doped segment of the drain region is arranged between the first gate region and the highly doped segment of the drain region.
17. The apparatus of claim 13 , further comprising a third shallow trench isolation disposed between the source region at a second end of the second semiconductor layer and the first semiconductor layer, wherein the third shallow trench isolation is extended from the second semiconductor layer to the first semiconductor layer, the source region is isolated from the first semiconductor layer by the third shallow trench isolation, and a second shallow trench isolation is extended from the second gate region to the first semiconductor layer.
18. The apparatus of claim 17 , wherein the second gate region is disposed between the first shallow trench isolation and the second shallow trench isolation.
19. A laterally diffused n-type MOSFET device, the device comprising:
a first gate region configured to be biased by using a positive gate voltage above a predetermined threshold voltage;
a second gate region disposed on an etched region of a first semiconductor layer between a first shallow trench isolation and a second shallow trench isolation and configured to be biased using the positive gate voltage;
a source region; and
a drain region,
wherein:
the first gate region is configured to operate based on an inversion layer generated by using the positive gate voltage to the first gate region; and
the second gate region is configured to operate based on a back bias generated by using the positive gate voltage to the second gate region.
20. The device of claim 19 , wherein the first shallow trench isolation is between the drain region at a first end of a second semiconductor layer and the first semiconductor layer disposed beneath the second semiconductor layer, and wherein the inversion layer and the back bias enable flow of a current from the drain region to the source region.
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US16/389,315 US20190245082A1 (en) | 2018-02-02 | 2019-04-19 | Laterally diffused mosfet on fully depleted soi |
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US15/887,932 US10312365B1 (en) | 2018-02-02 | 2018-02-02 | Laterally diffused MOSFET on fully depleted SOI having low on-resistance |
US16/389,315 US20190245082A1 (en) | 2018-02-02 | 2019-04-19 | Laterally diffused mosfet on fully depleted soi |
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CN112750911B (en) * | 2021-02-03 | 2022-06-17 | 南京邮电大学 | LDMOS with controllable three-dimensional electric field and preparation method thereof |
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US20060081836A1 (en) * | 2004-10-14 | 2006-04-20 | Yoshinobu Kimura | Semiconductor device and method of manufacturing the same |
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US5650340A (en) * | 1994-08-18 | 1997-07-22 | Sun Microsystems, Inc. | Method of making asymmetric low power MOS devices |
US6664598B1 (en) * | 2002-09-05 | 2003-12-16 | International Business Machines Corporation | Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control |
US7169654B2 (en) * | 2004-11-15 | 2007-01-30 | Freescale Semiconductor, Inc. | Method of forming a semiconductor device |
US8159008B2 (en) * | 2009-09-18 | 2012-04-17 | International Business Machines Corporation | Method of fabricating a trench-generated transistor structure |
CN103050525B (en) * | 2011-10-12 | 2015-06-17 | 中国科学院微电子研究所 | MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and manufacturing method thereof |
US8709890B2 (en) * | 2011-12-12 | 2014-04-29 | International Business Machines Corporation | Method and structure for forming ETSOI capacitors, diodes, resistors and back gate contacts |
CN103594517A (en) * | 2013-10-24 | 2014-02-19 | 中国科学院上海微***与信息技术研究所 | Multi-gate SOI-LDMOS device structure |
CN104201193A (en) * | 2014-09-28 | 2014-12-10 | 中国科学院上海微***与信息技术研究所 | Double-gate SOI (Signal Operation Instruction) device structure and manufacturing method thereof |
US9923527B2 (en) * | 2016-05-06 | 2018-03-20 | Globalfoundries Inc. | Method, apparatus and system for back gate biasing for FD-SOI devices |
US9865607B1 (en) * | 2016-06-27 | 2018-01-09 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method of making a fully depleted semiconductor-on-insulator programmable cell and structure thereof |
US9893157B1 (en) * | 2017-01-09 | 2018-02-13 | Globalfoundries Inc. | Structures with contact trenches and isolation trenches |
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