US20180191047A1 - Structure with integrated metallic waveguide - Google Patents

Structure with integrated metallic waveguide Download PDF

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Publication number
US20180191047A1
US20180191047A1 US15/395,197 US201615395197A US2018191047A1 US 20180191047 A1 US20180191047 A1 US 20180191047A1 US 201615395197 A US201615395197 A US 201615395197A US 2018191047 A1 US2018191047 A1 US 2018191047A1
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Prior art keywords
waveguide
carrier
metallic
features
bonded
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US15/395,197
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US10276909B2 (en
Inventor
Shaowu HUANG
Javier A. Delacruz
Belgacem Haba
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Adeia Semiconductor Bonding Technologies Inc
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Ziptronix Inc
Invensas Bonding Technologies Inc
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Priority to US15/395,197 priority Critical patent/US10276909B2/en
Assigned to ZIPTRONIX, INC. reassignment ZIPTRONIX, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DELACRUZ, JAVIER A., HABA, BELGACEM, HUANG, SHAOWU
Assigned to INVENSAS BONDING TECHNOLOGIES, INC. reassignment INVENSAS BONDING TECHNOLOGIES, INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: ZIPTRONIX , INC.
Priority to PCT/US2017/064735 priority patent/WO2018125527A1/en
Publication of US20180191047A1 publication Critical patent/US20180191047A1/en
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Assigned to BANK OF AMERICA, N.A. reassignment BANK OF AMERICA, N.A. SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DTS, INC., IBIQUITY DIGITAL CORPORATION, INVENSAS BONDING TECHNOLOGIES, INC., INVENSAS CORPORATION, PHORUS, INC., ROVI GUIDES, INC., ROVI SOLUTIONS CORPORATION, ROVI TECHNOLOGIES CORPORATION, TESSERA ADVANCED TECHNOLOGIES, INC., TESSERA, INC., TIVO SOLUTIONS INC., VEVEO, INC.
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00Waveguides; Transmission lines of the waveguide type
    • H01P3/12Hollow waveguides
    • H01P3/122Dielectric loaded (not air)
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00Waveguides; Transmission lines of the waveguide type
    • H01P3/16Dielectric waveguides, i.e. without a longitudinal conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00Auxiliary devices
    • H01P1/20Frequency-selective devices, e.g. filters
    • H01P1/2002Dielectric waveguide filters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00Auxiliary devices
    • H01P1/32Non-reciprocal transmission devices
    • H01P1/38Circulators
    • H01P1/383Junction circulators, e.g. Y-circulators
    • H01P1/39Hollow waveguide circulators
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P11/00Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
    • H01P11/001Manufacturing waveguides or transmission lines of the waveguide type
    • H01P11/003Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P11/00Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
    • H01P11/001Manufacturing waveguides or transmission lines of the waveguide type
    • H01P11/006Manufacturing dielectric waveguides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00Waveguides; Transmission lines of the waveguide type
    • H01P3/12Hollow waveguides
    • H01P3/121Hollow waveguides integrated in a substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00Coupling devices of the waveguide type
    • H01P5/08Coupling devices of the waveguide type for linking dissimilar lines or devices
    • H01P5/10Coupling devices of the waveguide type for linking dissimilar lines or devices for coupling balanced lines or devices with unbalanced lines or devices
    • H01P5/107Hollow-waveguide/strip-line transitions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00Coupling devices of the waveguide type
    • H01P5/12Coupling devices having more than two ports
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00Coupling devices of the waveguide type
    • H01P5/08Coupling devices of the waveguide type for linking dissimilar lines or devices
    • H01P5/10Coupling devices of the waveguide type for linking dissimilar lines or devices for coupling balanced lines or devices with unbalanced lines or devices
    • H01P5/103Hollow-waveguide/coaxial-line transitions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00Coupling devices of the waveguide type
    • H01P5/12Coupling devices having more than two ports
    • H01P5/16Conjugate devices, i.e. devices having at least one port decoupled from one other port
    • H01P5/18Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers
    • H01P5/181Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers the guides being hollow waveguides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00Coupling devices of the waveguide type
    • H01P5/12Coupling devices having more than two ports
    • H01P5/16Conjugate devices, i.e. devices having at least one port decoupled from one other port
    • H01P5/19Conjugate devices, i.e. devices having at least one port decoupled from one other port of the junction type
    • H01P5/22Hybrid ring junctions
    • H01P5/222180° rat race hybrid rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00Coupling devices of the waveguide type
    • H01P5/12Coupling devices having more than two ports
    • H01P5/16Conjugate devices, i.e. devices having at least one port decoupled from one other port
    • H01P5/19Conjugate devices, i.e. devices having at least one port decoupled from one other port of the junction type
    • H01P5/22Hybrid ring junctions
    • H01P5/22790° branch line couplers

Definitions

  • the field relates to structures with integrated waveguides, and in particular, to interconnects and circuit structures with integrated metallic waveguides.
  • multiple integrated device dies may be mounted to a carrier and may communicate with one another in a variety of ways.
  • two integrated device dies can communicate with one another by way of conductive traces or interconnects provided in an intervening package substrate such as a printed circuit board (PCB) or in a silicon interposer.
  • a silicon bridge or other interconnect structure can serve to electrically connect two dies within a package or system.
  • existing die-to-die interconnects may experience high losses due to conductor loss, crosstalk or other factors. Accordingly, there remains a continuing need for improved die-to-die communications.
  • FIG. 1 is a schematic side sectional view of a structure that includes integrated waveguides, according to some embodiments.
  • FIG. 2 is schematic perspective view of a waveguide according to various embodiments.
  • FIG. 3A is a schematic perspective view of a structure with an integrated waveguide, according to various embodiments.
  • FIG. 3B is a schematic side cross-sectional view of a first waveguide portion disposed between integrated device dies and a carrier.
  • FIG. 3C is a schematic side cross-sectional view a second waveguide portion disposed along and under a gap between the integrated device dies.
  • FIG. 4A is a schematic perspective view of a waveguide with metallic features that comprise continuous segments, prior to bonding.
  • FIG. 4B is a schematic perspective view of a waveguide in which portions of conductive features are patterned with discontinuities or gaps to avoid dishing.
  • FIG. 4C is a schematic perspective view of a waveguide in which both conductive features are patterned with discontinuities or gaps along their lengths to avoid dishing.
  • FIG. 5 is a schematic perspective view of a structure with a waveguide embedded in a carrier comprising a semiconductor element, prior to bonding of the dies to the carrier.
  • FIG. 6 is a schematic side view of a structure comprising a bridge between two dies that includes an integrated waveguide therein.
  • FIG. 7A is a top plan view of a power divider that incorporates any of the waveguides described herein.
  • FIG. 7B is a top plan view of a coupler that incorporates the waveguides described herein.
  • FIG. 7C is a top plan view of a circulator that incorporates the waveguides described herein.
  • FIG. 7D is a top plan view of a filter that incorporates the waveguides disclosed herein.
  • FIG. 8 is a schematic system diagram of an electronic system incorporating one or more structures, according to various embodiments.
  • Various embodiments disclosed herein relate to interconnects and structures with integrated waveguides, e.g., integrated conductive or metallic waveguides.
  • integrated waveguides e.g., integrated conductive or metallic waveguides.
  • existing techniques for providing die-to-die (or chip-to-chip) communications within a package or system may not provide adequate performance at high frequencies.
  • some die-to-die interconnects may experience high current densities which can lead to high losses due to conductor loss, crosstalk and other factors.
  • millimeter wave or sub-terahertz communications over a range of tens of gigahertz to hundreds of gigahertz (e.g., in a range of 10 GHz to 950 GHz, in a range of 20 GHz to 900 GHz) using coplanar or microstrip waveguides since such devices may be lossy at millimeter-sized wavelengths.
  • the embodiments disclosed herein beneficially enable the use of lower loss metallic waveguides for die-to-die communications, including communications at wavelengths in a range of 0.1 mm to 10 mm.
  • a metallic or conductive waveguide can comprise an effectively closed metallic or conductive channel as viewed from a side cross-section taken perpendicular to a propagation direction of the waveguide, and can include a low loss dielectric material within the effectively closed channel.
  • the metallic or conductive waveguide can comprise a metal, including metallic compounds.
  • the metallic waveguide can be defined by bonding two elements (e.g., two semiconductor elements) along an interface, with the waveguide defined at least in part by the interface. In some embodiments, the two elements can be directly bonded to one another without an intervening adhesive.
  • the metallic waveguide can be at least partially (e.g., completely) embedded in an element and can include one or a plurality of ports that can receive a radiating element for coupling electromagnetic waves to the waveguide.
  • the disclosed embodiments can therefore provide die-to-die communications with low loss and with little or no crosstalk, which can enable high frequency die-to-die communications.
  • the resulting structure can be constructed at lower costs than other techniques, since the waveguides can be constructed using the bonding layers defined for directly bonding two elements to one another.
  • the integrated waveguides disclosed herein can also advantageously reduce the number of radio frequency (RF) components provided in the package, since the waveguides described herein can be directly integrated into the dies and/or other elements.
  • RF radio frequency
  • FIG. 1 is a schematic side sectional view of a structure 1 that includes an integrated waveguide 10 (e.g., an integrated metallic or otherwise conductive waveguide), according to some embodiments.
  • the structure 1 can include a plurality of elements 2 mounted to another element, e.g., a carrier 3 .
  • the elements 2 can comprise a first integrated device die 2 a, a second integrated device die 2 b, and a third integrated device die 2 c, each of which are electrically and mechanically connected to the carrier 3 .
  • the device dies 2 a - 2 c can comprise processor dies, memory dies, sensor dies, communications dies, microelectromechanical systems (MEMS) dies, or any other suitable type of device.
  • MEMS microelectromechanical systems
  • the carrier 3 may be any suitable type of element, such as an integrated device die, an interposer, a reconstituted die or wafer, etc.
  • the elements 2 a - 2 c are shown as being mounted to the carrier 3 by way of a direct bond, but in other embodiments, the elements can be connected to the carrier in other ways.
  • the elements 2 a - 2 c and the carrier 3 comprise semiconductor elements (e.g., integrated device dies 2 a - 2 c, a semiconductor interposer, etc.), but in other embodiments, the elements and/or the carrier can comprise other types of elements that may or may not comprise a semiconductor material, such as various types of optical devices (e.g., lenses, filters, etc.).
  • the dies 2 a - 2 c can be laterally spaced from one another along the carrier 3 .
  • one or more of the device dies 2 a - 2 c are directly bonded to the carrier 3 without an intervening adhesive.
  • the direct bond between the dies 2 a - 2 c and the carrier 3 can include a direct bond between corresponding conductive features of the dies 2 a - 2 c (e.g., a processor die) and the carrier 3 (e.g., an integrated device die, an interposer, etc.) without an intervening adhesive, without being limited thereto.
  • the conductive features may be surrounded by non-conductive field regions.
  • respective bonding surfaces of the conductive features and the non-conductive field regions can be prepared for bonding.
  • Preparation can include provision of a nonconductive layer, such as silicon oxide or silicon nitride, with exposed conductive features, such as metal bond pads or contacts.
  • a nonconductive layer such as silicon oxide or silicon nitride
  • exposed conductive features such as metal bond pads or contacts.
  • the bonding surfaces of at least the non-conductive field regions, or both the conductive and non-conductive regions, can be polished to a very high degree of smoothness (e.g., less than 20 nm surface roughness, or more particularly, less than 5 nm surface roughness).
  • the surfaces to be bonded may be terminated with a suitable species and activated prior to bonding.
  • the non-conductive surfaces (e.g., field regions) of the bonding layer to be bonded may be very slightly etched for activation and exposed to a nitrogen-containing solution and terminated with a nitrogen-containing species.
  • the surfaces to be bonded e.g., field regions
  • DBI direct bond interconnect
  • nonconductive features of the dies and the carrier can directly bond to one another, even at room temperature and without the application of external pressure, while the conductive features of the dies and the carrier layer can also directly bond to one another, without any intervening adhesive layers. Bonding by DBI forms stronger bonds than Van der Waals bonding, including significant covalent bonding between the surfaces of interest. Subsequent annealing can further strengthen bonds, particularly between conductive features of the bonding interfaces.
  • the respective conductive features can be flush with the exterior surfaces (e.g., the field regions) of the dies and the carrier. In other embodiments, the conductive features may extend above the exterior surfaces. In still other embodiments, the conductive features of one or both of the dies and the carrier are recessed relative to the exterior surfaces (e.g., nonconductive field regions) of the dies and the carrier. For example, the conductive features can be recessed relative to the field regions by less than 20 nm, e.g., less than 10 nm.
  • the nonconductive field regions (such as silicon oxide) of the dies 2 a - 2 c can be brought into contact with corresponding nonconductive regions of the carrier 3 .
  • the interaction of the activated surfaces can cause the nonconductive regions of the dies 2 a - 2 c to directly bond with the corresponding nonconductive regions of the carrier 3 without an intervening adhesive, without application of external pressure, without application of voltage, and at room temperature.
  • the bonding forces of the nonconductive regions can include covalent bonds that are greater than Van der Waals bonds and exert significant forces between the conductive features.
  • the bonding energy of the dielectric-dielectric surface can be in a range from 150-300 mJ/m 2 , which can increase to 1500-4000 mJ/m 2 after a period of heat treatment.
  • direct bonding of the nonconductive regions can facilitate direct metal-to-metal bonding between the conductive features.
  • the dies 2 a - 2 c and the carrier 3 may be heated after bonding at least the nonconductive regions. As noted above, such heat treatment can strengthen the bonds between the nonconductive regions, between the conductive features, and/or between opposing conductive and non-conductive regions.
  • the conductive features are recessed, there may be an initial gap between the conductive features of the dies 2 a - 2 c and the carrier 3 , and heating after initially bonding the nonconductive regions can expand the conductive elements to close the gap. Regardless of whether there was an initial gap, heating can generate or increase pressure between the conductive elements of the opposing parts, aid bonding of the conductive features and form a direct electrical and mechanical connection.
  • Direct bonding of the dies 2 a - 2 c to the carrier 3 can result in a bond interface 6 between the elements 2 and the carrier 3 .
  • the waveguide 10 can be defined along the interface 6 between the carrier 3 and the elements 2 (the dies 2 a - 2 c ).
  • the waveguide 10 can comprise a first waveguide portion 10 a that is defined by features at the respective lower surfaces 12 of the elements 2 and at an upper surface 5 of the carrier 3 . As explained below in connection with FIGS.
  • metallic and/or dielectric features exposed on the lower surfaces 12 of the dies 2 a - 2 c can cooperate with corresponding metallic and/or dielectric features exposed on the upper surface 5 of the carrier 3 to define the first waveguide portion 10 a of the waveguide 10 .
  • the waveguide 10 can also comprise a second waveguide portion 10 b disposed along gaps 4 between the integrated device dies 2 a - 2 c.
  • the second waveguide portion 10 b can be embedded in the carrier 3 and can be defined by a metallic channel at or near the upper surface 5 .
  • the waveguide 10 can enable die-to-die communications between the first die 2 a and the second die 2 b, and between the second die 2 b and the third die 2 c.
  • the integrated waveguide 10 disclosed herein can be used in conjunction with any suitable type of element.
  • the dies 2 a - 2 c are directly bonded to the carrier 3 without an intervening adhesive in the illustrated embodiment, in other embodiments, the dies 2 a - 2 c can be bonded to the carrier 3 in other ways, such as by way of a conductive adhesive, solder, etc.
  • FIG. 2 is schematic perspective view of a portion of the waveguide 10 according to various embodiments.
  • the waveguide 10 shown in FIG. 2 is a metallic waveguide that has a polygonal, and particularly rectangular, cross-section.
  • the waveguide 10 can comprise a channel 11 defined by a plurality of metallic walls 11 a - 11 d that cooperate to delimit an effectively closed cross-sectional profile, as viewed along a cross-section taken transverse to the propagation direction (i.e., the x-axis).
  • a dielectric material 7 can be disposed within the effectively closed metallic channel 11 .
  • the side section of the channel 11 is completely closed such that the walls 11 a - 11 d define a continuous, closed boundary about the dielectric material 7 .
  • the effectively closed metallic channel 11 may have gaps or spaces in portions of some of the walls 11 a - 11 d.
  • the metallic walls 11 a - 11 d of the channel 11 can comprise copper or other metal materials.
  • the dielectric material 7 can comprise any suitable dielectric, such as silicon oxide.
  • the walls 11 a - 11 d can be electrically grounded so as to provide a bounded pathway along which electromagnetic waves can propagate.
  • input signals or waves W can enter at a first end of the waveguide 10 and can propagate parallel to the x-axis and can exit as an output signal at another end of the waveguide 10 .
  • radiating elements 13 a, 13 b can be provided at both ends of the waveguide 10 to transmit and/or receive electromagnetic waves W along the waveguide 10 .
  • the width of the waveguide 10 along the y-direction can define the cutoff frequency for the propagating mode.
  • a first radiating element 13 a can radiate signals or waves W at frequencies that can propagate along the waveguide 10 .
  • the radiating elements 13 a, 13 b can comprise conductive segments or probes inserted into the dielectric material 7 within the channel 11 .
  • electromagnetic waves can be coupled to the waveguide 10 in other suitable ways.
  • the radiating elements 13 a, 13 b can comprise a conductive loop with the plane of the loop perpendicular to the lines of magnetic force, a linear conductor or probe that is parallel to the lines of electric force, or an aperture in a side wall of the waveguide 10 disposed along the direction of the lines of magnetic force on the side wall.
  • the signals or waves W can propagate along the waveguide 10 and can be received by another radiating element 13 b which can convert the waves W to an electrical current.
  • the waveguide 10 can be integrated or embedded in an element (such as an interposer or integrated device die), or at the bond interface 6 between two elements (e.g., at the interface 6 between the dies 2 a - 2 c and the carrier 3 ).
  • the waveguide 10 is straight or generally linear as it extends between two dies.
  • any of the waveguides 10 disclosed herein may bend, curve, or otherwise change directions so as to guide the waves to any desirable location in the structure 1 .
  • FIG. 3A is a schematic perspective view of a structure 1 with an integrated waveguide 10 , according to various embodiments.
  • FIG. 3B is a schematic side cross-sectional view of the first waveguide portion 10 a disposed at interfaces 6 between the dies 2 a, 2 b and the carrier 3 .
  • FIG. 3C is a schematic side cross-sectional view of the second waveguide portion 10 b disposed along and under the gap 4 between the dies 2 a, 2 b.
  • the waveguide 10 can include the first waveguide portion 10 a defined at the interfaces 6 between the dies 2 a - 2 b and the carrier 3 , as shown in FIG. 3B .
  • FIG. 3B is a schematic perspective view of a structure 1 with an integrated waveguide 10 , according to various embodiments.
  • FIG. 3B is a schematic side cross-sectional view of the first waveguide portion 10 a disposed at interfaces 6 between the dies 2 a, 2 b and the carrier 3 .
  • the first waveguide portion 10 a can be defined by first metallic features 14 a and first dielectric features 7 a formed in and/or on the respective integrated device dies 2 a, 2 b, and second metallic features 14 b and second dielectric features 7 b formed in and/or on the carrier 3 .
  • the first waveguide portion 10 a can be formed in any suitable manner, such as by damascene processes.
  • trenches or recesses can be defined in the lower surfaces 12 , which may be the active surfaces, of the dies 2 a - 2 b and in the upper surface 5 of the carrier 3 .
  • a metallic layer can be deposited along the bottom and sidewalls of the trenches to define the first and second metallic feature 14 a, 14 b.
  • the dielectric features 7 a, 7 b can be deposited within the trenches over the metallic features 14 a, 14 b in the dies 2 a, 2 b and the carrier 3 .
  • the upper surface 5 of the carrier 3 and the lower surface 12 of the dies 2 a, 2 b can be prepared for direct bonding as explained above.
  • the upper surface 5 and the lower surface 12 can be polished to a very high surface smoothness, and can be activated and terminated with a suitable species (e.g., nitrogen).
  • the metallic features 14 a, 14 b may be recessed relative to the dielectric features 7 a, 7 b (e.g., recessed below the dielectric features 7 a, 7 b by less than 20 nm, or by less than 10 nm).
  • the lower surfaces 12 of the dies 2 a, 2 b can be brought into contact with the upper surface 5 of the carrier 3 at room temperature to form a direct bond between at least the non-conductive field regions of the dies 2 a, 2 b and the carrier 3 (e.g., a direct bond between the dielectric features 7 a, 7 b disposed in each element).
  • the non-conductive regions can be directly bonded without application of pressure or voltage in some arrangements.
  • the structure 1 can be heated to increase the bond strength and/or to cause the metallic features 14 a, 14 b to form an electrical contact with one another.
  • the resulting bonded structure 1 can be bonded along the interface 6 , and the waveguide 10 can be defined at least in part along the bond interface 6 .
  • the first and second metallic features 14 a, 14 b and the associated dielectric features 7 a, 7 b can cooperate along the interface 6 to form the first waveguide portion 10 a of the waveguide 10 .
  • the first and second metallic features 14 a, 14 b can bond to one another such that the walls 11 c, 11 d can be formed from respective side portions of the features 14 a, 14 b (e.g., the portions of the metal that line the sidewalls of the trenches in the elements).
  • the walls 11 a, 11 b can be defined by the portions of the metal that line the bottoms of the trenches in the respective elements. As shown in the side sectional view of FIG. 3B , the metallic features 14 a, 14 b can cooperate to define an effectively closed metallic channel (e.g., a completely closed metallic channel in the arrangement of FIG. 3B ) disposed about the dielectric material 7 (which is defined by the respective dielectric features 7 a, 7 b ).
  • an effectively closed metallic channel e.g., a completely closed metallic channel in the arrangement of FIG. 3B
  • the direct bond between the metallic features 14 a, 14 b and between the dielectric features 7 a, 7 b can enable face down solutions (e.g., with each die's active surface facing the carrier 3 ) for die-to-die communications with improved electrical performance and lower losses for frequencies below 1 THz (e.g., greater than 22 GHz, or in a range of 22 GHz to 1 THz), as compared with other die-to-die interconnects.
  • face down solutions e.g., with each die's active surface facing the carrier 3
  • die-to-die communications with improved electrical performance and lower losses for frequencies below 1 THz (e.g., greater than 22 GHz, or in a range of 22 GHz to 1 THz), as compared with other die-to-die interconnects.
  • the second waveguide portion 10 b can be defined along and underlying the gaps 4 between the dies 4 a , 4 b.
  • the channel 11 can be defined by the second metallic portion 14 b formed in the carrier 3 and by a first metallic portion 14 a that can be deposited or adhered over the second metallic portion 14 b and the dielectric material 7 .
  • the first and second metallic portions 14 a, 14 b may be separately defined or integrated so as to cooperate to define the waveguide portion 10 b .
  • the second waveguide portion 10 b can accordingly be embedded or buried in the carrier 3 , with the upper wall 11 a defined by metal applied over the upper surface 5 of the carrier 3 .
  • the height of the second waveguide portion 10 b along the z-axis can be less than the height of the first waveguide portion 10 a along the z-axis, as shown in FIGS. 3B and 3C .
  • the height differential between the first and second waveguide portions 10 a, 10 b may introduce some impedance discontinuities, but the overall effect on electrical performance is negligible.
  • the width of the first and second waveguide portions 10 a, 10 b along the y-axis see FIG.
  • the second waveguide portion 10 b can be embedded within a carrier 3 , which can be a semiconductor element (such as an interposer, an integrated device die, a reconstituted die or wafer, etc.) in the illustrated embodiment.
  • a carrier 3 can be a semiconductor element (such as an interposer, an integrated device die, a reconstituted die or wafer, etc.) in the illustrated embodiment.
  • FIGS. 4A-4C are schematic perspective views of waveguides 10 with different metallic patterns for the metallic channel 11 .
  • FIG. 4A is a schematic perspective view of a waveguide 10 which can be similar to the waveguide 10 shown in FIG. 2 , prior to bonding.
  • first metallic features 14 a can include the wall 11 a and metallic legs that are disposed on and/or extend from the wall 11 a to at least partially define the walls 11 c, 11 d, and which can be provided on a first element (such as the dies 2 a - 2 c ).
  • Second metallic features 14 b can include the wall 11 b and metallic legs that are disposed on and/or extend from the wall 11 b to at least partially define the walls 11 c, 11 d , and which can be provided on a second element (such as the carrier 3 ).
  • the metallic features 14 a, 14 b can be directly bonded to one another to define the walls 11 c, 11 d .
  • FIG. 1 In the embodiment of FIG. 1
  • the metallic features 14 a, 14 b comprise a continuous linear metallic segments such that, when the features 14 a, 14 b are directly bonded to one another, the walls 11 a - 11 d define a channel 11 that is effectively closed (e.g., completely closed) as viewed from a cross-section taken perpendicular to the propagation direction (e.g., the x-axis).
  • corresponding dielectric features 7 a, 7 b can also be directly bonded so as to define the dielectric material 7 disposed within the metallic channel 11 defined by the walls 11 a - 11 d .
  • the waveguide 10 shown in FIG. 4A is straight or linear, in other embodiments, the waveguide 10 can bend, turn, or curve so as to cause the waves W to follow a curved or angled pathway.
  • the metallic features 14 a, 14 b shown in FIG. 4A it may be undesirable to provide continuous linear segments, such as the metallic features 14 a, 14 b shown in FIG. 4A .
  • polishing the metallic features 14 a, 14 b and dielectric features 7 a, 7 b using processes such as chemical mechanical polishing can cause dishing along the bonding surfaces of the elements to be bonded. The dishing can cause uneven surfaces along the bonding surfaces, which may be undesirable.
  • the metallic features 14 a, 14 b that define the walls 11 c, 11 d of the channel 11 may instead be patterned to define smaller metallic features that are less susceptible to dishing.
  • FIG. 4B is a schematic perspective view of a waveguide 10 in which portions of conductive features 14 a, 14 b are patterned with discontinuities or gaps 15 to avoid dishing.
  • FIG. 4C is a schematic perspective view of a waveguide 10 in which both metallic features 14 a, 14 b are patterned with discontinuities or gaps 15 along their lengths to avoid dishing.
  • the metallic features 14 a , 14 b can be patterned (e.g., using lithography or by selective deposition) to have gaps 15 between the portions of the metallic feature 14 a, 14 b along the direction of propagation (the x-axis).
  • FIG. 4A is a schematic perspective view of a waveguide 10 in which portions of conductive features 14 a, 14 b are patterned with discontinuities or gaps 15 to avoid dishing.
  • the metallic features 14 a , 14 b can be patterned (e.g., using lithography or by selective deposition) to have gaps 15 between the portions of the metallic feature 14 a, 14 b
  • gaps 15 are provided, which may not affect the electrical performance of the waveguide 10 .
  • numerous gaps 15 are provided along the length of the waveguide 10 , which may slightly affect the electrical performance.
  • any degradation in electrical performance for the embodiment of FIG. 4C may be negligible or eliminated if the gaps 15 are significantly smaller than the wavelength of the waves W that are coupled to the waveguide 10 .
  • the metallic features 14 a, 14 b may have gaps 15 or discontinuities, the metallic channel 11 may nevertheless be effectively closed if the gaps 15 are sufficiently small as compared with the wavelength of the waves W.
  • the gaps 15 can be sized so as to be less than 20% (e.g., less than 15%, or less than 10%) of the wavelength of the waves W to be coupled to the waveguide 10 .
  • the gaps 15 can be sized so as to be in a range of 0.5% to 15%, in a range of 1% to 10%, or in a range of 2% to 5% of the wavelength of the waves W to be coupled to the waveguide 10 .
  • Relatively small pitches for the metallic features 14 a , 14 b and associated gaps 15 therein can be defined using lithographic techniques.
  • the pitch of the gaps 15 and metallic features 14 a, 14 b can be 30 microns or less for wavelengths greater than 300 microns.
  • the pitch of the gaps 15 and metallic features 14 a, 14 b can be less than 20 microns or less than 10 microns. In various embodiments, the pitch of the gaps 15 and metallic features 14 a, 14 b can be in a range of 1 micron to 40 microns, in a range of 1 micron to 30 microns, in a range of 5 microns to 30 microns, in a range of 5 microns to 20 microns, or in a range of 5 microns to 10 microns.
  • the ability to create small pitch discontinuities or gaps in the metallic features 14 a, 14 b in a semiconductor element can beneficially reduce dishing while enabling little or no degradation in electrical performance.
  • the pitch can be further reduced, e.g., to below 1 micron as defined by photolithographic limits.
  • FIG. 5 is a schematic perspective view of a structure 1 with a waveguide 10 embedded in a carrier 3 comprising a semiconductor element, prior to bonding of the dies 2 a, 2 b to the carrier 3 .
  • the waveguide 10 is at least partially embedded in the carrier 3 , which can comprise a semiconductor element such as an integrated device die, a semiconductor interposer, a reconstituted die or wafer, etc.
  • the waveguide 10 is completely embedded in the carrier 3 such that the walls 11 a - 11 d of the channel 11 are buried within the carrier 3 .
  • the waveguide 10 can be at least partially embedded in the carrier 3 but may have a wall 11 a that is exposed at or near the upper surface 5 of the carrier 3 .
  • the waveguide 10 can comprise a metallic channel 11 that defines an effectively closed metallic or conductive profile, as viewed from a side cross section taken along the direction of wave propagation.
  • the metallic channel 11 may comprise a continuous and completely closed profile, while in other embodiments, the metallic channel 11 may comprise gaps or discontinuities.
  • the carrier 3 can comprise ports 17 b, 17 d, and the dies 2 a - 2 b can comprise corresponding ports 17 a, 17 c.
  • the ports 17 b, 17 d can extend through the effectively closed metallic channel 11 to the upper surface 5 of the carrier 3 , and the ports 17 a, 17 c can be exposed on the lower surface 12 of the dies 2 a - 2 b.
  • the ports 17 a - 17 d can be configured to couple to radiating elements 13 a, 13 b to transmit electromagnetic radiation to, or to receive electromagnetic radiation from, the waveguide 10 .
  • the dies 2 a, 2 b can be aligned relative to the carrier 3 such that the port 17 a generally aligns with the port 17 b and the port 17 c aligns with the port 17 d .
  • the dies 2 a, 2 b can be bonded to the carrier 3 , including along the interface between the ports 17 a and 17 b and between the ports 17 c and 17 d .
  • a metallic periphery 18 a of the port 17 a can be directly bonded to a metallic periphery 18 b of the port 17 b without an intervening adhesive.
  • a metallic periphery 18 c of the port 17 c can be directly bonded to a metallic periphery 18 d of the port 17 d .
  • Dielectric features 7 a - 7 d within the metallic peripheries 18 a - 18 d can also be directly bonded to one another.
  • the metallic peripheries 18 a - 18 d can be bonded in other ways, such as by way of a conductive adhesive or solder.
  • the radiating elements 13 a, 13 b can electromagnetically couple to the waveguide 10 by way of the ports 17 b, 17 d .
  • the radiating elements 13 a, 13 b can comprise probes of a conductive segment that are inserted into openings in the metallic channel 11 defined by the ports 17 b, 17 d .
  • the radiating elements 13 a, 13 b can comprise other suitable structures, such as conductive loops or apertures. Accordingly, in the embodiment shown in FIG.
  • the waveguide 10 can be at least partially embedded in the carrier 3 which can comprise a semiconductor element or other substrate material with a bonding layer (e.g., silicon oxide) having metallic features embedded therein. Bonding the dies 2 a, 2 b to the carrier can provide electrical communication between the dies 2 a, 2 b by electromagnetically coupling the dies 2 a, 2 b to the waveguide 10 within the carrier 3 .
  • the carrier 3 can comprise a semiconductor element or other substrate material with a bonding layer (e.g., silicon oxide) having metallic features embedded therein. Bonding the dies 2 a, 2 b to the carrier can provide electrical communication between the dies 2 a, 2 b by electromagnetically coupling the dies 2 a, 2 b to the waveguide 10 within the carrier 3 .
  • FIG. 6 is a schematic side view of a structure 1 comprising a bridge 19 between the dies 2 a, 2 b that includes an integrated waveguide 10 therein.
  • the components of FIG. 6 may be the same as or generally similar to like numbered components of FIGS. 1-5 .
  • the structure can comprise integrated device dies 2 a, 2 b bonded (e.g., directly bonded) to the carrier 3 .
  • the bridge 19 can be bonded to the dies 2 a, 2 b on upper surfaces 20 , which can be the active surfaces, of the dies 2 a, 2 b, which are opposite the lower surfaces 12 and the carrier 3 .
  • the waveguide 10 can be provided at least partially in the bridge 19 as shown in FIG. 6 .
  • the waveguide 10 can be at least partially (e.g., completely) embedded in the bridge 19 , similar to the manner in which the waveguide 10 is embedded in the carrier 3 as shown in FIG. 5 .
  • the waveguide 10 can be defined by features along both sides of an interface between the dies 2 a , 2 b and the bridge 19 , similar to the manner in which the waveguide 10 is defined in FIGS. 3A-3B .
  • the waveguide 10 can comprise a metallic channel having an effectively closed profile (e.g., completely closed or including small discontinuities or gaps) and within which a dielectric material is disposed, as viewed along a cross section taken transverse to the propagation direction.
  • the bridge 19 comprises a semiconductor element, such as an interposer, an integrated device die, etc.
  • the bridge 19 may be the waveguide itself, such that the waveguide 10 spans the gap between the dies 2 a, 2 b.
  • the waveguide can be provided directly across the dies, instead of embedding it in a bridge structure.
  • FIGS. 7A-7D illustrate various devices that can be constructed utilizing the waveguides 10 disclosed herein.
  • the waveguides 10 utilized in FIGS. 7A-7D can comprise effectively closed metallic channels (e.g., completely closed or with discontinuities or gaps that are small compared to the electromagnetic wavelengths to be communicated therethrough).
  • the waveguides 10 utilized in FIGS. 7A-7D can be defined along an interface between two elements (such as between a die and a carrier, as in FIGS. 3A-3C ), or can be at least partially embedded in one element (similar to the embodiment of FIG. 5 ).
  • FIG. 7A is a top plan view of a power divider 30 that incorporates any of the waveguide structures 10 described above.
  • the power divider 30 can comprise waveguide structures 10 disposed in or on an element (such as a substrate, interposer, integrated device die, etc.).
  • the waveguide 10 can comprise a primary channel 31 that splits into a plurality of divided channels 32 a, 32 b at a junction 33 .
  • Divided channels 32 a, 32 b, 34 a, and 34 b can also be defined as waveguide structures similar to the waveguides 10 disclosed herein.
  • the power divider based on the integrated waveguide structures disclosed herein may function in a manner similar to conventional planar power dividers based on microstrips or striplines. However, beneficially, the embodiments disclosed herein can provide lower losses and better performance at higher frequencies.
  • the waveguide 10 may broaden out at the divided channels 32 a, 32 b.
  • the power divider 30 can divide or split the power of the electromagnetic waves that propagate along the waveguide 10 .
  • FIG. 7B is a top plan view of a coupler 40 that incorporates the waveguides 10 described herein.
  • the coupler 40 can comprise one or more waveguides 10 disposed in or on an element (such as a substrate, interposer, integrated device die, etc.).
  • the waveguide 10 can comprise first and second longitudinal arms 41 a, 41 b that are spaced apart from one another, e.g., by a quarter wavelength.
  • the arms 41 a, 41 b can be connected by connector waveguides 42 a, 42 b.
  • the connector waveguides 42 a, 42 b can be spaced apart from one another, e.g., by a quarter wavelength.
  • electromagnetic waves can propagate along the longitudinal arms 41 a, 41 b of the waveguide 10 .
  • the waves propagating along one of the arms 41 a, 41 b can couple to the waves propagating along the other of the arms 41 a, 41 b, by propagating along the connector waveguides 42 a, 42 b.
  • the coupler based on the integrated waveguide structures may function in a manner similar to a conventional planar coupler based on microstrips or striplines.
  • the embodiments disclosed herein may provide lower losses and better performance at higher frequencies.
  • FIG. 7C is a top plan view of a circulator 50 that incorporates the waveguides 10 described herein.
  • the circulator 50 can comprise one or more waveguides 10 disposed in or on an element (such as a substrate, interposer, integrated device die, etc.).
  • the circulator 50 can include a waveguide 10 having a curved or circular pathway 51 .
  • a first port 52 a can act as an input for coupling electromagnetic radiation into the circular pathway 51 .
  • Second and third ports 52 b, 52 c can act as in-phase output ports for directing electromagnetic radiation out of the circular pathway 51 .
  • a fourth port 52 d can comprise an isolated port.
  • the circulator based on the integrated waveguide structures disclosed herein may function in a manner similar to a conventional planar circulator based on microstrips or striplines. However, beneficially, the embodiments disclosed herein may provide lower losses and better performance at higher frequencies.
  • FIG. 7D is a top plan view of a filter 60 that incorporates the waveguides 10 disclosed herein.
  • the filter 60 can comprise one or more waveguides 10 disposed in or on an element (such as a substrate, interposer, integrated device die, etc.).
  • the waveguide 10 can comprise an input line 71 a and an output line 71 b.
  • a plurality of ring-shaped elements 72 a, 72 b can be provide between the input and output lines 71 a, 71 b.
  • the input line 71 a can electromagnetically couple with the ring-shaped element 72 a.
  • the ring-shaped element 72 a can couple with the ring-shaped element 72 b, which can in turn electromagnetically couple with the output line 71 b.
  • Selected wavelength(s) of radiation propagating along the input line 71 a can be filtered by the ring-shaped elements 72 a, 72 b , such that only the selected wavelength(s) are transmitted to the output line 71 b.
  • the filter based on the integrated waveguide structures disclosed herein may function in a manner similar to a conventional planar filter based on microstrips or striplines. However, beneficially, the embodiments disclosed herein may provide lower losses and better performance at higher frequencies.
  • the waveguides 10 disclosed herein in FIGS. 1-6 can be shaped in plan view in any suitable manner so as to define various components that have different electrical functionalities.
  • the waveguides 10 may accordingly be bent, angled, or curved, as seen from a top view.
  • the waveguides 10 can comprise multiple components that interact with one another to define various types of devices.
  • FIG. 8 is a schematic system diagram of an electronic system 80 incorporating one or more structures 1 , according to various embodiments.
  • the system 80 can comprise any suitable type of electronic device, such as a mobile electronic device (e.g., a smartphone, a tablet computing device, a laptop computer, etc.), a desktop computer, an automobile or components thereof, a stereo system, a medical device, a camera, or any other suitable type of system.
  • the electronic system 80 can comprise a microprocessor, a graphics processor, an electronic recording device, or digital memory.
  • the system 80 can include one or more device packages 82 which are mechanically and electrically connected to the system 80 , e.g., by way of one or more motherboards. Each package 82 can comprise one or more structures 1 .
  • the system 80 shown in FIG. 8 can comprise any of the structures 1 shown and described herein.
  • a structure in one embodiment, can include a first element and a carrier bonded to the first element along an interface.
  • the structure can include a waveguide defined at least in part along the interface between the first element and the carrier.
  • the waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel as viewed from a side cross-section of the structure.
  • a structure in another embodiment, can include a semiconductor element having a waveguide at least partially embedded therein.
  • the waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel as viewed from a side cross-section of the structure.
  • the structure can include a first port extending through the effectively closed metallic channel to an exterior surface of the semiconductor element. The first port can be configured to couple to a radiating element to transmit electromagnetic radiation to, or to receive electromagnetic radiation from, the waveguide.
  • a method of forming a structure can include providing a first element and a carrier.
  • the first element can comprise first metallic features and first dielectric features exposed on an exterior surface of the first element.
  • the carrier can comprise second metallic features and second dielectric features exposed on an exterior surface of the carrier.
  • the method can include bonding the first element to the carrier along an interface to bond the first metallic features and the second metallic features and to bond the first dielectric features and the second dielectric features.
  • the bonded first element and carrier can define a waveguide at least in part along the interface between the first element and the carrier.
  • the waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel as viewed from a side cross-section of the structure.

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Abstract

A structure can include a first element and a carrier bonded to the first element along an interface. A waveguide can be defined at least in part along the interface between the first element and the carrier. The waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel, as viewed from a side cross-section of the structure. Various millimeter-wave or sub-terahertz components or circuit structures can also be created based on the waveguide structures disclosed herein.

Description

    BACKGROUND Field
  • The field relates to structures with integrated waveguides, and in particular, to interconnects and circuit structures with integrated metallic waveguides.
  • Description of the Related Art
  • In some electronic systems, multiple integrated device dies may be mounted to a carrier and may communicate with one another in a variety of ways. For example, in some systems, two integrated device dies can communicate with one another by way of conductive traces or interconnects provided in an intervening package substrate such as a printed circuit board (PCB) or in a silicon interposer. In other systems, a silicon bridge or other interconnect structure can serve to electrically connect two dies within a package or system. However, existing die-to-die interconnects may experience high losses due to conductor loss, crosstalk or other factors. Accordingly, there remains a continuing need for improved die-to-die communications.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic side sectional view of a structure that includes integrated waveguides, according to some embodiments.
  • FIG. 2 is schematic perspective view of a waveguide according to various embodiments.
  • FIG. 3A is a schematic perspective view of a structure with an integrated waveguide, according to various embodiments.
  • FIG. 3B is a schematic side cross-sectional view of a first waveguide portion disposed between integrated device dies and a carrier.
  • FIG. 3C is a schematic side cross-sectional view a second waveguide portion disposed along and under a gap between the integrated device dies.
  • FIG. 4A is a schematic perspective view of a waveguide with metallic features that comprise continuous segments, prior to bonding.
  • FIG. 4B is a schematic perspective view of a waveguide in which portions of conductive features are patterned with discontinuities or gaps to avoid dishing.
  • FIG. 4C is a schematic perspective view of a waveguide in which both conductive features are patterned with discontinuities or gaps along their lengths to avoid dishing.
  • FIG. 5 is a schematic perspective view of a structure with a waveguide embedded in a carrier comprising a semiconductor element, prior to bonding of the dies to the carrier.
  • FIG. 6 is a schematic side view of a structure comprising a bridge between two dies that includes an integrated waveguide therein.
  • FIG. 7A is a top plan view of a power divider that incorporates any of the waveguides described herein.
  • FIG. 7B is a top plan view of a coupler that incorporates the waveguides described herein.
  • FIG. 7C is a top plan view of a circulator that incorporates the waveguides described herein.
  • FIG. 7D is a top plan view of a filter that incorporates the waveguides disclosed herein.
  • FIG. 8 is a schematic system diagram of an electronic system incorporating one or more structures, according to various embodiments.
  • DETAILED DESCRIPTION
  • Various embodiments disclosed herein relate to interconnects and structures with integrated waveguides, e.g., integrated conductive or metallic waveguides. As explained above, existing techniques for providing die-to-die (or chip-to-chip) communications within a package or system may not provide adequate performance at high frequencies. For example, some die-to-die interconnects may experience high current densities which can lead to high losses due to conductor loss, crosstalk and other factors. Moreover, in some systems, it may be difficult to provide millimeter wave or sub-terahertz communications over a range of tens of gigahertz to hundreds of gigahertz (e.g., in a range of 10 GHz to 950 GHz, in a range of 20 GHz to 900 GHz) using coplanar or microstrip waveguides since such devices may be lossy at millimeter-sized wavelengths. The embodiments disclosed herein beneficially enable the use of lower loss metallic waveguides for die-to-die communications, including communications at wavelengths in a range of 0.1 mm to 10 mm.
  • A metallic or conductive waveguide can comprise an effectively closed metallic or conductive channel as viewed from a side cross-section taken perpendicular to a propagation direction of the waveguide, and can include a low loss dielectric material within the effectively closed channel. In various embodiments, the metallic or conductive waveguide can comprise a metal, including metallic compounds. In some embodiments, the metallic waveguide can be defined by bonding two elements (e.g., two semiconductor elements) along an interface, with the waveguide defined at least in part by the interface. In some embodiments, the two elements can be directly bonded to one another without an intervening adhesive. In other embodiments, the metallic waveguide can be at least partially (e.g., completely) embedded in an element and can include one or a plurality of ports that can receive a radiating element for coupling electromagnetic waves to the waveguide. The disclosed embodiments can therefore provide die-to-die communications with low loss and with little or no crosstalk, which can enable high frequency die-to-die communications. Moreover, in embodiments that utilize direct bonding, the resulting structure can be constructed at lower costs than other techniques, since the waveguides can be constructed using the bonding layers defined for directly bonding two elements to one another. The integrated waveguides disclosed herein can also advantageously reduce the number of radio frequency (RF) components provided in the package, since the waveguides described herein can be directly integrated into the dies and/or other elements.
  • FIG. 1 is a schematic side sectional view of a structure 1 that includes an integrated waveguide 10 (e.g., an integrated metallic or otherwise conductive waveguide), according to some embodiments. The structure 1 can include a plurality of elements 2 mounted to another element, e.g., a carrier 3. For example, in FIG. 1, the elements 2 can comprise a first integrated device die 2 a, a second integrated device die 2 b, and a third integrated device die 2 c, each of which are electrically and mechanically connected to the carrier 3. In various embodiments, the device dies 2 a-2 c can comprise processor dies, memory dies, sensor dies, communications dies, microelectromechanical systems (MEMS) dies, or any other suitable type of device. The carrier 3 may be any suitable type of element, such as an integrated device die, an interposer, a reconstituted die or wafer, etc. As explained herein, the elements 2 a-2 c are shown as being mounted to the carrier 3 by way of a direct bond, but in other embodiments, the elements can be connected to the carrier in other ways. In the illustrated embodiment, the elements 2 a-2 c and the carrier 3 comprise semiconductor elements (e.g., integrated device dies 2 a-2 c, a semiconductor interposer, etc.), but in other embodiments, the elements and/or the carrier can comprise other types of elements that may or may not comprise a semiconductor material, such as various types of optical devices (e.g., lenses, filters, etc.). As shown, the dies 2 a-2 c can be laterally spaced from one another along the carrier 3.
  • In the illustrated embodiment, one or more of the device dies 2 a-2 c are directly bonded to the carrier 3 without an intervening adhesive. The direct bond between the dies 2 a-2 c and the carrier 3 can include a direct bond between corresponding conductive features of the dies 2 a-2 c (e.g., a processor die) and the carrier 3 (e.g., an integrated device die, an interposer, etc.) without an intervening adhesive, without being limited thereto. In some embodiments, the conductive features may be surrounded by non-conductive field regions. To accomplish the direct bonding, in some embodiments, respective bonding surfaces of the conductive features and the non-conductive field regions can be prepared for bonding. Preparation can include provision of a nonconductive layer, such as silicon oxide or silicon nitride, with exposed conductive features, such as metal bond pads or contacts. The bonding surfaces of at least the non-conductive field regions, or both the conductive and non-conductive regions, can be polished to a very high degree of smoothness (e.g., less than 20 nm surface roughness, or more particularly, less than 5 nm surface roughness). In some embodiments, the surfaces to be bonded may be terminated with a suitable species and activated prior to bonding. For example, in some embodiments, the non-conductive surfaces (e.g., field regions) of the bonding layer to be bonded, such as silicon oxide material, may be very slightly etched for activation and exposed to a nitrogen-containing solution and terminated with a nitrogen-containing species. As one example, the surfaces to be bonded (e.g., field regions) may be exposed to an ammonia dip after a very slight etch, and/or a nitrogen-containing plasma (with or without a separate etch). In a direct bond interconnect (DBI) process, nonconductive features of the dies and the carrier can directly bond to one another, even at room temperature and without the application of external pressure, while the conductive features of the dies and the carrier layer can also directly bond to one another, without any intervening adhesive layers. Bonding by DBI forms stronger bonds than Van der Waals bonding, including significant covalent bonding between the surfaces of interest. Subsequent annealing can further strengthen bonds, particularly between conductive features of the bonding interfaces.
  • In some embodiments, the respective conductive features can be flush with the exterior surfaces (e.g., the field regions) of the dies and the carrier. In other embodiments, the conductive features may extend above the exterior surfaces. In still other embodiments, the conductive features of one or both of the dies and the carrier are recessed relative to the exterior surfaces (e.g., nonconductive field regions) of the dies and the carrier. For example, the conductive features can be recessed relative to the field regions by less than 20 nm, e.g., less than 10 nm.
  • Once the respective surfaces are prepared, the nonconductive field regions (such as silicon oxide) of the dies 2 a-2 c can be brought into contact with corresponding nonconductive regions of the carrier 3. The interaction of the activated surfaces can cause the nonconductive regions of the dies 2 a-2 c to directly bond with the corresponding nonconductive regions of the carrier 3 without an intervening adhesive, without application of external pressure, without application of voltage, and at room temperature. In various embodiments, the bonding forces of the nonconductive regions can include covalent bonds that are greater than Van der Waals bonds and exert significant forces between the conductive features. Prior to any heat treatment, the bonding energy of the dielectric-dielectric surface can be in a range from 150-300 mJ/m2, which can increase to 1500-4000 mJ/m2 after a period of heat treatment. Regardless of whether the conductive features are flush with the nonconductive regions, recessed or protrude, direct bonding of the nonconductive regions can facilitate direct metal-to-metal bonding between the conductive features. In various embodiments, the dies 2 a-2 c and the carrier 3 may be heated after bonding at least the nonconductive regions. As noted above, such heat treatment can strengthen the bonds between the nonconductive regions, between the conductive features, and/or between opposing conductive and non-conductive regions. In embodiments where one or both of the conductive features are recessed, there may be an initial gap between the conductive features of the dies 2 a-2 c and the carrier 3, and heating after initially bonding the nonconductive regions can expand the conductive elements to close the gap. Regardless of whether there was an initial gap, heating can generate or increase pressure between the conductive elements of the opposing parts, aid bonding of the conductive features and form a direct electrical and mechanical connection.
  • Additional details of the direct bonding processes used in conjunction with each of the disclosed embodiments may be found throughout U.S. Pat. Nos. 7,126,212; 8,153,505; 7,622,324; 7,602,070; 8,163,373; 8,389,378; and 8,735,219, and throughout U.S. Patent Application Nos. 14/835,379; 62/278,354; 62/303,930; and 15/137,930, the contents of each of which are hereby incorporated by reference herein in their entirety and for all purposes.
  • Direct bonding of the dies 2 a-2 c to the carrier 3 can result in a bond interface 6 between the elements 2 and the carrier 3. The waveguide 10 can be defined along the interface 6 between the carrier 3 and the elements 2 (the dies 2 a-2 c). For example, as explained herein, the waveguide 10 can comprise a first waveguide portion 10 a that is defined by features at the respective lower surfaces 12 of the elements 2 and at an upper surface 5 of the carrier 3. As explained below in connection with FIGS. 3A-4C, metallic and/or dielectric features exposed on the lower surfaces 12 of the dies 2 a-2 c (the elements 2) can cooperate with corresponding metallic and/or dielectric features exposed on the upper surface 5 of the carrier 3 to define the first waveguide portion 10 a of the waveguide 10. The waveguide 10 can also comprise a second waveguide portion 10 b disposed along gaps 4 between the integrated device dies 2 a-2 c. The second waveguide portion 10 b can be embedded in the carrier 3 and can be defined by a metallic channel at or near the upper surface 5. The waveguide 10 can enable die-to-die communications between the first die 2 a and the second die 2 b, and between the second die 2 b and the third die 2 c. Although three dies 2 a-2 c are illustrated in FIG. 1, it should be appreciated that any suitable number of dies may be provided and may communicate with one another. Moreover, as explained above, the integrated waveguide 10 disclosed herein can be used in conjunction with any suitable type of element. In addition, although the dies 2 a-2 c are directly bonded to the carrier 3 without an intervening adhesive in the illustrated embodiment, in other embodiments, the dies 2 a-2 c can be bonded to the carrier 3 in other ways, such as by way of a conductive adhesive, solder, etc.
  • FIG. 2 is schematic perspective view of a portion of the waveguide 10 according to various embodiments. The waveguide 10 shown in FIG. 2 is a metallic waveguide that has a polygonal, and particularly rectangular, cross-section. For example, the waveguide 10 can comprise a channel 11 defined by a plurality of metallic walls 11 a-11 d that cooperate to delimit an effectively closed cross-sectional profile, as viewed along a cross-section taken transverse to the propagation direction (i.e., the x-axis). A dielectric material 7 can be disposed within the effectively closed metallic channel 11. In FIG. 2, the side section of the channel 11 is completely closed such that the walls 11 a-11 d define a continuous, closed boundary about the dielectric material 7. As explained below, however, in some embodiments, the effectively closed metallic channel 11 may have gaps or spaces in portions of some of the walls 11 a-11 d. In various embodiments, the metallic walls 11 a-11 d of the channel 11 can comprise copper or other metal materials. The dielectric material 7 can comprise any suitable dielectric, such as silicon oxide.
  • The walls 11 a-11 d can be electrically grounded so as to provide a bounded pathway along which electromagnetic waves can propagate. As shown in FIG. 2, input signals or waves W can enter at a first end of the waveguide 10 and can propagate parallel to the x-axis and can exit as an output signal at another end of the waveguide 10. In various embodiments, radiating elements 13 a, 13 b can be provided at both ends of the waveguide 10 to transmit and/or receive electromagnetic waves W along the waveguide 10. In various embodiments the width of the waveguide 10 along the y-direction can define the cutoff frequency for the propagating mode. During operation, a first radiating element 13 a can radiate signals or waves W at frequencies that can propagate along the waveguide 10. In some embodiments, the radiating elements 13 a, 13 b can comprise conductive segments or probes inserted into the dielectric material 7 within the channel 11. Skilled artisans will understand that electromagnetic waves can be coupled to the waveguide 10 in other suitable ways. For example, in some embodiments, the radiating elements 13 a, 13 b can comprise a conductive loop with the plane of the loop perpendicular to the lines of magnetic force, a linear conductor or probe that is parallel to the lines of electric force, or an aperture in a side wall of the waveguide 10 disposed along the direction of the lines of magnetic force on the side wall. The signals or waves W can propagate along the waveguide 10 and can be received by another radiating element 13 b which can convert the waves W to an electrical current. Beneficially, as explained herein, the waveguide 10 can be integrated or embedded in an element (such as an interposer or integrated device die), or at the bond interface 6 between two elements (e.g., at the interface 6 between the dies 2 a-2 c and the carrier 3). Moreover, in the illustrated embodiment, the waveguide 10 is straight or generally linear as it extends between two dies. However, in other embodiments, any of the waveguides 10 disclosed herein may bend, curve, or otherwise change directions so as to guide the waves to any desirable location in the structure 1.
  • FIG. 3A is a schematic perspective view of a structure 1 with an integrated waveguide 10, according to various embodiments. FIG. 3B is a schematic side cross-sectional view of the first waveguide portion 10 a disposed at interfaces 6 between the dies 2 a, 2 b and the carrier 3. FIG. 3C is a schematic side cross-sectional view of the second waveguide portion 10 b disposed along and under the gap 4 between the dies 2 a, 2 b. As explained above, in some embodiments, the waveguide 10 can include the first waveguide portion 10 a defined at the interfaces 6 between the dies 2 a-2 b and the carrier 3, as shown in FIG. 3B. In FIG. 3B, the first waveguide portion 10 a can be defined by first metallic features 14 a and first dielectric features 7 a formed in and/or on the respective integrated device dies 2 a, 2 b, and second metallic features 14 b and second dielectric features 7 b formed in and/or on the carrier 3.
  • The first waveguide portion 10 a can be formed in any suitable manner, such as by damascene processes. In the arrangement illustrated in FIG. 3B, for example, trenches or recesses can be defined in the lower surfaces 12, which may be the active surfaces, of the dies 2 a-2 b and in the upper surface 5 of the carrier 3. A metallic layer can be deposited along the bottom and sidewalls of the trenches to define the first and second metallic feature 14 a, 14 b. The dielectric features 7 a, 7 b can be deposited within the trenches over the metallic features 14 a, 14 b in the dies 2 a, 2 b and the carrier 3. The upper surface 5 of the carrier 3 and the lower surface 12 of the dies 2 a, 2 b can be prepared for direct bonding as explained above. For example, the upper surface 5 and the lower surface 12 can be polished to a very high surface smoothness, and can be activated and terminated with a suitable species (e.g., nitrogen). In some embodiments, the metallic features 14 a, 14 b may be recessed relative to the dielectric features 7 a, 7 b (e.g., recessed below the dielectric features 7 a, 7 b by less than 20 nm, or by less than 10 nm). The lower surfaces 12 of the dies 2 a, 2 b can be brought into contact with the upper surface 5 of the carrier 3 at room temperature to form a direct bond between at least the non-conductive field regions of the dies 2 a, 2 b and the carrier 3 (e.g., a direct bond between the dielectric features 7 a, 7 b disposed in each element). The non-conductive regions can be directly bonded without application of pressure or voltage in some arrangements. In some embodiments, the structure 1 can be heated to increase the bond strength and/or to cause the metallic features 14 a, 14 b to form an electrical contact with one another.
  • The resulting bonded structure 1 can be bonded along the interface 6, and the waveguide 10 can be defined at least in part along the bond interface 6. For example, the first and second metallic features 14 a, 14 b and the associated dielectric features 7 a, 7 b can cooperate along the interface 6 to form the first waveguide portion 10 a of the waveguide 10. In particular, the first and second metallic features 14 a, 14 b can bond to one another such that the walls 11 c, 11 d can be formed from respective side portions of the features 14 a, 14 b (e.g., the portions of the metal that line the sidewalls of the trenches in the elements). The walls 11 a, 11 b can be defined by the portions of the metal that line the bottoms of the trenches in the respective elements. As shown in the side sectional view of FIG. 3B, the metallic features 14 a, 14 b can cooperate to define an effectively closed metallic channel (e.g., a completely closed metallic channel in the arrangement of FIG. 3B) disposed about the dielectric material 7 (which is defined by the respective dielectric features 7 a, 7 b). Beneficially, the direct bond between the metallic features 14 a, 14 b and between the dielectric features 7 a, 7 b can enable face down solutions (e.g., with each die's active surface facing the carrier 3) for die-to-die communications with improved electrical performance and lower losses for frequencies below 1 THz (e.g., greater than 22 GHz, or in a range of 22 GHz to 1 THz), as compared with other die-to-die interconnects.
  • Turning to FIG. 3C, in the illustrated embodiment, the second waveguide portion 10 b can be defined along and underlying the gaps 4 between the dies 4 a, 4 b. In the second waveguide portion 10 b, the channel 11 can be defined by the second metallic portion 14 b formed in the carrier 3 and by a first metallic portion 14 a that can be deposited or adhered over the second metallic portion 14 b and the dielectric material 7. As with FIG. 3B, the first and second metallic portions 14 a, 14 b may be separately defined or integrated so as to cooperate to define the waveguide portion 10 b. The second waveguide portion 10 b can accordingly be embedded or buried in the carrier 3, with the upper wall 11 a defined by metal applied over the upper surface 5 of the carrier 3. The height of the second waveguide portion 10 b along the z-axis (see FIG. 2) can be less than the height of the first waveguide portion 10 a along the z-axis, as shown in FIGS. 3B and 3C. The height differential between the first and second waveguide portions 10 a, 10 b may introduce some impedance discontinuities, but the overall effect on electrical performance is negligible. The width of the first and second waveguide portions 10 a, 10 b along the y-axis (see FIG. 2) may be substantially the same, which can ensure effective propagation along the x-axis. Beneficially, the second waveguide portion 10 b can be embedded within a carrier 3, which can be a semiconductor element (such as an interposer, an integrated device die, a reconstituted die or wafer, etc.) in the illustrated embodiment.
  • FIGS. 4A-4C are schematic perspective views of waveguides 10 with different metallic patterns for the metallic channel 11. In particular, FIG. 4A is a schematic perspective view of a waveguide 10 which can be similar to the waveguide 10 shown in FIG. 2, prior to bonding. In FIG. 4A, for example, first metallic features 14 a can include the wall 11 a and metallic legs that are disposed on and/or extend from the wall 11 a to at least partially define the walls 11 c, 11 d, and which can be provided on a first element (such as the dies 2 a-2 c). Second metallic features 14 b can include the wall 11 b and metallic legs that are disposed on and/or extend from the wall 11 b to at least partially define the walls 11 c, 11 d, and which can be provided on a second element (such as the carrier 3). The metallic features 14 a, 14 b can be directly bonded to one another to define the walls 11 c, 11 d. In the embodiment of FIG. 4A, the metallic features 14 a, 14 b comprise a continuous linear metallic segments such that, when the features 14 a, 14 b are directly bonded to one another, the walls 11 a-11 d define a channel 11 that is effectively closed (e.g., completely closed) as viewed from a cross-section taken perpendicular to the propagation direction (e.g., the x-axis). Although not illustrated in FIG. 4A, it should be appreciated that corresponding dielectric features 7 a, 7 b (see FIG. 3B) can also be directly bonded so as to define the dielectric material 7 disposed within the metallic channel 11 defined by the walls 11 a-11 d. Furthermore, although the waveguide 10 shown in FIG. 4A is straight or linear, in other embodiments, the waveguide 10 can bend, turn, or curve so as to cause the waves W to follow a curved or angled pathway.
  • In some arrangements, it may be undesirable to provide continuous linear segments, such as the metallic features 14 a, 14 b shown in FIG. 4A. For example, in some cases, polishing the metallic features 14 a, 14 b and dielectric features 7 a, 7 b using processes such as chemical mechanical polishing can cause dishing along the bonding surfaces of the elements to be bonded. The dishing can cause uneven surfaces along the bonding surfaces, which may be undesirable. Thus, in some embodiments, the metallic features 14 a, 14 b that define the walls 11 c, 11 d of the channel 11 may instead be patterned to define smaller metallic features that are less susceptible to dishing.
  • Accordingly, FIG. 4B is a schematic perspective view of a waveguide 10 in which portions of conductive features 14 a, 14 b are patterned with discontinuities or gaps 15 to avoid dishing. FIG. 4C is a schematic perspective view of a waveguide 10 in which both metallic features 14 a, 14 b are patterned with discontinuities or gaps 15 along their lengths to avoid dishing. Unlike FIG. 4A, in FIGS. 4B and 4C, the metallic features 14 a, 14 b can be patterned (e.g., using lithography or by selective deposition) to have gaps 15 between the portions of the metallic feature 14 a, 14 b along the direction of propagation (the x-axis). In FIG. 4B, only a few small discontinuities or gaps 15 are provided, which may not affect the electrical performance of the waveguide 10. In FIG. 4C, numerous gaps 15 are provided along the length of the waveguide 10, which may slightly affect the electrical performance. However, any degradation in electrical performance for the embodiment of FIG. 4C may be negligible or eliminated if the gaps 15 are significantly smaller than the wavelength of the waves W that are coupled to the waveguide 10. Thus, even though the metallic features 14 a, 14 b may have gaps 15 or discontinuities, the metallic channel 11 may nevertheless be effectively closed if the gaps 15 are sufficiently small as compared with the wavelength of the waves W.
  • For example, the gaps 15 can be sized so as to be less than 20% (e.g., less than 15%, or less than 10%) of the wavelength of the waves W to be coupled to the waveguide 10. In some embodiments, the gaps 15 can be sized so as to be in a range of 0.5% to 15%, in a range of 1% to 10%, or in a range of 2% to 5% of the wavelength of the waves W to be coupled to the waveguide 10. Relatively small pitches for the metallic features 14 a, 14 b and associated gaps 15 therein can be defined using lithographic techniques. In various embodiments, for example, the pitch of the gaps 15 and metallic features 14 a, 14 b can be 30 microns or less for wavelengths greater than 300 microns. In various embodiments, the pitch of the gaps 15 and metallic features 14 a, 14 b can be less than 20 microns or less than 10 microns. In various embodiments, the pitch of the gaps 15 and metallic features 14 a, 14 b can be in a range of 1 micron to 40 microns, in a range of 1 micron to 30 microns, in a range of 5 microns to 30 microns, in a range of 5 microns to 20 microns, or in a range of 5 microns to 10 microns. The ability to create small pitch discontinuities or gaps in the metallic features 14 a, 14 b in a semiconductor element (such as a die or interposer) can beneficially reduce dishing while enabling little or no degradation in electrical performance. For waveguides 10 that are completely embedded in the semiconductor element, the pitch can be further reduced, e.g., to below 1 micron as defined by photolithographic limits.
  • FIG. 5 is a schematic perspective view of a structure 1 with a waveguide 10 embedded in a carrier 3 comprising a semiconductor element, prior to bonding of the dies 2 a, 2 b to the carrier 3. In the embodiment of FIG. 5, the waveguide 10 is at least partially embedded in the carrier 3, which can comprise a semiconductor element such as an integrated device die, a semiconductor interposer, a reconstituted die or wafer, etc. In some embodiments, the waveguide 10 is completely embedded in the carrier 3 such that the walls 11 a-11 d of the channel 11 are buried within the carrier 3. In other embodiments, the waveguide 10 can be at least partially embedded in the carrier 3 but may have a wall 11 a that is exposed at or near the upper surface 5 of the carrier 3. As with the embodiments of FIGS. 1-4C, the waveguide 10 can comprise a metallic channel 11 that defines an effectively closed metallic or conductive profile, as viewed from a side cross section taken along the direction of wave propagation. In some embodiments, the metallic channel 11 may comprise a continuous and completely closed profile, while in other embodiments, the metallic channel 11 may comprise gaps or discontinuities.
  • As shown in FIG. 5, the carrier 3 can comprise ports 17 b, 17 d, and the dies 2 a-2 b can comprise corresponding ports 17 a, 17 c. The ports 17 b, 17 d can extend through the effectively closed metallic channel 11 to the upper surface 5 of the carrier 3, and the ports 17 a, 17 c can be exposed on the lower surface 12 of the dies 2 a-2 b. The ports 17 a-17 d can be configured to couple to radiating elements 13 a, 13 b to transmit electromagnetic radiation to, or to receive electromagnetic radiation from, the waveguide 10. For example, the dies 2 a, 2 b can be aligned relative to the carrier 3 such that the port 17 a generally aligns with the port 17 b and the port 17 c aligns with the port 17 d. The dies 2 a, 2 b can be bonded to the carrier 3, including along the interface between the ports 17 a and 17 b and between the ports 17 c and 17 d. In the illustrated embodiment, for example, a metallic periphery 18 a of the port 17 a can be directly bonded to a metallic periphery 18 b of the port 17 b without an intervening adhesive. Similarly, a metallic periphery 18 c of the port 17 c can be directly bonded to a metallic periphery 18 d of the port 17 d. Dielectric features 7 a-7 d within the metallic peripheries 18 a-18 d can also be directly bonded to one another. In other embodiments, the metallic peripheries 18 a-18 d can be bonded in other ways, such as by way of a conductive adhesive or solder.
  • Upon bonding of the dies 2 a, 2 b to the carrier 3, the radiating elements 13 a, 13 b can electromagnetically couple to the waveguide 10 by way of the ports 17 b, 17 d. In the illustrated embodiment, the radiating elements 13 a, 13 b can comprise probes of a conductive segment that are inserted into openings in the metallic channel 11 defined by the ports 17 b, 17 d. In other embodiments, as explained above, the radiating elements 13 a, 13 b can comprise other suitable structures, such as conductive loops or apertures. Accordingly, in the embodiment shown in FIG. 5, the waveguide 10 can be at least partially embedded in the carrier 3 which can comprise a semiconductor element or other substrate material with a bonding layer (e.g., silicon oxide) having metallic features embedded therein. Bonding the dies 2 a, 2 b to the carrier can provide electrical communication between the dies 2 a, 2 b by electromagnetically coupling the dies 2 a, 2 b to the waveguide 10 within the carrier 3.
  • FIG. 6 is a schematic side view of a structure 1 comprising a bridge 19 between the dies 2 a, 2 b that includes an integrated waveguide 10 therein. Unless otherwise noted, the components of FIG. 6 may be the same as or generally similar to like numbered components of FIGS. 1-5. For example, in FIG. 6, the structure can comprise integrated device dies 2 a, 2 b bonded (e.g., directly bonded) to the carrier 3. However, unlike the embodiments of FIGS. 1-5, in FIG. 6, the bridge 19 can be bonded to the dies 2 a, 2 b on upper surfaces 20, which can be the active surfaces, of the dies 2 a, 2 b, which are opposite the lower surfaces 12 and the carrier 3. The waveguide 10 can be provided at least partially in the bridge 19 as shown in FIG. 6. In some embodiments, the waveguide 10 can be at least partially (e.g., completely) embedded in the bridge 19, similar to the manner in which the waveguide 10 is embedded in the carrier 3 as shown in FIG. 5. In other embodiments, the waveguide 10 can be defined by features along both sides of an interface between the dies 2 a, 2 b and the bridge 19, similar to the manner in which the waveguide 10 is defined in FIGS. 3A-3B. As with the above embodiments, the waveguide 10 can comprise a metallic channel having an effectively closed profile (e.g., completely closed or including small discontinuities or gaps) and within which a dielectric material is disposed, as viewed along a cross section taken transverse to the propagation direction. In some embodiments, the bridge 19 comprises a semiconductor element, such as an interposer, an integrated device die, etc. In some embodiments, the bridge 19 may be the waveguide itself, such that the waveguide 10 spans the gap between the dies 2 a, 2 b. In other embodiments, the waveguide can be provided directly across the dies, instead of embedding it in a bridge structure.
  • FIGS. 7A-7D illustrate various devices that can be constructed utilizing the waveguides 10 disclosed herein. As explained above, the waveguides 10 utilized in FIGS. 7A-7D can comprise effectively closed metallic channels (e.g., completely closed or with discontinuities or gaps that are small compared to the electromagnetic wavelengths to be communicated therethrough). The waveguides 10 utilized in FIGS. 7A-7D can be defined along an interface between two elements (such as between a die and a carrier, as in FIGS. 3A-3C), or can be at least partially embedded in one element (similar to the embodiment of FIG. 5). FIG. 7A is a top plan view of a power divider 30 that incorporates any of the waveguide structures 10 described above. The power divider 30 can comprise waveguide structures 10 disposed in or on an element (such as a substrate, interposer, integrated device die, etc.). The waveguide 10 can comprise a primary channel 31 that splits into a plurality of divided channels 32 a, 32 b at a junction 33. Divided channels 32 a, 32 b, 34 a, and 34 b can also be defined as waveguide structures similar to the waveguides 10 disclosed herein. The power divider based on the integrated waveguide structures disclosed herein may function in a manner similar to conventional planar power dividers based on microstrips or striplines. However, beneficially, the embodiments disclosed herein can provide lower losses and better performance at higher frequencies. The waveguide 10 may broaden out at the divided channels 32 a, 32 b. The power divider 30 can divide or split the power of the electromagnetic waves that propagate along the waveguide 10.
  • FIG. 7B is a top plan view of a coupler 40 that incorporates the waveguides 10 described herein. The coupler 40 can comprise one or more waveguides 10 disposed in or on an element (such as a substrate, interposer, integrated device die, etc.). The waveguide 10 can comprise first and second longitudinal arms 41 a, 41 b that are spaced apart from one another, e.g., by a quarter wavelength. As shown in FIG. 7B, the arms 41 a, 41 b can be connected by connector waveguides 42 a, 42 b. The connector waveguides 42 a, 42 b can be spaced apart from one another, e.g., by a quarter wavelength. During operation, electromagnetic waves can propagate along the longitudinal arms 41 a, 41 b of the waveguide 10. The waves propagating along one of the arms 41 a, 41 b can couple to the waves propagating along the other of the arms 41 a, 41 b, by propagating along the connector waveguides 42 a, 42 b. The coupler based on the integrated waveguide structures may function in a manner similar to a conventional planar coupler based on microstrips or striplines. However, beneficially, the embodiments disclosed herein may provide lower losses and better performance at higher frequencies.
  • FIG. 7C is a top plan view of a circulator 50 that incorporates the waveguides 10 described herein. The circulator 50 can comprise one or more waveguides 10 disposed in or on an element (such as a substrate, interposer, integrated device die, etc.). The circulator 50 can include a waveguide 10 having a curved or circular pathway 51. A first port 52 a can act as an input for coupling electromagnetic radiation into the circular pathway 51. Second and third ports 52 b, 52 c can act as in-phase output ports for directing electromagnetic radiation out of the circular pathway 51. A fourth port 52 d can comprise an isolated port. The circulator based on the integrated waveguide structures disclosed herein may function in a manner similar to a conventional planar circulator based on microstrips or striplines. However, beneficially, the embodiments disclosed herein may provide lower losses and better performance at higher frequencies.
  • FIG. 7D is a top plan view of a filter 60 that incorporates the waveguides 10 disclosed herein. The filter 60 can comprise one or more waveguides 10 disposed in or on an element (such as a substrate, interposer, integrated device die, etc.). The waveguide 10 can comprise an input line 71 a and an output line 71 b. A plurality of ring-shaped elements 72 a, 72 b can be provide between the input and output lines 71 a, 71 b. For example, the input line 71 a can electromagnetically couple with the ring-shaped element 72 a. The ring-shaped element 72 a can couple with the ring-shaped element 72 b, which can in turn electromagnetically couple with the output line 71 b. Selected wavelength(s) of radiation propagating along the input line 71 a can be filtered by the ring-shaped elements 72 a, 72 b, such that only the selected wavelength(s) are transmitted to the output line 71 b. The filter based on the integrated waveguide structures disclosed herein may function in a manner similar to a conventional planar filter based on microstrips or striplines. However, beneficially, the embodiments disclosed herein may provide lower losses and better performance at higher frequencies.
  • Thus, as shown in FIGS. 7A-7D, the waveguides 10 disclosed herein in FIGS. 1-6 can be shaped in plan view in any suitable manner so as to define various components that have different electrical functionalities. The waveguides 10 may accordingly be bent, angled, or curved, as seen from a top view. Moreover, the waveguides 10 can comprise multiple components that interact with one another to define various types of devices.
  • FIG. 8 is a schematic system diagram of an electronic system 80 incorporating one or more structures 1, according to various embodiments. The system 80 can comprise any suitable type of electronic device, such as a mobile electronic device (e.g., a smartphone, a tablet computing device, a laptop computer, etc.), a desktop computer, an automobile or components thereof, a stereo system, a medical device, a camera, or any other suitable type of system. In some embodiments, the electronic system 80 can comprise a microprocessor, a graphics processor, an electronic recording device, or digital memory. The system 80 can include one or more device packages 82 which are mechanically and electrically connected to the system 80, e.g., by way of one or more motherboards. Each package 82 can comprise one or more structures 1. The system 80 shown in FIG. 8 can comprise any of the structures 1 shown and described herein.
  • In one embodiment, a structure is disclosed. The structure can include a first element and a carrier bonded to the first element along an interface. The structure can include a waveguide defined at least in part along the interface between the first element and the carrier. The waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel as viewed from a side cross-section of the structure.
  • In another embodiment, a structure is disclosed. The structure can include a semiconductor element having a waveguide at least partially embedded therein. The waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel as viewed from a side cross-section of the structure. The structure can include a first port extending through the effectively closed metallic channel to an exterior surface of the semiconductor element. The first port can be configured to couple to a radiating element to transmit electromagnetic radiation to, or to receive electromagnetic radiation from, the waveguide.
  • In another embodiment, a method of forming a structure is disclosed. The method can include providing a first element and a carrier. The first element can comprise first metallic features and first dielectric features exposed on an exterior surface of the first element. The carrier can comprise second metallic features and second dielectric features exposed on an exterior surface of the carrier. The method can include bonding the first element to the carrier along an interface to bond the first metallic features and the second metallic features and to bond the first dielectric features and the second dielectric features. The bonded first element and carrier can define a waveguide at least in part along the interface between the first element and the carrier. The waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel as viewed from a side cross-section of the structure.
  • For purposes of summarizing the disclosed embodiments and the advantages achieved over the prior art, certain objects and advantages have been described herein. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment. Thus, for example, those skilled in the art will recognize that the disclosed implementations may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught or suggested herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
  • All of these embodiments are intended to be within the scope of this disclosure. These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of the embodiments having reference to the attached figures, the claims not being limited to any particular embodiment(s) disclosed. Although this certain embodiments and examples have been disclosed herein, it will be understood by those skilled in the art that the disclosed implementations extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and obvious modifications and equivalents thereof. In addition, while several variations have been shown and described in detail, other modifications will be readily apparent to those of skill in the art based upon this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope. It should be understood that various features and aspects of the disclosed embodiments can be combined with, or substituted for, one another in order to form varying modes of the disclosed implementations. Thus, it is intended that the scope of the subject matter herein disclosed should not be limited by the particular disclosed embodiments described above, but should be determined only by a fair reading of the claims that follow.

Claims (20)

What is claimed is:
1. A structure comprising:
a first element;
a carrier bonded to the first element along an interface; and
a waveguide defined at least in part along the interface between the first element and the carrier, the waveguide comprising an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel as viewed from a side cross-section of the structure.
2. The structure of claim 1, wherein the first element and the carrier are directly bonded to one another without an intervening adhesive.
3. The structure of claim 1, wherein first metallic features are defined in the first element and second metallic features are defined in the carrier, the first and second metallic features being bonded to one another to define the effectively closed metallic channel.
4. The structure of claim 3, wherein first dielectric features are defined in the first element and second dielectric features are defined in the carrier, the first and second dielectric features being bonded to one another to define the dielectric material.
5. The structure of claim 1, wherein the effectively closed metallic channel comprises gaps between portions of the metallic channel, the gaps being smaller than a wavelength of electromagnetic radiation to be propagated along the waveguide.
6. The structure of claim 5, wherein the gaps are less than 10% of the wavelength of the electromagnetic radiation.
7. The structure of claim 6, further comprising a second element bonded to the carrier along a second interface and spaced laterally from the first element, the waveguide extending from the first element to the second element and being defined at least in part along the second interface between the carrier and the second element.
8. The structure of claim 7, wherein the waveguide comprises a first waveguide portion defined by a lower surface of the first element and an upper surface of the carrier and a second waveguide portion underlying a gap between the first and second elements, wherein a height of the second waveguide portion is less than a height of the first waveguide portion.
9. The structure of claim 8, further comprising a first port extending from the first element through the metallic channel, the first port configured to couple to a first radiating element to transmit electromagnetic radiation to, or to receive electromagnetic radiation from, the waveguide.
10. The structure of claim 1, wherein the waveguide is at least partially embedded in the carrier with a wall of the metallic channel exposed at an upper surface of the carrier.
11. The structure of claim 1, wherein the carrier comprises a bridge extending between an upper surface of the first element and an upper surface a second element spaced apart from the first element, the waveguide at least partially embedded in the bridge, wherein the structure further comprises a second carrier, wherein lower surfaces of the first and second elements are bonded to the second carrier.
12. The structure of claim 1, wherein the waveguide is shaped so as to define a device comprising at least one a power divider, a coupler, a circulator, and a filter.
13. A structure comprising:
a semiconductor element having a waveguide at least partially embedded therein, the waveguide comprising an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel as viewed from a side cross-section of the structure; and
a first port extending through the effectively closed metallic channel to an exterior surface of the semiconductor element, the first port configured to couple to a radiating element to transmit electromagnetic radiation to, or to receive electromagnetic radiation from, the waveguide.
14. The structure of claim 13, wherein the first port comprises a first metallic boundary, the structure further comprising a first element bonded to the semiconductor element, the first element comprising a second port having a second metallic boundary, the first and second metallic boundaries aligned with and bonded to one another.
15. The structure of claim 14, further comprising a third port having a third metallic boundary and extending through the effectively closed metallic channel to the exterior surface of the semiconductor element, and a second element bonded to the semiconductor element and laterally spaced from the first element, the second element comprising a fourth port having a fourth metallic boundary, the third and fourth metallic boundaries aligned with and bonded to one another.
16. The structure of claim 13, wherein the effectively closed metallic channel comprises a completely closed metallic channel.
17. The structure of claim 13, wherein the effectively closed metallic channel comprises gaps between portions of the metallic channel, the gaps being smaller than a wavelength of electromagnetic radiation to be propagated along the waveguide.
18. The structure of claim 13, wherein the waveguide is completely embedded in the semiconductor element.
19. A method of forming a structure, the method comprising:
providing a first element and a carrier, wherein the first element comprises first metallic features and first dielectric features exposed on an exterior surface of the first element and the carrier comprises second metallic features and second dielectric features exposed on an exterior surface of the carrier;
bonding the first element to the carrier along an interface to bond the first metallic features and the second metallic features and to bond the first dielectric features and the second dielectric features, the bonded first element and carrier defining a waveguide at least in part along the interface between the first element and the carrier, the waveguide comprising an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel as viewed from a side cross-section of the structure.
20. The method of claim 19, wherein bonding comprises directly bonding the first element to the carrier without an intervening adhesive.
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Cited By (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170373714A1 (en) * 2016-06-28 2017-12-28 Taiwan Semiconductor Manufacturing Company Limited Systems and Methods for Die-to-Die Communication
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
US10366962B2 (en) 1999-10-01 2019-07-30 Invensas Bonding Technologies, Inc. Three dimensional device integration method and integrated device
US10434749B2 (en) 2003-05-19 2019-10-08 Invensas Bonding Technologies, Inc. Method of room temperature covalent bonding
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10522499B2 (en) 2017-02-09 2019-12-31 Invensas Bonding Technologies, Inc. Bonded structures
US10546832B2 (en) 2016-12-21 2020-01-28 Invensas Bonding Technologies, Inc. Bonded structures
US10607937B2 (en) 2015-12-18 2020-03-31 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10777533B2 (en) 2012-08-30 2020-09-15 Invensas Bonding Technologies, Inc. Heterogeneous device
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10879226B2 (en) 2016-05-19 2020-12-29 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11011418B2 (en) 2005-08-11 2021-05-18 Invensas Bonding Technologies, Inc. 3D IC method and device
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11205600B2 (en) 2014-03-12 2021-12-21 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US11257727B2 (en) 2017-03-21 2022-02-22 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US11264687B2 (en) * 2018-04-03 2022-03-01 Intel Corporation Microelectronic assemblies comprising a package substrate portion integrated with a substrate integrated waveguide filter
CN114639934A (en) * 2022-05-19 2022-06-17 四川太赫兹通信有限公司 Terahertz branch waveguide directional coupler
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US11387214B2 (en) 2017-06-15 2022-07-12 Invensas Llc Multi-chip modules formed using wafer-level processing of a reconstituted wafer
US11462480B2 (en) * 2018-06-27 2022-10-04 Intel Corporation Microelectronic assemblies having interposers
US20220352617A1 (en) * 2020-04-17 2022-11-03 Honeywell Federal Manufacturing & Technologies, Llc Blind, buried, multi-layer substrate-embedded waveguide
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11538781B2 (en) 2020-06-30 2022-12-27 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages including bonded structures
US11626363B2 (en) 2016-12-29 2023-04-11 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US11652083B2 (en) 2017-05-11 2023-05-16 Adeia Semiconductor Bonding Technologies Inc. Processed stacked dies
US11715730B2 (en) 2017-03-16 2023-08-01 Adeia Semiconductor Technologies Llc Direct-bonded LED arrays including optical elements configured to transmit optical signals from LED elements
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764189B2 (en) 2018-07-06 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Molded direct bonded and interconnected stack
US11881454B2 (en) 2016-10-07 2024-01-23 Adeia Semiconductor Inc. Stacked IC structure with orthogonal interconnect layers
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US11916054B2 (en) 2018-05-15 2024-02-27 Adeia Semiconductor Bonding Technologies Inc. Stacked devices and methods of fabrication
US11935907B2 (en) 2014-12-11 2024-03-19 Adeia Semiconductor Technologies Llc Image sensor device
US11955463B2 (en) 2019-06-26 2024-04-09 Adeia Semiconductor Bonding Technologies Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10607136B2 (en) 2017-08-03 2020-03-31 Xcelsis Corporation Time borrowing between layers of a three dimensional chip stack
TWI822659B (en) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 Structures and methods for low temperature bonding
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
WO2019241417A1 (en) 2018-06-13 2019-12-19 Invensas Bonding Technologies, Inc. Tsv as pad
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US20200075533A1 (en) 2018-08-29 2020-03-05 Invensas Bonding Technologies, Inc. Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
CN113330557A (en) 2019-01-14 2021-08-31 伊文萨思粘合技术公司 Bonding structure
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
WO2021133741A1 (en) 2019-12-23 2021-07-01 Invensas Bonding Technologies, Inc. Electrical redundancy for bonded structures
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5408053A (en) * 1993-11-30 1995-04-18 Hughes Aircraft Company Layered planar transmission lines
US20060145778A1 (en) * 2004-12-30 2006-07-06 Pleva Joseph S Waveguide - printed wiring board (PWB) interconnection
US20110115579A1 (en) * 2007-05-01 2011-05-19 Broadcom Corporation High frequency signal combining
US20120013499A1 (en) * 2009-03-31 2012-01-19 Kyocera Corporation Circuit Board, High Frequency Module, and Radar Apparatus
US20130265733A1 (en) * 2012-04-04 2013-10-10 Texas Instruments Incorporated Interchip communication using an embedded dielectric waveguide
US20140184351A1 (en) * 2012-12-27 2014-07-03 Korea Advanced Institute Of Science And Technology Low Power, High Speed Multi-Channel Chip-to-Chip Interface using Dielectric Waveguide
US20160197630A1 (en) * 2008-09-25 2016-07-07 Sony Corporation Millimeter wave transmission device, millimeter wave transmission method, and millimeter wave transmission system
US9537199B2 (en) * 2015-03-19 2017-01-03 International Business Machines Corporation Package structure having an integrated waveguide configured to communicate between first and second integrated circuit chips

Family Cites Families (104)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0272642A (en) 1988-09-07 1990-03-12 Nec Corp Structure and method for connecting substrates
JPH0344067A (en) 1989-07-11 1991-02-25 Nec Corp Laminating method of semiconductor substrate
US5015052A (en) 1989-07-20 1991-05-14 Battelle Memorial Institute Optical modulation at millimeter-wave frequencies
CA2083072C (en) 1991-11-21 1998-02-03 Shinichi Hasegawa Method for manufacturing polyimide multilayer wiring substrate
US6008126A (en) 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
US5225797A (en) 1992-04-27 1993-07-06 Cornell Research Foundation, Inc. Dielectric waveguide-to-coplanar transmission line transitions
US5471090A (en) 1993-03-08 1995-11-28 International Business Machines Corporation Electronic structures having a joining geometry providing reduced capacitive loading
US5363464A (en) 1993-06-28 1994-11-08 Tangible Domain Inc. Dielectric/conductive waveguide
DE4433330C2 (en) 1994-09-19 1997-01-30 Fraunhofer Ges Forschung Method for producing semiconductor structures with advantageous high-frequency properties and a semiconductor wafer structure
JP3979687B2 (en) 1995-10-26 2007-09-19 アプライド マテリアルズ インコーポレイテッド Method for improving film stability of halogen-doped silicon oxide films
JP3210889B2 (en) 1997-01-14 2001-09-25 シャープ株式会社 Orthogonal dual polarization waveguide input device and satellite broadcast receiving converter using the same
US6221753B1 (en) 1997-01-24 2001-04-24 Micron Technology, Inc. Flip chip technique for chip assembly
JP4032454B2 (en) 1997-06-27 2008-01-16 ソニー株式会社 Manufacturing method of three-dimensional circuit element
US6097096A (en) 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
JP2000100679A (en) 1998-09-22 2000-04-07 Canon Inc Substrate-to-substrate microregion solid-phase junction method with thinner piece and element structure
JP2001102479A (en) 1999-09-27 2001-04-13 Toshiba Corp Semiconductor integrated circuit device and manufacturing method thereof
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6442321B1 (en) 1999-12-23 2002-08-27 Spectalis Corp. Optical waveguide structures
US6614960B2 (en) 1999-12-23 2003-09-02 Speotalis Corp. Optical waveguide structures
US6801691B2 (en) 1999-12-23 2004-10-05 Spectalis Corp. Optical waveguide structures
US6300161B1 (en) 2000-02-15 2001-10-09 Alpine Microsystems, Inc. Module and method for interconnecting integrated circuits that facilitates high speed signal propagation with reduced noise
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6418029B1 (en) 2000-02-28 2002-07-09 Mckee James S. Interconnect system having vertically mounted passive components on an underside of a substrate
DE10120248A1 (en) 2000-04-26 2002-03-28 Kyocera Corp Structure for connecting a non-radiating dielectric waveguide and a metal waveguide, transmitter / receiver module for millimeter waves and transmitter / receiver for millimeter waves
JP4322402B2 (en) 2000-06-22 2009-09-02 大日本印刷株式会社 Printed wiring board and manufacturing method thereof
JP3440057B2 (en) 2000-07-05 2003-08-25 唯知 須賀 Semiconductor device and manufacturing method thereof
JP2004505294A (en) 2000-07-21 2004-02-19 マイクロ マネージド フォトンズ アクティーゼルスカブ Surface plasmon polariton band gap structure
US6970362B1 (en) 2000-07-31 2005-11-29 Intel Corporation Electronic assemblies and systems comprising interposer with embedded capacitors
US6936854B2 (en) 2001-05-10 2005-08-30 Canon Kabushiki Kaisha Optoelectronic substrate
US7010183B2 (en) 2002-03-20 2006-03-07 The Regents Of The University Of Colorado Surface plasmon devices
JP2002353416A (en) 2001-05-25 2002-12-06 Sony Corp Semiconductor storage device and manufacturing method therefor
JP2003043281A (en) 2001-07-26 2003-02-13 Kyocera Chemical Corp Optical wave guide circuit and method for manufacturing the same
US6638808B1 (en) 2002-02-04 2003-10-28 Ixys Corporation Method of manufacturing gate driver with level shift circuit
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6713871B2 (en) 2002-05-21 2004-03-30 Intel Corporation Surface mount solder method and apparatus for decoupling capacitance and process of making
US7354798B2 (en) 2002-12-20 2008-04-08 International Business Machines Corporation Three-dimensional device fabrication method
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US6943294B2 (en) 2003-12-22 2005-09-13 Intel Corporation Integrating passive components on spacer in stacked dies
US7132743B2 (en) 2003-12-23 2006-11-07 Intel Corporation Integrated circuit package substrate having a thin film capacitor structure
JP4260650B2 (en) 2004-02-26 2009-04-30 新光電気工業株式会社 Photoelectric composite substrate and manufacturing method thereof
US7842948B2 (en) 2004-02-27 2010-11-30 Nvidia Corporation Flip chip semiconductor die internal signal access system and method
TW200535878A (en) 2004-04-16 2005-11-01 Ind Tech Res Inst Tunable passive device
JP4657640B2 (en) 2004-07-21 2011-03-23 株式会社日立製作所 Semiconductor device
US7355836B2 (en) 2005-06-07 2008-04-08 Intel Corporation Array capacitor for decoupling multiple voltage rails
JP4572759B2 (en) 2005-07-06 2010-11-04 セイコーエプソン株式会社 Semiconductor device and electronic equipment
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US7705691B2 (en) 2005-10-18 2010-04-27 Agency For Science, Technology & Research Capacitor interconnection
US7626216B2 (en) 2005-10-21 2009-12-01 Mckinzie Iii William E Systems and methods for electromagnetic noise suppression using hybrid electromagnetic bandgap structures
TWI305119B (en) 2005-12-22 2009-01-01 Phoenix Prec Technology Corp Circuit board structure having capacitance array and embedded electronic component and method for fabricating the same
US7750488B2 (en) 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
US7949210B2 (en) 2006-10-09 2011-05-24 Colorado School Of Mines Silicon-compatible surface plasmon optical elements
US20080124835A1 (en) 2006-11-03 2008-05-29 International Business Machines Corporation Hermetic seal and reliable bonding structures for 3d applications
EP1936741A1 (en) 2006-12-22 2008-06-25 Sony Deutschland GmbH Flexible substrate integrated waveguides
JP2008258258A (en) 2007-04-02 2008-10-23 Sanyo Electric Co Ltd Semiconductor device
US7924113B2 (en) 2008-02-15 2011-04-12 Realtek Semiconductor Corp. Integrated front-end passive equalizer and method thereof
EP2258022A4 (en) 2008-03-18 2012-10-31 Shi Cheng Substrate integrated waveguide
US8344503B2 (en) 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
KR100945800B1 (en) 2008-12-09 2010-03-05 김영혜 Method for manufacturing heterogeneous bonded wafer
FR2954585B1 (en) 2009-12-23 2012-03-02 Soitec Silicon Insulator Technologies METHOD FOR MAKING A HETEROSTRUCTURE WITH MINIMIZATION OF STRESS
US9048112B2 (en) 2010-06-29 2015-06-02 Qualcomm Incorporated Integrated voltage regulator with embedded passive device(s) for a stacked IC
US8476146B2 (en) 2010-12-03 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing wafer distortion through a low CTE layer
TWI405322B (en) 2010-12-29 2013-08-11 Ind Tech Res Inst Embedded capacitive substrate module
FR2970594B1 (en) 2011-01-13 2013-01-18 Batscap Sa ELECTRIC ENERGY STORAGE ASSEMBLY WITH ACCORDIED STACKING ELEMENT
US8686537B2 (en) 2011-03-03 2014-04-01 Skyworks Solutions, Inc. Apparatus and methods for reducing impact of high RF loss plating
US9160346B2 (en) 2011-03-15 2015-10-13 Rambus Inc. Area and power efficient clock generation
KR101952976B1 (en) 2011-05-24 2019-02-27 소니 주식회사 Semiconductor device
US20130009595A1 (en) 2011-07-08 2013-01-10 Brown Kevin L Devices for receiving periodic charging
TWI438882B (en) 2011-11-01 2014-05-21 Unimicron Technology Corp Package substrate having embedded capacitors and fabrication method thereof
JP5703206B2 (en) 2011-12-19 2015-04-15 株式会社日立製作所 Semiconductor device, signal transmission system, and signal transmission method
US8698323B2 (en) 2012-06-18 2014-04-15 Invensas Corporation Microelectronic assembly tolerant to misplacement of microelectronic elements therein
US9502424B2 (en) 2012-06-29 2016-11-22 Qualcomm Incorporated Integrated circuit device featuring an antifuse and method of making same
TWI497661B (en) 2012-08-15 2015-08-21 Ind Tech Res Inst Semiconductor substrate assembly
US9343393B2 (en) 2012-08-15 2016-05-17 Industrial Technology Research Institute Semiconductor substrate assembly with embedded resistance element
US8829673B2 (en) 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US8916448B2 (en) 2013-01-09 2014-12-23 International Business Machines Corporation Metal to metal bonding for stacked (3D) integrated circuits
US9263186B2 (en) 2013-03-05 2016-02-16 Qualcomm Incorporated DC/ AC dual function Power Delivery Network (PDN) decoupling capacitor
US9105485B2 (en) 2013-03-08 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structures and methods of forming the same
US9029983B2 (en) 2013-03-12 2015-05-12 Qualcomm Incorporated Metal-insulator-metal (MIM) capacitor
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US9508637B2 (en) 2014-01-06 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US10090327B2 (en) 2014-01-17 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device and method for forming the same
US9853361B2 (en) 2014-05-02 2017-12-26 The Invention Science Fund I Llc Surface scattering antennas with lumped elements
US9372316B2 (en) 2014-09-11 2016-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon interface for dielectric slab waveguide
DE102014117723B4 (en) 2014-12-02 2019-01-24 Infineon Technologies Ag Semiconductor device and method of manufacturing a semiconductor device
WO2016105425A1 (en) 2014-12-24 2016-06-30 Intel Corporation Integrated passive components in a stacked integrated circuit package
JP2016143853A (en) 2015-02-05 2016-08-08 富士通株式会社 Layered semiconductor device
US20160254345A1 (en) 2015-02-27 2016-09-01 Globalfoundries Inc. Metal-insulator-metal capacitor architecture
KR101681410B1 (en) 2015-04-20 2016-11-30 삼성전기주식회사 Capacitor Component
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9627373B2 (en) 2015-08-25 2017-04-18 International Business Machines Corporation CMOS compatible fuse or resistor using self-aligned contacts
US9496239B1 (en) 2015-12-11 2016-11-15 International Business Machines Corporation Nitride-enriched oxide-to-oxide 3D wafer bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10522400B2 (en) 2016-05-27 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded temperature control system for a biosensor
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
KR20190092584A (en) 2016-12-29 2019-08-07 인벤사스 본딩 테크놀로지스 인코포레이티드 Bonded structure with integrated passive components
US20180190583A1 (en) 2016-12-29 2018-07-05 Invensas Bonding Technologies, Inc. Bonded structures with integrated passive component
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
WO2018147940A1 (en) 2017-02-09 2018-08-16 Invensas Bonding Technologies, Inc. Bonded structures
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5408053A (en) * 1993-11-30 1995-04-18 Hughes Aircraft Company Layered planar transmission lines
US20060145778A1 (en) * 2004-12-30 2006-07-06 Pleva Joseph S Waveguide - printed wiring board (PWB) interconnection
US20110115579A1 (en) * 2007-05-01 2011-05-19 Broadcom Corporation High frequency signal combining
US20160197630A1 (en) * 2008-09-25 2016-07-07 Sony Corporation Millimeter wave transmission device, millimeter wave transmission method, and millimeter wave transmission system
US20120013499A1 (en) * 2009-03-31 2012-01-19 Kyocera Corporation Circuit Board, High Frequency Module, and Radar Apparatus
US20130265733A1 (en) * 2012-04-04 2013-10-10 Texas Instruments Incorporated Interchip communication using an embedded dielectric waveguide
US20140184351A1 (en) * 2012-12-27 2014-07-03 Korea Advanced Institute Of Science And Technology Low Power, High Speed Multi-Channel Chip-to-Chip Interface using Dielectric Waveguide
US9537199B2 (en) * 2015-03-19 2017-01-03 International Business Machines Corporation Package structure having an integrated waveguide configured to communicate between first and second integrated circuit chips

Cited By (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10366962B2 (en) 1999-10-01 2019-07-30 Invensas Bonding Technologies, Inc. Three dimensional device integration method and integrated device
US10434749B2 (en) 2003-05-19 2019-10-08 Invensas Bonding Technologies, Inc. Method of room temperature covalent bonding
US11760059B2 (en) 2003-05-19 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Method of room temperature covalent bonding
US11515202B2 (en) 2005-08-11 2022-11-29 Adeia Semiconductor Bonding Technologies Inc. 3D IC method and device
US11289372B2 (en) 2005-08-11 2022-03-29 Invensas Bonding Technologies, Inc. 3D IC method and device
US11011418B2 (en) 2005-08-11 2021-05-18 Invensas Bonding Technologies, Inc. 3D IC method and device
US10777533B2 (en) 2012-08-30 2020-09-15 Invensas Bonding Technologies, Inc. Heterogeneous device
US11631586B2 (en) 2012-08-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Heterogeneous annealing method
US11205600B2 (en) 2014-03-12 2021-12-21 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US11935907B2 (en) 2014-12-11 2024-03-19 Adeia Semiconductor Technologies Llc Image sensor device
US10607937B2 (en) 2015-12-18 2020-03-31 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10896902B2 (en) 2016-01-13 2021-01-19 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US11837596B2 (en) 2016-05-19 2023-12-05 Adeia Semiconductor Bonding Technologies Inc. Stacked dies and methods for forming bonded structures
US10879226B2 (en) 2016-05-19 2020-12-29 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US11658173B2 (en) 2016-05-19 2023-05-23 Adeia Semiconductor Bonding Technologies Inc. Stacked dies and methods for forming bonded structures
US11509346B2 (en) 2016-06-28 2022-11-22 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for die-to-die communication
US20170373714A1 (en) * 2016-06-28 2017-12-28 Taiwan Semiconductor Manufacturing Company Limited Systems and Methods for Die-to-Die Communication
US10447328B2 (en) * 2016-06-28 2019-10-15 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for die-to-die communication
US11095333B2 (en) 2016-06-28 2021-08-17 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for die-to-die communication
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10998265B2 (en) 2016-09-30 2021-05-04 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US11881454B2 (en) 2016-10-07 2024-01-23 Adeia Semiconductor Inc. Stacked IC structure with orthogonal interconnect layers
US10546832B2 (en) 2016-12-21 2020-01-28 Invensas Bonding Technologies, Inc. Bonded structures
US11670615B2 (en) 2016-12-21 2023-06-06 Adeia Semiconductor Bonding Technologies Inc. Bonded structures
US10879207B2 (en) 2016-12-21 2020-12-29 Invensas Bonding Technologies, Inc. Bonded structures
US11626363B2 (en) 2016-12-29 2023-04-11 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
US10879210B2 (en) 2017-02-09 2020-12-29 Invensas Bonding Technologies, Inc. Bonded structures
US10522499B2 (en) 2017-02-09 2019-12-31 Invensas Bonding Technologies, Inc. Bonded structures
US11715730B2 (en) 2017-03-16 2023-08-01 Adeia Semiconductor Technologies Llc Direct-bonded LED arrays including optical elements configured to transmit optical signals from LED elements
US11257727B2 (en) 2017-03-21 2022-02-22 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US11417576B2 (en) 2017-03-21 2022-08-16 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US11652083B2 (en) 2017-05-11 2023-05-16 Adeia Semiconductor Bonding Technologies Inc. Processed stacked dies
US11387214B2 (en) 2017-06-15 2022-07-12 Invensas Llc Multi-chip modules formed using wafer-level processing of a reconstituted wafer
US11948847B2 (en) 2017-12-22 2024-04-02 Adeia Semiconductor Bonding Technologies Inc. Bonded structures
US11600542B2 (en) 2017-12-22 2023-03-07 Adeia Semiconductor Bonding Technologies Inc. Cavity packages
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11860415B2 (en) 2018-02-26 2024-01-02 Adeia Semiconductor Bonding Technologies Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11652264B2 (en) 2018-04-03 2023-05-16 Intel Corporation Microelectronic assemblies with substrate integrated waveguide
US11264687B2 (en) * 2018-04-03 2022-03-01 Intel Corporation Microelectronic assemblies comprising a package substrate portion integrated with a substrate integrated waveguide filter
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11955393B2 (en) 2018-05-14 2024-04-09 Adeia Semiconductor Bonding Technologies Inc. Structures for bonding elements including conductive interface features
US11916054B2 (en) 2018-05-15 2024-02-27 Adeia Semiconductor Bonding Technologies Inc. Stacked devices and methods of fabrication
US11462480B2 (en) * 2018-06-27 2022-10-04 Intel Corporation Microelectronic assemblies having interposers
US11764189B2 (en) 2018-07-06 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Molded direct bonded and interconnected stack
US11837582B2 (en) 2018-07-06 2023-12-05 Adeia Semiconductor Bonding Technologies Inc. Molded direct bonded and interconnected stack
US11894345B2 (en) 2018-08-28 2024-02-06 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US11955463B2 (en) 2019-06-26 2024-04-09 Adeia Semiconductor Bonding Technologies Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US20230335877A1 (en) * 2020-04-17 2023-10-19 Honeywell Federal Manufacturing & Technologies, Llc Blind, buried, multi-layer substrate-embedded waveguide
US11710884B2 (en) * 2020-04-17 2023-07-25 Honeywell Federal Manufacturing & Technologies, Llc Embedded waveguide including a substrate with a channel formed therein which includes conductive walls formed thereon and with solid via connections
US20220352617A1 (en) * 2020-04-17 2022-11-03 Honeywell Federal Manufacturing & Technologies, Llc Blind, buried, multi-layer substrate-embedded waveguide
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11538781B2 (en) 2020-06-30 2022-12-27 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages including bonded structures
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
CN114639934A (en) * 2022-05-19 2022-06-17 四川太赫兹通信有限公司 Terahertz branch waveguide directional coupler

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