US20180102296A1 - Substrate - Google Patents
Substrate Download PDFInfo
- Publication number
- US20180102296A1 US20180102296A1 US15/837,762 US201715837762A US2018102296A1 US 20180102296 A1 US20180102296 A1 US 20180102296A1 US 201715837762 A US201715837762 A US 201715837762A US 2018102296 A1 US2018102296 A1 US 2018102296A1
- Authority
- US
- United States
- Prior art keywords
- solder resist
- grooves
- substrate
- parallel
- build
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/036—Multilayers with layers of different types
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0209—Inorganic, non-metallic particles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Definitions
- the present invention relates generally to semiconductor technology including flip chip technologies. More specifically, the present invention relates to a substrate, in particular a stress relief pattern on solder resist layer of a substrate.
- a substrate is used for a die to be assembled thereon.
- a substrate usually comprises a build-up and a solder resist layer disposed on the build-up.
- the existing pattern of solder resist layer on a build-up of a substrate is a form of continuous flat plate.
- FIG. 1 shows an existing substrate 100 in which the pattern of the solder resist layer 101 on build-up 102 is a continuous flat plate.
- this kind of solder resist pattern layer has the several shortcomings.
- thermal expansion mismatch between the die and substrate materials induces high stress
- the continuous flat plate type pattern of solder resist layer is not beneficial to reduce the stress accumulated on large solder resist area and relieve the stress induced by material coefficient of thermal expansion (CTE) mismatch of the substrate, which causes it to be easier to render warpage of the substrate or package.
- CTE material coefficient of thermal expansion
- this pattern of the solder resist layer in the existing art is not beneficial to reduce die crack risk induced by die-substrate CTE mismatch.
- the present invention provides a substrate having an improved pattern on substrate solder resist with better performance.
- some embodiments of the present invention provide a substrate which comprises a build-up and a solder resist layer disposed on the build-up.
- the solder resist layer has an upper surface facing away from the build-up.
- the solder resist layer has a plurality of grooves on its upper surface.
- the plurality of grooves is parallel with each other.
- the plurality of parallel grooves can have a plurality of extending directions.
- the plurality of grooves comprise a first groove set including a plurality of parallel first grooves and a second groove set including a plurality of parallel second grooves, wherein the plurality of parallel first grooves intersect with the plurality of parallel second grooves.
- the intersecting angle between the plurality of parallel first grooves and the plurality of p arallel second grooves can be any angle from 0° to 90°. Preferably, the intersecting angle is 90°.
- the plurality of grooves is defined by a plurality of solder resist paths, wherein the solder resist path between every two adjacent grooves is continuous.
- the plurality of grooves is defined by a plurality of solder resist paths, wherein the solder resist path between adjacent two grooves is discontinuous.
- the discontinuous solder resist path comprises a plurality of cylindrical solder resist bumps spaced from each other.
- the discontinuous solder resist path comprises a plurality of prismatic solder resist bumps spaced from each other.
- the discontinuous solder resist path comprises a plurality of cubic solder resist bumps spaced from each other.
- the discontinuous solder resist path comprises a plurality of cylindrical, cubic and/or prismatic solder resist bumps spaced from each other.
- the present invention overcomes the above mentioned shortcomings in the existing substrate.
- FIG. 1 depicts a side schematic view of solder resist pattern in existing substrate
- FIG. 2 depicts a top schematic view of a substrate according to one explanatory embodiment
- FIG. 3 depicts a side schematic view of the substrate shown in FIG. 2 ;
- FIG. 4 depicts a top schematic view of a substrate according to another explanatory embodiment
- FIGS. 5 depicts a top schematic view of a substrate according to another explanatory embodiment
- FIG. 6 depicts a partial enlarged schematic view of an explanatory embodiment of the solder resist path shown in FIGS. 2-5 ;
- FIG. 7 depicts a partial enlarged schematic view of another explanatory embodiment of the solder resist path shown in FIGS. 2-5 ;
- FIG. 8 depicts a partial enlarged schematic view of another explanatory embodiment of the solder resist path shown in FIGS. 2-5 ;
- FIG. 9 depicts a partial enlarged schematic view of another explanatory embodiment of the solder resist path shown in FIGS. 2-5 ;
- FIG. 10 depicts a partial enlarged schematic view of another explanatory embodiment of the solder resist path shown in FIGS. 2-5 .
- the substrate 200 comprises a build-up 202 and a solder resist layer 203 .
- a C 4 area 201 of the substrate 200 is used to assemble die.
- the solder resist layer 203 is disposed on the build-up 202 and has an upper surface facing away from the build-up.
- the solder resist layer 203 has a plurality of grooves 204 on its upper surface.
- the plurality of grooves 204 are defined by a plurality of solder resist path 205 . That is to say, between every two adjacent grooves there is a solder resist path 205 .
- the plurality of grooves 204 are parallel with each other; however, this is not essential and the plurality of grooves 204 also may not be parallel with each other.
- the extending direction of the plurality of parallel grooves 204 can be any directions.
- FIG. 4 shows another embodiment of the plurality of parallel grooves 404 having different extending direction from that in FIG. 3 .
- FIG. 5 there is shown a top schematic view of a substrate 500 according to another explanatory embodiment.
- the first groove set 501 includes a plurality of parallel first grooves 503 .
- the second groove set 502 includes a plurality of parallel second grooves 504 .
- the plurality of parallel first grooves 503 intersect with the plurality of parallel second grooves 504 .
- the intersecting angle between the plurality of parallel first grooves 503 and the plurality of parallel second grooves 504 shown in FIG. 5 is 90°. However, the intersecting angle can be any angle from 0°-90°.
- solder resist path 605 is continuous.
- the solder resist paths 705 , 805 , 905 and 1005 are discontinuous.
- the solder resist path 705 in FIG. 7 comprises a plurality of cylindrical solder resist bumps 709 spaced from each other.
- the solder resist path 805 in FIG. 8 comprises a plurality of cubic solder resist bumps 809 spaced from each other.
- the prismatic solder resist bump 909 or 1009 can have other number of side.
- the substrate of present invention because there are a plurality of grooves on the upper surface of the solder resist, it can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.
- the substrate of present invention also can have reduced die crack risk induced by die-substrate CTE mismatch.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.
Description
- This application claims priority to Chinese Patent Application No. 201310066146.1, filed Mar. 1, 2013 and U.S. patent application Ser. No. 14/193,462 filed on Feb. 28, 2014, which is incorporated by reference as if fully set forth herein.
- The present invention relates generally to semiconductor technology including flip chip technologies. More specifically, the present invention relates to a substrate, in particular a stress relief pattern on solder resist layer of a substrate.
- In the die packaging technical field, a substrate is used for a die to be assembled thereon. A substrate usually comprises a build-up and a solder resist layer disposed on the build-up. The existing pattern of solder resist layer on a build-up of a substrate is a form of continuous flat plate.
FIG. 1 shows anexisting substrate 100 in which the pattern of thesolder resist layer 101 on build-up 102 is a continuous flat plate. However, this kind of solder resist pattern layer has the several shortcomings. For example, thermal expansion mismatch between the die and substrate materials induces high stress, and the continuous flat plate type pattern of solder resist layer is not beneficial to reduce the stress accumulated on large solder resist area and relieve the stress induced by material coefficient of thermal expansion (CTE) mismatch of the substrate, which causes it to be easier to render warpage of the substrate or package. In addition, this pattern of the solder resist layer in the existing art is not beneficial to reduce die crack risk induced by die-substrate CTE mismatch. - Therefore, it is desirable to provide an improved stress relief pattern of substrate solder resist to eliminate or relieve the above shortcomings in existing art.
- To overcome the shortcomings in the existing art, the present invention provides a substrate having an improved pattern on substrate solder resist with better performance.
- Specifically, some embodiments of the present invention provide a substrate which comprises a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface.
- In some embodiments, the plurality of grooves is parallel with each other.
- In certain further embodiments, the plurality of parallel grooves can have a plurality of extending directions.
- In certain further embodiments, the plurality of grooves comprise a first groove set including a plurality of parallel first grooves and a second groove set including a plurality of parallel second grooves, wherein the plurality of parallel first grooves intersect with the plurality of parallel second grooves.
- In certain further embodiments, the intersecting angle between the plurality of parallel first grooves and the plurality of p arallel second grooves can be any angle from 0° to 90°. Preferably, the intersecting angle is 90°.
- In certain further embodiments, the plurality of grooves is defined by a plurality of solder resist paths, wherein the solder resist path between every two adjacent grooves is continuous.
- In certain further embodiments, the plurality of grooves is defined by a plurality of solder resist paths, wherein the solder resist path between adjacent two grooves is discontinuous.
- In certain further embodiments, the discontinuous solder resist path comprises a plurality of cylindrical solder resist bumps spaced from each other.
- In certain further embodiments, the discontinuous solder resist path comprises a plurality of prismatic solder resist bumps spaced from each other.
- In certain further embodiments, the discontinuous solder resist path comprises a plurality of cubic solder resist bumps spaced from each other.
- In certain further embodiments, the discontinuous solder resist path comprises a plurality of cylindrical, cubic and/or prismatic solder resist bumps spaced from each other.
- By providing the above-mentioned substrate, the present invention overcomes the above mentioned shortcomings in the existing substrate.
- The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
-
FIG. 1 depicts a side schematic view of solder resist pattern in existing substrate; -
FIG. 2 depicts a top schematic view of a substrate according to one explanatory embodiment; -
FIG. 3 depicts a side schematic view of the substrate shown inFIG. 2 ; -
FIG. 4 depicts a top schematic view of a substrate according to another explanatory embodiment; -
FIGS. 5 depicts a top schematic view of a substrate according to another explanatory embodiment; -
FIG. 6 depicts a partial enlarged schematic view of an explanatory embodiment of the solder resist path shown inFIGS. 2-5 ; -
FIG. 7 depicts a partial enlarged schematic view of another explanatory embodiment of the solder resist path shown inFIGS. 2-5 ; -
FIG. 8 depicts a partial enlarged schematic view of another explanatory embodiment of the solder resist path shown inFIGS. 2-5 ; -
FIG. 9 depicts a partial enlarged schematic view of another explanatory embodiment of the solder resist path shown inFIGS. 2-5 ; and -
FIG. 10 depicts a partial enlarged schematic view of another explanatory embodiment of the solder resist path shown inFIGS. 2-5 . - Exemplary embodiments will now be described in detail with reference to a few embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention. In addition, in the detailed description of the embodiments, directional terminology, such as “top,” “bottom,” “front,” “rear,” “side,” “left,” “right,” “forward,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting.
- Referring to
FIGS. 2-3 , there is shown a top schematic view and a side schematic view of asubstrate 200 according to one explanatory embodiment. As shown inFIGS. 2-3 , thesubstrate 200 comprises a build-up 202 and asolder resist layer 203. A C4area 201 of thesubstrate 200 is used to assemble die. Thesolder resist layer 203 is disposed on the build-up 202 and has an upper surface facing away from the build-up. Thesolder resist layer 203 has a plurality ofgrooves 204 on its upper surface. The plurality ofgrooves 204 are defined by a plurality ofsolder resist path 205. That is to say, between every two adjacent grooves there is asolder resist path 205. InFIGS. 2-3 , the plurality ofgrooves 204 are parallel with each other; however, this is not essential and the plurality ofgrooves 204 also may not be parallel with each other. In addition, the extending direction of the plurality ofparallel grooves 204 can be any directions. For example,FIG. 4 shows another embodiment of the plurality ofparallel grooves 404 having different extending direction from that inFIG. 3 . - Referring to
FIG. 5 , there is shown a top schematic view of asubstrate 500 according to another explanatory embodiment. As shown inFIG. 5 , there are two groove sets on the upper surface of the solder resist layer, namely a first groove set 501 and a second groove set 502. Thefirst groove set 501 includes a plurality of parallelfirst grooves 503. Thesecond groove set 502 includes a plurality of parallelsecond grooves 504. The plurality of parallelfirst grooves 503 intersect with the plurality of parallelsecond grooves 504. The intersecting angle between the plurality of parallelfirst grooves 503 and the plurality of parallelsecond grooves 504 shown inFIG. 5 is 90°. However, the intersecting angle can be any angle from 0°-90°. - Referring to
FIGS. 6-10 , there are shown partial enlarged views of the explanatory embodiments of the solder resist paths shown inFIGS. 2-5 . InFIG. 6 , the solder resistpath 605 is continuous. InFIGS. 7-10 , the solder resistpaths path 705 inFIG. 7 comprises a plurality of cylindrical solder resistbumps 709 spaced from each other. The solder resistpath 805 inFIG. 8 comprises a plurality of cubic solder resistbumps 809 spaced from each other. The solder resistpath 905 inFIG. 9 and the solder resistpath 1005 inFIG. 10 comprise respectively a plurality of prismatic solder resistbumps bump 909 is four and the number of the side of the prismatic solder resistbump 1009 is five. Of course, the prismatic solder resistbump - In the substrate as described above, because there are a plurality of grooves on the upper surface of the solder resist, it can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package. In addition, the substrate of present invention also can have reduced die crack risk induced by die-substrate CTE mismatch.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments described herein without departing from the spirit and scope of the claimed subject matter. Thus, it is intended that the specification cover the modifications and variations of the various embodiments described herein, provided such modification and variations come within the scope of the appended claims and their equivalents.
Claims (8)
1. A substrate, comprising:
a build-up layer; and
a solder resist layer disposed on the build-up and extending a width in a first direction and a length in a second direction different from the first direction, the solder resist layer comprising:
an upper surface facing away from the build-up layer, and
a plurality of grooves disposed on the upper surface of the solder resist layer,
wherein the plurality of grooves comprise:
a first groove set including a plurality of parallel first grooves; and
a second groove set including a plurality of parallel second grooves, wherein the plurality of parallel first grooves intersect with the plurality of parallel second grooves.
2. The substrate of claim 1 , wherein the plurality of parallel first grooves intersects at an intersecting angle with the plurality of parallel second grooves and the intersecting angle is in a range from 0° to 90°.
3. The substrate of claim 1 , wherein the plurality of parallel first grooves intersects at an intersecting angle of 90° with the plurality of parallel second grooves and the intersecting angle is 90°.
4. A substrate, comprising:
a build-up layer; and
a solder resist layer disposed on the build-up and extending a width in a first direction and a length in a second direction different from the first direction, the solder resist layer comprising:
an upper surface facing away from the build-up layer, and
a plurality of grooves disposed on the upper surface of the solder resist layer,
wherein the grooves are defined by solder resist paths and a solder resist path disposed between two adjacent grooves is a discontinuous solder resist path.
5. The substrate of claim 4 , wherein the discontinuous solder resist path comprises a plurality of cylindrical solder resist bumps spaced from each other.
6. The substrate of claim 4 , wherein the discontinuous solder resist path comprises a plurality of prismatic solder resist bumps spaced from each other.
7. The substrate of claim 4 , wherein the discontinuous solder resist path comprises a plurality of cubic solder resist bumps spaced from each other.
8. The substrate of claim 4 , wherein the discontinuous solder resist path comprises a plurality of cylindrical, cubic and/or prismatic solder resist bumps spaced from each other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/837,762 US20180102296A1 (en) | 2013-03-01 | 2017-12-11 | Substrate |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310066146.1 | 2013-03-01 | ||
CN201310066146.1A CN104022085B (en) | 2013-03-01 | 2013-03-01 | A kind of substrate |
US14/193,462 US9870969B2 (en) | 2013-03-01 | 2014-02-28 | Substrate |
US15/837,762 US20180102296A1 (en) | 2013-03-01 | 2017-12-11 | Substrate |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/193,462 Division US9870969B2 (en) | 2013-03-01 | 2014-02-28 | Substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
US20180102296A1 true US20180102296A1 (en) | 2018-04-12 |
Family
ID=51420355
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/193,462 Active 2034-08-01 US9870969B2 (en) | 2013-03-01 | 2014-02-28 | Substrate |
US15/837,762 Abandoned US20180102296A1 (en) | 2013-03-01 | 2017-12-11 | Substrate |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/193,462 Active 2034-08-01 US9870969B2 (en) | 2013-03-01 | 2014-02-28 | Substrate |
Country Status (2)
Country | Link |
---|---|
US (2) | US9870969B2 (en) |
CN (1) | CN104022085B (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9530762B2 (en) | 2014-01-10 | 2016-12-27 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor package, semiconductor device and method of forming the same |
CN105657975B (en) * | 2014-12-03 | 2019-04-05 | 北大方正集团有限公司 | The production method and circuit board of circuit board |
CN105439073B (en) * | 2015-11-13 | 2017-10-24 | 华天科技(昆山)电子有限公司 | MEMS chip encapsulating structure and wafer-level packaging method |
CN105347292A (en) * | 2015-11-13 | 2016-02-24 | 华天科技(昆山)电子有限公司 | Micro-electro-mechanical-systems (MEMS) capsulation structure capable of relieving cover plate stress and capsulation method thereof |
CN110600416A (en) * | 2018-06-12 | 2019-12-20 | 上海新微技术研发中心有限公司 | Processing method of thin substrate |
CN111263507A (en) * | 2018-11-30 | 2020-06-09 | 宁波舜宇光电信息有限公司 | Circuit board jointed board and manufacturing method thereof, photosensitive assembly and camera module |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4020535A (en) * | 1975-08-01 | 1977-05-03 | Metropolitan Circuits, Inc. | Method of making an electro-discharge electrode |
JP3370498B2 (en) * | 1995-12-19 | 2003-01-27 | 新光電気工業株式会社 | Substrate for semiconductor device |
JP2003218279A (en) * | 2002-01-23 | 2003-07-31 | Shinko Electric Ind Co Ltd | Circuit board and method for manufacturing the same |
US8837161B2 (en) * | 2002-07-16 | 2014-09-16 | Nvidia Corporation | Multi-configuration processor-memory substrate device |
JP2005294546A (en) * | 2004-03-31 | 2005-10-20 | Casio Comput Co Ltd | Forming method of plated pattern |
US20080305306A1 (en) * | 2007-06-07 | 2008-12-11 | Cheemen Yu | Semiconductor molded panel having reduced warpage |
KR20100062550A (en) * | 2008-12-02 | 2010-06-10 | 삼성전기주식회사 | A package substrate including solder resist layers having pattern and a fabricating method the same |
JP2011060892A (en) * | 2009-09-08 | 2011-03-24 | Renesas Electronics Corp | Electronic device and method for manufacturing the same |
JP2011071181A (en) * | 2009-09-24 | 2011-04-07 | Hitachi Chem Co Ltd | Printed wiring board |
JP5762376B2 (en) * | 2012-09-21 | 2015-08-12 | 日本特殊陶業株式会社 | Wiring board and manufacturing method thereof |
-
2013
- 2013-03-01 CN CN201310066146.1A patent/CN104022085B/en active Active
-
2014
- 2014-02-28 US US14/193,462 patent/US9870969B2/en active Active
-
2017
- 2017-12-11 US US15/837,762 patent/US20180102296A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
CN104022085A (en) | 2014-09-03 |
US9870969B2 (en) | 2018-01-16 |
US20140246223A1 (en) | 2014-09-04 |
CN104022085B (en) | 2019-04-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20180102296A1 (en) | Substrate | |
TW200802767A (en) | A flip-chip package structure with stiffener | |
CN103000591B (en) | The ring structure of chip package | |
CN102593072A (en) | Lid design for reliability enhancement in flip package | |
US9831151B1 (en) | Heat sink for semiconductor modules | |
US9653376B1 (en) | Heat dissipation package structure | |
JP2008218669A (en) | Semiconductor device | |
US20160209121A1 (en) | Heat-dissipating structure | |
WO2009042546A3 (en) | Stacked dual-die packages, methods of making, and systems incorporating said packages | |
US20120188721A1 (en) | Non-metal stiffener ring for fcbga | |
US6825556B2 (en) | Integrated circuit package design with non-orthogonal die cut out | |
US20160284620A1 (en) | Low profile ic package | |
US20160233205A1 (en) | Method for fabricating semiconductor package | |
US9455244B2 (en) | Semiconductor package | |
US8436304B2 (en) | Infrared light transmissivity for a membrane sensor | |
US9397052B2 (en) | Semiconductor package | |
US7768131B1 (en) | Package structure preventing solder overflow on substrate solder pads | |
US20200126899A1 (en) | Printed circuit board and a semiconductor package including the same | |
US10403578B2 (en) | Electronic device package | |
US8237253B2 (en) | Package structures | |
US20150054150A1 (en) | Semiconductor package and fabrication method thereof | |
US20160118273A1 (en) | Semiconductor package and method of manufacturing the same | |
US20130233519A1 (en) | Flat heat pipe | |
US20200381320A1 (en) | Semiconductor device with a dielectric between portions | |
TWI567891B (en) | Whole layout structure of package substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD., CHINA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, I-TSENG;HSIEH, YU-LING;REEL/FRAME:044367/0575 Effective date: 20140401 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |