US20170374748A1 - Package structure and manufacturing method thereof - Google Patents

Package structure and manufacturing method thereof Download PDF

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Publication number
US20170374748A1
US20170374748A1 US15/701,435 US201715701435A US2017374748A1 US 20170374748 A1 US20170374748 A1 US 20170374748A1 US 201715701435 A US201715701435 A US 201715701435A US 2017374748 A1 US2017374748 A1 US 2017374748A1
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United States
Prior art keywords
layer
resins
circuit layer
composite
sealant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US15/701,435
Inventor
Kai-Ming Yang
Chen-Hao LIN
Wang-Hsiang Tsai
Cheng-Ta Ko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unimicron Technology Corp
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Unimicron Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW100139667A external-priority patent/TWI476888B/en
Priority claimed from TW105133848A external-priority patent/TWI637663B/en
Priority claimed from US15/391,861 external-priority patent/US11127664B2/en
Application filed by Unimicron Technology Corp filed Critical Unimicron Technology Corp
Priority to US15/701,435 priority Critical patent/US20170374748A1/en
Assigned to UNIMICRON TECHNOLOGY CORP. reassignment UNIMICRON TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KO, CHENG-TA, LIN, CHEN-HAO, TSAI, WANG-HSIANG, YANG, Kai-ming
Publication of US20170374748A1 publication Critical patent/US20170374748A1/en
Priority to US16/379,816 priority patent/US11445617B2/en
Priority to US16/672,512 priority patent/US20200068721A1/en
Priority to US17/194,323 priority patent/US11895780B2/en
Priority to US17/818,006 priority patent/US20220375919A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • the present disclosure relates to a package structure and a manufacturing method thereof.
  • one type of semiconductor devices allows a semiconductor chip having an integrated circuit (IC) to be embedded in and electrically integrated with a package substrate.
  • This semiconductor device may desirably reduce the overall size and improve the electrical functionality thereof.
  • An aspect of the disclosure is to provide a package structure and a manufacturing method thereof to solve the foregoing problems.
  • a package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer.
  • the composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer.
  • the sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material.
  • the chip is embedded in the sealant, and the chip has electrode pads. The electrode pads are exposed from the sealant.
  • the circuit layer structure is formed on the sealant and the chip.
  • the circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes.
  • the circuit layer is located on the dielectric layer and extends into the conductive blind holes.
  • the bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes.
  • the insulating protective layer is formed on the circuit layer structure.
  • the insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.
  • the chip has a chip bottom surface exposed from the sealant.
  • the material of the composite layer of the non-conductor inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.
  • the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof
  • the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.
  • the composite layer of the non-conductor inorganic material and the organic material is an imitation nacreous layer.
  • a method of manufacturing package structures includes the following steps: providing a carrier, in which the carrier includes a supporting layer having opposite two surfaces, a release layer disposed on each of the two surfaces, and a metal layer disposed on each of the release layers; disposing a composite layer of a non-conductor inorganic material and an organic material on each of the metal layers; bonding a chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material, in which the chip embedded substrate includes a plurality of chips and a sealant, the chips are embedded in the sealant, each of the chips has a plurality of electrode pads, and the electrode pads are exposed from the sealant; forming a circuit layer structure on each of the chip embedded substrates, in which the circuit layer structure includes at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and the bottommost circuit layer is electrical
  • each of the sealant has a sealant bottom surface
  • each of the chips has a chip bottom surface.
  • the step of bonding the chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material includes the following steps: grinding the sealant bottom surface to expose the chip bottom surface, so as to form a ground chip embedded substrate; and bonding the ground chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material.
  • the material of the composite layer of the non-conductor inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.
  • the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof
  • the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.
  • the composite layer of the non-conductor inorganic material and the organic material is an imitation nacreous layer.
  • the package structure and the manufacturing method thereof of the disclosure form the package substrate on the composite layer of the non-conductor inorganic material and the organic material. That is, the composite layer of the non-conductor inorganic material and the organic material can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material.
  • the overall structural strength of the package structure and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material, so as to prevent the carrier from warping, thereby improving not only the process yield, but also the reliability of the package structure.
  • FIG. 1A to FIG. 1G are cross-sectional views illustrating the steps in a manufacturing method of a package structure according to one embodiment of the disclosure
  • FIG. 2A to FIG. 2B are cross-sectional views illustrating some steps in a manufacturing method of a package structure according to another embodiment of the disclosure.
  • FIG. 3 is a cross-sectional view illustrating the package structure obtained by the manufacturing method according to FIG. 2A to FIG. 2B .
  • FIG. 1A to FIG. 1G are cross-sectional views illustrating the steps in a manufacturing method of a package structure 18 according to one embodiment of the disclosure.
  • a carrier 10 is provided.
  • Carrier 10 includes a supporting layer 100 having opposite two surfaces 100 A and 100 B, a release layer 102 disposed on each of the two surfaces 100 A and 100 B, and a metal layer 104 disposed on each of the release layers 102 .
  • the material of the supporting layer 100 may be organic polymer material such as bismaleimide triazine (BT).
  • supporting layer 100 may be a copper clad laminate (CCL) (not shown) with a dielectric material (such as prepreg) formed on the opposite two surfaces 100 A and 100 B.
  • the release layer 102 may be a release film.
  • a copper foil bonded with a release layer as provided by companies such as Mitsui, Nippon-Denk, Furukawa or Olin can be used to provide the release layer 102 .
  • the thickness of the metal layer 104 is in the range of about 1 ⁇ m to 10 ⁇ m, and the material of the metal layer 104 may be copper.
  • additional metal layer may exist between each of the opposite two surfaces 100 A and 100 B of supporting layer 100 and each release layer 102 .
  • the thickness of the additional metal layer may be in the range of about 5 ⁇ m to 40 ⁇ m, and the material of the additional metal layer may be the same as or different from that of the metal layer 104 , such as copper.
  • a composite layer of a non-conductor inorganic material and an organic material 106 is disposed on each of the metal layers 104 .
  • the material of the composite layer of the non-conductor inorganic material and the organic material 106 of this embodiment is a composite material composed of a ceramic material and a polymer material, for example.
  • the ceramic material includes zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof
  • the polymer material includes epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.
  • the ceramic material may be ceramic layers or ceramic powders, but the ceramic material of this embodiment is not limited thereto.
  • the polymer material can be impregnated in the ceramic powders using a vacuum dipping technique in the manufacturing method of the composite layer of the non-conductor inorganic material and the organic material 106 , so as to manufacture the composite layer of the non-conductor inorganic material and the organic material 106 composed of a composite material formed of the ceramic powders and the polymer material.
  • the polymer material is a photosensitive resin composition including such as an epoxy-based resin and an imide-based resin, for example
  • the composite layer of the non-conductor inorganic material and the organic material 106 is disposed on the metal layer 104 by hot pressing or vacuum dipping and then irradiating with ultraviolet light and heating, for example.
  • the polymer material can be impregnated in the ceramic layers using a vacuum dipping technique in the manufacturing method of the composite layer of the non-conductor inorganic material and the organic material 106 , so as to manufacture the composite layer of the non-conductor inorganic material and the organic material 106 composed of a composite material formed of the ceramic layers and the polymer material.
  • the manufacturing method of the composite layer of the non-conductor inorganic material and the organic material 106 of the embodiment is not limited thereto. Other methods capable of forming the composite material from the polymer material and the ceramic material are suitable.
  • the composite layer of the non-conductor inorganic material and the organic material 106 includes a composite composition of an organic matter and an inorganic matter (e.g., a composite composition of the polymer material and the ceramic layers).
  • the ceramic layers of the composite layer of the non-conductor inorganic material and the organic material 106 has a microscopic laminated structure in a sheet-shape, a brick-shape, or a combination thereof arrangement. The arrangement suppresses the conduction of transverse rupture forces, thereby significantly improving its hardness.
  • the material is strong and has flexibility, which is able to increase ceramic strength and improve ceramic brittleness, and with excellent toughness at the same time.
  • the composite layer of the non-conductor inorganic material and the organic material 106 may be an imitation nacreous layer.
  • a Young's modulus of the composite layer of the non-conductor inorganic material and the organic material 106 is between 20 GPa and 100 GPa, for example.
  • the composite layer of the non-conductor inorganic material and the organic material 106 of the embodiment has an excellent hardness, such that a structural strength of the package structure can be effectively enhanced.
  • a chip embedded substrate 12 is bonded on each of the composite layers of the non-conductor inorganic material and the organic material 106 .
  • the chip embedded substrate 12 includes a plurality of chips 120 and a sealant 122 .
  • the chips 120 are embedded in the sealant 122 , and each of the chips 120 has a plurality of electrode pads 120 P.
  • the electrode pads 120 P are exposed from the sealant 122 .
  • an adhesive layer may be used to bond the chip embedded substrate 12 on the composite layer of the non-conductor inorganic material and the organic material 106 .
  • the adhesive layer can be adhered to a substrate bottom surface 12 S of the chip embedded substrate 12 first, and then bond the chip embedded substrate 12 on the composite layer of the non-conductor inorganic material and the organic material 106 .
  • the adhesive layer can include thermal grease with high heat dissipation or high temperature resistance, but the disclosure is not limited thereto.
  • a circuit layer structure 14 is formed on each of the chip embedded substrates 12 .
  • the circuit layer structure 14 includes at least one dielectric layer and at least one circuit layer.
  • Each dielectric layer has a plurality of conductive blind holes.
  • Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes.
  • the bottommost circuit layer is electrically connected to the electrode pads 120 P through the conductive blind holes.
  • a basic unit of the circuit layer structure 14 is consisted of at least one dielectric layer and at least one circuit layer.
  • a person having ordinary skill in the art may make proper modification to the number of layers of the dielectric layer and the circuit layer according to actual needs.
  • the circuit layer structure 14 will be specify in the case of including two dielectric layers (first dielectric layer 108 and second dielectric layer 208 ) and two circuit layers (first circuit layer 110 and second circuit layer 210 ) in the following descriptions.
  • a first dielectric layer 108 is formed on each of the chip embedded substrates 12 .
  • the first dielectric layer 108 has a plurality of first conductive blind holes 108 H.
  • the material of the first dielectric layer 108 may include resin and glass fibers.
  • the resin may be novolak resin, epoxy resin, polyimide resin, or polytetrafluoroethylene.
  • the material of the first dielectric layer 108 may include photo-imageable dielectric (PID).
  • the first dielectric layer 108 may be formed by lamination.
  • the first conductive blind holes 108 H can be formed by performing a laser ablation process to the first dielectric layer 108 , or using PID as the material of the first dielectric layer 108 so as to form the first conductive blind holes 108 H by photolithography process, but not limited thereto.
  • a first circuit layer 110 is formed on each of the first dielectric layers 108 .
  • the first circuit layer 110 extends into the first conductive blind holes 108 H, such that the first circuit layer 110 is electrically connected to the electrode pads 120 P through the first conductive blind holes 108 H.
  • the first circuit layer 110 may be formed by the following steps: forming a photoresist layer (not shown) such as a dry film on the first dielectric layer 108 ; performing a photolithography process to patterning the photoresist layer, so as to expose parts of the first dielectric layer 108 ; and performing an electroplating process and removing the photoresist layer to form the first circuit layer 110 .
  • the material of the first circuit layer 110 may be copper.
  • a seed layer may be formed on the first dielectric layer 108 before forming the first circuit layer 110 .
  • the seed layer may have a single layer structure or a multi-layer structure consisted of sub-layers having different materials, such as a metal layer consisted of a titanium layer and a copper layer located on the titanium layer.
  • the method of forming the seed layer may include, but not limited to, physical methods such as titanium and copper sputtering, or chemical methods such as chemical palladium and copper plating, and copper electroplating.
  • a second dielectric layer 208 is formed on each of the first dielectric layers 108 and each of the first circuit layers 110 .
  • the second dielectric layer 208 has a plurality of second conductive blind holes 208 H.
  • a second circuit layer 210 is formed on each of the second dielectric layers 208 .
  • the second circuit layer 210 extends into the second conductive blind holes 208 H, such that the second circuit layer 210 is electrically connected to the first circuit layer 110 through second conductive blind holes 208 H.
  • the circuit layer structure 14 is formed on each of the chip embedded substrates 12 .
  • the circuit layer structure 14 includes the first dielectric layer 108 , the first circuit layer 110 , the second dielectric layer 208 , and the second circuit layer 210 .
  • the first dielectric layer 108 has a plurality of the first conductive blind holes 108 H, and the first circuit layer 110 is electrically connected to the electrode pads 120 P through the first conductive blind holes 108 H.
  • the second dielectric layer 208 has a plurality of the second conductive blind holes 208 H, and the second circuit layer 210 is electrically connected to the first circuit layer 110 through the second conductive blind holes 208 H.
  • the circuit layer structure 14 includes at least one dielectric layer (first dielectric layer 108 and second dielectric layer 208 ) and at least one circuit layer (first circuit layer 110 and second circuit layer 210 ).
  • Each dielectric layer has a plurality of conductive blind holes (first conductive blind holes 108 H and second conductive blind holes 208 H).
  • Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes.
  • the bottommost circuit layer (first circuit layer 110 ) is electrically connected to the electrode pads 120 P through the conductive blind holes (first conductive blind holes 108 H).
  • the second dielectric layer 208 , the second circuit layer 210 , and the second conductive blind holes 208 H may be similar to those of the first dielectric layer 108 , the first circuit layer 110 , and the first conductive blind holes 108 H mentioned above respectively, and therefor they are not to be repeated here again.
  • a seed layer may also be formed on the second dielectric layer 208 before forming the second circuit layer 210 as mentioned above, and therefore it is not to be repeated here again.
  • FIG. 1E An insulating protective layer 112 is formed on each of the circuit layer structures 14 .
  • the insulating protective layer 112 has a plurality of openings 112 O, so as to expose parts of the surface of the circuit layer structure 14 in the openings 112 O. Specifically, as shown in FIG. 1E , parts of the surface of the outermost second circuit layer 210 of the circuit layer structure 14 are exposed in the openings 112 O.
  • the material of the insulating protective layer 112 may be solder resist material or resin material such as epoxy resin. In other embodiments, the material of the insulating protective layer 112 may also be the same as above-mentioned material of the first dielectric layer 108 or second dielectric layer 208 .
  • the insulating protective layer 112 may be formed by laminating, printing, or coating.
  • this embodiment provides the same processes on the opposite two surfaces 100 A and 100 B of the supporting layer 100 respectively at the same time to form up-down symmetrical two package substrates 16 , so as to prevent the supporting layer 100 from warping phenomenon, and improve the reliability of the overall package structure.
  • each of the package substrates 16 is cut to obtain a plurality of package structures 18 .
  • the two package substrates 16 manufactured through FIG. 1A to FIG. 1F can produce 2N package structures 18 , and thereby the process yield can be improved significantly.
  • the package structure 18 includes the metal layer 104 , the composite layer of the non-conductor inorganic material and the organic material 106 , the sealant 122 , the chip 120 , the circuit layer structure 14 , and the insulating protective layer 112 .
  • the composite layer of the non-conductor inorganic material and the organic material 106 is disposed on the metal layer 104 .
  • the sealant 122 is bonded on the composite layer of the non-conductor inorganic material and the organic material 106 .
  • the chip 120 is embedded in the sealant 122 .
  • the chip 120 has a plurality of electrode pads 120 P, and the electrode pads 120 P are exposed from the sealant 122 .
  • the circuit layer structure 14 is formed on the sealant 122 and the chip 120 .
  • the circuit layer structure 14 includes at least one dielectric layer and at least one circuit layer. Each dielectric layer has a plurality of conductive blind holes. Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes. The bottommost circuit layer is electrically connected to the electrode pads 120 P through the conductive blind holes.
  • An insulating protective layer 112 is formed on the circuit layer structure 14 .
  • the insulating protective layer 112 has a plurality of openings 112 O, so as to expose parts of the surface of the circuit layer structure 14 in the openings 112 O.
  • the package substrate 16 is formed on the composite layer of the non-conductor inorganic material and the organic material 106 . That is, the composite layer of the non-conductor inorganic material and the organic material 106 can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material.
  • the overall structural strength of the package structure 18 and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material 106 , so as to prevent the carrier from warping phenomenon, thereby improving not only the process yield, but also the reliability of the package structure 18 .
  • the package structure 18 has the metal layer 104 in the bottom, the heat generated by the chip 120 can be dissipated by the metal layer 104 to achieve an effect of heat dissipation.
  • FIG. 2A to FIG. 2B are cross-sectional views illustrating some steps in a manufacturing method of a package structure 18 A according to another embodiment of the disclosure.
  • FIG. 3 is a cross-sectional view illustrating the package structure 18 A obtained by the manufacturing method according to FIG. 2A to FIG. 2B .
  • the method of manufacturing package structure 18 A according to this embodiment is similar to the method of manufacturing the package structure 18 as mentioned above, and the difference is that in this embodiment, the step of bonding the chip embedded substrate 12 on each of the composite layers of the non-conductor inorganic material and the organic material 106 further includes the following sub-step: grinding a sealant bottom surface 122 S to expose a chip bottom surface 120 S.
  • a sealant bottom surface 122 S is ground to expose a chip bottom surface 120 S, so as to form a ground chip embedded substrate 12 A before bonding the chip embedded substrate 12 on each of the composite layers of the non-conductor inorganic material and the organic material 106 .
  • the method of grinding the sealant bottom surface 122 S may be chemical-mechanical polishing (CMP).
  • the ground chip embedded substrate 12 A is bonded on each of the composite layers of the non-conductor inorganic material and the organic material 106 . That is, when the ground chip embedded substrate 12 A is bonded on the composite layer of the non-conductor inorganic material and the organic material 106 , the chip bottom surface 120 S is exposed from the sealant 122 .
  • an adhesive layer (not shown) may be used herein to bond the ground chip embedded substrate 12 A on each of the composite layers of the non-conductor inorganic material and the organic material 106 as above-mentioned embodiment, and therefore it is not to be repeated here again.
  • the package structure 18 A as shown in FIG. 3 is accordingly obtained.
  • the chip bottom surface 120 S is exposed from the sealant 122 , the heat generated by the chip 120 can be dissipated by the metal layer 104 more effectively thereby to further improve the effect of heat dissipation.
  • the thickness of the package structure 18 A is also reduced, which is beneficial to the miniaturization of products.
  • the package structure and the manufacturing method thereof of the disclosure form the package substrate on the composite layer of the non-conductor inorganic material and the organic material. That is, the composite layer of the non-conductor inorganic material and the organic material can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material.
  • the overall structural strength of the package structure and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material, so as to prevent the carrier from warping phenomenon, thereby improving not only the process yield, but also the reliability of the package structure.

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Abstract

A package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a continuation-in-part of U.S. application Ser. No. 15/391,861, filed Dec. 28, 2016, now pending, which is a continuation-in-part of U.S. application Ser. No. 14/602,656, filed Jan. 22, 2015, now pending, which is a divisional of U.S. application Ser. No. 13/604,968, filed Sep. 6, 2012, now patented as U.S. Pat. No. 8,946,564. The prior U.S. application Ser. No. 15/391,861 claims priority to Taiwan Application serial number 105133848, filed Oct. 20, 2016. The prior U.S. application Ser. No. 13/604,968 claims priority to Taiwan Application serial number 100139667, filed Oct. 31, 2011. This application also claims priority to Taiwan Application Serial Number 106123710, filed Jul. 14, 2017. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
    • BACKGROUND Technical Field
  • The present disclosure relates to a package structure and a manufacturing method thereof.
    • Description of Related Art
  • As the technology of semiconductor packaging advances, there have been various types of packages for semiconductor devices developed besides the conventional wire bonding semiconductor packaging technique. For example, one type of semiconductor devices allows a semiconductor chip having an integrated circuit (IC) to be embedded in and electrically integrated with a package substrate. This semiconductor device may desirably reduce the overall size and improve the electrical functionality thereof.
  • In order to satisfy the demands of shortening the length of conductive wires, reducing structure thickness, and responding to the trends of high-frequency and miniaturization, a method of processing a chip embedded substrate on a coreless carrier has been developed. However, since the coreless carrier lacks the support of a hard core board, it typically results in an insufficient strength and warpage of the overall structure may easily be caused.
    • SUMMARY
  • An aspect of the disclosure is to provide a package structure and a manufacturing method thereof to solve the foregoing problems.
  • To achieve the foregoing purpose, according to one embodiment of the disclosure, a package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The electrode pads are exposed from the sealant. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The circuit layer is located on the dielectric layer and extends into the conductive blind holes. The bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.
  • In one or more embodiments of the disclosure, the chip has a chip bottom surface exposed from the sealant.
  • In one or more embodiments of the disclosure, the material of the composite layer of the non-conductor inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.
  • In one or more embodiments of the disclosure, the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.
  • In one or more embodiments of the disclosure, the composite layer of the non-conductor inorganic material and the organic material is an imitation nacreous layer.
  • According to another embodiment of the disclosure, a method of manufacturing package structures includes the following steps: providing a carrier, in which the carrier includes a supporting layer having opposite two surfaces, a release layer disposed on each of the two surfaces, and a metal layer disposed on each of the release layers; disposing a composite layer of a non-conductor inorganic material and an organic material on each of the metal layers; bonding a chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material, in which the chip embedded substrate includes a plurality of chips and a sealant, the chips are embedded in the sealant, each of the chips has a plurality of electrode pads, and the electrode pads are exposed from the sealant; forming a circuit layer structure on each of the chip embedded substrates, in which the circuit layer structure includes at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and the bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes; forming an insulating protective layer on each of the circuit layer structures, in which the insulating protective layer has a plurality of openings, so as to expose parts of the surface of the circuit layer structure in the openings; removing the supporting layer and the release layers to form two package substrates; and cutting each of the package substrates to obtain a plurality of package structures.
  • In one or more embodiments of the disclosure, each of the sealant has a sealant bottom surface, and each of the chips has a chip bottom surface. The step of bonding the chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material includes the following steps: grinding the sealant bottom surface to expose the chip bottom surface, so as to form a ground chip embedded substrate; and bonding the ground chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material.
  • In one or more embodiments of the disclosure, the material of the composite layer of the non-conductor inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.
  • In one or more embodiments of the disclosure, the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.
  • In one or more embodiments of the disclosure, the composite layer of the non-conductor inorganic material and the organic material is an imitation nacreous layer.
  • Based on the above, the package structure and the manufacturing method thereof of the disclosure form the package substrate on the composite layer of the non-conductor inorganic material and the organic material. That is, the composite layer of the non-conductor inorganic material and the organic material can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material. Thus, the overall structural strength of the package structure and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material, so as to prevent the carrier from warping, thereby improving not only the process yield, but also the reliability of the package structure.
  • It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
  • FIG. 1A to FIG. 1G are cross-sectional views illustrating the steps in a manufacturing method of a package structure according to one embodiment of the disclosure;
  • FIG. 2A to FIG. 2B are cross-sectional views illustrating some steps in a manufacturing method of a package structure according to another embodiment of the disclosure; and
  • FIG. 3 is a cross-sectional view illustrating the package structure obtained by the manufacturing method according to FIG. 2A to FIG. 2B.
    •  DETAILED DESCRIPTION
  • Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
  • FIG. 1A to FIG. 1G are cross-sectional views illustrating the steps in a manufacturing method of a package structure 18 according to one embodiment of the disclosure. As shown in FIG. 1A, a carrier 10 is provided. Carrier 10 includes a supporting layer 100 having opposite two surfaces 100A and 100B, a release layer 102 disposed on each of the two surfaces 100A and 100B, and a metal layer 104 disposed on each of the release layers 102. In some embodiments, the material of the supporting layer 100 may be organic polymer material such as bismaleimide triazine (BT). In some embodiments, supporting layer 100 may be a copper clad laminate (CCL) (not shown) with a dielectric material (such as prepreg) formed on the opposite two surfaces 100A and 100B. In some embodiments, the release layer 102 may be a release film. In other embodiments, a copper foil bonded with a release layer as provided by companies such as Mitsui, Nippon-Denk, Furukawa or Olin can be used to provide the release layer 102. In some embodiments, the thickness of the metal layer 104 is in the range of about 1 μm to 10 μm, and the material of the metal layer 104 may be copper.
  • In some embodiments, additional metal layer may exist between each of the opposite two surfaces 100A and 100B of supporting layer 100 and each release layer 102. The thickness of the additional metal layer may be in the range of about 5 μm to 40 μm, and the material of the additional metal layer may be the same as or different from that of the metal layer 104, such as copper.
  • As shown in FIG. 1B, a composite layer of a non-conductor inorganic material and an organic material 106 is disposed on each of the metal layers 104.
  • For example, the material of the composite layer of the non-conductor inorganic material and the organic material 106 of this embodiment is a composite material composed of a ceramic material and a polymer material, for example. The ceramic material includes zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material includes epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof. The ceramic material may be ceramic layers or ceramic powders, but the ceramic material of this embodiment is not limited thereto.
  • In the embodiment of the ceramic powders, the polymer material can be impregnated in the ceramic powders using a vacuum dipping technique in the manufacturing method of the composite layer of the non-conductor inorganic material and the organic material 106, so as to manufacture the composite layer of the non-conductor inorganic material and the organic material 106 composed of a composite material formed of the ceramic powders and the polymer material. In the embodiment that the polymer material is a photosensitive resin composition including such as an epoxy-based resin and an imide-based resin, for example, the composite layer of the non-conductor inorganic material and the organic material 106 is disposed on the metal layer 104 by hot pressing or vacuum dipping and then irradiating with ultraviolet light and heating, for example.
  • In the embodiment of the ceramic layers, the polymer material can be impregnated in the ceramic layers using a vacuum dipping technique in the manufacturing method of the composite layer of the non-conductor inorganic material and the organic material 106, so as to manufacture the composite layer of the non-conductor inorganic material and the organic material 106 composed of a composite material formed of the ceramic layers and the polymer material. However, the manufacturing method of the composite layer of the non-conductor inorganic material and the organic material 106 of the embodiment is not limited thereto. Other methods capable of forming the composite material from the polymer material and the ceramic material are suitable. In the embodiment of the ceramic layers, more specifically, the composite layer of the non-conductor inorganic material and the organic material 106 includes a composite composition of an organic matter and an inorganic matter (e.g., a composite composition of the polymer material and the ceramic layers). Based on the adhesion of the organic matter to the inorganic matter, the ceramic layers of the composite layer of the non-conductor inorganic material and the organic material 106 has a microscopic laminated structure in a sheet-shape, a brick-shape, or a combination thereof arrangement. The arrangement suppresses the conduction of transverse rupture forces, thereby significantly improving its hardness. Therefore, the material is strong and has flexibility, which is able to increase ceramic strength and improve ceramic brittleness, and with excellent toughness at the same time. The composite layer of the non-conductor inorganic material and the organic material 106 may be an imitation nacreous layer.
  • In some embodiments, a Young's modulus of the composite layer of the non-conductor inorganic material and the organic material 106 is between 20 GPa and 100 GPa, for example. Compared with a commonly used dielectric layer (with a Young's modulus not more than 10 GPa) and an encapsulating material (with a Young's modulus not more than 20 GPa), the composite layer of the non-conductor inorganic material and the organic material 106 of the embodiment has an excellent hardness, such that a structural strength of the package structure can be effectively enhanced.
  • As shown in FIG. 1C, a chip embedded substrate 12 is bonded on each of the composite layers of the non-conductor inorganic material and the organic material 106. The chip embedded substrate 12 includes a plurality of chips 120 and a sealant 122. The chips 120 are embedded in the sealant 122, and each of the chips 120 has a plurality of electrode pads 120P. The electrode pads 120P are exposed from the sealant 122.
  • In some embodiments, an adhesive layer (not shown) may be used to bond the chip embedded substrate 12 on the composite layer of the non-conductor inorganic material and the organic material 106. Specifically, the adhesive layer can be adhered to a substrate bottom surface 12S of the chip embedded substrate 12 first, and then bond the chip embedded substrate 12 on the composite layer of the non-conductor inorganic material and the organic material 106. The adhesive layer can include thermal grease with high heat dissipation or high temperature resistance, but the disclosure is not limited thereto.
  • As shown in FIG. 1D to FIG. 1E, a circuit layer structure 14 is formed on each of the chip embedded substrates 12. The circuit layer structure 14 includes at least one dielectric layer and at least one circuit layer. Each dielectric layer has a plurality of conductive blind holes. Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes. The bottommost circuit layer is electrically connected to the electrode pads 120P through the conductive blind holes.
  • A basic unit of the circuit layer structure 14 is consisted of at least one dielectric layer and at least one circuit layer. A person having ordinary skill in the art may make proper modification to the number of layers of the dielectric layer and the circuit layer according to actual needs. In this embodiment, the circuit layer structure 14 will be specify in the case of including two dielectric layers (first dielectric layer 108 and second dielectric layer 208) and two circuit layers (first circuit layer 110 and second circuit layer 210) in the following descriptions.
  • As shown in FIG. 1D, a first dielectric layer 108 is formed on each of the chip embedded substrates 12. The first dielectric layer 108 has a plurality of first conductive blind holes 108H. In some embodiments, the material of the first dielectric layer 108 may include resin and glass fibers. The resin may be novolak resin, epoxy resin, polyimide resin, or polytetrafluoroethylene. In other embodiments, the material of the first dielectric layer 108 may include photo-imageable dielectric (PID). In some embodiments, the first dielectric layer 108 may be formed by lamination. In some embodiments, the first conductive blind holes 108H can be formed by performing a laser ablation process to the first dielectric layer 108, or using PID as the material of the first dielectric layer 108 so as to form the first conductive blind holes 108H by photolithography process, but not limited thereto.
  • Please continue to refer to FIG. 1D. A first circuit layer 110 is formed on each of the first dielectric layers 108. The first circuit layer 110 extends into the first conductive blind holes 108H, such that the first circuit layer 110 is electrically connected to the electrode pads 120P through the first conductive blind holes 108H. In some embodiments, the first circuit layer 110 may be formed by the following steps: forming a photoresist layer (not shown) such as a dry film on the first dielectric layer 108; performing a photolithography process to patterning the photoresist layer, so as to expose parts of the first dielectric layer 108; and performing an electroplating process and removing the photoresist layer to form the first circuit layer 110. In some embodiment, the material of the first circuit layer 110 may be copper.
  • In some embodiment, a seed layer may be formed on the first dielectric layer 108 before forming the first circuit layer 110. The seed layer may have a single layer structure or a multi-layer structure consisted of sub-layers having different materials, such as a metal layer consisted of a titanium layer and a copper layer located on the titanium layer. The method of forming the seed layer may include, but not limited to, physical methods such as titanium and copper sputtering, or chemical methods such as chemical palladium and copper plating, and copper electroplating.
  • As shown in FIG. 1E, a second dielectric layer 208 is formed on each of the first dielectric layers 108 and each of the first circuit layers 110. The second dielectric layer 208 has a plurality of second conductive blind holes 208H. A second circuit layer 210 is formed on each of the second dielectric layers 208. The second circuit layer 210 extends into the second conductive blind holes 208H, such that the second circuit layer 210 is electrically connected to the first circuit layer 110 through second conductive blind holes 208H.
  • Accordingly, the circuit layer structure 14 is formed on each of the chip embedded substrates 12. The circuit layer structure 14 includes the first dielectric layer 108, the first circuit layer 110, the second dielectric layer 208, and the second circuit layer 210. The first dielectric layer 108 has a plurality of the first conductive blind holes 108H, and the first circuit layer 110 is electrically connected to the electrode pads 120P through the first conductive blind holes 108H. The second dielectric layer 208 has a plurality of the second conductive blind holes 208H, and the second circuit layer 210 is electrically connected to the first circuit layer 110 through the second conductive blind holes 208H. That is, the circuit layer structure 14 includes at least one dielectric layer (first dielectric layer 108 and second dielectric layer 208) and at least one circuit layer (first circuit layer 110 and second circuit layer 210). Each dielectric layer has a plurality of conductive blind holes (first conductive blind holes 108H and second conductive blind holes 208H). Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes. The bottommost circuit layer (first circuit layer 110) is electrically connected to the electrode pads 120P through the conductive blind holes (first conductive blind holes 108H).
  • Details about the forming methods and the materials of the second dielectric layer 208, the second circuit layer 210, and the second conductive blind holes 208H may be similar to those of the first dielectric layer 108, the first circuit layer 110, and the first conductive blind holes 108H mentioned above respectively, and therefor they are not to be repeated here again. Moreover, a seed layer may also be formed on the second dielectric layer 208 before forming the second circuit layer 210 as mentioned above, and therefore it is not to be repeated here again.
  • Reference is made to FIG. 1E. An insulating protective layer 112 is formed on each of the circuit layer structures 14. The insulating protective layer 112 has a plurality of openings 112O, so as to expose parts of the surface of the circuit layer structure 14 in the openings 112O. Specifically, as shown in FIG. 1E, parts of the surface of the outermost second circuit layer 210 of the circuit layer structure 14 are exposed in the openings 112O.
  • In some embodiments, the material of the insulating protective layer 112 may be solder resist material or resin material such as epoxy resin. In other embodiments, the material of the insulating protective layer 112 may also be the same as above-mentioned material of the first dielectric layer 108 or second dielectric layer 208. The insulating protective layer 112 may be formed by laminating, printing, or coating.
  • As shown on FIG. 1F, the supporting layer 100 and the release layers 102 are removed to form two package substrates 16. Therefore, compared to conventional one-side manufacturing method, which easily causes the warpage because of its structural asymmetry, this embodiment provides the same processes on the opposite two surfaces 100A and 100B of the supporting layer 100 respectively at the same time to form up-down symmetrical two package substrates 16, so as to prevent the supporting layer 100 from warping phenomenon, and improve the reliability of the overall package structure.
  • Lastly, as shown in FIG. 1G, each of the package substrates 16 is cut to obtain a plurality of package structures 18. Thus, if each package substrate 16 can produce N package structures 18, the two package substrates 16 manufactured through FIG. 1A to FIG. 1F can produce 2N package structures 18, and thereby the process yield can be improved significantly.
  • Accordingly, the package structure 18 according to this embodiment is obtained. The package structure 18 includes the metal layer 104, the composite layer of the non-conductor inorganic material and the organic material 106, the sealant 122, the chip 120, the circuit layer structure 14, and the insulating protective layer 112. The composite layer of the non-conductor inorganic material and the organic material 106 is disposed on the metal layer 104. The sealant 122 is bonded on the composite layer of the non-conductor inorganic material and the organic material 106. The chip 120 is embedded in the sealant 122. The chip 120 has a plurality of electrode pads 120P, and the electrode pads 120P are exposed from the sealant 122. The circuit layer structure 14 is formed on the sealant 122 and the chip 120. The circuit layer structure 14 includes at least one dielectric layer and at least one circuit layer. Each dielectric layer has a plurality of conductive blind holes. Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes. The bottommost circuit layer is electrically connected to the electrode pads 120P through the conductive blind holes. An insulating protective layer 112 is formed on the circuit layer structure 14. The insulating protective layer 112 has a plurality of openings 112O, so as to expose parts of the surface of the circuit layer structure 14 in the openings 112O.
  • According to the package structure 18 and the manufacturing method thereof provided in the disclosure, the package substrate 16 is formed on the composite layer of the non-conductor inorganic material and the organic material 106. That is, the composite layer of the non-conductor inorganic material and the organic material 106 can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material. Thus, the overall structural strength of the package structure 18 and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material 106, so as to prevent the carrier from warping phenomenon, thereby improving not only the process yield, but also the reliability of the package structure 18.
  • Moreover, since the package structure 18 has the metal layer 104 in the bottom, the heat generated by the chip 120 can be dissipated by the metal layer 104 to achieve an effect of heat dissipation.
  • FIG. 2A to FIG. 2B are cross-sectional views illustrating some steps in a manufacturing method of a package structure 18A according to another embodiment of the disclosure. FIG. 3 is a cross-sectional view illustrating the package structure 18A obtained by the manufacturing method according to FIG. 2A to FIG. 2B. The method of manufacturing package structure 18A according to this embodiment is similar to the method of manufacturing the package structure 18 as mentioned above, and the difference is that in this embodiment, the step of bonding the chip embedded substrate 12 on each of the composite layers of the non-conductor inorganic material and the organic material 106 further includes the following sub-step: grinding a sealant bottom surface 122S to expose a chip bottom surface 120S.
  • Please refer to FIG. 2A and FIG. 1C at the same time. The difference between this embodiment and the step shown in FIG. 1C is that a sealant bottom surface 122S is ground to expose a chip bottom surface 120S, so as to form a ground chip embedded substrate 12A before bonding the chip embedded substrate 12 on each of the composite layers of the non-conductor inorganic material and the organic material 106. In some embodiment, the method of grinding the sealant bottom surface 122S may be chemical-mechanical polishing (CMP).
  • As shown in FIG. 2B, the ground chip embedded substrate 12A is bonded on each of the composite layers of the non-conductor inorganic material and the organic material 106. That is, when the ground chip embedded substrate 12A is bonded on the composite layer of the non-conductor inorganic material and the organic material 106, the chip bottom surface 120S is exposed from the sealant 122.
  • In some embodiments, an adhesive layer (not shown) may be used herein to bond the ground chip embedded substrate 12A on each of the composite layers of the non-conductor inorganic material and the organic material 106 as above-mentioned embodiment, and therefore it is not to be repeated here again.
  • Then, continue the steps in FIG. 1D to FIG. 1G, and the package structure 18A as shown in FIG. 3 is accordingly obtained. In this embodiment, since the chip bottom surface 120S is exposed from the sealant 122, the heat generated by the chip 120 can be dissipated by the metal layer 104 more effectively thereby to further improve the effect of heat dissipation. Moreover, the thickness of the package structure 18A is also reduced, which is beneficial to the miniaturization of products.
  • According to the foregoing recitations of the embodiments of the disclosure, it can be seen that the package structure and the manufacturing method thereof of the disclosure form the package substrate on the composite layer of the non-conductor inorganic material and the organic material. That is, the composite layer of the non-conductor inorganic material and the organic material can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material. Thus, the overall structural strength of the package structure and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material, so as to prevent the carrier from warping phenomenon, thereby improving not only the process yield, but also the reliability of the package structure.
  • Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.

Claims (10)

What is claimed is:
1. A package structure, comprising:
a metal layer;
a composite layer of a non-conductor inorganic material and an organic material disposed on the metal layer;
a sealant bonded on the composite layer of the non-conductive inorganic material and the organic material;
a chip embedded in the sealant, wherein the chip has a plurality of electrode pads, and the electrode pads are exposed from the sealant;
a circuit layer structure formed on the sealant and the chip, wherein the circuit layer structure comprises at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and a bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes; and
an insulating protective layer formed on the circuit layer structure, wherein the insulating protective layer has a plurality of openings, so as to expose parts of a surface of the circuit layer structure in the openings.
2. The package structure of claim 1, wherein the chip has a chip bottom surface exposed from the sealant.
3. The package structure of claim 1, wherein a material of the composite layer of the non-conductor inorganic material and the organic material comprises a composite material composed of a ceramic material and a polymer material.
4. The package structure of claim 3, wherein the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.
5. The package structure of claim 1, wherein the composite layer of the non-conductor inorganic material and the organic material is an imitation nacreous layer.
6. A method of manufacturing package structures, comprising:
providing a carrier, wherein the carrier comprises a supporting layer having opposite two surfaces, a release layer disposed on each of the two surfaces, and a metal layer disposed on each of the release layers;
disposing a composite layer of a non-conductor inorganic material and an organic material on each of the metal layers;
bonding a chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material, wherein the chip embedded substrate comprises a plurality of chips and a sealant, the chips are embedded in the sealant, each of the chips has a plurality of electrode pads, and the electrode pads are exposed from the sealant;
forming a circuit layer structure on each of the chip embedded substrates, wherein the circuit layer structure comprises at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and a bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes;
forming an insulating protective layer on each of the circuit layer structures, wherein the insulating protective layer has a plurality of openings, so as to expose parts of a surface of the circuit layer structure in the openings;
removing the supporting layer and the release layers to form two package substrates; and
cutting each of the package substrates to obtain a plurality of the package structures.
7. The method of claim 6, wherein each of the sealants has a sealant bottom surface, and each of the chips has a chip bottom surface, wherein the step of bonding the chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material comprises:
grinding the sealant bottom surface to expose the chip bottom surface, so as to form a ground chip embedded substrate; and
bonding the ground chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material.
8. The method of claim 6, wherein a material of each of the composite layers of the non-conductor inorganic material and the organic material comprises a composite material composed of a ceramic material and a polymer material.
9. The method of claim 8, wherein the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.
10. The method of claim 6, wherein each of the composite layers of the non-conductor inorganic material and the organic material is an imitation nacreous layer.
US15/701,435 2011-10-31 2017-09-11 Package structure and manufacturing method thereof Abandoned US20170374748A1 (en)

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US15/701,435 US20170374748A1 (en) 2011-10-31 2017-09-11 Package structure and manufacturing method thereof
US16/379,816 US11445617B2 (en) 2011-10-31 2019-04-10 Package structure and manufacturing method thereof
US16/672,512 US20200068721A1 (en) 2011-10-31 2019-11-03 Package structure and manufacturing method thereof
US17/194,323 US11895780B2 (en) 2011-10-31 2021-03-08 Manufacturing method of package structure
US17/818,006 US20220375919A1 (en) 2011-10-31 2022-08-08 Manufacturing method of package structure

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
TW100139667A TWI476888B (en) 2011-10-31 2011-10-31 Package substrate having embedded via hole medium layer and fabrication method thereof
TW100139667 2011-10-31
US13/604,968 US8946564B2 (en) 2011-10-31 2012-09-06 Packaging substrate having embedded through-via interposer and method of fabricating the same
US14/602,656 US9781843B2 (en) 2011-10-31 2015-01-22 Method of fabricating packaging substrate having embedded through-via interposer
TW105133848A TWI637663B (en) 2016-10-20 2016-10-20 Circuit board and manufacturing method thereof
TW105133848 2016-10-20
US15/391,861 US11127664B2 (en) 2011-10-31 2016-12-28 Circuit board and manufacturing method thereof
TW103123710 2017-07-14
US15/701,435 US20170374748A1 (en) 2011-10-31 2017-09-11 Package structure and manufacturing method thereof

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