US20170236750A1 - Method for Via Plating with Seed Layer - Google Patents

Method for Via Plating with Seed Layer Download PDF

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Publication number
US20170236750A1
US20170236750A1 US15/584,981 US201715584981A US2017236750A1 US 20170236750 A1 US20170236750 A1 US 20170236750A1 US 201715584981 A US201715584981 A US 201715584981A US 2017236750 A1 US2017236750 A1 US 2017236750A1
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Prior art keywords
layer
forming
electroplating solution
metallic
seed layer
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US15/584,981
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Shin-Yi Yang
Ching-Fu YEH
Tz-Jun Kuo
Hsiang-Huan Lee
Ming-Han Lee
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US15/584,981 priority Critical patent/US20170236750A1/en
Publication of US20170236750A1 publication Critical patent/US20170236750A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428

Definitions

  • the plating process may be performed by electroplating, where an electric current is used to transfer metal in an aqueous solution to a surface.
  • a seed layer may be deposited prior to electroplating. The seed layer provides nucleation sites where the electroplated metal initially forms. The electroplated metal deposits more uniformly on a conformal and even seed layer than on a bare dielectric.
  • FIGS. 1-9 are cross-sectional views of intermediate steps in a plating process for a via opening according to an embodiment
  • FIG. 10 is a flow diagram illustrating a method of plating using protection layer according to an embodiment.
  • the present disclosure describes embodiments with regard to a specific context, namely plating using a protection layer over a seed layer.
  • the embodiments of the disclosure may also be applied, however, to a variety of semiconductor devices, plating scenarios or other electrochemical deposition techniques.
  • various embodiments will be explained in detail with reference to the accompanying drawings.
  • Plating of semiconductor device surface features is commonly achieved using an electroplating technique, where an ionic metal in solution is deposited on a substrate.
  • a metal may be deposited directly on a semiconductor substrate, or on a seed layer.
  • An electric current passed through the substrate and into the solution causes migration of the metal in the solution to the surface of the substrate.
  • Copper is a commonly used metal for electroplating due to its cost, well understood plating properties, and adhesion to many different substrates.
  • Other metals used in the electroplating process may include gold, aluminum, tungsten, cobalt, nickel, chromium, silver, compounds, or alloys of the same, or other conductive materials.
  • various additives may be added to the electroplating solution.
  • Disclosed herein is a method for reducing defects and providing uniform plating using a protection layer over a seed layer.
  • the protection layer is removed during the plating process by an acid in the electroplating solution.
  • the protection layer removal and plating process are performed in the same processing step, preventing the seed layer from oxidizing and eliminating voids and plating failures where the plated layer adjoins the seed layer.
  • FIG. 1 illustrates an initial step in electroplating according to an embodiment.
  • a substrate 102 has a conductive trace 108 disposed therein.
  • An etch stop layer 104 is formed over the substrate 102 and trace 108 , and a dielectric layer 106 is formed over the etch stop layer 106 .
  • the conductive trace 108 is exposed at the top surface of the substrate 102 so that a via may be formed over and in electrical contact with the conductive trace 108 by etching the etch stop layer 104 and the dielectric layer 106 .
  • the etch stop layer 104 is a nitride, oxynitride, carbide, a carbon nitride or the like.
  • the dielectric layer 106 may be an oxide, oxynitride or another dielectric material.
  • the material of the etch stop layer 104 is selected to have a high etch selectivity compared to the dielectric layer 106 .
  • the dielectric layer may be silicon dioxide (SiO 2 ), and the etch stop layer 104 may be silicon oxynitride (SiON), silicon carbide (SiC), silicon nitride (SiN) or silicon carbon nitride (SiCN), which each have a high etch selectivity compared to SiO 2 .
  • SiON silicon oxynitride
  • SiC silicon carbide
  • SiN silicon nitride
  • SiCN silicon carbon nitride
  • the etch stop layer 104 and dielectric layer 106 are each formed separately using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), by a spin-on process, or another deposition process.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced CVD
  • the etch stop layer 104 is, in an embodiment, formed with a thickness between about 1 Angstrom and about 100 Angstroms and the dielectric layer is formed with a thickness between about 1000 Angstroms and about 3000 Angstroms.
  • FIG. 2 is a cross-sectional view illustrating formation of a mask 202 on the dielectric layer 106 according to an embodiment.
  • a mask 202 such as a photoresist, hard mask or the like is formed on the dielectric layer 106 .
  • the mask 202 is patterned with one or more openings 204 through which the dielectric 106 is etched. For example, where the mask 202 is a photoresist, the photoresist is spun on, sprayed on, or otherwise applied, and exposed and developed to form the opening 204 .
  • FIG. 3 is a cross-sectional view illustrating etching of the dielectric 106 according to an embodiment.
  • a trench opening or via opening 302 is formed by etching the dielectric layer 106 and etch stop layer 104 to expose at least a portion of the conductive trace 108 . While the masking and etching is shown as using a single mask 202 , in some embodiments the via opening 302 is formed from multiple masking and etching steps to result in a stepped via opening 302 profile as shown in FIG. 3 .
  • the via opening 302 is etched to have sidewalls 304 defined by the dielectric layer 106 and the etch stop layer 104 .
  • the via opening 302 is formed using a dry etch such as a plasma etch to result in a substantially anisotropic etch, with substantially vertical sidewalls and without undercutting the mask 202 (See, e.g., FIG. 2 ).
  • a dry etch such as a plasma etch to result in a substantially anisotropic etch, with substantially vertical sidewalls and without undercutting the mask 202 (See, e.g., FIG. 2 ).
  • the via opening 302 may be etched with carbon tetraflouride (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen triflouride (NF 3 ), or the like in a plasma or reactive ion etching (RIE) chamber.
  • RIE reactive ion etching
  • wet etching, ion milling, or another etching technique may be advantageously employed depending on the desired etched via opening 302 shape, material of the dielectric layer 106 , material of the etch stop layer 104
  • FIG. 4 is a cross-sectional view illustrating formation of a seed layer 402 in the via opening 302 according to an embodiment.
  • the seed layer 402 is formed as a conformal coating on the via opening surface 304 , and in some embodiments, is also formed on the top surface of the dielectric layer 106 .
  • the seed layer 402 extends through the dielectric layer 106 and the etch stop layer 104 to the bottom of the via opening 302 to contact the trace 108
  • the seed layer 402 is a metal such as copper (Cu), aluminum (Al), titanium (Ti), gold (Au), manganese (Mn), an alloy, or another material that accepts an electroplated layer.
  • the seed layer 402 is formed by atomic layer deposition (ALD), plasma enhanced ALD (PEALD), CVD, PECVD or another process to a thickness between about 1 Angstrom and about 100 Angstroms.
  • FIG. 5 is a cross-sectional view illustrating formation of a protection layer 502 according to an embodiment.
  • the protection layer 502 is formed over the seed layer 402 , protecting the seed layer 402 from oxidation and contamination.
  • the protection layer 502 is formed by ALD, PEALD, CVD, PECVD or another deposition process to a thickness between about 1 Angstrom and about 50 Angstroms.
  • the seed layer 402 and the protection layer 502 are formed in an inert environment to prevent oxidation of the seed layer prior to and during formation of the protection layer.
  • the seed layer 402 and protection layer 502 are formed in a single CVD processing chamber in an argon (Ar) environment.
  • the argon environment is maintained during formation of the seed layer 402 and through the formation of the protection layer 502 .
  • the argon displaces oxygen that would oxidize the seed layer 402 , resulting in a seed layer 402 substantially free of oxidation after formation of the protection layer 502 .
  • the protection layer 502 is formed from a material having a lower reduction-oxidation potential than the material to be plated.
  • the protection layer 502 is Mn, cobalt (Co), Ti, Al, vanadium (V), chromium (Cr), zinc (Zn), zirconium (Zr), and alloys or oxides of the same.
  • FIG. 6 is a cross sectional view illustrating removal of the protection layer 502 and formation of the via layer 602 by in a single process step according to an embodiment.
  • Impurities introduced into the seed layer 402 by oxidation cause gaps, voids and defects in the electroplated structure, resulting in inconsistencies and reliability problems in finished devices.
  • the via layer 602 and seed layer 402 are substantially free of oxidation in the center region of the via opening 302 .
  • the simultaneous removal of the protection layer 502 and formation of the via layer 602 in a single process step prevents oxidation of the seed layer since the seed layer 402 is never exposed to an oxidizer prior to formation of the via layer 602 .
  • the via layer 602 is formed by electroplating.
  • the workpiece with the protection layer 502 (See, FIG. 5 ) and seed layer 402 are submersed in an electroplating solution 604 having an acid that removes the protection layer 502 without significantly interfering with the electroplating process.
  • the acid component of the electroplating solution 604 permits the removal of the protection layer 502 and formation of the via layer 602 in a single processing step. Maintaining the seed layer 402 in the electroplating solution 604 during removal of the protection layer 402 and through formation of the via layer 602 prevents oxidation of the seed layer 402 .
  • the via layer 602 is formed by a wet plating process such as electroless nickel plating, electroless palladium plating, immersion tin plating, immersion gold plating, immersion silver plating or another plating process.
  • the via layer 602 is copper
  • the electroplating solution has copper sulfate (CuSO 4 ) and sulfuric acid (H 2 SO 4 ) providing the ionic copper plating source and the acid for removing the protection layer 302 .
  • the electroplating solution has an ionic copper (Cu+) concentration by weight between about 2.0% and about 3.7%.
  • the sulfuric acid concentration is great enough to reduce the pH of the electroplating solution to about 6.0 or less.
  • the electroplating process is accomplished by applying a voltage potential between the seed layer 402 and an anode in the electroplating solution 604 .
  • a positive voltage is applied to the anode, with a lower voltage applied to the seed layer 402 .
  • the voltage causes the ionic copper in the electroplating solution 604 to deposit on the seed layer 402 .
  • the electroplating voltage controls the rate at which the deposition material accumulates on the seed layer 402 .
  • a higher voltage results in a more rapid via layer 602 formation.
  • the voltage is maintained at a level sufficient to overcome the etching of the via layer 602 by the acid in the electroplating solution 604 .
  • the voltage will cause the electroplating material to be deposited faster than it is etched away by the acid in the electroplating solution 604 .
  • the pH or reactivity of the electroplating solution 604 dictates adjustments of the voltage. For example, a pH of around 6 require a lower electroplating voltage to prevent overgrowth of the via layer 602 and formation of voids in the via opening as the corners of the via later close at the top of the via opening. In contrast, a pH of, for example 4 requires a higher voltage since the higher reactivity of the acid in the electroplating solution 604 removes material from the via layer 602 faster than a lower pH solution.
  • the electroplating solution 604 may also have additional processing components.
  • many electroplating solutions also include additives such as brighteners, levelers, and suppressors.
  • Organic compounds are added to an electroplating solution and act as levelers and brighteners, increasing uniformity of metal deposition on different regions of the target surface including through holes and recesses.
  • salts such as chlorides
  • Organic compound such as polyethylene glycol (PEG) or, alternatively, polyalkylene glycol (PAG) function as suppressors, while organic sulfides such as Bis(3-sulfopropyl)-disodium-sulfonate (C 6 H 12 Na 2 O 6 S 4 ) (SPS) work as accelerators.
  • PEG polyethylene glycol
  • PAG polyalkylene glycol
  • SPS Bis(3-sulfopropyl)-disodium-sulfonate
  • FIG. 7 is a cross-sectional illustrating a via layer 602 after electroplating according to an embodiment.
  • the via layer 602 extends above the top surface of the dielectric layer 106 and contacts the upper or outer surface of the seed layer 402 .
  • FIG. 8 is a cross-sectional illustrating a via layer 602 after electroplating according to an embodiment.
  • the via layer 602 is removed to expose an upper surface of the dielectric layer 106 .
  • the via layer 602 (See, FIG. 7 ) and seed layer 402 are reduced, for example, by chemical-mechanical polishing (CMP), grinding, milling, polishing, etching or another technique to result in a via 802 in the dielectric layer and extending to the trace 108 .
  • CMP chemical-mechanical polishing
  • the dielectric layer 106 , etch stop layer 104 and via 802 form a structure such as an intermetal dielectric (ILD).
  • the electroplating process described herein may also be used for forming metal structures in passivation layers, on PCBs, on packaging, or in other fabrication scenarios.
  • a redistribution layer may have a plurality of dielectric layers with vias formed therein by electroplating in successive electroplating processing steps.
  • FIG. 9 is a cross sectional view of a device having a plurality of intermetal dielectric layers (IMDs) 804 with electroplated vias 802 disposed therein according to an embodiment.
  • An active device 902 such as a transistor has source/drain regions 904 disposed in a substrate 910 .
  • Such a transistor also has a gate with a gate contact 906 disposed over a gate oxide 908 and gate spacers 912 disposed on the sidewalls of the gate contact 906 .
  • a passivation layer 914 such as an oxide, nitride or the like is disposed over the transistor 902 and has one or more contacts 916 extending there through to the transistor 902 to provide electrical connectivity to higher layers.
  • An RDL over the passivation layer 914 has one or more ILD layers 804 and one or more metallization layers 918 arranged in a stack to provide connectivity between the transistor 902 and an external die, device, board, contact grid or like structure.
  • the ILD layers 804 each have a dielectric layer 106 and etch top layer 104 , with one or more vias 802 disposed therein.
  • Each ILD layer 804 is formed using an iteration of the protection layer and electroplating process described above with respect to FIGS. 1-8 .
  • Metallization layers 918 having a dielectric and one or more metal features 922 may be disposed between the ILD layers 804 , providing lateral connectivity between the vias 802 .
  • FIG. 10 is a flow diagram illustrating a method 100 for forming a plated via according to an embodiment.
  • the via layer is formed by electroplating.
  • a dielectric layer is formed in block 1002 , and a mask is formed and patterned in block 1004 .
  • the dielectric layer is etched in block 1006 using the patterned mask.
  • the forming the mask, patterning the mask and etching the dielectric layer are performed multiple times to form a via opening with a complex or stepped profile.
  • a seed layer is formed within the via opening in block 1008 , and a protection layer is formed over the seed layer in block 1010 .
  • the dielectric layer, with the seed layer and protection layer, is submersed in a plating solution such as a electroplating solution, in block 1012 .
  • the protection layer is removed in block 1014 and the via layer is plated in block 1016 .
  • the protection layer is removed and the via layer is plated in a single process step, namely, while the dielectric layer is submersed in the plating solution.
  • Excess via layer material and seed layer material are removed in block 1018 by reducing the via layer and seed layer though polishing, CMP, or the like. Additionally layers are formed in block 1020 .
  • a method of forming a structure comprises forming a via opening in a dielectric layer, forming a seed layer on a sidewall of the via opening, forming a protection layer over the seed layer, and exposing the protection layer and the seed layer to an electroplating solution, the electroplating solution removing the protection layer and depositing a via layer on the seed layer.
  • a via is formed by reducing a surface of the via layer.
  • the electroplating solution comprises an acid, and the acid removes the protection layer during exposure of the protection layer to the electroplating solution.
  • the electroplating solution has a pH of less than about 6 and comprises an ionic metal at a concentration by weight between about 2.0% and about 3.7%, with the ionic metal deposited on the seed layer to form the via layer.
  • the protection layer has a reduction-oxidation potential lower than a material of the ionic metal.
  • the ionic metal is copper, and the protection layer comprises at least one of manganese, cobalt, titanium, aluminum, vanadium, chromium, zinc, zirconium, or oxides of the same.
  • a method for plating comprises providing a substrate having a dielectric layer formed over a trace, and forming a via opening extending through the dielectric layer, the via opening exposing a surface of the trace.
  • the method further comprises forming a seed layer in the via opening and contacting the trace and forming a protection layer over the seed layer.
  • the protection layer is removed and a via layer deposited on the seed layer in a single plating process step by applying a plating solution in the via opening.
  • a method of forming a structure comprises a plurality of intermetal dielectrics (IMDs) having at least one via disposed through dielectric layer.
  • Forming each of the plurality of IMDs comprises forming a seed layer in a via opening in dielectric layer, forming a seed layer in the via opening and contacting a metal feature below the etch stop layer, forming a protection layer over the seed layer and forming a via layer in the via opening and in contact with the seed layer by applying an electroplating solution in the via opening, the electroplating solution removing the protection layer and depositing a via layer on the seed layer.
  • a via is formed by reducing a surface of the via layer, the via disposed in the via opening.
  • a metallization layer is formed over at least one of the plurality of IMDs.
  • embodiments disclosed herein may provide for a method of forming a structure that includes forming a via opening in a dielectric layer, and forming a seed layer on a sidewall of the via opening. The method further includes forming a metallic protection layer over the seed layer, and simultaneously removing the metallic protection layer and depositing a via layer on the seed layer.
  • embodiments disclosed herein may provide for a method including providing a substrate having a dielectric layer formed over a trace, and forming a via opening extending through the dielectric layer, the via opening exposing a surface of the trace. The method further includes forming a seed layer in the via opening and contacting the trace, and forming a conductive protection layer over the seed layer. The method yet further includes simultaneously removing the protection layer and depositing a via layer on the seed layer in a single plating process step.
  • embodiments disclosed herein may provide for a method of forming a structure that includes forming a plurality of intermetal dielectrics (IMDs) having at least one via disposed through a dielectric layer.
  • Forming each of the plurality of IMDs includes the steps of forming a seed layer in the via opening and contacting a metal feature below the dielectric layer, forming a protection layer over the seed layer, and simultaneously removing the protection layer and forming a via layer in the via opening and in contact with the seed layer by applying an electroplating solution in the via opening.
  • a metallization layer may be formed over at least one of the plurality of IMDs.
  • embodiments described herein provide for a method of forming a structure, comprising forming an opening in a material layer, lining the opening with a metallic protection layer, and simultaneously removing the metallic protection layer and depositing a conductor in the opening.
  • embodiments described herein provide for a method comprising forming a conductive trace in an integrated circuit, depositing a dielectric layer over the conductive trace, and patterning the dielectric layer to form an opening therein, the opening exposing at least a portion of the conductive trace.
  • the method further includes lining the opening with a seed layer, depositing a protection layer over the seed layer, submersing the protection layer and the seed layer in an electroplating solution, and filling the lined opening with a conductor, while removing the protection layer using an acidic component of the electroplating solution.
  • embodiments described herein provide for a method comprising: forming a material layer on a workpiece, forming an opening in the material layer, and lining the opening with a seed layer.
  • the method further comprises covering the seed layer with metallic protection layer, and subjecting the workpiece to a plating process, wherein the protection layer is removed and a conductor is plated on the seed layer in a single process chamber.

Abstract

Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

Description

    PRIORITY CLAIM
  • This application is a continuation of U.S. patent application Ser. No. 15/138,033, filed on Apr. 25, 2016, and entitled “Method for Via Plating with Seed Layer,” which is a continuation of U.S. patent application Ser. No. 14/720,264, now U.S. Pat. No. 9,324,608, filed on May 22, 2015, and entitled “Method for Via Plating with Seed Layer” which claims priority to and is a continuation application of U.S. patent application Ser. No. 14/072,890, filed Nov. 6, 2013, now U.S. Pat. No. 9,054,163 issued on Jun. 9, 2015, and entitled “Method for Via Plating with Seed Layer,” which applications are incorporated herein by reference.
    • BACKGROUND
  • As modern integrated circuits shrink in size, the associated features shrink in size as well. As transistor shrink, features such as through vias and other electroplated elements shrink in size as well. In many instances, various layers of circuit on chips, dies, in packages, on PCBs and other substrates are interconnected between various layers by way of vias. Typically, the vias are connected to traces or other conductive structures to route electrical signals through dielectric layers. One way of forming a conductive interconnect in a via or trench opening is to form the opening and then plate a conductive metal in the inside of the opening. In some instances, copper, gold, aluminum or other material are plated in the via/trench openings.
  • The plating process may be performed by electroplating, where an electric current is used to transfer metal in an aqueous solution to a surface. In order to facilitate the plating process, a seed layer may be deposited prior to electroplating. The seed layer provides nucleation sites where the electroplated metal initially forms. The electroplated metal deposits more uniformly on a conformal and even seed layer than on a bare dielectric.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
  • FIGS. 1-9 are cross-sectional views of intermediate steps in a plating process for a via opening according to an embodiment; and
  • FIG. 10 is a flow diagram illustrating a method of plating using protection layer according to an embodiment.
    •
  • Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.
    • DETAILED DESCRIPTION
  • The making and using of the illustrative embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments of the disclosure, and do not limit the scope of the disclosure.
  • The present disclosure describes embodiments with regard to a specific context, namely plating using a protection layer over a seed layer. The embodiments of the disclosure may also be applied, however, to a variety of semiconductor devices, plating scenarios or other electrochemical deposition techniques. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.
  • Plating of semiconductor device surface features is commonly achieved using an electroplating technique, where an ionic metal in solution is deposited on a substrate. In some instances, a metal may be deposited directly on a semiconductor substrate, or on a seed layer. An electric current passed through the substrate and into the solution causes migration of the metal in the solution to the surface of the substrate. Copper is a commonly used metal for electroplating due to its cost, well understood plating properties, and adhesion to many different substrates. Other metals used in the electroplating process may include gold, aluminum, tungsten, cobalt, nickel, chromium, silver, compounds, or alloys of the same, or other conductive materials. In order to control the rate and quality of plating, surface properties, and other variables related to electroplating, various additives may be added to the electroplating solution.
  • Disclosed herein is a method for reducing defects and providing uniform plating using a protection layer over a seed layer. The protection layer is removed during the plating process by an acid in the electroplating solution. The protection layer removal and plating process are performed in the same processing step, preventing the seed layer from oxidizing and eliminating voids and plating failures where the plated layer adjoins the seed layer.
  • FIG. 1 illustrates an initial step in electroplating according to an embodiment. A substrate 102 has a conductive trace 108 disposed therein. An etch stop layer 104 is formed over the substrate 102 and trace 108, and a dielectric layer 106 is formed over the etch stop layer 106.
  • The conductive trace 108 is exposed at the top surface of the substrate 102 so that a via may be formed over and in electrical contact with the conductive trace 108 by etching the etch stop layer 104 and the dielectric layer 106. In an embodiment, the etch stop layer 104 is a nitride, oxynitride, carbide, a carbon nitride or the like. The dielectric layer 106 may be an oxide, oxynitride or another dielectric material. The material of the etch stop layer 104 is selected to have a high etch selectivity compared to the dielectric layer 106. For example, the dielectric layer may be silicon dioxide (SiO2), and the etch stop layer 104 may be silicon oxynitride (SiON), silicon carbide (SiC), silicon nitride (SiN) or silicon carbon nitride (SiCN), which each have a high etch selectivity compared to SiO2.
  • The etch stop layer 104 and dielectric layer 106 are each formed separately using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), by a spin-on process, or another deposition process. The etch stop layer 104 is, in an embodiment, formed with a thickness between about 1 Angstrom and about 100 Angstroms and the dielectric layer is formed with a thickness between about 1000 Angstroms and about 3000 Angstroms.
  • FIG. 2 is a cross-sectional view illustrating formation of a mask 202 on the dielectric layer 106 according to an embodiment. A mask 202 such as a photoresist, hard mask or the like is formed on the dielectric layer 106. The mask 202 is patterned with one or more openings 204 through which the dielectric 106 is etched. For example, where the mask 202 is a photoresist, the photoresist is spun on, sprayed on, or otherwise applied, and exposed and developed to form the opening 204.
  • FIG. 3 is a cross-sectional view illustrating etching of the dielectric 106 according to an embodiment. A trench opening or via opening 302 is formed by etching the dielectric layer 106 and etch stop layer 104 to expose at least a portion of the conductive trace 108. While the masking and etching is shown as using a single mask 202, in some embodiments the via opening 302 is formed from multiple masking and etching steps to result in a stepped via opening 302 profile as shown in FIG. 3. The via opening 302 is etched to have sidewalls 304 defined by the dielectric layer 106 and the etch stop layer 104.
  • In an embodiment, the via opening 302 is formed using a dry etch such as a plasma etch to result in a substantially anisotropic etch, with substantially vertical sidewalls and without undercutting the mask 202 (See, e.g., FIG. 2). For example, where the dielectric layer is SiO2, the via opening 302 may be etched with carbon tetraflouride (CF4), sulfur hexafluoride (SF6), nitrogen triflouride (NF3), or the like in a plasma or reactive ion etching (RIE) chamber. However, wet etching, ion milling, or another etching technique may be advantageously employed depending on the desired etched via opening 302 shape, material of the dielectric layer 106, material of the etch stop layer 104, or other processing parameter.
  • FIG. 4 is a cross-sectional view illustrating formation of a seed layer 402 in the via opening 302 according to an embodiment. In an embodiment, the seed layer 402 is formed as a conformal coating on the via opening surface 304, and in some embodiments, is also formed on the top surface of the dielectric layer 106. The seed layer 402 extends through the dielectric layer 106 and the etch stop layer 104 to the bottom of the via opening 302 to contact the trace 108
  • In an embodiment, the seed layer 402 is a metal such as copper (Cu), aluminum (Al), titanium (Ti), gold (Au), manganese (Mn), an alloy, or another material that accepts an electroplated layer. The seed layer 402 is formed by atomic layer deposition (ALD), plasma enhanced ALD (PEALD), CVD, PECVD or another process to a thickness between about 1 Angstrom and about 100 Angstroms.
  • FIG. 5 is a cross-sectional view illustrating formation of a protection layer 502 according to an embodiment. The protection layer 502 is formed over the seed layer 402, protecting the seed layer 402 from oxidation and contamination. The protection layer 502 is formed by ALD, PEALD, CVD, PECVD or another deposition process to a thickness between about 1 Angstrom and about 50 Angstroms. In an embodiment, the seed layer 402 and the protection layer 502 are formed in an inert environment to prevent oxidation of the seed layer prior to and during formation of the protection layer. For example, the seed layer 402 and protection layer 502 are formed in a single CVD processing chamber in an argon (Ar) environment. The argon environment is maintained during formation of the seed layer 402 and through the formation of the protection layer 502. The argon displaces oxygen that would oxidize the seed layer 402, resulting in a seed layer 402 substantially free of oxidation after formation of the protection layer 502.
  • The protection layer 502 is formed from a material having a lower reduction-oxidation potential than the material to be plated. For example, in an embodiment where the seed layer 402 is copper, and the electroplating material is copper, the protection layer 502 is Mn, cobalt (Co), Ti, Al, vanadium (V), chromium (Cr), zinc (Zn), zirconium (Zr), and alloys or oxides of the same.
  • FIG. 6 is a cross sectional view illustrating removal of the protection layer 502 and formation of the via layer 602 by in a single process step according to an embodiment. Impurities introduced into the seed layer 402 by oxidation cause gaps, voids and defects in the electroplated structure, resulting in inconsistencies and reliability problems in finished devices. Thus, by removing the protection layer 502 and forming the via layer 602, simultaneously, or in a single step while in a plating bath such as an electroplating solution, the via layer 602 and seed layer 402 are substantially free of oxidation in the center region of the via opening 302. The simultaneous removal of the protection layer 502 and formation of the via layer 602 in a single process step prevents oxidation of the seed layer since the seed layer 402 is never exposed to an oxidizer prior to formation of the via layer 602.
  • In an embodiment, the via layer 602 is formed by electroplating. The workpiece with the protection layer 502 (See, FIG. 5) and seed layer 402 are submersed in an electroplating solution 604 having an acid that removes the protection layer 502 without significantly interfering with the electroplating process. The acid component of the electroplating solution 604 permits the removal of the protection layer 502 and formation of the via layer 602 in a single processing step. Maintaining the seed layer 402 in the electroplating solution 604 during removal of the protection layer 402 and through formation of the via layer 602 prevents oxidation of the seed layer 402. In other embodiment, the via layer 602 is formed by a wet plating process such as electroless nickel plating, electroless palladium plating, immersion tin plating, immersion gold plating, immersion silver plating or another plating process.
  • In an embodiment, the via layer 602 is copper, and the electroplating solution has copper sulfate (CuSO4) and sulfuric acid (H2SO4) providing the ionic copper plating source and the acid for removing the protection layer 302. In such an embodiment, the electroplating solution has an ionic copper (Cu+) concentration by weight between about 2.0% and about 3.7%. In such an embodiment, the sulfuric acid concentration is great enough to reduce the pH of the electroplating solution to about 6.0 or less.
  • The electroplating process is accomplished by applying a voltage potential between the seed layer 402 and an anode in the electroplating solution 604. A positive voltage is applied to the anode, with a lower voltage applied to the seed layer 402. The voltage causes the ionic copper in the electroplating solution 604 to deposit on the seed layer 402. The electroplating voltage controls the rate at which the deposition material accumulates on the seed layer 402. A higher voltage results in a more rapid via layer 602 formation. The voltage is maintained at a level sufficient to overcome the etching of the via layer 602 by the acid in the electroplating solution 604. Thus, the voltage will cause the electroplating material to be deposited faster than it is etched away by the acid in the electroplating solution 604. The pH or reactivity of the electroplating solution 604 dictates adjustments of the voltage. For example, a pH of around 6 require a lower electroplating voltage to prevent overgrowth of the via layer 602 and formation of voids in the via opening as the corners of the via later close at the top of the via opening. In contrast, a pH of, for example 4 requires a higher voltage since the higher reactivity of the acid in the electroplating solution 604 removes material from the via layer 602 faster than a lower pH solution.
  • The electroplating solution 604 may also have additional processing components. In order to provide a smoother plated surface and reduce the errors introduced in small features by plating, many electroplating solutions also include additives such as brighteners, levelers, and suppressors. Organic compounds are added to an electroplating solution and act as levelers and brighteners, increasing uniformity of metal deposition on different regions of the target surface including through holes and recesses. Additionally, salts such as chlorides, may also be included in an electroplating bath to as a brightener and to increase the deposition of plating materials Organic compound such polyethylene glycol (PEG) or, alternatively, polyalkylene glycol (PAG) function as suppressors, while organic sulfides such as Bis(3-sulfopropyl)-disodium-sulfonate (C6H12Na2O6S4) (SPS) work as accelerators.
  • FIG. 7 is a cross-sectional illustrating a via layer 602 after electroplating according to an embodiment. The via layer 602 extends above the top surface of the dielectric layer 106 and contacts the upper or outer surface of the seed layer 402.
  • FIG. 8 is a cross-sectional illustrating a via layer 602 after electroplating according to an embodiment. In such an embodiment, the via layer 602 is removed to expose an upper surface of the dielectric layer 106. The via layer 602 (See, FIG. 7) and seed layer 402 are reduced, for example, by chemical-mechanical polishing (CMP), grinding, milling, polishing, etching or another technique to result in a via 802 in the dielectric layer and extending to the trace 108. Thus, in an embodiment, the dielectric layer 106, etch stop layer 104 and via 802 form a structure such as an intermetal dielectric (ILD). However, in other embodiments, the electroplating process described herein may also be used for forming metal structures in passivation layers, on PCBs, on packaging, or in other fabrication scenarios.
  • The embodiments described above with respect to FIGS. 1-8 illustrate formation of a single via in a single dielectric layer. However, the above described embodiments are illustrative as to a method for electroplating a via, and are not intended to be limiting. For example, in an embodiment, a redistribution layer (RDL) may have a plurality of dielectric layers with vias formed therein by electroplating in successive electroplating processing steps.
  • FIG. 9 is a cross sectional view of a device having a plurality of intermetal dielectric layers (IMDs) 804 with electroplated vias 802 disposed therein according to an embodiment. An active device 902 such as a transistor has source/drain regions 904 disposed in a substrate 910. Such a transistor also has a gate with a gate contact 906 disposed over a gate oxide 908 and gate spacers 912 disposed on the sidewalls of the gate contact 906. A passivation layer 914 such as an oxide, nitride or the like is disposed over the transistor 902 and has one or more contacts 916 extending there through to the transistor 902 to provide electrical connectivity to higher layers.
  • An RDL over the passivation layer 914 has one or more ILD layers 804 and one or more metallization layers 918 arranged in a stack to provide connectivity between the transistor 902 and an external die, device, board, contact grid or like structure. The ILD layers 804 each have a dielectric layer 106 and etch top layer 104, with one or more vias 802 disposed therein. Each ILD layer 804 is formed using an iteration of the protection layer and electroplating process described above with respect to FIGS. 1-8. Metallization layers 918 having a dielectric and one or more metal features 922 may be disposed between the ILD layers 804, providing lateral connectivity between the vias 802.
  • FIG. 10 is a flow diagram illustrating a method 100 for forming a plated via according to an embodiment. In such an embodiment, the via layer is formed by electroplating. A dielectric layer is formed in block 1002, and a mask is formed and patterned in block 1004. The dielectric layer is etched in block 1006 using the patterned mask. In an embodiment, the forming the mask, patterning the mask and etching the dielectric layer are performed multiple times to form a via opening with a complex or stepped profile. A seed layer is formed within the via opening in block 1008, and a protection layer is formed over the seed layer in block 1010. The dielectric layer, with the seed layer and protection layer, is submersed in a plating solution such as a electroplating solution, in block 1012. The protection layer is removed in block 1014 and the via layer is plated in block 1016. The protection layer is removed and the via layer is plated in a single process step, namely, while the dielectric layer is submersed in the plating solution. Excess via layer material and seed layer material are removed in block 1018 by reducing the via layer and seed layer though polishing, CMP, or the like. Additionally layers are formed in block 1020.
  • Thus, according to an embodiment, a method of forming a structure comprises forming a via opening in a dielectric layer, forming a seed layer on a sidewall of the via opening, forming a protection layer over the seed layer, and exposing the protection layer and the seed layer to an electroplating solution, the electroplating solution removing the protection layer and depositing a via layer on the seed layer. A via is formed by reducing a surface of the via layer. The electroplating solution comprises an acid, and the acid removes the protection layer during exposure of the protection layer to the electroplating solution. The electroplating solution has a pH of less than about 6 and comprises an ionic metal at a concentration by weight between about 2.0% and about 3.7%, with the ionic metal deposited on the seed layer to form the via layer. The protection layer has a reduction-oxidation potential lower than a material of the ionic metal. The ionic metal is copper, and the protection layer comprises at least one of manganese, cobalt, titanium, aluminum, vanadium, chromium, zinc, zirconium, or oxides of the same.
  • According to another embodiment, a method for plating comprises providing a substrate having a dielectric layer formed over a trace, and forming a via opening extending through the dielectric layer, the via opening exposing a surface of the trace. The method further comprises forming a seed layer in the via opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a via layer deposited on the seed layer in a single plating process step by applying a plating solution in the via opening.
  • According to another embodiment, a method of forming a structure comprises a plurality of intermetal dielectrics (IMDs) having at least one via disposed through dielectric layer. Forming each of the plurality of IMDs comprises forming a seed layer in a via opening in dielectric layer, forming a seed layer in the via opening and contacting a metal feature below the etch stop layer, forming a protection layer over the seed layer and forming a via layer in the via opening and in contact with the seed layer by applying an electroplating solution in the via opening, the electroplating solution removing the protection layer and depositing a via layer on the seed layer. A via is formed by reducing a surface of the via layer, the via disposed in the via opening. A metallization layer is formed over at least one of the plurality of IMDs.
  • In one aspect, embodiments disclosed herein may provide for a method of forming a structure that includes forming a via opening in a dielectric layer, and forming a seed layer on a sidewall of the via opening. The method further includes forming a metallic protection layer over the seed layer, and simultaneously removing the metallic protection layer and depositing a via layer on the seed layer.
  • In another aspect, embodiments disclosed herein may provide for a method including providing a substrate having a dielectric layer formed over a trace, and forming a via opening extending through the dielectric layer, the via opening exposing a surface of the trace. The method further includes forming a seed layer in the via opening and contacting the trace, and forming a conductive protection layer over the seed layer. The method yet further includes simultaneously removing the protection layer and depositing a via layer on the seed layer in a single plating process step.
  • In yet another aspects embodiments disclosed herein may provide for a method of forming a structure that includes forming a plurality of intermetal dielectrics (IMDs) having at least one via disposed through a dielectric layer. Forming each of the plurality of IMDs includes the steps of forming a seed layer in the via opening and contacting a metal feature below the dielectric layer, forming a protection layer over the seed layer, and simultaneously removing the protection layer and forming a via layer in the via opening and in contact with the seed layer by applying an electroplating solution in the via opening. Additionally, a metallization layer may be formed over at least one of the plurality of IMDs.
  • In one aspect, embodiments described herein provide for a method of forming a structure, comprising forming an opening in a material layer, lining the opening with a metallic protection layer, and simultaneously removing the metallic protection layer and depositing a conductor in the opening.
  • In another aspect, embodiments described herein provide for a method comprising forming a conductive trace in an integrated circuit, depositing a dielectric layer over the conductive trace, and patterning the dielectric layer to form an opening therein, the opening exposing at least a portion of the conductive trace. The method further includes lining the opening with a seed layer, depositing a protection layer over the seed layer, submersing the protection layer and the seed layer in an electroplating solution, and filling the lined opening with a conductor, while removing the protection layer using an acidic component of the electroplating solution.
  • In yet another aspect, embodiments described herein provide for a method comprising: forming a material layer on a workpiece, forming an opening in the material layer, and lining the opening with a seed layer. The method further comprises covering the seed layer with metallic protection layer, and subjecting the workpiece to a plating process, wherein the protection layer is removed and a conductor is plated on the seed layer in a single process chamber.
  • Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.
  • Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (20)

What is claimed is:
1. A method of forming a structure, the method comprising:
etching an opening in a dielectric layer;
depositing a seed layer on the dielectric layer in the opening;
depositing a metallic protection layer over the seed layer; and
removing the metallic protection layer while forming a conductor in the opening, wherein the seed layer is protected from oxidation during the depositing the metallic protection layer, the removing the metallic protection layer, and the depositing the conductor.
2. The method of claim 1, wherein removing the metallic protection layer and forming the conductor comprises exposing the metallic protection layer to an electroplating solution.
3. The method of claim 2, wherein the electroplating solution comprises copper sulfate (CuSO4) and sulfuric acid (H2 50 4).
4. The method of claim 3, wherein the electroplating solution comprises acid for removing the metallic protection layer.
5. The method of claim 3, wherein the electroplating solution has an ionic copper (Cu+) concentration by weight between about 2.0% and about 3.7%.
6. The method of claim 3, wherein a pH of the electroplating solution to about 6.0 or less.
7. The method of claim 1, wherein the metallic protection layer has a thickness between about 1 Angstrom and about 50 Angstroms.
8. The method of claim 1, wherein depositing the metallic protection layer is performed in an inert environment.
9. A method of forming a structure, the method comprising:
forming a seed layer on exposed surfaces of an opening in a dielectric layer;
forming a metallic protecting layer on the seed layer, wherein the seed layer and the metallic protecting layer are formed in an inert environment; and
forming a conductor in the opening using an electroplating solution, the electroplating solution comprising an agent for removing the metallic protecting layer during the forming the conductor in the opening.
10. The method of claim 9, wherein the metallic protecting layer comprises manganese (Mn), cobalt (Co), Ti, Al, vanadium (V), chromium (Cr), zinc (Zn), or zirconium (Zr).
11. The method of claim 9, wherein the agent for removing the metallic protecting layer comprises an acid.
12. The method of claim 9, wherein the electroplating solution has an ionic copper (Cu+) concentration by weight between about 2.0% and about 3.7%.
13. The method of claim 9, wherein the metallic protecting layer has a lower reduction-oxidation potential than the conductor.
14. The method of claim 9, wherein the electroplating solution comprises copper sulfate (CuSO4) and sulfuric acid (H2SO4).
15. The method of claim 9, wherein removing the metallic protecting layer comprises submerging the metallic protecting layer in the electroplating solution.
16. A method of forming a structure, the method comprising:
forming a plurality of intermetal dielectrics (IMDs) having at least one via disposed through a dielectric layer, wherein forming each of the plurality of IMDs comprising:
forming a seed layer in an opening in the dielectric layer, the seed layer contacting a metal feature below the dielectric layer;
forming a metallic protection layer over the seed layer; and
applying an electroplating solution in the opening to form a via layer in the opening, the electroplating solution removing the metallic protection layer and depositing the via layer such that the via layer directly contacts the seed layer; and
forming a metallization layer over at least one of the plurality of IMDs.
17. The method of claim 16, wherein the electroplating solution comprises copper sulfate (CuSO4) and sulfuric acid (H2SO4).
18. The method of claim 16, wherein the electroplating solution has an ionic copper (Cu+) concentration by weight between about 2.0% and about 3.7%.
19. The method of claim 16, wherein applying the electroplating solution comprises submerging the metallic protection layer in the electroplating solution.
20. The method of claim 16, wherein the metallic protection layer comprises manganese (Mn), cobalt (Co), Ti, Al, vanadium (V), chromium (Cr), zinc (Zn), or zirconium (Zr).
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