US20170203961A1 - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
- Publication number
- US20170203961A1 US20170203961A1 US15/000,521 US201615000521A US2017203961A1 US 20170203961 A1 US20170203961 A1 US 20170203961A1 US 201615000521 A US201615000521 A US 201615000521A US 2017203961 A1 US2017203961 A1 US 2017203961A1
- Authority
- US
- United States
- Prior art keywords
- membrane
- plate
- conductor
- dielectric
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title description 18
- 239000012528 membrane Substances 0.000 claims abstract description 117
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 239000004020 conductor Substances 0.000 claims abstract description 62
- 239000010703 silicon Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000011135 tin Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 229910000597 tin-copper alloy Inorganic materials 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 229910001020 Au alloy Inorganic materials 0.000 claims 2
- 229910000881 Cu alloy Inorganic materials 0.000 claims 2
- 229910000676 Si alloy Inorganic materials 0.000 claims 2
- 229910001128 Sn alloy Inorganic materials 0.000 claims 2
- 239000010410 layer Substances 0.000 description 67
- 239000011241 protective layer Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000002829 reductive effect Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000002094 self assembled monolayer Substances 0.000 description 3
- 239000013545 self-assembled monolayer Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910008433 SnCU Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
- B81C1/00158—Diaphragms, membranes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
- B81B3/0018—Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
- B81B3/0027—Structures for transforming mechanical energy, e.g. potential energy of a spring into translation, sound into translation
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
- B81B3/0018—Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
- B81B3/0021—Transducers for transforming electrical into mechanical energy or vice versa
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
- B81B3/0064—Constitution or structural means for improving or controlling the physical properties of a device
- B81B3/0067—Mechanical properties
- B81B3/0078—Constitution or structural means for improving mechanical properties not provided for in B81B3/007 - B81B3/0075
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
- B81C1/0038—Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R1/00—Details of transducers, loudspeakers or microphones
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R19/00—Electrostatic transducers
- H04R19/005—Electrostatic transducers using semiconductor materials
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R19/00—Electrostatic transducers
- H04R19/04—Microphones
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R31/00—Apparatus or processes specially adapted for the manufacture of transducers or diaphragms therefor
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R7/00—Diaphragms for electromechanical transducers; Cones
- H04R7/02—Diaphragms for electromechanical transducers; Cones characterised by the construction
- H04R7/12—Non-planar diaphragms or cones
- H04R7/14—Non-planar diaphragms or cones corrugated, pleated or ribbed
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0257—Microphones or microspeakers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2203/00—Basic microelectromechanical structures
- B81B2203/01—Suspended structures, i.e. structures allowing a movement
- B81B2203/0127—Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2203/00—Basic microelectromechanical structures
- B81B2203/03—Static structures
- B81B2203/0315—Cavities
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/01—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
- B81B2207/012—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being separate parts in the same package
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/07—Interconnects
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
Definitions
- MEMS devices have been recently developed and are also commonly involved in electronic equipment.
- the MEMS device is a micro-sized device, usually in a range from less than 1 micron to several millimeters in size.
- the MEMS device includes fabrication using semiconductive materials to form mechanical and electrical features.
- the MEMS device may include a number of elements (e.g., stationary or movable elements) for achieving electro-mechanical functionality.
- MEMS devices are widely used in various applications.
- MEMS applications include motion sensors, pressure sensors, printer nozzles, or the like.
- Other MEMS applications include inertial sensors, such as accelerometers for measuring linear acceleration and gyroscopes for measuring angular velocity.
- MEMS applications are extended to optical applications, such as movable mirrors, and radio frequency (RF) applications, such as RF switches or the like.
- RF radio frequency
- FIG. 1 is a schematic view of a semiconductor structure in accordance with some embodiments.
- FIG. 2 is a schematic view of a semiconductor structure in accordance with some embodiments.
- FIG. 3 is a top view of the semiconductor structure in FIG. 2 in accordance with some embodiments.
- FIG. 4 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments.
- FIGS. 5A-5I are cross-sectional views of intermediate structures for a method of manufacturing a semiconductor structure in FIG. 4 , in accordance with some embodiments.
- FIG. 6 is a flow diagram of a method of manufacturing a semiconductor device in accordance with some embodiments.
- FIGS. 7A-7J are cross-sectional views of intermediate structures for a method of manufacturing a semiconductor device in FIG. 6 , in accordance with some embodiments.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- a semiconductor structure in the present disclosure, includes a MEMS device.
- the MEMS device includes a plate and a membrane.
- the plate is stationary while the membrane is moveable relative to the plate in response to ambient environment change such as acoustic pressure.
- the semiconductor structure is a microphone and responds as sound wave striking on the membrane.
- the plate of the MEMS device includes semiconductive layer. The plate would not have undesired bending and a straightness of the plate can be maintained during manufacturing or during use. Thus, a noise is reduced, the SNR is increased.
- the plate and the membrane are supported by a handle substrate (such as silicon substrate) during formation of the plate and the membrane.
- a thickness of the handle substrate is much greater than a thickness of the plate and the membrane.
- the handle substrate would be thinned down and partially removed after formation of the plate and the membrane and bonding with another substrate such as CMOS substrate. As a result, an overall thickness of the device is reduced. A form factor of the microphone is also reduced.
- FIG. 1 is a schematic perspective view of a semiconductor structure 10 in accordance with some embodiments of the present disclosure.
- Semiconductor structure 10 includes a housing 15 enclosing a MEMS device 100 . Housing 15 is depicted in a dotted line. There may be some apertures on housing 15 so as to provide channels for MEMS device 100 communicating with environment external to housing 15 .
- semiconductor structure 10 is configured to sense an atmospheric pressure.
- semiconductor structure 10 is configured to sense an acoustic pressure such as sound wave.
- semiconductor structure 10 is a part of a microphone. The acoustic pressure is received by MEMS device 100 and then is converted into an electrical signal.
- MEMS device 100 has a thickness of about less than 100 um. In some embodiments, MEMS device 100 has a thickness of less than about 2 um. In some embodiments, MEMS device 100 is disposed over and bonded with another substrate. In some embodiments, MEMS device 100 includes an anti-stiction coating structures.
- MEMS device 100 is further illustrated in FIG. 2 .
- MEMS device 100 includes a plate 101 , a membrane 102 and several conductors 103 ( 103 - 1 or 103 - 2 ).
- Conductor 103 can be disposed between a substrate 201 and plate 101 as conductor 103 - 1 , or can be disposed between substrate 201 and membrane 102 as conductor 103 - 2 .
- Plate 101 is a stationary element and served as a back plate of MEMS device 100 . Plate 101 is not movable by the acoustic pressure received by MEMS device 100 .
- plate 101 is a stiff perforated element which allows the acoustic pressure passing through.
- plate 101 has a thickness of about 1 um to about 20 um. In some embodiments, the thickness of the plate 101 is about 0.3 um to about 20 um.
- plate 101 has a small thickness while has sufficient stiffness to resist residual stress developed upon manufacturing and the acoustic pressure striking thereon. In some embodiments, plate 101 has stiffness such that the plate 101 would not be bent when the acoustic pressure is received by MEMS device 100 and passes through plate 101 . In some embodiments, plate 101 would not be bent by the stiction caused by membrane 102 disposed opposite to the plate 101 . The straightness of plate 101 is maintained.
- plate 101 is doped with suitable dopants to include several doped regions. In some embodiments, plate 101 is doped with a p-type dopant such as boron or an n-type dopant such as phosphorous. In some embodiments, plate 101 uses the same type of dopant to prevent a p-n junction and have better conductivity.
- a p-type dopant such as boron or an n-type dopant such as phosphorous.
- plate 101 uses the same type of dopant to prevent a p-n junction and have better conductivity.
- an anti-stiction coating is optionally applied on plate 101 or membrane 102 .
- the anti-stiction coating is a self-assembled monolayer (SAM) coating which can prevent or reduce stiction between plate 101 and membrane 102 .
- plate 101 is in circular, rectangular, quadrilateral, triangular, hexagon, or any other suitable shapes.
- plate 101 includes a semiconductive layer, an SOI (silicon on insulator), polysilicon, oxide, or epitaxial silicon.
- Plate 101 includes several apertures 101 a . Each aperture 101 a passes through plate 101 .
- apertures 101 a are configured for the acoustic pressure received by the MEMS device 100 to pass through. Apertures 101 a can relieve a stress on plate 101 caused by the acoustic pressure, such that plate 101 would not be bent by the acoustic pressure. Furthermore, apertures 101 a are configured to prevent membrane 102 from sticking with plate 101 by the acoustic pressure and the stiction between plate 101 and membrane 102 .
- apertures 101 a are arranged in any suitable patterns. In some embodiments, apertures 101 a are arranged in a regular or an irregular array over the plate 101 . In some embodiments, aperture 101 a is in a circular, quadrilateral, elliptical, triangular, hexagon, or any other suitable shapes. In some embodiments, aperture 101 a has a width of about 0.5 um to about 5 um. In some embodiments, a pitch between adjacent apertures 101 a is about 1 um to about 100 um.
- a total number of the apertures 101 a , the pitch between adjacent apertures 101 a or the width of each aperture 101 a is predetermined and designed, so that plate 101 would not be bent by the acoustic pressure received and the stiction between plate 101 and membrane 102 , and the straightness of plate 101 can be maintained.
- Membrane 102 is disposed opposite to plate 101 . In some embodiments, membrane 102 is disposed between plate 101 and cavity 204 . In some embodiments, membrane 102 is disposed away from the plate 101 in a distance of about 0.5 um to about 5 um, or about 0.3 um to about 5 um. In some embodiments, membrane 102 is in circular, rectangular, quadrilateral, triangular, hexagon, or any other suitable shapes. In some embodiments, membrane 102 includes polysilicon. In some embodiments, membrane 102 is conductive and capacitive. In some embodiments, membrane 102 is supplied with a predetermined charge. In some embodiments, membrane 102 includes an anti-stiction coating disposed over membrane 102 to prevent or reduce a stiction between plate 101 and membrane 102 . In some embodiments, the anti-stiction coating is a SAM coating. In some embodiments, membrane 102 has a thickness of about 0.1 um to about 5 um.
- Membrane 102 is a movable or oscillatable element. Membrane 102 is displaceable relative to plate 101 and is served as a diaphragm. In some embodiments, membrane 102 is configured to sense the acoustic pressure received by the MEMS device 100 . When the acoustic pressure is impinged on membrane 102 , membrane 102 would be displaced or oscillated corresponding to the acoustic pressure impinged on membrane 102 . In some embodiments, a magnitude and/or a frequency of the displacement of membrane 102 corresponds to a volume and/or pitch of the acoustic pressure impinged on membrane 102 .
- the displacement of membrane 102 relative to plate 101 would cause a capacitance change between membrane 102 and plate 101 .
- the capacitance change would then be translated into an electrical signal by a circuitry connected with plate 101 and membrane 102 .
- the acoustic pressure impinging on membrane 102 is converted into the electrical signal representing the acoustic pressure impinged on membrane 102 .
- the electrical signal generated would be transmitted to another device, another substrate or another circuitry for further processing.
- membrane 102 includes an anti-stiction structure configured to reduce the contact area between membrane 102 and plate 101 . Further, the anti-stiction structure may be configured to supply a restoring force on membrane 102 to avoid stiction between plate 101 and membrane 102 .
- membrane 102 includes several corrugations 102 a . Corrugations 102 a are arranged over membrane 102 . In some embodiments, corrugations 102 a face to and are opposite to apertures 101 a of plate 101 . In some embodiments, corrugations 102 a are substantially aligned or not aligned with apertures 101 a of plate 101 . In some embodiments, corrugations 102 a are protruded or recessed from a surface of the membrane 102 .
- corrugation 102 a is a groove extending across the surface of plate 101 . In some embodiments, corrugation 102 a is a protruded portion or a recessed portion of the surface of plate 101 . In some embodiments, corrugation 102 a is a bump on plate 101 .
- corrugations 102 a are configured to relieve undesired stress over the membrane 102 .
- corrugations 102 a prevent membrane 102 from sticking with plate 101 .
- corrugations 102 a prevent undesired deflection of membrane 102 .
- Corrugations 102 a can facilitate membrane 102 to return to its initial straight configuration after receiving and being bent by the acoustic pressure. When membrane 102 is displaced by the acoustic pressure, membrane 102 would be bent. After the receipt of the acoustic pressure, it is desirable the membrane 102 would be returned to the initial straight configuration.
- corrugation 102 a is in a closed loop, a quadrilateral ring, an annular shape, an elliptical shape, a pyramid shape or any other suitable configurations.
- corrugation 102 a has a width of about 0.1 um to about 10 um.
- a pitch between adjacent corrugations 102 a is about 1 um to about 200 um.
- corrugation 102 a is arranged in a nano-scaled structure.
- the shape, the width, the pitch or the number of corrugations 102 a is predetermined and designed, so that membrane 102 would not have undesired bending. In some embodiments, the shape, the width or the number of corrugations 102 a is chosen to optimize the straightness and the sensitivity of membrane 102 .
- the membrane 102 can sense the acoustic pressure accurately and promptly, and can be returned to the initial straight configuration after sensing the acoustic pressure.
- membrane 102 includes several holes 102 b over membrane 102 .
- holes 102 b are configured to relieve undesired stress over membrane 102 .
- holes 102 b can prevent or minimize membrane 102 from sticking with plate 101 .
- holes 102 b are substantially aligned or not aligned with apertures 101 a .
- a total number of holes 102 b is chosen, so that membrane 102 would not have undesired bending.
- a total number of holes 102 b is less than a total number of apertures 101 a over plate 101 .
- the total number of the holes 102 b is chosen to optimize the straightness and the sensitivity of membrane 102 .
- Membrane 102 can sense the acoustic pressure accurately and promptly, and can be returned to the initial straight configuration after sensing the acoustic pressure. Also, membrane 102 can be prevented from sticking with plate 101 by stiction.
- Plate 101 or membrane 102 is electrically communicating with substrate 201 through conductor 103 .
- conductor 103 also provides mechanical support to plate 101 or membrane 102 .
- conductor 103 has a height from plate 101 of about 5 um to about 20 um.
- conductor 103 has a height from the membrane 102 of about 2 um to about 20 um.
- Each conductor 103 has at least two different portions.
- a first portion 103 a and a second portion 103 b constitute conductor 103 .
- First portion 103 a and second portion 103 b may include a same conductive or semiconductive material such as gold, tin, silicon, tin, copper, tin copper alloy (SnCu) or other suitable materials.
- first portion 103 a and second portion 103 b includes metal like copper, silver, or gold.
- First portion 103 a is bonded with second portion 103 b , for example, in a metal-to-metal bonding manner. Because atoms from each side may be fused during bonding operation, the interface between first portion 103 a and second portion 103 b may not be easy to be observed under optical microscope. However, some surface treatments, such as chemical stain or plasma bombardment can be applied on a cross section of conductor 103 . Seams or voids along the interface may be observed under a higher magnitude microscope such as SEM (Scanning Electron Microscope) or TEM (Transmission Electron Microscope).
- first portion conductor 103 a is adjacent to a dielectric 105 .
- a sidewall of first portion 103 a is substantially extended along the thickness of dielectric 105 .
- Dielectric 105 is disposed under plate 101 and configured to provide mechanical support to plate 101 or membrane 102 .
- first portion 103 a is surrounded by dielectric 105 as conductor 103 - 1 .
- a sidewall of first portion 103 a is partially exposed from dielectric 105 .
- one side of first portion 103 a is in contact with dielectric 105 and the opposite side is exposed to cavity 204 .
- First portion 103 a can be a barrier to block chemicals from cavity 204 penetrating into dielectric 105 .
- second portion conductor 103 b is proximal to substrate 201 .
- Second portion conductor 103 b is extended from an interconnect 203 .
- Interconnect 203 and substrate 201 together form a semiconductor device.
- interconnect 203 includes conductive traces, vias, or inter metallic dielectric.
- Substrate 201 includes doped semiconductor wells, regions, and transistor gates.
- Interconnect 203 provides backend connection for devices built in substrate 201 .
- Plate 101 or membrane 102 are communicating with substrate 201 through interconnect 203 .
- a conductive pad 202 may be disposed on an upmost level of interconnect 203 as a terminal to communicate with plate 101 or membrane 102 .
- Second portion conductor 103 b is extended from pad 202 and along the direction in which plate 101 is stacked over substrate 201 .
- Conductive pad 202 may include copper, silver, gold, aluminum, or alloy thereof.
- second portion conductor 103 b is surrounded by a dielectric 214 .
- Dielectric 214 is disposed between first portion conductor 103 a and interconnect 203 .
- Second portion conductor 103 b is further exposed from dielectric 214 and has a section 103 b - 1 overlying dielectric 214 .
- the overlying section 103 b - 1 is in contact with first portion conductor 103 a as shown in FIG. 2 .
- the overlying section 103 b - 1 is a conductive layer inserted between dielectric 214 and dielectric 105 .
- Second portion conductor 103 b is like a plug in dielectric 214 with only one end exposed from dielectric 214 . The exposed end is in contact with first portion conductor 103 a.
- second portion conductor 103 b is in a loop shape.
- the drawing is a top view of MEMS device 100 in FIG. 2 .
- Second portion conductor 103 b is a loop and cavity 204 is defined inside the loop.
- MEMS structures like plate 101 and membrane 102 are integrated with the device in substrate 201 . Without extra wire bonding feature included, the size of monolithic MEMS device 100 can be shrunk and the thickness can reduced to be below 200 um.
- dielectric 105 may be disposed on an edge of membrane 102 or an edge of plate 101 .
- Dielectric 105 forms a continuous stiff structure between plate 101 and membrane 102 .
- membrane 102 is clamped at its edges by dielectric 105 .
- dielectric 105 is disposed around conductor 103 and a peripheral portion of membrane 102 .
- dielectric 105 may surround membrane 102 .
- Dielectric 105 provides partial isolation between plate 101 , membrane 102 , and conductor 103 from each other.
- dielectric 105 is disposed over a peripheral portion of plate 101 or surrounds plate 101 .
- dielectric 105 is disposed between plate 101 and a device substrate 106 (would be shown later).
- a thickness of dielectric 105 may be about 1 um to about 20 um.
- a method 500 of manufacturing a semiconductor device like MEMS device 100 of FIG. 2 is disclosed.
- the method includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.
- FIG. 4 is an embodiment of method 500 for manufacturing a portion of MEMS device 100 .
- Method 500 includes a number of operations ( 501 , 502 , 503 , 504 , 505 , 506 , 507 ).
- first substrate 106 is received or provided as shown in FIGS. 5A and 5B .
- first substrate 106 is a handle substrate or a handle wafer.
- first substrate 106 includes silicon.
- first substrate 106 is a silicon substrate.
- First substrate 106 has a thickness of about 400 um to about 1000 um.
- a layer 107 is disposed over first substrate 106 with reference to operation 502 .
- layer 107 includes an epitaxial silicon layer, silicon on insulator (SOI), or any other suitable materials.
- a thickness of layer 107 is about 1 um to about 5 um.
- Layer 107 has an etch selectivity with first substrate 106 .
- first plate 101 is disposed over first substrate 106 and layer 107 as shown in FIG. 5C .
- first plate 101 is bonded silicon with thickness of about 5 um to about 50 um.
- first sacrificial layer 105 a is disposed over plate 101 as shown in FIG. 5D .
- first sacrificial layer 105 a is disposed by any suitable deposition techniques such as chemical vapor deposition (CVD) and the like.
- first sacrificial layer 105 a includes dielectric material such as silicon oxide.
- first sacrificial layer 105 a has a thickness of about 0.3 um to about 5 um. In some embodiments, first sacrificial layer 105 a has a thickness of about 0.3 um to about 10 um.
- recesses 105 c are formed over a surface of the sacrificial layer 105 a as shown in FIG. 5E .
- recesses 105 c are indented from the surface of first sacrificial layer 105 a .
- some portions of first sacrificial layer 105 a are removed from the surface to form the recesses 105 c .
- recesses 105 c are formed by photolithography and wet or dry etching operations.
- membrane 102 is disposed and then patterned over first sacrificial layer 105 a as shown in FIG. 5F .
- membrane 102 is disposed over the first sacrificial layer 105 a by any suitable deposition operations.
- the membrane 102 includes polysilicon.
- membrane 102 is doped with any suitable dopants.
- membrane 102 has a thickness of about 0.1 um to about 5 um.
- membrane 102 is patterned by photolithography and etching operations after the deposition operations, so that several corrugations 102 a and several holes 102 b are formed over the membrane 102 . In some embodiments, some portions of membrane 102 are removed to form the holes 102 b . The holes 102 b expose a portion of first sacrificial layer 105 a.
- a second sacrificial layer 105 b is disposed over a portion of first sacrificial layer 105 a (exposed through holes 102 b ) and surrounds membrane 102 as shown in FIG. 5G .
- second sacrificial layer 105 b covers first sacrificial layer 105 a .
- second sacrificial layer 105 b is disposed over membrane 102 and first sacrificial layer 105 a by any suitable deposition operations.
- second sacrificial layer 105 b includes same or different materials as first sacrificial layer 105 a .
- second sacrificial layer 105 b includes dielectric material such as silicon oxide. In some embodiments, second sacrificial layer 105 b has a thickness of about 0.3 um to about 5 um. In some embodiments, second sacrificial layer 105 b has a thickness of about 0.3 um to about 10 um. In some embodiments, second sacrificial layer 105 b is planarized to a reduced height than as deposited. In some embodiments, second sacrificial layer 105 b is polished by chemical mechanical polishing (CMP) operations.
- CMP chemical mechanical polishing
- first sacrificial layer 105 a or second sacrificial layer 105 b are partially removed and stopped at plate 101 to form vias 105 d .
- first sacrificial layer 105 a or second sacrificial layer 105 b are partially removed and stopped at membrane 102 to form vias 105 e.
- vias 105 d are deposited and filled by conductive materials such as copper to form conductive plugs (or first portion conductor) 103 a as shown in FIG. 5I .
- conductive plugs 103 a pass through first sacrificial layer 105 a or second sacrificial layer 105 b .
- conductive plug 103 a is extended from plate 101 through the membrane 102 .
- conductive plug 103 a is extended from or through membrane 102 .
- conductive plug 103 a includes a silicide portion configured to provide an ohmic contact between plate 101 and metallic plug 103 a.
- conductive plugs 103 a are formed by partially removing first sacrificial layer 105 a or second sacrificial layer 105 b and then disposing copper.
- first sacrificial layer 105 a or second sacrificial layer 105 b is partially removed by photolithography and etching operations.
- copper is disposed by any suitable deposition operations.
- conductive plug 103 a has a height of about 1 um to about 50 um.
- FIG. 6 is an embodiment of method 600 for manufacturing a portion of MEMS device 100 .
- Method 600 includes a number of operations ( 601 , 602 , 603 , 604 , 605 and 606 ).
- second substrate 201 is provided or received as shown in FIG. 7A .
- second substrate 201 includes several active devices such as CMOS devices.
- Second substrate 201 includes interconnect 203 disposed over second substrate 201 and several conductive pads 202 disposed in upper level of layer 203 .
- interconnect 203 is partially removed as shown in FIG. 7B .
- layer 203 is partially removed by any suitable operations such as photolithography and etching.
- a protective layer 205 is disposed over interconnect 203 , pads 202 and second substrate 201 as shown in FIG. 7C .
- protective layer 205 is configured to prevent second substrate 201 , layer 203 , pad 202 or other components disposed over second substrate 201 from being etched or removed.
- protective layer 205 is an etching stop layer to prevent second substrate 201 and the components disposed over second substrate 201 from being attacked by hydrofluoric acid vapor.
- an additional dielectric layer 206 is disposed over protective layer 205 as shown in FIG. 7D .
- protective layer 205 and additional dielectric layer 206 disposed on pads 202 are removed as shown in FIG. 7E .
- Pads 202 are exposed from interconnect 203 , protective layer 205 and through holes 206 a in dielectric layer 206 .
- a conductive material is filled into through holes 206 a as shown in FIG. 7F and forms second portion conductor 103 b .
- Through holes 206 a can be overfilled by the overlying section as mentioned is the description corresponding to FIG. 2 .
- first substrate 106 is flipped so that first portion conductor 103 a and second portion conductor 103 b are bonded as shown in FIG. 7G .
- first substrate 106 and second substrate 201 are thinned down as shown in FIG. 7H .
- first substrate 106 and second substrate 201 are thinned down by grinding operations.
- first substrate 106 is wholly or partially removed.
- some portions or all of first substrate 106 are removed by grinding or etching operations.
- first substrate 106 is thinned down or removed by dry or wet etching.
- the dry or wet etching of first substrate 106 is stopped at plate 101 .
- second substrate 201 is thinned down from the thickness of about 800 um to about 100 um.
- second substrate 201 is thinned down from the thickness of about 800 um to about 50 um.
- plate 101 is partially removed to have several through holes 101 a as shown in FIG. 7I .
- a first cavity 104 is formed by partially removing first sacrificial layer 105 a and second sacrificial layer 105 b as in FIG. 7J .
- a second cavity 204 is formed as well by partially removing second substrate 201 , protective layer 205 , and layer 206 .
- second cavity 204 passes through second substrate 201 and layer 203 .
- second cavity 204 is aligned with first cavity 104 .
- a monolithic MEMS device as shown in FIG. 2 is formed.
- a semiconductor device comprises a plate including a plurality of apertures.
- the semiconductor device also comprises a membrane disposed opposite to the plate and including a plurality of corrugations, a dielectric surrounding and covering an edge of the membrane, and a substrate.
- the semiconductor device further includes a metallic conductor comprising a first portion extending through the dielectric, and a second portion over the substrate, where the second portion is bonded with the first portion.
- a semiconductor comprises a monolithic sensor comprising a micro-electro mechanical system (MEMS) device and a complementary metal oxide semiconductor (CMOS) device.
- MEMS device comprises a plate including a plurality of apertures.
- the MEMS device also includes a membrane disposed opposite to the plate and including a plurality of corrugations.
- the MEMS device further includes a first conductor disposed below the plate, and a first cavity between the plate and the membrane.
- the CMOS device comprises a substrate, an interconnect disposed over the substrate, and a second conductor electrically coupled to the interconnect and extruded from the interconnect toward the membrane. The first conductor is connected with the second conductor in a metal bond manner.
- a method of manufacturing a semiconductor structure comprises: providing a first substrate; disposing a plate over the first substrate; disposing a first sacrificial layer over the plate; forming a plurality of recesses over a surface of the first sacrificial layer; disposing and patterning a membrane over the first sacrificial layer; disposing a second sacrificial layer to surround the membrane and cover the first sacrificial layer; and forming a plurality of conductors passing through the second sacrificial layer or the membrane.
- a second substrate is provided.
- a protective is provided over the second substrate and a dielectric layer is provided over the protective layer. Second conductors are filled in holes through the dielectric layer.
- the first substrate is flipped and the conductors are bonded with second conductors.
- a first cavity is formed by partially removing the first sacrificial layer and the second sacrificial layer.
- a second cavity is formed by partially removing the second substrate, the protective layer, and the dielectric layer.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Multimedia (AREA)
- Micromachines (AREA)
- Pressure Sensors (AREA)
Abstract
In the present disclosure a semiconductor device comprises a plate including a plurality of apertures. The semiconductor device also comprises a membrane disposed opposite to the plate and including a plurality of corrugations, a dielectric surrounding and covering an edge of the membrane, and a substrate. The semiconductor device further includes a metallic conductor comprising a first portion extending through the dielectric, and a second portion over the substrate, where the second portion is bonded with the first portion.
Description
- Electronic equipment involving semiconductive devices are essential for many modern applications. Technological advances in materials and design have produced generations of semiconductive devices where each generation has smaller and more complex circuits than the previous generation. In the course of advancement and innovation, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component that can be created using a fabrication process) has decreased. Such advances have increased the complexity of processing and manufacturing semiconductive devices.
- Micro-electro mechanical system (MEMS) devices have been recently developed and are also commonly involved in electronic equipment. The MEMS device is a micro-sized device, usually in a range from less than 1 micron to several millimeters in size. The MEMS device includes fabrication using semiconductive materials to form mechanical and electrical features. The MEMS device may include a number of elements (e.g., stationary or movable elements) for achieving electro-mechanical functionality. MEMS devices are widely used in various applications. MEMS applications include motion sensors, pressure sensors, printer nozzles, or the like. Other MEMS applications include inertial sensors, such as accelerometers for measuring linear acceleration and gyroscopes for measuring angular velocity. Moreover, MEMS applications are extended to optical applications, such as movable mirrors, and radio frequency (RF) applications, such as RF switches or the like.
- As technologies evolve, designs for devices become more complicated in view of smaller dimension and an increase of functionality and the amount of circuitries. The devices involve many complicated steps and increases complexity of manufacturing, and the increase in complexity of manufacturing may cause deficiencies such as high yield loss, warpage, low signal to noise ratio (SNR) and other problems. Therefore, there is a continuous need to modify the structure and manufacturing method of the devices in the electronic equipment in order to improve the device performance as well as reduce manufacturing cost and processing time.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 is a schematic view of a semiconductor structure in accordance with some embodiments. -
FIG. 2 is a schematic view of a semiconductor structure in accordance with some embodiments. -
FIG. 3 is a top view of the semiconductor structure inFIG. 2 in accordance with some embodiments. -
FIG. 4 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments. -
FIGS. 5A-5I are cross-sectional views of intermediate structures for a method of manufacturing a semiconductor structure inFIG. 4 , in accordance with some embodiments. -
FIG. 6 is a flow diagram of a method of manufacturing a semiconductor device in accordance with some embodiments. -
FIGS. 7A-7J are cross-sectional views of intermediate structures for a method of manufacturing a semiconductor device inFIG. 6 , in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- In the present disclosure, a semiconductor structure is disclosed. The semiconductor structure includes a MEMS device. The MEMS device includes a plate and a membrane. The plate is stationary while the membrane is moveable relative to the plate in response to ambient environment change such as acoustic pressure. In some embodiments, the semiconductor structure is a microphone and responds as sound wave striking on the membrane. The plate of the MEMS device includes semiconductive layer. The plate would not have undesired bending and a straightness of the plate can be maintained during manufacturing or during use. Thus, a noise is reduced, the SNR is increased.
- Furthermore, the plate and the membrane are supported by a handle substrate (such as silicon substrate) during formation of the plate and the membrane. A thickness of the handle substrate is much greater than a thickness of the plate and the membrane. The handle substrate would be thinned down and partially removed after formation of the plate and the membrane and bonding with another substrate such as CMOS substrate. As a result, an overall thickness of the device is reduced. A form factor of the microphone is also reduced.
-
FIG. 1 is a schematic perspective view of asemiconductor structure 10 in accordance with some embodiments of the present disclosure.Semiconductor structure 10 includes ahousing 15 enclosing aMEMS device 100.Housing 15 is depicted in a dotted line. There may be some apertures onhousing 15 so as to provide channels forMEMS device 100 communicating with environment external to housing 15. In some embodiments,semiconductor structure 10 is configured to sense an atmospheric pressure. In some embodiments,semiconductor structure 10 is configured to sense an acoustic pressure such as sound wave. In some embodiments,semiconductor structure 10 is a part of a microphone. The acoustic pressure is received byMEMS device 100 and then is converted into an electrical signal. In some embodiments,MEMS device 100 has a thickness of about less than 100 um. In some embodiments,MEMS device 100 has a thickness of less than about 2 um. In some embodiments,MEMS device 100 is disposed over and bonded with another substrate. In some embodiments,MEMS device 100 includes an anti-stiction coating structures. -
MEMS device 100 is further illustrated inFIG. 2 .MEMS device 100 includes aplate 101, amembrane 102 and several conductors 103 (103-1 or 103-2). Conductor 103 can be disposed between asubstrate 201 andplate 101 as conductor 103-1, or can be disposed betweensubstrate 201 andmembrane 102 as conductor 103-2.Plate 101 is a stationary element and served as a back plate ofMEMS device 100.Plate 101 is not movable by the acoustic pressure received byMEMS device 100. In some embodiments,plate 101 is a stiff perforated element which allows the acoustic pressure passing through. In some embodiments,plate 101 has a thickness of about 1 um to about 20 um. In some embodiments, the thickness of theplate 101 is about 0.3 um to about 20 um. - In some embodiments,
plate 101 has a small thickness while has sufficient stiffness to resist residual stress developed upon manufacturing and the acoustic pressure striking thereon. In some embodiments,plate 101 has stiffness such that theplate 101 would not be bent when the acoustic pressure is received byMEMS device 100 and passes throughplate 101. In some embodiments,plate 101 would not be bent by the stiction caused bymembrane 102 disposed opposite to theplate 101. The straightness ofplate 101 is maintained. - In some embodiments,
plate 101 is doped with suitable dopants to include several doped regions. In some embodiments,plate 101 is doped with a p-type dopant such as boron or an n-type dopant such as phosphorous. In some embodiments,plate 101 uses the same type of dopant to prevent a p-n junction and have better conductivity. - An anti-stiction coating is optionally applied on
plate 101 ormembrane 102. In some embodiments, the anti-stiction coating is a self-assembled monolayer (SAM) coating which can prevent or reduce stiction betweenplate 101 andmembrane 102. In some embodiments,plate 101 is in circular, rectangular, quadrilateral, triangular, hexagon, or any other suitable shapes. In some embodiments,plate 101 includes a semiconductive layer, an SOI (silicon on insulator), polysilicon, oxide, or epitaxial silicon. -
Plate 101 includesseveral apertures 101 a. Eachaperture 101 a passes throughplate 101. In some embodiments,apertures 101 a are configured for the acoustic pressure received by theMEMS device 100 to pass through.Apertures 101 a can relieve a stress onplate 101 caused by the acoustic pressure, such thatplate 101 would not be bent by the acoustic pressure. Furthermore,apertures 101 a are configured to preventmembrane 102 from sticking withplate 101 by the acoustic pressure and the stiction betweenplate 101 andmembrane 102. -
Apertures 101 a are arranged in any suitable patterns. In some embodiments,apertures 101 a are arranged in a regular or an irregular array over theplate 101. In some embodiments,aperture 101 a is in a circular, quadrilateral, elliptical, triangular, hexagon, or any other suitable shapes. In some embodiments,aperture 101 a has a width of about 0.5 um to about 5 um. In some embodiments, a pitch betweenadjacent apertures 101 a is about 1 um to about 100 um. In some embodiments, a total number of theapertures 101 a, the pitch betweenadjacent apertures 101 a or the width of eachaperture 101 a is predetermined and designed, so thatplate 101 would not be bent by the acoustic pressure received and the stiction betweenplate 101 andmembrane 102, and the straightness ofplate 101 can be maintained. -
Membrane 102 is disposed opposite toplate 101. In some embodiments,membrane 102 is disposed betweenplate 101 andcavity 204. In some embodiments,membrane 102 is disposed away from theplate 101 in a distance of about 0.5 um to about 5 um, or about 0.3 um to about 5 um. In some embodiments,membrane 102 is in circular, rectangular, quadrilateral, triangular, hexagon, or any other suitable shapes. In some embodiments,membrane 102 includes polysilicon. In some embodiments,membrane 102 is conductive and capacitive. In some embodiments,membrane 102 is supplied with a predetermined charge. In some embodiments,membrane 102 includes an anti-stiction coating disposed overmembrane 102 to prevent or reduce a stiction betweenplate 101 andmembrane 102. In some embodiments, the anti-stiction coating is a SAM coating. In some embodiments,membrane 102 has a thickness of about 0.1 um to about 5 um. -
Membrane 102 is a movable or oscillatable element.Membrane 102 is displaceable relative to plate 101 and is served as a diaphragm. In some embodiments,membrane 102 is configured to sense the acoustic pressure received by theMEMS device 100. When the acoustic pressure is impinged onmembrane 102,membrane 102 would be displaced or oscillated corresponding to the acoustic pressure impinged onmembrane 102. In some embodiments, a magnitude and/or a frequency of the displacement ofmembrane 102 corresponds to a volume and/or pitch of the acoustic pressure impinged onmembrane 102. - In some embodiments, the displacement of
membrane 102 relative to plate 101 would cause a capacitance change betweenmembrane 102 andplate 101. The capacitance change would then be translated into an electrical signal by a circuitry connected withplate 101 andmembrane 102. In some embodiments, the acoustic pressure impinging onmembrane 102 is converted into the electrical signal representing the acoustic pressure impinged onmembrane 102. In some embodiments, the electrical signal generated would be transmitted to another device, another substrate or another circuitry for further processing. - In some embodiments,
membrane 102 includes an anti-stiction structure configured to reduce the contact area betweenmembrane 102 andplate 101. Further, the anti-stiction structure may be configured to supply a restoring force onmembrane 102 to avoid stiction betweenplate 101 andmembrane 102. For example,membrane 102 includesseveral corrugations 102 a.Corrugations 102 a are arranged overmembrane 102. In some embodiments,corrugations 102 a face to and are opposite toapertures 101 a ofplate 101. In some embodiments,corrugations 102 a are substantially aligned or not aligned withapertures 101 a ofplate 101. In some embodiments,corrugations 102 a are protruded or recessed from a surface of themembrane 102. In some embodiments,corrugation 102 a is a groove extending across the surface ofplate 101. In some embodiments,corrugation 102 a is a protruded portion or a recessed portion of the surface ofplate 101. In some embodiments,corrugation 102 a is a bump onplate 101. - In some embodiments,
corrugations 102 a are configured to relieve undesired stress over themembrane 102. In some embodiments,corrugations 102 a preventmembrane 102 from sticking withplate 101. In some embodiments,corrugations 102 a prevent undesired deflection ofmembrane 102.Corrugations 102 a can facilitatemembrane 102 to return to its initial straight configuration after receiving and being bent by the acoustic pressure. Whenmembrane 102 is displaced by the acoustic pressure,membrane 102 would be bent. After the receipt of the acoustic pressure, it is desirable themembrane 102 would be returned to the initial straight configuration. - In some embodiments,
corrugation 102 a is in a closed loop, a quadrilateral ring, an annular shape, an elliptical shape, a pyramid shape or any other suitable configurations. In some embodiments,corrugation 102 a has a width of about 0.1 um to about 10 um. In some embodiments, a pitch betweenadjacent corrugations 102 a is about 1 um to about 200 um. In some embodiments,corrugation 102 a is arranged in a nano-scaled structure. In some embodiments, there are a number ofcorrugations 102 a disposed onmembrane 102. For example, there are twoannular corrugations 102 a as illustrated inFIG. 2 . - In some embodiments, the shape, the width, the pitch or the number of
corrugations 102 a is predetermined and designed, so thatmembrane 102 would not have undesired bending. In some embodiments, the shape, the width or the number ofcorrugations 102 a is chosen to optimize the straightness and the sensitivity ofmembrane 102. Themembrane 102 can sense the acoustic pressure accurately and promptly, and can be returned to the initial straight configuration after sensing the acoustic pressure. - In some embodiments,
membrane 102 includesseveral holes 102 b overmembrane 102. In some embodiments, holes 102 b are configured to relieve undesired stress overmembrane 102. In some embodiments, holes 102 b can prevent or minimizemembrane 102 from sticking withplate 101. In some embodiments, holes 102 b are substantially aligned or not aligned withapertures 101 a. In some embodiments, a total number ofholes 102 b is chosen, so thatmembrane 102 would not have undesired bending. In some embodiments, a total number ofholes 102 b is less than a total number ofapertures 101 a overplate 101. In some embodiments, the total number of theholes 102 b is chosen to optimize the straightness and the sensitivity ofmembrane 102.Membrane 102 can sense the acoustic pressure accurately and promptly, and can be returned to the initial straight configuration after sensing the acoustic pressure. Also,membrane 102 can be prevented from sticking withplate 101 by stiction. -
Plate 101 ormembrane 102 is electrically communicating withsubstrate 201 through conductor 103. In addition to electrical communication, conductor 103 also provides mechanical support to plate 101 ormembrane 102. In some embodiments, conductor 103 has a height fromplate 101 of about 5 um to about 20 um. In some embodiments, conductor 103 has a height from themembrane 102 of about 2 um to about 20 um. Each conductor 103 has at least two different portions. Afirst portion 103 a and asecond portion 103 b constitute conductor 103.First portion 103 a andsecond portion 103 b may include a same conductive or semiconductive material such as gold, tin, silicon, tin, copper, tin copper alloy (SnCu) or other suitable materials. In some embodiments,first portion 103 a andsecond portion 103 b includes metal like copper, silver, or gold.First portion 103 a is bonded withsecond portion 103 b, for example, in a metal-to-metal bonding manner. Because atoms from each side may be fused during bonding operation, the interface betweenfirst portion 103 a andsecond portion 103 b may not be easy to be observed under optical microscope. However, some surface treatments, such as chemical stain or plasma bombardment can be applied on a cross section of conductor 103. Seams or voids along the interface may be observed under a higher magnitude microscope such as SEM (Scanning Electron Microscope) or TEM (Transmission Electron Microscope). - In some embodiments,
first portion conductor 103 a is adjacent to a dielectric 105. A sidewall offirst portion 103 a is substantially extended along the thickness ofdielectric 105.Dielectric 105 is disposed underplate 101 and configured to provide mechanical support to plate 101 ormembrane 102. In some embodiments,first portion 103 a is surrounded by dielectric 105 as conductor 103-1. In some embodiments, a sidewall offirst portion 103 a is partially exposed fromdielectric 105. As illustrated in conductor 103-2, one side offirst portion 103 a is in contact withdielectric 105 and the opposite side is exposed tocavity 204.First portion 103 a can be a barrier to block chemicals fromcavity 204 penetrating intodielectric 105. - Compared to
first portion conductor 103 a,second portion conductor 103 b is proximal tosubstrate 201.Second portion conductor 103 b is extended from aninterconnect 203.Interconnect 203 andsubstrate 201 together form a semiconductor device. In some embodiments,interconnect 203 includes conductive traces, vias, or inter metallic dielectric.Substrate 201 includes doped semiconductor wells, regions, and transistor gates.Interconnect 203 provides backend connection for devices built insubstrate 201.Plate 101 ormembrane 102 are communicating withsubstrate 201 throughinterconnect 203. Aconductive pad 202 may be disposed on an upmost level ofinterconnect 203 as a terminal to communicate withplate 101 ormembrane 102.Second portion conductor 103 b is extended frompad 202 and along the direction in whichplate 101 is stacked oversubstrate 201.Conductive pad 202 may include copper, silver, gold, aluminum, or alloy thereof. - Alternatively,
second portion conductor 103 b is surrounded by a dielectric 214.Dielectric 214 is disposed betweenfirst portion conductor 103 a andinterconnect 203.Second portion conductor 103 b is further exposed fromdielectric 214 and has asection 103 b-1overlying dielectric 214. Theoverlying section 103 b-1 is in contact withfirst portion conductor 103 a as shown inFIG. 2 . Theoverlying section 103 b-1 is a conductive layer inserted betweendielectric 214 and dielectric 105. However, for some other embodiments, there is no overlying section insecond portion conductor 103 b.Second portion conductor 103 b is like a plug indielectric 214 with only one end exposed fromdielectric 214. The exposed end is in contact withfirst portion conductor 103 a. - In some embodiments,
second portion conductor 103 b is in a loop shape. Referring toFIG. 3 , the drawing is a top view ofMEMS device 100 inFIG. 2 .Second portion conductor 103 b is a loop andcavity 204 is defined inside the loop. Through conductor 103, MEMS structures likeplate 101 andmembrane 102 are integrated with the device insubstrate 201. Without extra wire bonding feature included, the size ofmonolithic MEMS device 100 can be shrunk and the thickness can reduced to be below 200 um. - Referring back to
FIG. 2 , dielectric 105 may be disposed on an edge ofmembrane 102 or an edge ofplate 101. Dielectric 105 forms a continuous stiff structure betweenplate 101 andmembrane 102. In some embodiments,membrane 102 is clamped at its edges bydielectric 105. In some embodiments dielectric 105 is disposed around conductor 103 and a peripheral portion ofmembrane 102. Alternatively, dielectric 105 may surroundmembrane 102.Dielectric 105 provides partial isolation betweenplate 101,membrane 102, and conductor 103 from each other. In some embodiments, dielectric 105 is disposed over a peripheral portion ofplate 101 or surroundsplate 101. In some embodiments, dielectric 105 is disposed betweenplate 101 and a device substrate 106 (would be shown later). A thickness ofdielectric 105 may be about 1 um to about 20 um. - In the present disclosure, a
method 500 of manufacturing a semiconductor device likeMEMS device 100 ofFIG. 2 is disclosed. The method includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.FIG. 4 is an embodiment ofmethod 500 for manufacturing a portion ofMEMS device 100.Method 500 includes a number of operations (501, 502, 503, 504, 505, 506, 507). - In
operation 501, afirst substrate 106 is received or provided as shown inFIGS. 5A and 5B . In some embodiments,first substrate 106 is a handle substrate or a handle wafer. In some embodiments,first substrate 106 includes silicon. In some embodiments,first substrate 106 is a silicon substrate.First substrate 106 has a thickness of about 400 um to about 1000 um. - In
FIG. 5B , alayer 107 is disposed overfirst substrate 106 with reference tooperation 502. In some embodiments,layer 107 includes an epitaxial silicon layer, silicon on insulator (SOI), or any other suitable materials. In some embodiments, a thickness oflayer 107 is about 1 um to about 5 um.Layer 107 has an etch selectivity withfirst substrate 106. Then,first plate 101 is disposed overfirst substrate 106 andlayer 107 as shown inFIG. 5C . In some embodiments,first plate 101 is bonded silicon with thickness of about 5 um to about 50 um. - In
operation 503, a firstsacrificial layer 105 a is disposed overplate 101 as shown inFIG. 5D . In some embodiments, firstsacrificial layer 105 a is disposed by any suitable deposition techniques such as chemical vapor deposition (CVD) and the like. In some embodiments, firstsacrificial layer 105 a includes dielectric material such as silicon oxide. In some embodiments, firstsacrificial layer 105 a has a thickness of about 0.3 um to about 5 um. In some embodiments, firstsacrificial layer 105 a has a thickness of about 0.3 um to about 10 um. - In
operation 504,several recesses 105 c are formed over a surface of thesacrificial layer 105 a as shown inFIG. 5E . In some embodiments, recesses 105 c are indented from the surface of firstsacrificial layer 105 a. In some embodiments, some portions of firstsacrificial layer 105 a are removed from the surface to form therecesses 105 c. In some embodiments, recesses 105 c are formed by photolithography and wet or dry etching operations. - In
operation 505,membrane 102 is disposed and then patterned over firstsacrificial layer 105 a as shown inFIG. 5F . In some embodiments,membrane 102 is disposed over the firstsacrificial layer 105 a by any suitable deposition operations. In some embodiments, themembrane 102 includes polysilicon. In some embodiments,membrane 102 is doped with any suitable dopants. In some embodiments,membrane 102 has a thickness of about 0.1 um to about 5 um. - In some embodiments,
membrane 102 is patterned by photolithography and etching operations after the deposition operations, so thatseveral corrugations 102 a andseveral holes 102 b are formed over themembrane 102. In some embodiments, some portions ofmembrane 102 are removed to form theholes 102 b. Theholes 102 b expose a portion of firstsacrificial layer 105 a. - In
operation 506, a secondsacrificial layer 105 b is disposed over a portion of firstsacrificial layer 105 a (exposed throughholes 102 b) and surroundsmembrane 102 as shown inFIG. 5G . In some embodiments, secondsacrificial layer 105 b covers firstsacrificial layer 105 a. In some embodiments, secondsacrificial layer 105 b is disposed overmembrane 102 and firstsacrificial layer 105 a by any suitable deposition operations. In some embodiments, secondsacrificial layer 105 b includes same or different materials as firstsacrificial layer 105 a. In some embodiments, secondsacrificial layer 105 b includes dielectric material such as silicon oxide. In some embodiments, secondsacrificial layer 105 b has a thickness of about 0.3 um to about 5 um. In some embodiments, secondsacrificial layer 105 b has a thickness of about 0.3 um to about 10 um. In some embodiments, secondsacrificial layer 105 b is planarized to a reduced height than as deposited. In some embodiments, secondsacrificial layer 105 b is polished by chemical mechanical polishing (CMP) operations. - In
operation 507, several a portion of conductor is formed as shown inFIGS. 5H and 5I . In some embodiments,several vias 105 d passing through firstsacrificial layer 105 a or secondsacrificial layer 105 b are formed as shown inFIG. 5H . In some embodiments, vias 105 d are formed by any suitable operation such as photolithography and etching. In some embodiments, firstsacrificial layer 105 a or secondsacrificial layer 105 b are partially removed and stopped atplate 101 to form vias 105 d. In some embodiments, firstsacrificial layer 105 a or secondsacrificial layer 105 b are partially removed and stopped atmembrane 102 to form vias 105 e. - In some embodiments, vias 105 d are deposited and filled by conductive materials such as copper to form conductive plugs (or first portion conductor) 103 a as shown in
FIG. 5I . In some embodiments,conductive plugs 103 a pass through firstsacrificial layer 105 a or secondsacrificial layer 105 b. In some embodiments,conductive plug 103 a is extended fromplate 101 through themembrane 102. In some embodiments,conductive plug 103 a is extended from or throughmembrane 102. In some embodiments,conductive plug 103 a includes a silicide portion configured to provide an ohmic contact betweenplate 101 andmetallic plug 103 a. - In some embodiments,
conductive plugs 103 a are formed by partially removing firstsacrificial layer 105 a or secondsacrificial layer 105 b and then disposing copper. In some embodiments, firstsacrificial layer 105 a or secondsacrificial layer 105 b is partially removed by photolithography and etching operations. In some embodiments, copper is disposed by any suitable deposition operations. In some embodiments,conductive plug 103 a has a height of about 1 um to about 50 um. -
FIG. 6 is an embodiment ofmethod 600 for manufacturing a portion ofMEMS device 100.Method 600 includes a number of operations (601, 602, 603, 604, 605 and 606). Inoperation 601,second substrate 201 is provided or received as shown inFIG. 7A . In some embodiments,second substrate 201 includes several active devices such as CMOS devices.Second substrate 201 includesinterconnect 203 disposed oversecond substrate 201 and severalconductive pads 202 disposed in upper level oflayer 203. - In
operation 602,interconnect 203 is partially removed as shown inFIG. 7B . In some embodiments,layer 203 is partially removed by any suitable operations such as photolithography and etching. - In
operation 603, aprotective layer 205 is disposed overinterconnect 203,pads 202 andsecond substrate 201 as shown inFIG. 7C . In some embodiments,protective layer 205 is configured to preventsecond substrate 201,layer 203,pad 202 or other components disposed oversecond substrate 201 from being etched or removed. In some embodiments,protective layer 205 is an etching stop layer to preventsecond substrate 201 and the components disposed oversecond substrate 201 from being attacked by hydrofluoric acid vapor. - In some embodiments, an additional
dielectric layer 206 is disposed overprotective layer 205 as shown inFIG. 7D . In some embodiments,protective layer 205 and additionaldielectric layer 206 disposed onpads 202 are removed as shown inFIG. 7E .Pads 202 are exposed frominterconnect 203,protective layer 205 and throughholes 206 a indielectric layer 206. - A conductive material is filled into through
holes 206 a as shown inFIG. 7F and formssecond portion conductor 103 b. Throughholes 206 a can be overfilled by the overlying section as mentioned is the description corresponding toFIG. 2 . - In
operation 604,first substrate 106 is flipped so thatfirst portion conductor 103 a andsecond portion conductor 103 b are bonded as shown inFIG. 7G . - In
operation 605,first substrate 106 andsecond substrate 201 are thinned down as shown inFIG. 7H . In some embodiments,first substrate 106 andsecond substrate 201 are thinned down by grinding operations. In some embodiments as shown inFIG. 7I ,first substrate 106 is wholly or partially removed. In some embodiments, some portions or all offirst substrate 106 are removed by grinding or etching operations. In some embodiments,first substrate 106 is thinned down or removed by dry or wet etching. In some embodiments, the dry or wet etching offirst substrate 106 is stopped atplate 101. In some embodiments,second substrate 201 is thinned down from the thickness of about 800 um to about 100 um. In some embodiments,second substrate 201 is thinned down from the thickness of about 800 um to about 50 um. - In
operation 606,plate 101 is partially removed to have several throughholes 101 a as shown inFIG. 7I . Inoperation 607, afirst cavity 104 is formed by partially removing firstsacrificial layer 105 a and secondsacrificial layer 105 b as inFIG. 7J . Asecond cavity 204 is formed as well by partially removingsecond substrate 201,protective layer 205, andlayer 206. In some embodiments,second cavity 204 passes throughsecond substrate 201 andlayer 203. In some embodiments,second cavity 204 is aligned withfirst cavity 104. A monolithic MEMS device as shown inFIG. 2 is formed. - In the present disclosure a semiconductor device comprises a plate including a plurality of apertures. The semiconductor device also comprises a membrane disposed opposite to the plate and including a plurality of corrugations, a dielectric surrounding and covering an edge of the membrane, and a substrate. The semiconductor device further includes a metallic conductor comprising a first portion extending through the dielectric, and a second portion over the substrate, where the second portion is bonded with the first portion.
- In the present disclosure a semiconductor comprises a monolithic sensor comprising a micro-electro mechanical system (MEMS) device and a complementary metal oxide semiconductor (CMOS) device. The MEMS device comprises a plate including a plurality of apertures. The MEMS device also includes a membrane disposed opposite to the plate and including a plurality of corrugations. The MEMS device further includes a first conductor disposed below the plate, and a first cavity between the plate and the membrane. Furthermore, the CMOS device comprises a substrate, an interconnect disposed over the substrate, and a second conductor electrically coupled to the interconnect and extruded from the interconnect toward the membrane. The first conductor is connected with the second conductor in a metal bond manner.
- In the present disclosure a method of manufacturing a semiconductor structure comprises: providing a first substrate; disposing a plate over the first substrate; disposing a first sacrificial layer over the plate; forming a plurality of recesses over a surface of the first sacrificial layer; disposing and patterning a membrane over the first sacrificial layer; disposing a second sacrificial layer to surround the membrane and cover the first sacrificial layer; and forming a plurality of conductors passing through the second sacrificial layer or the membrane. A second substrate is provided. A protective is provided over the second substrate and a dielectric layer is provided over the protective layer. Second conductors are filled in holes through the dielectric layer. The first substrate is flipped and the conductors are bonded with second conductors. A first cavity is formed by partially removing the first sacrificial layer and the second sacrificial layer. A second cavity is formed by partially removing the second substrate, the protective layer, and the dielectric layer.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (23)
1. A semiconductor device, comprising:
a plate including a plurality of apertures;
a membrane disposed opposite to the plate and including a plurality of corrugations on a surface;
a first dielectric surrounding and covering an edge of the membrane;
a substrate;
a second dielectric between the substrate and the first dielectric; and
a metallic conductor, comprising
a first portion extending through the first dielectric along a first central axis of the first portion; and
a second portion over the substrate, an end of the second portion extending through the second dielectric along a second central axis of the end, wherein the second portion is bonded with the first portion and the second central axis is offset from the first central axis.
2. The semiconductor device of claim 1 , wherein the membrane is configured to be displaceable relative to the plate.
3. The semiconductor structure of claim 1 , wherein the membrane is within a cavity defined by the plate and the membrane.
4. The semiconductor structure of claim 1 , wherein the first portion conductor includes one of gold, tin, silicon, copper and tin copper alloy.
5. The semiconductor structure of claim 1 , wherein the second portion conductor includes one of gold, tin, silicon, copper and tin copper alloy.
6. The semiconductor structure of claim 1 , wherein the membrane is sensitive to an acoustic pressure.
7. The semiconductor structure of claim 1 , wherein the first portion conductor is electrically coupled to the membrane.
8. The semiconductor structure of claim 1 , wherein the plate comprises a silicon-on-insulator layer, polysilicon, oxide, or epitaxial silicon.
9. The semiconductor structure of claim 1 , wherein the second portion conductor is configured as a loop.
10. The semiconductor structure of claim 1 , wherein each of the plurality of corrugations is protruded from membrane and toward the plate.
11. A monolithic sensor, comprising:
a micro-electro mechanical system (MEMS) device comprising:
a plate including a plurality of apertures;
a membrane disposed opposite to the plate and including a plurality of corrugations;
a first conductor disposed below the plate and extending along a first central axis of the first conductor, and
a first cavity between the plate and the membrane; and
a complementary metal oxide semiconductor (CMOS) device comprising:
a substrate;
an interconnect disposed over the substrate and
a second conductor electrically coupled to the interconnect and extruded from the interconnect toward the membrane along a second central axis of the second conductor,
wherein the first conductor is connected with the second conductor in a metal bond manner and the first central axis is in parallel but not aligned with the second central axis.
12. The monolithic sensor of claim 11 , wherein a total thickness from the MEMS to the CMOS device is less than about 200 um.
13. The monolithic sensor of claim 11 , wherein the plate is stationary and the membrane is movable within the first cavity and relative to the plate.
14. The monolithic sensor of claim 11 , wherein the MEMS device includes a dielectric disposed around a peripheral portion of the membrane.
15. The monolithic sensor of claim 11 , wherein the CMOS device includes a dielectric between the interconnect and the first conductor, wherein a portion of the second conductor is partially interposed between the interconnect and the first conductor.
16. The monolithic sensor of claim 11 , wherein the plate has a thickness of about 0.3 um to about 50 um.
17. The monolithic sensor of claim 11 , wherein the plate is disposed away from the membrane in a distance of about 0.1 um to about 5 um.
18. (canceled)
19. (canceled)
20. (canceled)
21. A semiconductor device, comprising:
a plate including a plurality of apertures;
a movable membrane including a plurality of corrugations;
a first cavity between the plate and the movable membrane;
a substrate;
a first dielectric between the plate and the substrate;
a metallic conductor, comprising
a first portion being in contact with the first dielectric; and
a second portion over the substrate, wherein the second portion is bonded with the first portion, wherein a central axis shared by the first portion and the second portion staggers conformally to the first portion and the second portion.
22. The semiconductor device of claim 21 , wherein a sidewall of the first portion is partially exposed from the first dielectric.
23. The semiconductor device of claim 21 , further comprising a second dielectric between the substrate and the first dielectric, wherein the second portion is surrounded by the second dielectric.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/000,521 US9718677B1 (en) | 2016-01-19 | 2016-01-19 | Semiconductor structure and manufacturing method thereof |
TW105137310A TWI733711B (en) | 2016-01-19 | 2016-11-15 | Semiconductor structure and manufacturing method thereof |
CN201611139549.4A CN106976836A (en) | 2016-01-19 | 2016-12-12 | Semiconductor structure and its manufacture method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/000,521 US9718677B1 (en) | 2016-01-19 | 2016-01-19 | Semiconductor structure and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
US20170203961A1 true US20170203961A1 (en) | 2017-07-20 |
US9718677B1 US9718677B1 (en) | 2017-08-01 |
Family
ID=59314310
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/000,521 Active US9718677B1 (en) | 2016-01-19 | 2016-01-19 | Semiconductor structure and manufacturing method thereof |
Country Status (3)
Country | Link |
---|---|
US (1) | US9718677B1 (en) |
CN (1) | CN106976836A (en) |
TW (1) | TWI733711B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190062146A1 (en) * | 2017-08-31 | 2019-02-28 | Cirrus Logic International Semiconductor Ltd. | Mems devices and processes |
US20200223687A1 (en) * | 2019-01-14 | 2020-07-16 | United Microelectronics Corp. | Micro-electro-mechanical system structure and method for fabricating the same |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9589941B1 (en) * | 2016-01-15 | 2017-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip package system and methods of forming the same |
CN112088539B (en) * | 2018-03-21 | 2022-06-03 | 美商楼氏电子有限公司 | Microphone and control circuit for same |
US11731871B2 (en) * | 2021-05-28 | 2023-08-22 | Invensense, Inc. | Actuator layer patterning with polysilicon and etch stop layer |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6859542B2 (en) * | 2001-05-31 | 2005-02-22 | Sonion Lyngby A/S | Method of providing a hydrophobic layer and a condenser microphone having such a layer |
US8093119B2 (en) * | 2009-06-24 | 2012-01-10 | Solid State System Co., Ltd. | CMOS microelectromechanical system (MEMS) device and fabrication method thereof |
US8486744B2 (en) * | 2010-09-28 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple bonding in wafer level packaging |
US20130161702A1 (en) * | 2011-12-25 | 2013-06-27 | Kun-Lung Chen | Integrated mems device |
US9139423B2 (en) * | 2012-01-19 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Micro electro mechanical system structures |
US9409763B2 (en) * | 2012-04-04 | 2016-08-09 | Infineon Technologies Ag | MEMS device and method of making a MEMS device |
DE102012210052B4 (en) * | 2012-06-14 | 2023-12-14 | Robert Bosch Gmbh | Hybrid integrated component and method for its production |
US9264833B2 (en) * | 2013-03-14 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for integrated microphone |
US9681234B2 (en) * | 2013-05-09 | 2017-06-13 | Shanghai Ic R&D Center Co., Ltd | MEMS microphone structure and method of manufacturing the same |
CN103281661B (en) * | 2013-05-09 | 2019-02-05 | 上海集成电路研发中心有限公司 | A kind of MEMS microphone structure and its manufacturing method |
US9299671B2 (en) * | 2013-10-15 | 2016-03-29 | Invensense, Inc. | Integrated CMOS back cavity acoustic transducer and the method of producing the same |
TWI538762B (en) * | 2014-01-03 | 2016-06-21 | 樂金股份有限公司 | Stud bump and package structure thereof and method of forming the same |
TWI542019B (en) * | 2014-06-25 | 2016-07-11 | 明銳光電股份有限公司 | Pressure sensor and manufacture method thereof |
-
2016
- 2016-01-19 US US15/000,521 patent/US9718677B1/en active Active
- 2016-11-15 TW TW105137310A patent/TWI733711B/en active
- 2016-12-12 CN CN201611139549.4A patent/CN106976836A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190062146A1 (en) * | 2017-08-31 | 2019-02-28 | Cirrus Logic International Semiconductor Ltd. | Mems devices and processes |
US20200223687A1 (en) * | 2019-01-14 | 2020-07-16 | United Microelectronics Corp. | Micro-electro-mechanical system structure and method for fabricating the same |
US10737932B2 (en) * | 2019-01-14 | 2020-08-11 | United Microelectronics Corp. | Micro-electro-mechanical system structure and method for fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
TW201736241A (en) | 2017-10-16 |
CN106976836A (en) | 2017-07-25 |
TWI733711B (en) | 2021-07-21 |
US9718677B1 (en) | 2017-08-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9815685B2 (en) | Semiconductor sensing structure and manufacturing method thereof | |
US9718677B1 (en) | Semiconductor structure and manufacturing method thereof | |
US9738516B2 (en) | Structure to reduce backside silicon damage | |
US20200213701A1 (en) | Integrated microphone device and manufacturing method thereof | |
US10787360B2 (en) | Semiconductor MEMS structure | |
US8252695B2 (en) | Method for manufacturing a micro-electromechanical structure | |
KR20080023313A (en) | A method of manufacturing a mems element | |
US11203522B2 (en) | Sidewall stopper for MEMS device | |
US10968097B2 (en) | Support structure for MEMS device with particle filter | |
US10266399B2 (en) | Apparatus and method of manufacturing for combo MEMS device accommodating different working pressures | |
US11708262B2 (en) | Manufacturing method of semiconductor structure | |
US10087071B2 (en) | Semiconductor structure and manufacturing method thereof | |
US9975754B2 (en) | Semiconductor structure and manufacturing method thereof | |
US11993512B2 (en) | Dual micro-electro mechanical system and manufacturing method thereof | |
US10266396B2 (en) | MEMS device with enhanced sensing structure and manufacturing method thereof | |
CN112744779B (en) | Microelectromechanical system and method of manufacturing the same | |
US20170044004A1 (en) | Micro-electro-mechanical system and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., T Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, YI-HSIEN;CHENG, CHUN-REN;REEL/FRAME:037522/0651 Effective date: 20160113 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |