US20170186688A1 - Methods and devices for metal filling processes - Google Patents
Methods and devices for metal filling processes Download PDFInfo
- Publication number
- US20170186688A1 US20170186688A1 US15/460,976 US201715460976A US2017186688A1 US 20170186688 A1 US20170186688 A1 US 20170186688A1 US 201715460976 A US201715460976 A US 201715460976A US 2017186688 A1 US2017186688 A1 US 2017186688A1
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- Prior art keywords
- layer
- metal
- over
- hard mask
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 75
- 239000002184 metal Substances 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title abstract description 45
- 238000005429 filling process Methods 0.000 title abstract description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 137
- 239000000463 material Substances 0.000 claims description 34
- 238000001459 lithography Methods 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000011572 manganese Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical group [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052748 manganese Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 36
- 229910001092 metal group alloy Inorganic materials 0.000 abstract description 8
- 230000004888 barrier function Effects 0.000 abstract description 6
- 239000007769 metal material Substances 0.000 abstract description 2
- 238000001465 metallisation Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000956 alloy Substances 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910001080 W alloy Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- -1 SiON Chemical compound 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- HPDFFVBPXCTEDN-UHFFFAOYSA-N copper manganese Chemical compound [Mn].[Cu] HPDFFVBPXCTEDN-UHFFFAOYSA-N 0.000 description 1
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005191 phase separation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
Definitions
- the present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly, to methods and devices for metal filling processes.
- the size of trenches and vias continue to decrease.
- the semiconductor devices may experience gap filling issues resulting in, for example, line voids in the trenches and vias. These line voids may decrease the device yield and reliability and also increase defectivity. Thus, new methods and devices for metal filling are needed.
- a method includes obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings.
- an intermediate semiconductor device which includes, for instance: a substrate; at least one contact opening in the substrate; a first material in a bottom portion of the at least one contact opening; and at least one second material over the first material in a top portion of the at least one contact opening
- FIG. 1 depicts one embodiment of a method for metal filling process, in accordance with one or more aspects of the present invention
- FIG. 2 depicts a cross-sectional elevation view of one embodiment of an integrated circuit with contacts disposed over a substrate structure and a first metal layer over the device, in accordance with one or more aspects of the present invention
- FIG. 3 depicts the cross-sectional elevation view of the semiconductor device of FIG. 2 after chemical mechanical planarization (CMP), in accordance with one or more aspects of the present invention
- FIG. 4 depicts the cross-sectional elevation view of the semiconductor device of FIG. 3 after depositing an etch stop layer, an interlayer dielectric layer, a first dielectric hard mask, a metal hard mask layer, a second dielectric hard mask, and a first lithography stack, in accordance with one or more aspects of the present invention
- FIG. 5 depicts the cross-sectional elevation view of the semiconductor device of FIG. 4 after performing lithography to pattern trenches and etching to form the trenches, in accordance with one or more aspects of the present invention
- FIG. 6 depicts the cross-sectional elevation view of the semiconductor device of FIG. 5 after depositing a second lithography stack and performing lithography to pattern vias, in accordance with one or more aspects of the present invention
- FIG. 7 depicts the cross-sectional elevation view of the semiconductor device of FIG. 6 after performing a full etch to open the trenches and vias, in accordance with one or more aspects of the present invention
- FIG. 8 depicts the cross-sectional elevation view of the semiconductor device of FIG. 7 after performing a wet etch clean to remove the titanium nitride (TiN), in accordance with one or more aspects of the present invention
- FIG. 9 depicts the cross-sectional elevation view of the semiconductor device of FIG. 8 after depositing a second metal, in accordance with one or more aspects of the present invention.
- FIG. 10 depicts the cross-sectional elevation view of the semiconductor device of FIG. 9 after CMP, in accordance with one or more aspects of the present invention
- FIG. 11 depicts a cross-sectional elevation view of another embodiment semiconductor device with contacts disposed in a substrate structure, in accordance with one or more aspects of the present invention
- FIG. 12 depicts the cross-sectional elevation view of the semiconductor device of FIG. 11 after performing CMP and an anneal, in accordance with one or more aspects of the present invention
- FIG. 13 depicts the cross-sectional elevation view of the semiconductor device of FIG. 12 after depositing an etch stop layer, an interlayer dielectric layer, a first dielectric hard mask, a metal hard mask layer, a second dielectric hard mask, and a first lithography stack, in accordance with one or more aspects of the present invention
- FIG. 14 depicts the cross-sectional elevation view of the semiconductor device of FIG. 13 after performing lithography to pattern trenches and etching to form the trenches, in accordance with one or more aspects of the present invention
- FIG. 15 depicts the cross-sectional elevation view of the semiconductor device of FIG. 14 after depositing a second lithography stack and performing lithography to pattern vias, in accordance with one or more aspects of the present invention
- FIG. 16 depicts the cross-sectional elevation view of the semiconductor device of FIG. 15 after performing a full etch to open the trenches and vias, in accordance with one or more aspects of the present invention
- FIG. 17 depicts the cross-sectional elevation view of the semiconductor device of FIG. 16 after performing a wet etch clean to open the trenches and vias, in accordance with one or more aspects of the present invention
- FIG. 18 depicts the cross-sectional elevation view of the semiconductor device of FIG. 17 after depositing a metal layer, in accordance with one or more aspects of the present invention.
- FIG. 19 depicts the cross-sectional elevation view of the semiconductor device of FIG. 18 after performing a CMP, in accordance with one or more aspects of the present invention.
- FETs field-effect transistors
- the semiconductor device fabrication processes disclosed herein provide for devices with improved yield, defectivity, and reliability.
- the semiconductor device formation process in accordance with one or more aspects of the present invention may include, for instance: obtaining a wafer with contact openings 100 ; depositing a first metal into the contact openings 110 ; depositing a metal alloy over the wafer 112 ; performing chemical mechanical planarization (CMP) 114 ; depositing an etch stop layer 130 ; depositing an interlayer dielectric layer 132 ; depositing a first dielectric hard mask 134 ; depositing a metal hard mask layer 136 ; depositing a second dielectric hard mask 138 ; depositing a first lithography stack 140 ; performing lithography to form at least one trench 142 ; depositing a second lithography stack 144 ; performing lithography to form at least one via 146 ; etching to open the at least one trench and the at least one via 148 ; performing a wet etching to remove the metal hard mask layer 150 ; and depositing a metal layer and performing C
- the semiconductor device formation process in accordance with one or more aspects of the present invention may include, for instance: obtaining a wafer with contact openings 100 ; depositing a metal alloy into the contacts 120 ; performing CMP 122 ; performing an anneal to separate the metal alloy 124 ; depositing an etch stop layer 130 ; depositing an interlayer dielectric layer 132 ; depositing a first dielectric hard mask 134 ; depositing a metal hard mask layer 136 ; depositing a second dielectric hard mask 138 ; depositing a first lithography stack 140 ; performing lithography to form at least one trench 142 ; depositing a second lithography stack 144 ; performing lithography to form at least one via 146 ; etching to open the at least one trench and the at least one via 148 ; performing a wet etching to remove the metal hard mask layer 150 ; depositing a metal layer and performing CMP 152 .
- FIGS. 2-19 depict, by way of example only, several detailed embodiments of a portion of a semiconductor device formation process of FIG. 1 and an intermediate semiconductor device, in accordance with one or more aspects of the present invention. Note again that these figures are not drawn to scale in order to facilitate understanding of the invention, and that the same reference numerals used throughout different figures designate the same or similar elements.
- FIG. 2 shows a portion of a semiconductor device 200 obtained during the fabrication process.
- the device 200 may have been processed through initial device processing steps in accordance with the design of the device 200 being fabricated, for example, the device 200 may include, for example, a substrate 202 with at least one contact opening 204 .
- the substrate 202 may in some embodiments have or be a substantially crystalline substrate material (i.e., bulk silicon), whereas in other embodiments, substrate 202 may be formed on the basis of a silicon-on-insulator (SOI) architecture.
- SOI silicon-on-insulator
- the at least one contact opening 204 may be filled with a metal 206 , for example, tungsten (W).
- the device 200 may also include an alloy material layer 208 , for example, copper manganese (CuMn).
- the device 200 may also include at least one isolation region (not shown), at least one fin (not shown), source regions (not shown), drain regions (not shown) and the like.
- a CMP may be performed to the alloy material layer 208 of the device 200 .
- an etch stop layer 214 may be deposited over the device 200 . Deposition of the etch stop layer 214 may cause the alloy material layer 208 to separate into a first metal layer 210 and a second metal layer 212 . Where the alloy material layer 208 is CuMn, the first metal layer 210 may be, for example, a copper (Cu) layer, and the second metal layer 212 may be, for example, a manganese (Mn) layer. Then, an interlayer dielectric (ILD) layer 216 may be deposited over the etch stop layer 214 .
- ILD interlayer dielectric
- the ILD layer 216 may include, for example, silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and the like, or a combination of these commonly used dielectric materials.
- a first dielectric hard mask 218 may be deposited over the ILD layer 216 .
- a metal hard mask layer 220 may then be deposited over the first dielectric hard mask 218 .
- the metal hard mask layer 220 may be, for example, titanium nitride (TiN).
- a second dielectric hard mask 222 may be deposited over the metal hard mask layer 220 .
- the first and second dielectric hard masks 218 , 222 may act as a protective layers for the underlying layers during the device fabrication, for example, during an ashing process of a photoresist mask layer.
- the first and second dielectric hard masks 218 , 222 may have an etch selectivity relative to at least the material including the upper surface portion of the ILD layer 216 , such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), and the like.
- the dielectric hard masks 218 , 222 may be formed above the contacts 204 by performing a suitable deposition process based on device parameters well known in the art, such as, chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, atomic layer deposition (ALD), spin on coating, and the like.
- a first lithography stack 224 may be applied over the second dielectric hard mask 222 based on typical photolithography processes.
- the first lithography stack 224 may include, for example, a spin-on hardmask (SOH) layer 226 , a SiON layer 228 , a bottom anti-reflection coating (BARC) layer (not shown), and a photoresist layer (not shown).
- lithography may be performed to pattern and etch trenches or trench openings 230 , 232 in the second dielectric hard mask 222 and the metal hard mask layer 220 .
- any remaining portion of the first lithography stack 224 may be removed from the device.
- a second lithography stack 234 may be deposited over the device 200 , as shown in FIG. 6 .
- the second lithography stack 234 may include, for example, a SOH layer 236 , a SiON layer 238 , a BARC layer 240 , and a photoresist layer 242 .
- Lithography may then be performed to pattern the photoresist layer 242 to form via openings 244 .
- a full etch may be performed to open the trench openings 246 and via openings 248 , as shown in FIG. 7 .
- the vias 248 may be, for example, etched down to contact at least one contact metal 206 .
- a wet etch clean may then be performed over the device 200 , to remove any of the remaining metal hard mask layer 220 , as shown in FIG. 8 .
- a metal deposition process may then be performed to deposit at least one metal layer 250 into the trench openings 246 and via openings 248 , as shown in FIG. 9 .
- the metal deposition process may be any suitable metal deposition process based known in the art.
- the metal deposition process may include depositing a barrier layer (not shown) over the device 200 and into the trench openings 246 and via openings 248 .
- the metal deposition process may include depositing a seed layer (not shown) over the barrier layer (not shown).
- the trench openings 246 and via openings 248 may be filled with a layer of conductive contact material 250 based on a substantially “bottom-up” deposition process well known to those skilled in the art, such as, a suitably designed electrochemical plating (ECP) process and the like, thereby reducing the likelihood of voids formed and/or trapped in the finished trenches 252 and vias 254 , as shown in FIG. 10 after a CMP.
- ECP electrochemical plating
- FIG. 11 shows a portion of a semiconductor device 300 obtained during the fabrication process.
- the device 300 may have been processed through initial device processing steps in accordance with the design of the device 300 being fabricated, for example, the device 300 may include, for example, a substrate 302 with at least one contact 304 .
- the substrate 302 may in some embodiments have or be a substantially crystalline substrate material (i.e., bulk silicon), whereas in other embodiments, substrate 302 may be formed on the basis of a silicon-on-insulator (SOI) architecture.
- SOI silicon-on-insulator
- the at least one contact 304 may be, for example, a copper tungsten alloy (Cu—W) which has been deposited into the contact openings and a CMP performed to form the at least one contact 304 .
- the Cu—W alloy may be, for example, deposited as a film by a direct current magnetron sputtering technique.
- the device 300 may also include at least one isolation region (not shown), at least one fin (not shown), source regions (not shown), drain regions (not shown) and the like.
- an anneal process may be performed to separate the two metals in the metal alloy filling the at least one contact 304 .
- the tungsten (W) and copper (Cu) may separate such that the W fills the bottom portion 306 of the contact opening and the Cu forms a layer 308 on the top of the contact opening over the W bottom portion 306 .
- the anneal process may be, for example, a laser based anneal which causes a phase separation of the Cu and W.
- an etch stop layer 310 may then be deposited over the device 300 .
- an interlayer dielectric (ILD) layer 312 may be deposited over the etch stop layer 310 .
- the ILD layer 312 may include, for example, SiO 2 , SiN, SiON, and the like, or a combination of these commonly used dielectric materials.
- a first dielectric hard mask 314 may be deposited over the ILD layer 312 .
- a metal hard mask layer 316 may then be deposited over the first dielectric hard mask 314 .
- the metal hard mask layer 316 may be, for example, TiN.
- a second dielectric hard mask 318 may be deposited over the metal hard mask layer 316 .
- the first and second dielectric hard masks 314 , 318 may act as a protective layers for the underlying layers during the device fabrication, for example, during an ashing process of a photoresist mask layer.
- the first and second dielectric hard masks 314 , 318 may have an etch selectivity relative to at least the material including the upper surface portion of the ILD layer 312 , such as SiN, SiON, SiC, SiCN, and the like.
- the dielectric hard masks 314 , 318 may be formed above the contacts 304 by performing a suitable deposition process based on device parameters well known in the art, such as, CVD process, a PVD process, ALD process, spin on coating, and the like.
- a first lithography stack 324 may be applied over the second dielectric hard mask 318 based on typical photolithography processes.
- the first lithography stack 324 may include, for example, a SOH layer 320 , a SiON layer 322 , a BARC layer (not shown), and a photoresist layer (not shown).
- lithography and etching may be performed to pattern and etch trenches or trench openings 326 , 328 in the second dielectric hard mask 318 and the metal hard mask layer 316 .
- any remaining portion of the first lithography stack 324 may be removed from the device 300 .
- a second lithography stack 330 may be deposited over the device 300 , as shown in FIG. 15 .
- the second lithography stack 330 may include, for example, a SOH layer 332 , a SiON layer 334 , a BARC layer 336 , and a photoresist layer 338 .
- Lithography and etching may then be performed to pattern the photoresist layer 338 to form via openings 340 .
- a full etch may be performed to open the trench openings 326 and via openings 340 , as shown in FIG. 16 .
- the via openings 340 may be, for example, etched down to the Cu layer 308 of the at least one contact 304 .
- a wet etch clean may then be performed over the device 300 , to remove any of the remaining metal hard mask layer 316 , as shown in FIG. 17 .
- a metal deposition process may then be performed to deposit at least one metal layer 346 into the trench openings 326 and via openings 340 , as shown in FIG. 18 .
- the metal deposition process may be any suitable metal deposition process based known in the art.
- the metal deposition process may include depositing a barrier layer (not shown) over the device 300 and into the trench openings 326 and via openings 340 .
- the metal deposition process may include depositing a seed layer (not shown) over the barrier layer (not shown).
- the trench openings 326 and via openings 340 may be filled with a layer of conductive contact material 346 based on a substantially “bottom-up” deposition process well known to those skilled in the art, such as, a suitably designed ECP process and the like, thereby reducing the likelihood of voids formed and/or trapped in the finished trenches 348 and vias 350 , as shown in FIG. 19 after CMP processing.
- a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements.
- a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features.
- a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
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Abstract
Description
- This application is a divisional of U.S. application Ser. No. 14/824,181 filed Aug. 12, 2015, which is hereby incorporated herein by reference in its entirety.
- The present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly, to methods and devices for metal filling processes.
- As semiconductor devices continue to decrease in size, the size of trenches and vias continue to decrease. With smaller trenches and vias the semiconductor devices may experience gap filling issues resulting in, for example, line voids in the trenches and vias. These line voids may decrease the device yield and reliability and also increase defectivity. Thus, new methods and devices for metal filling are needed.
- The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, a method includes obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings.
- In another aspect, an intermediate semiconductor device is provided which includes, for instance: a substrate; at least one contact opening in the substrate; a first material in a bottom portion of the at least one contact opening; and at least one second material over the first material in a top portion of the at least one contact opening
- Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.
- One or more aspects of the present invention are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
-
FIG. 1 depicts one embodiment of a method for metal filling process, in accordance with one or more aspects of the present invention; -
FIG. 2 depicts a cross-sectional elevation view of one embodiment of an integrated circuit with contacts disposed over a substrate structure and a first metal layer over the device, in accordance with one or more aspects of the present invention; -
FIG. 3 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 2 after chemical mechanical planarization (CMP), in accordance with one or more aspects of the present invention; -
FIG. 4 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 3 after depositing an etch stop layer, an interlayer dielectric layer, a first dielectric hard mask, a metal hard mask layer, a second dielectric hard mask, and a first lithography stack, in accordance with one or more aspects of the present invention; -
FIG. 5 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 4 after performing lithography to pattern trenches and etching to form the trenches, in accordance with one or more aspects of the present invention; -
FIG. 6 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 5 after depositing a second lithography stack and performing lithography to pattern vias, in accordance with one or more aspects of the present invention; -
FIG. 7 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 6 after performing a full etch to open the trenches and vias, in accordance with one or more aspects of the present invention; -
FIG. 8 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 7 after performing a wet etch clean to remove the titanium nitride (TiN), in accordance with one or more aspects of the present invention; -
FIG. 9 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 8 after depositing a second metal, in accordance with one or more aspects of the present invention; -
FIG. 10 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 9 after CMP, in accordance with one or more aspects of the present invention; -
FIG. 11 depicts a cross-sectional elevation view of another embodiment semiconductor device with contacts disposed in a substrate structure, in accordance with one or more aspects of the present invention; -
FIG. 12 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 11 after performing CMP and an anneal, in accordance with one or more aspects of the present invention; -
FIG. 13 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 12 after depositing an etch stop layer, an interlayer dielectric layer, a first dielectric hard mask, a metal hard mask layer, a second dielectric hard mask, and a first lithography stack, in accordance with one or more aspects of the present invention; -
FIG. 14 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 13 after performing lithography to pattern trenches and etching to form the trenches, in accordance with one or more aspects of the present invention; -
FIG. 15 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 14 after depositing a second lithography stack and performing lithography to pattern vias, in accordance with one or more aspects of the present invention; -
FIG. 16 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 15 after performing a full etch to open the trenches and vias, in accordance with one or more aspects of the present invention; -
FIG. 17 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 16 after performing a wet etch clean to open the trenches and vias, in accordance with one or more aspects of the present invention; -
FIG. 18 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 17 after depositing a metal layer, in accordance with one or more aspects of the present invention; and -
FIG. 19 depicts the cross-sectional elevation view of the semiconductor device ofFIG. 18 after performing a CMP, in accordance with one or more aspects of the present invention. - Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as to not unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions and/or arrangements within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure. Note also that reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components.
- Generally stated, disclosed herein are certain semiconductor devices, for example, field-effect transistors (FETs), which provide advantages over the above noted, existing semiconductor devices and fabrication processes. Advantageously, the semiconductor device fabrication processes disclosed herein provide for devices with improved yield, defectivity, and reliability.
- In one aspect, in one embodiment, as shown in
FIG. 1 , the semiconductor device formation process in accordance with one or more aspects of the present invention may include, for instance: obtaining a wafer withcontact openings 100; depositing a first metal into thecontact openings 110; depositing a metal alloy over thewafer 112; performing chemical mechanical planarization (CMP) 114; depositing anetch stop layer 130; depositing an interlayerdielectric layer 132; depositing a first dielectrichard mask 134; depositing a metalhard mask layer 136; depositing a second dielectrichard mask 138; depositing afirst lithography stack 140; performing lithography to form at least onetrench 142; depositing asecond lithography stack 144; performing lithography to form at least one via 146; etching to open the at least one trench and the at least one via 148; performing a wet etching to remove the metalhard mask layer 150; and depositing a metal layer and performingCMP 152. - In another aspect, in one embodiment, as shown in
FIG. 1 , the semiconductor device formation process in accordance with one or more aspects of the present invention may include, for instance: obtaining a wafer withcontact openings 100; depositing a metal alloy into thecontacts 120; performingCMP 122; performing an anneal to separate themetal alloy 124; depositing anetch stop layer 130; depositing an interlayerdielectric layer 132; depositing a first dielectrichard mask 134; depositing a metalhard mask layer 136; depositing a second dielectrichard mask 138; depositing afirst lithography stack 140; performing lithography to form at least onetrench 142; depositing asecond lithography stack 144; performing lithography to form at least one via 146; etching to open the at least one trench and the at least one via 148; performing a wet etching to remove the metalhard mask layer 150; depositing a metal layer and performingCMP 152. -
FIGS. 2-19 depict, by way of example only, several detailed embodiments of a portion of a semiconductor device formation process ofFIG. 1 and an intermediate semiconductor device, in accordance with one or more aspects of the present invention. Note again that these figures are not drawn to scale in order to facilitate understanding of the invention, and that the same reference numerals used throughout different figures designate the same or similar elements. - One detailed embodiment of a portion of the semiconductor device formation process of
FIG. 1 is depicted, by way of example only, inFIGS. 2-10 .FIG. 2 shows a portion of asemiconductor device 200 obtained during the fabrication process. Thedevice 200 may have been processed through initial device processing steps in accordance with the design of thedevice 200 being fabricated, for example, thedevice 200 may include, for example, asubstrate 202 with at least one contact opening 204. Thesubstrate 202 may in some embodiments have or be a substantially crystalline substrate material (i.e., bulk silicon), whereas in other embodiments,substrate 202 may be formed on the basis of a silicon-on-insulator (SOI) architecture. The at least onecontact opening 204 may be filled with ametal 206, for example, tungsten (W). Thedevice 200 may also include analloy material layer 208, for example, copper manganese (CuMn). Thedevice 200 may also include at least one isolation region (not shown), at least one fin (not shown), source regions (not shown), drain regions (not shown) and the like. Next, as shown inFIG. 3 , a CMP may be performed to thealloy material layer 208 of thedevice 200. - Referring now to
FIG. 4 , anetch stop layer 214 may be deposited over thedevice 200. Deposition of theetch stop layer 214 may cause thealloy material layer 208 to separate into afirst metal layer 210 and asecond metal layer 212. Where thealloy material layer 208 is CuMn, thefirst metal layer 210 may be, for example, a copper (Cu) layer, and thesecond metal layer 212 may be, for example, a manganese (Mn) layer. Then, an interlayer dielectric (ILD)layer 216 may be deposited over theetch stop layer 214. TheILD layer 216 may include, for example, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and the like, or a combination of these commonly used dielectric materials. Next, a first dielectrichard mask 218 may be deposited over theILD layer 216. A metalhard mask layer 220 may then be deposited over the first dielectrichard mask 218. The metalhard mask layer 220 may be, for example, titanium nitride (TiN). Then, a second dielectrichard mask 222 may be deposited over the metalhard mask layer 220. The first and second dielectrichard masks hard masks ILD layer 216, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), and the like. The dielectrichard masks contacts 204 by performing a suitable deposition process based on device parameters well known in the art, such as, chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, atomic layer deposition (ALD), spin on coating, and the like. Afirst lithography stack 224 may be applied over the second dielectrichard mask 222 based on typical photolithography processes. Thefirst lithography stack 224 may include, for example, a spin-on hardmask (SOH)layer 226, aSiON layer 228, a bottom anti-reflection coating (BARC) layer (not shown), and a photoresist layer (not shown). - Next, as shown in
FIG. 5 , lithography may be performed to pattern and etch trenches ortrench openings hard mask 222 and the metalhard mask layer 220. Once theopenings first lithography stack 224 may be removed from the device. After theopenings second lithography stack 234 may be deposited over thedevice 200, as shown inFIG. 6 . Thesecond lithography stack 234 may include, for example, aSOH layer 236, aSiON layer 238, aBARC layer 240, and aphotoresist layer 242. Lithography may then be performed to pattern thephotoresist layer 242 to form viaopenings 244. After the viaopenings 244 are formed, a full etch may be performed to open thetrench openings 246 and viaopenings 248, as shown inFIG. 7 . Thevias 248 may be, for example, etched down to contact at least onecontact metal 206. A wet etch clean may then be performed over thedevice 200, to remove any of the remaining metalhard mask layer 220, as shown inFIG. 8 . - A metal deposition process may then be performed to deposit at least one
metal layer 250 into thetrench openings 246 and viaopenings 248, as shown inFIG. 9 . The metal deposition process may be any suitable metal deposition process based known in the art. For example, the metal deposition process may include depositing a barrier layer (not shown) over thedevice 200 and into thetrench openings 246 and viaopenings 248. Next the metal deposition process may include depositing a seed layer (not shown) over the barrier layer (not shown). Finally, thetrench openings 246 and viaopenings 248 may be filled with a layer ofconductive contact material 250 based on a substantially “bottom-up” deposition process well known to those skilled in the art, such as, a suitably designed electrochemical plating (ECP) process and the like, thereby reducing the likelihood of voids formed and/or trapped in thefinished trenches 252 and vias 254, as shown inFIG. 10 after a CMP. - Referring now to
FIGS. 11-19 , another detailed embodiment of a portion of the semiconductor device formation process ofFIG. 1 is depicted.FIG. 11 shows a portion of asemiconductor device 300 obtained during the fabrication process. Thedevice 300 may have been processed through initial device processing steps in accordance with the design of thedevice 300 being fabricated, for example, thedevice 300 may include, for example, asubstrate 302 with at least onecontact 304. Thesubstrate 302 may in some embodiments have or be a substantially crystalline substrate material (i.e., bulk silicon), whereas in other embodiments,substrate 302 may be formed on the basis of a silicon-on-insulator (SOI) architecture. The at least onecontact 304 may be, for example, a copper tungsten alloy (Cu—W) which has been deposited into the contact openings and a CMP performed to form the at least onecontact 304. The Cu—W alloy may be, for example, deposited as a film by a direct current magnetron sputtering technique. Thedevice 300 may also include at least one isolation region (not shown), at least one fin (not shown), source regions (not shown), drain regions (not shown) and the like. Next, as shown inFIG. 12 , an anneal process may be performed to separate the two metals in the metal alloy filling the at least onecontact 304. For example, the tungsten (W) and copper (Cu) may separate such that the W fills thebottom portion 306 of the contact opening and the Cu forms alayer 308 on the top of the contact opening over the Wbottom portion 306. The anneal process may be, for example, a laser based anneal which causes a phase separation of the Cu and W. - As shown in
FIG. 13 , anetch stop layer 310 may then be deposited over thedevice 300. Then, an interlayer dielectric (ILD)layer 312 may be deposited over theetch stop layer 310. TheILD layer 312 may include, for example, SiO2, SiN, SiON, and the like, or a combination of these commonly used dielectric materials. Next, a first dielectrichard mask 314 may be deposited over theILD layer 312. A metalhard mask layer 316 may then be deposited over the first dielectrichard mask 314. The metalhard mask layer 316 may be, for example, TiN. Then, a second dielectrichard mask 318 may be deposited over the metalhard mask layer 316. The first and second dielectrichard masks hard masks ILD layer 312, such as SiN, SiON, SiC, SiCN, and the like. The dielectrichard masks contacts 304 by performing a suitable deposition process based on device parameters well known in the art, such as, CVD process, a PVD process, ALD process, spin on coating, and the like. Afirst lithography stack 324 may be applied over the second dielectrichard mask 318 based on typical photolithography processes. Thefirst lithography stack 324 may include, for example, aSOH layer 320, aSiON layer 322, a BARC layer (not shown), and a photoresist layer (not shown). - Next, as shown in
FIG. 14 , lithography and etching may be performed to pattern and etch trenches ortrench openings hard mask 318 and the metalhard mask layer 316. Once theopenings first lithography stack 324 may be removed from thedevice 300. Then, asecond lithography stack 330 may be deposited over thedevice 300, as shown inFIG. 15 . Thesecond lithography stack 330 may include, for example, aSOH layer 332, aSiON layer 334, aBARC layer 336, and aphotoresist layer 338. Lithography and etching may then be performed to pattern thephotoresist layer 338 to form viaopenings 340. After the viaopenings 340 are formed, a full etch may be performed to open thetrench openings 326 and viaopenings 340, as shown inFIG. 16 . The viaopenings 340 may be, for example, etched down to theCu layer 308 of the at least onecontact 304. A wet etch clean may then be performed over thedevice 300, to remove any of the remaining metalhard mask layer 316, as shown inFIG. 17 . - A metal deposition process may then be performed to deposit at least one
metal layer 346 into thetrench openings 326 and viaopenings 340, as shown inFIG. 18 . The metal deposition process may be any suitable metal deposition process based known in the art. For example, the metal deposition process may include depositing a barrier layer (not shown) over thedevice 300 and into thetrench openings 326 and viaopenings 340. Next the metal deposition process may include depositing a seed layer (not shown) over the barrier layer (not shown). Finally, thetrench openings 326 and viaopenings 340 may be filled with a layer ofconductive contact material 346 based on a substantially “bottom-up” deposition process well known to those skilled in the art, such as, a suitably designed ECP process and the like, thereby reducing the likelihood of voids formed and/or trapped in thefinished trenches 348 and vias 350, as shown inFIG. 19 after CMP processing. - The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”), and “contain” (and any form contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of one or more aspects of the invention and the practical application, and to enable others of ordinary skill in the art to understand one or more aspects of the invention for various embodiments with various modifications as are suited to the particular use contemplated.
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US9659864B2 (en) | 2015-10-20 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer |
US11508617B2 (en) * | 2019-10-24 | 2022-11-22 | Applied Materials, Inc. | Method of forming interconnect for semiconductor device |
US11257677B2 (en) | 2020-01-24 | 2022-02-22 | Applied Materials, Inc. | Methods and devices for subtractive self-alignment |
CN111403342A (en) * | 2020-03-30 | 2020-07-10 | 上海华力集成电路制造有限公司 | Fin type field effect transistor and preparation method of connecting piece of fin type field effect transistor |
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