US20170121172A1 - Integrated mems-cmos devices and integrated circuits with mems devices and cmos devices - Google Patents
Integrated mems-cmos devices and integrated circuits with mems devices and cmos devices Download PDFInfo
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- US20170121172A1 US20170121172A1 US15/405,911 US201715405911A US2017121172A1 US 20170121172 A1 US20170121172 A1 US 20170121172A1 US 201715405911 A US201715405911 A US 201715405911A US 2017121172 A1 US2017121172 A1 US 2017121172A1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00253—Processes for integrating an electronic processing unit with a micromechanical structure not provided for in B81C1/0023 - B81C1/00246
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/007—Interconnections between the MEMS and external electrical signals
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/01—Switches
- B81B2201/012—Switches characterised by the shape
- B81B2201/016—Switches characterised by the shape having a bridge fixed on two ends and connected to one or more dimples
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0271—Resonators; ultrasonic resonators
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/01—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
- B81B2207/015—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being integrated on the same substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/07—Interconnects
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0128—Processes for removing material
- B81C2201/013—Etching
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
- B81C2201/019—Bonding or gluing multiple substrate layers
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/05—Temporary protection of devices or parts of the devices during manufacturing
- B81C2201/053—Depositing a protective layers
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
- B81C2203/0735—Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
- B81C2203/0757—Topology for facilitating the monolithic integration
- B81C2203/0771—Stacking the electronic processing unit and the micromechanical structure
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0785—Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
- B81C2203/0792—Forming interconnections between the electronic processing unit and the micromechanical structure
Definitions
- the technical field generally relates to Micro-Electro-Mechanical-Systems (MEMS) devices and complementary metal-oxide-semiconductor (CMOS) devices, and more particularly relates to integrated MEMS-CMOS devices and methods for fabricating such devices.
- MEMS Micro-Electro-Mechanical-Systems
- CMOS complementary metal-oxide-semiconductor
- CMOS technology has become the predominant fabrication technology for integrated circuits.
- MEMS technology continues to rely upon conventional processing.
- microelectronic integrated circuits are the “brains” of an integrated device which provides decision-making capabilities, whereas MEMS are the “eyes” and “arms” that provide the ability to sense and control the environment.
- Some examples of the widespread application of these technologies are the switches in radio frequency (RF) antenna systems, and accelerometers in sensor-equipped game devices.
- Monolithic integration of MEMS devices and CMOS devices offers significant benefits enabling high volume production driving down the per-unit costs of sensor and actuator systems significantly.
- Micromechanical transducer systems not only need to receive analog and digital electrical inputs and transmit the output, but should also be able to measure rotation, strain, temperature, pressure, acceleration, infrared radiation, or micro fluidic chemical properties of liquids and gasses.
- Effective integration offers other benefits, including, simplifying interconnect issues, reduced packaging and fabrication complexity and significantly improving the overall performance and ease of use for the device.
- CMOS complementary metal-oxide semiconductor
- MEMS complementary metal-oxide semiconductor
- An exemplary integrated MEMS-CMOS device is vertically integrated and includes a substrate having a first side and a second side opposite the first side. Further, the exemplary vertically integrated MEMS-CMOS device includes a CMOS device located in and/or over the first side of the substrate. Also, the exemplary vertically integrated MEMS-CMOS device includes a MEMS device located in and/or under the second side of the substrate.
- an integrated circuit in another exemplary embodiment, includes a semiconductor substrate having a first side and an opposite second side.
- the integrated circuit further includes an interconnect extending through the first side of a semiconductor substrate and a dielectric layer overlying the first side of the semiconductor substrate.
- the integrated circuit includes a CMOS device in or on the dielectric layer overlying the first side of the semiconductor substrate and a first conductive structure in the dielectric layer and in electrical contact with the interconnect.
- the integrated circuit includes a MEMS device under or on the second side of the semiconductor substrate and in electrical connection with the interconnect.
- a vertically integrated MEMS-CMOS device in yet another exemplary embodiment, includes a semiconductor substrate defining a center plane and an interconnect passing through the center plane of the semiconductor substrate.
- the vertically integrated MEMS-CMOS device includes a CMOS device over the semiconductor substrate and electrically connected to the interconnect.
- the vertically integrated MEMS-CMOS device includes a MEMS device under the semiconductor substrate. The center plane is located between the CMOS device and the MEMS device.
- the vertically integrated MEMS-CMOS device includes a conductive structure under the semiconductor substrate and electrically connected to the interconnect to electrically connect the CMOS device and the MEMS device via the interconnect extending through the semiconductor substrate.
- FIGS. 1-15 illustrate, in cross section, exemplary methods for fabricating a MEMS device and CMOS device:
- FIGS. 1-6 illustrate exemplary steps for the formation of a CMOS device over a side of a semiconductor substrate in accordance with an embodiment herein;
- FIGS. 7-12 illustrate exemplary steps for the formation of a MEMS device under an opposite side of the semiconductor substrate of FIGS. 1-6 , in accordance with an embodiment herein;
- FIGS. 13-15 illustrate exemplary steps for the formation of a MEMS device under an opposite side of the semiconductor substrate of FIGS. 1-6 , in accordance with another embodiment herein.
- the exemplary term “under” can encompass either an orientation of above or below.
- the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- a vertically-aligned integrated MEMS-CMOS device is fabricated by forming one or more CMOS devices in or over a side of a semiconductor substrate and by forming one or more MEMS devices in or under an opposite side of the semiconductor substrate.
- the distance between the CMOS device(s) and MEMS device(s) includes the thickness of the semiconductor substrate.
- the semiconductor substrate may be provided as high resistivity silicon, thereby further inhibiting cross talk between MEMS and CMOS devices.
- interlayer dielectric over a device is not necessary for sufficient resistivity.
- the integrated MEMS-CMOS device takes up less chip size as compared to conventional side-by-side structures.
- FIGS. 1-6 illustrate exemplary steps for the formation of a CMOS device over a side of a semiconductor substrate.
- FIGS. 7-12 illustrate exemplary steps for the formation of a MEMS device under an opposite side of the semiconductor substrate of FIGS. 1-6 .
- FIGS. 13-15 illustrate exemplary steps for the formation of a MEMS device under an opposite side of the semiconductor substrate of FIGS. 1-6 , in accordance with another embodiment.
- a semiconductor substrate 10 is provided and processed. It is to be appreciated that various fabrication techniques may be conducted in accordance with the methods described herein to form the semiconductor substrate 10 as shown.
- semiconductor substrate will be used to encompass semiconductor materials conventionally used in the semiconductor industry from which to make electrical devices.
- Semiconductor materials include monocrystalline silicon materials, such as the relatively pure or lightly impurity-doped monocrystalline silicon materials typically used in the semiconductor industry, as well as polycrystalline silicon materials, and silicon admixed with other elements such as germanium, carbon, and the like.
- semiconductor material encompasses other materials such as relatively pure and impurity-doped germanium, gallium arsenide, zinc oxide, glass, and the like.
- the semiconductor substrate 10 may include a compound semiconductor such as silicon carbide, silicon germanide, gallium arsenide, gallium nitride, indium arsenide, indium gallium arsenide, indium gallium arsenide phosphide, or indium phosphide and combinations thereof.
- the semiconductor material is a silicon substrate.
- a material that includes a recited element/compound includes the recited element/compound in an amount of at least 25 weight percent based on the total weight of the material unless otherwise indicated.
- An exemplary semiconductor substrate is formed by high resistivity silicon, such as silicon having resistivity greater than 40 ohm-cm.
- An exemplary semiconductor substrate 10 is a bulk silicon wafer.
- An exemplary semiconductor substrate has a thickness of from about 250 to about 1000 microns, such as from about 400 to about 600 microns.
- the semiconductor substrate 10 includes a planar surface at side 12 and a planar surface at an opposite side 14 . Further, the semiconductor substrate 10 defines a center plane 16 parallel to and equidistant from the sides 12 and 14 . In the context of FIG.
- side 12 may be considered to be an “upper” side and side 14 may be considered to be a “lower” side, such that side 12 is positioned “over” the center plane 16 and side 14 is positioned “under” the center plane 16 .
- the orientation of FIG. 1 will be used in naming spatial elements or relationships despite the rotation of the semiconductor substrate 10 in later Figures, as will be explained.
- a via formation process has commenced. Specifically, masking and etching has been performed similar to a conventional through silicon via (TSV) formation process.
- TSV through silicon via
- Through-silicon-vias can be formed utilizing a variety of different approaches, which are conventionally known and which may be performed at various junctures throughout fabrication processes.
- Useful approaches for forming TSVs include, but are not limited to, “Via First prior to Front-End-of-the-Line (FEOL),” “Via First after Back-End-of-the-Line (BEOL),” and “Via Last” approaches, all of which are well-documented in industry literature.
- the vias described herein can be formed utilizing any TSV formation technique, whether currently known or later developed.
- an illustrative fabrication method utilizing a “Via First prior to FEOL” approach includes etching blind vias 20 within semiconductor substrate 10 .
- Blind vias 20 extend through side 12 and toward side 14 of semiconductor substrate 10 , but do not penetrate through to side 14 of semiconductor substrate 10 .
- the blind vias 20 pass through the center plane 16 .
- blind vias 20 extend from about 50 to about 500 microns into semiconductor substrate 10 .
- Blind vias 20 can be formed utilizing a number of conventionally-known processes, including laser drilling and anisotropic etching processes.
- blind vias 20 are formed utilizing photolithography and etching processes capable of producing vias having relatively high aspect ratios.
- blind vias 20 may be formed utilizing a deep reactive ion etching process, such as a two mode Bosch process.
- a deep reactive ion etching process such as a two mode Bosch process.
- an anisotropic plasma etch is performed utilizing a chemistry selective to semiconductor substrate 10 ; e.g., when semiconductor substrate 10 includes silicon, a sulfur hexafluoride chemistry (SF 6 ) is conveniently employed.
- SF 6 sulfur hexafluoride chemistry
- SF 6 sulfur hexafluoride chemistry
- SF 6 sulfur hexafluoride chemistry
- SF 6 sulfur hexafluoride chemistry
- SF 6 sulfur hexafluoride chemistry
- SF 6 sulfur hexafluoride chemistry
- SF 6 sulfur hexafluoride chemistry
- blind vias 20 are utilized to electrically couple one or more frontside CMOS devices to one or more backside MEMS devices.
- multiple (e.g., two) blind vias 20 are formed within semiconductor substrate 10 .
- a liner 22 is formed on the side 12 of the semiconductor substrate 10 , including within the blind vias 20 .
- An exemplary liner 22 is formed by liner material, such as silicon oxide.
- the liner material is deposited with a linear oxide deposition process, such as by thermal oxidation or by chemical vapor deposition (CVD).
- An exemplary liner 22 is formed with a thickness of from about 1 to about 10 microns, such as from about 1 to about 3 microns.
- the method may continue with the deposition of a conductive material to form a conductive plug 24 within each blind via 20 .
- An exemplary conductive material is doped polysilicon.
- the conductive material is deposited by low pressure chemical vapor deposition (LPCVD).
- LPCVD low pressure chemical vapor deposition
- the conductive material is deposited to fill the blind vias 20 as well as form an overburden portion over the side 12 of the semiconductor substrate 10 .
- the overburden portion is removed by a chemical mechanical planarization (CMP) and clean process.
- CMP chemical mechanical planarization
- the liner material deposited outside of the blind vias 20 is removed by wet or dry etch.
- a polysilicon recess process may be performed, such as by wet or dry etch to lower the surface of the polysilicon within the blind vias 20 .
- the liner 22 and conductive plug 24 may be considered to form a conductive interconnect 26 .
- CMOS device fabrication processing continues in FIG. 2 with conventional CMOS device fabrication processing.
- one or more CMOS devices 30 are formed in and/or over the side 12 of the semiconductor substrate 10 in accordance with conventional processing.
- an interlayer dielectric 32 is formed over the side 12 of the semiconductor substrate 10 and encapsulates the CMOS devices 30 .
- the interlayer dielectric 32 is planarized to surface 36 , which is parallel to surface of side 12 .
- a trench 38 is etched over each interconnect 26 .
- a mask (not shown) is formed over the surface 36 of the interlayer dielectric 32 and is patterned before an etch process is performed to form the trenches 38 .
- the mask is formed by a plasma-enhanced chemical vapor deposition (PECVD) process that deposits a thick oxide over the interlayer dielectric 32 , i.e., oxide having a thickness of greater that about 10 microns.
- PECVD plasma-enhanced chemical vapor deposition
- a plasma etch process is performed to etch the unmasked regions of the interlayer dielectric 32 .
- the etch reaches the side 12 of the semiconductor substrate 10 and exposes each interconnect 26 .
- the mask is removed, such as by a wet clean process.
- a contact plug 40 is formed in each trench 38 .
- An exemplary contact plug 40 is formed from a metal material such as tungsten. In an exemplary embodiment, the material is deposited by CVD. The material fills the trench 38 and may form an overburden portion over the surface 36 of the interlayer dielectric 32 . A CMP process may be performed to remove the overburden portion of the material to form the contact plug 40 within each trench 38 .
- a conductive material is deposited over the contact plug 40 and the surface 36 of the interlayer dielectric 32 .
- An exemplary conductive material is copper, tungsten, or aluminum or alloys thereof.
- the conductive material may be deposited by physical vapor deposition (PVD).
- PVD physical vapor deposition
- the conductive material is then etched to form a conductive line 44 in electrical connection with each contact plug 40 .
- a lithography mask may be formed over the conductive material and patterned before an etch process to define the conductive lines 44 . The mask is then removed.
- a protective layer 50 is formed over the conductive lines 44 and interlayer dielectric 32 .
- the protective layer 50 may be a wafer, film, tape or other suitable material.
- the protective layer 50 includes a wafer 52 .
- An exemplary wafer 52 is silicon.
- the wafer 52 may be bonded to the conductive lines 44 and interlayer dielectric 32 through eutectic bonding, adhesive bonding, fusion bonding, or another suitable bonding technique.
- the protective layer 50 includes an intermediate layer 54 , such as gold, aluminum, an alloy thereof or another conventional eutectic alloy.
- the protective layer includes an intermediate layer 54 , such as an organic or inorganic adhesive.
- the intermediate layer 54 may be an epoxy or benzocyclobutene (BCB).
- BCB benzocyclobutene
- the intermediate layer 54 may be absent from the protective layer 50 . Rather, wafer 52 is forced into contact with the conductive lines 44 and interlayer dielectric 32 and may be anneal to form a bond between the protective layer 50 and the conductive lines 44 and interlayer dielectric 32 .
- the semiconductor substrate 10 is flipped or rotated 180 degrees such that the side 12 is at the bottom of the Figures.
- This flipped orientation is representative of the actual processing of the semiconductor substrate 10 .
- the CMOS device processing is completed on side 12 and the semiconductor substrate 10 is flipped so that processing of side 14 can be commenced to form MEMS devices.
- spatial references to the processing of side 14 will be made with the orientation of FIGS. 1-6 .
- arrow 56 points downward for the purposes of this description despite the actual orientation of the semiconductor substrate 10 during processing.
- a grinding process is performed to remove the portion of the semiconductor substrate 10 under each blind via 20 , i.e., between each blind via 20 and side 14 .
- the semiconductor substrate 10 is recessed to a recessed surface 58 at side 14 and each blind via 20 is exposed and formed as a through via 60 .
- Each through via 60 extends from side 12 to side 14 , as recessed.
- a trap-rich material may be formed on the recessed surface 58 .
- an argon implant process may be performed to convert the recessed surface 58 into a trap-rich material to increase the effective resistivity of the semiconductor substrate 10 .
- the MEMS device fabrication process deposits and etches a sacrificial material to form sacrificial layer 64 under the recessed surface 58 of side 14 .
- the sacrificial material may be oxide.
- the sacrificial material is deposited by CVD.
- a mask is formed and patterned under the sacrificial material before the sacrificial is etched to form the sacrificial layer 64 shown in FIG. 7 .
- the method continues in FIG. 8 with the formation of a first electrode 68 for the MEMS device.
- the first electrode 68 may be formed by depositing and etching an electrode material such as molybdenum under the sacrificial layer 64 .
- the electrode material is deposited by PVD.
- a hard mask, such as oxide, is formed and patterned under the electrode material before an etch process, such as a plasma etch, is performed to define the first electrode 68 .
- a thin film 72 is formed under the first electrode 68 and under the sacrificial layer 64 . As shown, different portions of the thin film 72 directly contact the first electrode 68 and the sacrificial layer 64 .
- the thin film 72 is formed from a thin film material that is piezoelectric.
- the thin film 72 may be formed from aluminum nitride (AlN) or another suitable piezoelectric material.
- the thin film 72 is formed by depositing the thin film material by PVD, formation and patterning of a mask under the thin film material, and etching of the thin film material to define the thin film 72 . The mask is then removed.
- the second electrode 76 may be formed by depositing and etching an electrode material such as molybdenum under the thin film 72 . As shown, the different portions of the second electrode 76 may contact the thin film 72 and the sacrificial layer 64 .
- the electrode material is deposited by PVD.
- a hard mask, such as oxide, is formed and patterned under the electrode material before an etch process, such as a plasma etch, is performed to define the second electrode 76 .
- a contact layer 80 is formed under the second electrode 76 , thin film 72 , first electrode 68 , and sacrificial layer 64 in FIG. 11 .
- An exemplary contact layer 80 formed from contact layer material such as oxide.
- An exemplary contact layer material is the same material that forms the sacrificial layer 64 .
- contact layer material is deposited by CVD.
- a mask is formed under the contact layer material and is patterned before the contact layer material is etched to form the contact layer 80 . The mask is then removed.
- the contact layer 80 exposes each interconnect 26 at the recessed surface 58 of side 14 of the semiconductor substrate 10 , as well as a selected region 82 of the first electrode 68 and a selected region 84 of the second electrode 76 .
- a conductive pad 90 is formed on each conductive region exposed by the contact layer 80 in FIG. 11 .
- a conductive material such as a metal like tungsten or copper, is deposited under the contact layer 80 , each exposed interconnect 26 , the exposed region 82 of the first electrode 68 , and the exposed region 84 of the second electrode 76 .
- a mask is formed and patterned under the conductive material and an etch is performed to define the conductive pads 90 . The mask is then removed.
- a release etch is performed to remove the sacrificial layer 64 (shown in FIG. 11 ) and the contact layer 80 (shown in FIG. 11 ).
- an etch may be performed with vapor hydrofluoric acid (VHF).
- VHF vapor hydrofluoric acid
- FIGS. 7-12 describe a surface machining process for forming the MEMS device.
- a surface machining process uses a succession of thin film deposition and selective etching.
- a bulk machining process may be used.
- FIGS. 13-15 illustrate a bulk machining process.
- a bulk micromachining process defines structures by selectively etching inside a substrate. Whereas surface micromachining creates structures on top of a substrate, bulk micromachining produces structures inside a substrate.
- a MEMS device layer 110 is bonded to the recessed surface 58 .
- the MEMS device layer 110 may include an intermediate layer 112 and a semiconductor layer 114 .
- An exemplary intermediate layer 112 is a conductive material such as gold, aluminum, an alloy thereof or another conventional alloy for eutectic bonding.
- An exemplary semiconductor layer 114 is silicon.
- a conductive layer 116 is formed under the semiconductor layer 114 .
- a metal such as copper, tungsten, or aluminum or alloys thereof may be deposited, such as by PVD.
- Masks may be sequentially formed and patterned to etch the metal to form the conductive layer 116 and to etch openings 120 through the semiconductor layer 114 .
- the intermediate layer exposed by the openings 120 may be removed by an etch process such as an etch with vapor hydrofluoric acid (VHF).
- VHF vapor hydrofluoric acid
- trenches 126 may be etched through the conductive layer 116 , the semiconductor layer 114 and intermediate layer 112 and filled with a conductive material to form conductive pads 128 .
- An exemplary conductive material is aluminum.
- the openings 120 are filled with a thin film 130 .
- a plasma enhanced chemical vapor deposition (PECVD) process may be performed to deposit a thin film material, such as for example silicon oxide or amorphous silicon.
- PECVD plasma enhanced chemical vapor deposition
- a MEMS device 96 is formed in the MEMS device layer 110 under side 14 of semiconductor substrate 10 .
- an exemplary MEMS device 96 is a radiofrequency (RF) MEMS device.
- the MEMS device 96 may be a switch, variable capacitor, surface acoustic wave (SAW) filter, bulk acoustic wave (BAW) filter, film bulk acoustic resonator (FBAR) filter, or other non-RF MEMS device such as a pressure sensor, optical device, microfluidic device, or other device as desired.
- SAW surface acoustic wave
- BAW bulk acoustic wave
- FBAR film bulk acoustic resonator
- the MEMS device 96 may be selectively electrically connected with the CMOS devices 30 formed over side 12 of the semiconductor substrate 10 . Specifically, each electrode 68 and 76 of the MEMS device 96 may be connected through selected conductive pads 90 or 128 , through interconnect 26 , through contact plug 40 , and through conductive lines 44 to CMOS devices 30 . As shown, the structure in each of FIGS. 12 and 15 forms an integrated MEMS-CMOS device 100 .
- the methods provide for fabrication of at least one CMOS device on one side of a semiconductor substrate and of at least one MEMS device on the opposite side of the semiconductor substrate.
- the CMOS device(s) and MEMS device(s) are vertically aligned.
- the distance between the CMOS device(s) and MEMS device(s) includes the thickness of the semiconductor substrate 10 , i.e., the distance between the surface of each side of the semiconductor substrate.
- the semiconductor substrate may be provided as high resistivity silicon, thereby further inhibiting cross talk between MEMS and CMOS devices.
- the integrated MEMS-CMOS device takes up less chip size as compared to conventional side-by-side structures.
Abstract
Description
- This application claims priority to U.S. patent application Ser. No. 14/826,449, filed Aug. 14, 2015, which is incorporated herein by reference in its entirety.
- The technical field generally relates to Micro-Electro-Mechanical-Systems (MEMS) devices and complementary metal-oxide-semiconductor (CMOS) devices, and more particularly relates to integrated MEMS-CMOS devices and methods for fabricating such devices.
- Research and development in integrated microelectronics have continued to produce astounding progress in CMOS and MEMS. CMOS technology has become the predominant fabrication technology for integrated circuits. MEMS technology continues to rely upon conventional processing. In layman's terms, microelectronic integrated circuits are the “brains” of an integrated device which provides decision-making capabilities, whereas MEMS are the “eyes” and “arms” that provide the ability to sense and control the environment. Some examples of the widespread application of these technologies are the switches in radio frequency (RF) antenna systems, and accelerometers in sensor-equipped game devices. These technologies are becoming ever more prevalent in society every day. Use of integrated circuits and MEMS has limitless applications through modular measurement devices such as accelerometers, gyroscopes, actuators, microphones, and sensors including magnetic field sensors, pressure sensors, humidity sensors, temperature sensors, chemical sensors, biosensors, and inertial sensors
- Monolithic integration of MEMS devices and CMOS devices offers significant benefits enabling high volume production driving down the per-unit costs of sensor and actuator systems significantly. Micromechanical transducer systems not only need to receive analog and digital electrical inputs and transmit the output, but should also be able to measure rotation, strain, temperature, pressure, acceleration, infrared radiation, or micro fluidic chemical properties of liquids and gasses. Effective integration offers other benefits, including, simplifying interconnect issues, reduced packaging and fabrication complexity and significantly improving the overall performance and ease of use for the device.
- One approach to the monolithic integration of CMOS and MEMS is to modify the complementary metal-oxide semiconductor (CMOS) foundry facility to fabricate micromechanical structures. In such an approach, CMOS devices and MEMS devices may be fabricated side-by-side on a semiconductor substrate. A disadvantage of this arrangement is cross talk caused by the MEMS devices and CMOS devices. Shielding has been proposed to reduce cross talk; however, use of shielding increases processing costs as well as the chip space required by the devices.
- Accordingly, it is desirable to provide a method for fabricating an improved integrated MEMS-CMOS device. Further, it is desirable to provide an improved integrated MEMS-CMOS device. Also, it is desirable to provide an improved method for fabricating MEMS devices and CMOS devices on a substrate. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.
- Integrated MEMS-CMOS devices and integrated circuits with MEMS devices and CMOS devices are provided. An exemplary integrated MEMS-CMOS device is vertically integrated and includes a substrate having a first side and a second side opposite the first side. Further, the exemplary vertically integrated MEMS-CMOS device includes a CMOS device located in and/or over the first side of the substrate. Also, the exemplary vertically integrated MEMS-CMOS device includes a MEMS device located in and/or under the second side of the substrate.
- In another exemplary embodiment, an integrated circuit includes a semiconductor substrate having a first side and an opposite second side. The integrated circuit further includes an interconnect extending through the first side of a semiconductor substrate and a dielectric layer overlying the first side of the semiconductor substrate. Also, the integrated circuit includes a CMOS device in or on the dielectric layer overlying the first side of the semiconductor substrate and a first conductive structure in the dielectric layer and in electrical contact with the interconnect. Further, the integrated circuit includes a MEMS device under or on the second side of the semiconductor substrate and in electrical connection with the interconnect.
- In yet another exemplary embodiment, a vertically integrated MEMS-CMOS device includes a semiconductor substrate defining a center plane and an interconnect passing through the center plane of the semiconductor substrate. The vertically integrated MEMS-CMOS device includes a CMOS device over the semiconductor substrate and electrically connected to the interconnect. Also, the vertically integrated MEMS-CMOS device includes a MEMS device under the semiconductor substrate. The center plane is located between the CMOS device and the MEMS device. Further, the vertically integrated MEMS-CMOS device includes a conductive structure under the semiconductor substrate and electrically connected to the interconnect to electrically connect the CMOS device and the MEMS device via the interconnect extending through the semiconductor substrate.
- This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
- The various embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
-
FIGS. 1-15 illustrate, in cross section, exemplary methods for fabricating a MEMS device and CMOS device: -
FIGS. 1-6 illustrate exemplary steps for the formation of a CMOS device over a side of a semiconductor substrate in accordance with an embodiment herein; -
FIGS. 7-12 illustrate exemplary steps for the formation of a MEMS device under an opposite side of the semiconductor substrate ofFIGS. 1-6 , in accordance with an embodiment herein; -
FIGS. 13-15 illustrate exemplary steps for the formation of a MEMS device under an opposite side of the semiconductor substrate ofFIGS. 1-6 , in accordance with another embodiment herein. - The following detailed description is merely exemplary in nature and is not intended to limit the integrated MEMS-CMOS devices, methods for fabricating integrated MEMS-CMOS devices, or methods for fabricating MEMS devices and CMOS devices. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background or brief summary, or in the following detailed description.
- For the sake of brevity, conventional techniques related to conventional device fabrication may not be described in detail herein. Moreover, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the fabrication of MEMS and CMOS devices are well-known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. Further, it is noted that integrated circuits include a varying number of components and that single components shown in the illustrations may be representative of multiple components.
- As used herein, it will be understood that when an element or layer is referred to as being “over” or “under” another element or layer, it may be directly on the other element or layer, or intervening elements or layers may be present. When an element or layer is referred to as being “on” another element or layer, it is directly on and in contact with the other element or layer. Further, spatially relative terms, such as “upper”, “over”, “lower”, “under” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being “under” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “under” can encompass either an orientation of above or below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- As described herein, a vertically-aligned integrated MEMS-CMOS device is fabricated by forming one or more CMOS devices in or over a side of a semiconductor substrate and by forming one or more MEMS devices in or under an opposite side of the semiconductor substrate. The distance between the CMOS device(s) and MEMS device(s) includes the thickness of the semiconductor substrate. Also, the semiconductor substrate may be provided as high resistivity silicon, thereby further inhibiting cross talk between MEMS and CMOS devices. As a result, interlayer dielectric over a device is not necessary for sufficient resistivity. Also, due to the vertical alignment of the CMOS device(s) and MEMS device(s), the integrated MEMS-CMOS device takes up less chip size as compared to conventional side-by-side structures.
-
FIGS. 1-6 illustrate exemplary steps for the formation of a CMOS device over a side of a semiconductor substrate.FIGS. 7-12 illustrate exemplary steps for the formation of a MEMS device under an opposite side of the semiconductor substrate ofFIGS. 1-6 .FIGS. 13-15 illustrate exemplary steps for the formation of a MEMS device under an opposite side of the semiconductor substrate ofFIGS. 1-6 , in accordance with another embodiment. - In
FIG. 1 , asemiconductor substrate 10 is provided and processed. It is to be appreciated that various fabrication techniques may be conducted in accordance with the methods described herein to form thesemiconductor substrate 10 as shown. Herein, the term “semiconductor substrate” will be used to encompass semiconductor materials conventionally used in the semiconductor industry from which to make electrical devices. Semiconductor materials include monocrystalline silicon materials, such as the relatively pure or lightly impurity-doped monocrystalline silicon materials typically used in the semiconductor industry, as well as polycrystalline silicon materials, and silicon admixed with other elements such as germanium, carbon, and the like. In addition, “semiconductor material” encompasses other materials such as relatively pure and impurity-doped germanium, gallium arsenide, zinc oxide, glass, and the like. Thesemiconductor substrate 10 may include a compound semiconductor such as silicon carbide, silicon germanide, gallium arsenide, gallium nitride, indium arsenide, indium gallium arsenide, indium gallium arsenide phosphide, or indium phosphide and combinations thereof. In an exemplary embodiment, the semiconductor material is a silicon substrate. As referred to herein, a material that includes a recited element/compound includes the recited element/compound in an amount of at least 25 weight percent based on the total weight of the material unless otherwise indicated. - An exemplary semiconductor substrate is formed by high resistivity silicon, such as silicon having resistivity greater than 40 ohm-cm. An
exemplary semiconductor substrate 10 is a bulk silicon wafer. An exemplary semiconductor substrate has a thickness of from about 250 to about 1000 microns, such as from about 400 to about 600 microns. As shown thesemiconductor substrate 10 includes a planar surface atside 12 and a planar surface at anopposite side 14. Further, thesemiconductor substrate 10 defines a center plane 16 parallel to and equidistant from thesides FIG. 1 ,side 12 may be considered to be an “upper” side andside 14 may be considered to be a “lower” side, such thatside 12 is positioned “over” the center plane 16 andside 14 is positioned “under” the center plane 16. The orientation ofFIG. 1 will be used in naming spatial elements or relationships despite the rotation of thesemiconductor substrate 10 in later Figures, as will be explained. - In
FIG. 1 , a via formation process has commenced. Specifically, masking and etching has been performed similar to a conventional through silicon via (TSV) formation process. Through-silicon-vias can be formed utilizing a variety of different approaches, which are conventionally known and which may be performed at various junctures throughout fabrication processes. Useful approaches for forming TSVs include, but are not limited to, “Via First prior to Front-End-of-the-Line (FEOL),” “Via First after Back-End-of-the-Line (BEOL),” and “Via Last” approaches, all of which are well-documented in industry literature. The vias described herein can be formed utilizing any TSV formation technique, whether currently known or later developed. To provide one non-limiting example, an illustrative fabrication method utilizing a “Via First prior to FEOL” approach includes etchingblind vias 20 withinsemiconductor substrate 10.Blind vias 20 extend throughside 12 and towardside 14 ofsemiconductor substrate 10, but do not penetrate through toside 14 ofsemiconductor substrate 10. In the illustrated embodiment, theblind vias 20 pass through the center plane 16. In one embodiment,blind vias 20 extend from about 50 to about 500 microns intosemiconductor substrate 10.Blind vias 20 can be formed utilizing a number of conventionally-known processes, including laser drilling and anisotropic etching processes. In an exemplary embodiment,blind vias 20 are formed utilizing photolithography and etching processes capable of producing vias having relatively high aspect ratios. As a specific example,blind vias 20 may be formed utilizing a deep reactive ion etching process, such as a two mode Bosch process. In the first mode of the Bosch process, an anisotropic plasma etch is performed utilizing a chemistry selective tosemiconductor substrate 10; e.g., whensemiconductor substrate 10 includes silicon, a sulfur hexafluoride chemistry (SF6) is conveniently employed. In the second mode of the Bosch process, a chemically inert passivation layer is deposited oversemiconductor substrate 10 utilizing, for example, an octafluorobutene (C4F8) source gas. By continually alternating between the first mode and the second mode of the Bosch process, vias having nearly vertical sidewalls and relatively high aspect ratios (such as, for example, approximately 28:1 or up to about 50:1) can be formed insemiconductor substrate 10. - As will become apparent in the course of the subsequent description, the location at which blind vias 20 are formed within
semiconductor substrate 10 will generally be determined by MEMS device and CMOS device layout; i.e., the locations at which electrical interconnections will ultimately be formed over and under thesemiconductor substrate 10. As noted above, and as will be described more fully below,blind vias 20 are utilized to electrically couple one or more frontside CMOS devices to one or more backside MEMS devices. In the illustrated example, multiple (e.g., two)blind vias 20 are formed withinsemiconductor substrate 10. - After the formation of
blind vias 20, aliner 22 is formed on theside 12 of thesemiconductor substrate 10, including within theblind vias 20. Anexemplary liner 22 is formed by liner material, such as silicon oxide. In an exemplary embodiment, the liner material is deposited with a linear oxide deposition process, such as by thermal oxidation or by chemical vapor deposition (CVD). Anexemplary liner 22 is formed with a thickness of from about 1 to about 10 microns, such as from about 1 to about 3 microns. - After formation of the
liner 22, the method may continue with the deposition of a conductive material to form aconductive plug 24 within each blind via 20. An exemplary conductive material is doped polysilicon. In an exemplary embodiment, the conductive material is deposited by low pressure chemical vapor deposition (LPCVD). The conductive material is deposited to fill theblind vias 20 as well as form an overburden portion over theside 12 of thesemiconductor substrate 10. InFIG. 1 , the overburden portion is removed by a chemical mechanical planarization (CMP) and clean process. Further, the liner material deposited outside of theblind vias 20 is removed by wet or dry etch. Additionally, a polysilicon recess process may be performed, such as by wet or dry etch to lower the surface of the polysilicon within theblind vias 20. Theliner 22 andconductive plug 24 may be considered to form aconductive interconnect 26. - The method continues in
FIG. 2 with conventional CMOS device fabrication processing. Specifically, one ormore CMOS devices 30 are formed in and/or over theside 12 of thesemiconductor substrate 10 in accordance with conventional processing. As shown, aninterlayer dielectric 32, or a plurality of dielectric layers, is formed over theside 12 of thesemiconductor substrate 10 and encapsulates theCMOS devices 30. In an exemplary embodiment, theinterlayer dielectric 32 is planarized to surface 36, which is parallel to surface ofside 12. - In
FIG. 3 , atrench 38 is etched over eachinterconnect 26. Specifically, a mask (not shown) is formed over thesurface 36 of theinterlayer dielectric 32 and is patterned before an etch process is performed to form thetrenches 38. In an exemplary embodiment, the mask is formed by a plasma-enhanced chemical vapor deposition (PECVD) process that deposits a thick oxide over theinterlayer dielectric 32, i.e., oxide having a thickness of greater that about 10 microns. Then, a plasma etch process is performed to etch the unmasked regions of theinterlayer dielectric 32. The etch reaches theside 12 of thesemiconductor substrate 10 and exposes eachinterconnect 26. After performing the etch, the mask is removed, such as by a wet clean process. - As shown in
FIG. 4 , acontact plug 40 is formed in eachtrench 38. Anexemplary contact plug 40 is formed from a metal material such as tungsten. In an exemplary embodiment, the material is deposited by CVD. The material fills thetrench 38 and may form an overburden portion over thesurface 36 of theinterlayer dielectric 32. A CMP process may be performed to remove the overburden portion of the material to form thecontact plug 40 within eachtrench 38. - In
FIG. 5 , a conductive material is deposited over thecontact plug 40 and thesurface 36 of theinterlayer dielectric 32. An exemplary conductive material is copper, tungsten, or aluminum or alloys thereof. The conductive material may be deposited by physical vapor deposition (PVD). The conductive material is then etched to form aconductive line 44 in electrical connection with eachcontact plug 40. For example, a lithography mask may be formed over the conductive material and patterned before an etch process to define theconductive lines 44. The mask is then removed. - As shown in
FIG. 6 , aprotective layer 50 is formed over theconductive lines 44 andinterlayer dielectric 32. Theprotective layer 50 may be a wafer, film, tape or other suitable material. In an exemplary embodiment, theprotective layer 50 includes awafer 52. Anexemplary wafer 52 is silicon. Thewafer 52 may be bonded to theconductive lines 44 andinterlayer dielectric 32 through eutectic bonding, adhesive bonding, fusion bonding, or another suitable bonding technique. For eutectic bonding, theprotective layer 50 includes anintermediate layer 54, such as gold, aluminum, an alloy thereof or another conventional eutectic alloy. For adhesive bonding, the protective layer includes anintermediate layer 54, such as an organic or inorganic adhesive. For example, theintermediate layer 54 may be an epoxy or benzocyclobutene (BCB). For fusion bonding, theintermediate layer 54 may be absent from theprotective layer 50. Rather,wafer 52 is forced into contact with theconductive lines 44 andinterlayer dielectric 32 and may be anneal to form a bond between theprotective layer 50 and theconductive lines 44 andinterlayer dielectric 32. - In
FIGS. 7-12 , thesemiconductor substrate 10 is flipped or rotated 180 degrees such that theside 12 is at the bottom of the Figures. This flipped orientation is representative of the actual processing of thesemiconductor substrate 10. In other words, the CMOS device processing is completed onside 12 and thesemiconductor substrate 10 is flipped so that processing ofside 14 can be commenced to form MEMS devices. However, spatial references to the processing ofside 14 will be made with the orientation ofFIGS. 1-6 . For clarity,arrow 56 points downward for the purposes of this description despite the actual orientation of thesemiconductor substrate 10 during processing. - In
FIG. 7 a grinding process is performed to remove the portion of thesemiconductor substrate 10 under each blind via 20, i.e., between each blind via 20 andside 14. As a result, thesemiconductor substrate 10 is recessed to a recessedsurface 58 atside 14 and each blind via 20 is exposed and formed as a through via 60. Each through via 60 extends fromside 12 toside 14, as recessed. - After establishing the through
vias 60, a trap-rich material may be formed on the recessedsurface 58. For example, an argon implant process may be performed to convert the recessedsurface 58 into a trap-rich material to increase the effective resistivity of thesemiconductor substrate 10. Then, the MEMS device fabrication process deposits and etches a sacrificial material to formsacrificial layer 64 under the recessedsurface 58 ofside 14. For example, the sacrificial material may be oxide. In an exemplary embodiment, the sacrificial material is deposited by CVD. Then a mask is formed and patterned under the sacrificial material before the sacrificial is etched to form thesacrificial layer 64 shown inFIG. 7 . - The method continues in
FIG. 8 with the formation of afirst electrode 68 for the MEMS device. Specifically, thefirst electrode 68 may be formed by depositing and etching an electrode material such as molybdenum under thesacrificial layer 64. In an exemplary embodiment, the electrode material is deposited by PVD. A hard mask, such as oxide, is formed and patterned under the electrode material before an etch process, such as a plasma etch, is performed to define thefirst electrode 68. - In
FIG. 9 , athin film 72 is formed under thefirst electrode 68 and under thesacrificial layer 64. As shown, different portions of thethin film 72 directly contact thefirst electrode 68 and thesacrificial layer 64. In an exemplary embodiment, thethin film 72 is formed from a thin film material that is piezoelectric. For example, thethin film 72 may be formed from aluminum nitride (AlN) or another suitable piezoelectric material. In an exemplary embodiment, thethin film 72 is formed by depositing the thin film material by PVD, formation and patterning of a mask under the thin film material, and etching of the thin film material to define thethin film 72. The mask is then removed. - The method continues in
FIG. 10 with the formation of asecond electrode 76 for the MEMS device. Specifically, thesecond electrode 76 may be formed by depositing and etching an electrode material such as molybdenum under thethin film 72. As shown, the different portions of thesecond electrode 76 may contact thethin film 72 and thesacrificial layer 64. In an exemplary embodiment, the electrode material is deposited by PVD. A hard mask, such as oxide, is formed and patterned under the electrode material before an etch process, such as a plasma etch, is performed to define thesecond electrode 76. - A contact layer 80 is formed under the
second electrode 76,thin film 72,first electrode 68, andsacrificial layer 64 inFIG. 11 . An exemplary contact layer 80 formed from contact layer material such as oxide. An exemplary contact layer material is the same material that forms thesacrificial layer 64. In an exemplary embodiment, contact layer material is deposited by CVD. A mask is formed under the contact layer material and is patterned before the contact layer material is etched to form the contact layer 80. The mask is then removed. The contact layer 80 exposes eachinterconnect 26 at the recessedsurface 58 ofside 14 of thesemiconductor substrate 10, as well as a selectedregion 82 of thefirst electrode 68 and a selectedregion 84 of thesecond electrode 76. - In
FIG. 12 , aconductive pad 90 is formed on each conductive region exposed by the contact layer 80 inFIG. 11 . Specifically, a conductive material such as a metal like tungsten or copper, is deposited under the contact layer 80, each exposedinterconnect 26, the exposedregion 82 of thefirst electrode 68, and the exposedregion 84 of thesecond electrode 76. After deposition of the conductive material, a mask is formed and patterned under the conductive material and an etch is performed to define theconductive pads 90. The mask is then removed. - Further, in
FIG. 12 , a release etch is performed to remove the sacrificial layer 64 (shown inFIG. 11 ) and the contact layer 80 (shown inFIG. 11 ). For example, for embodiments in which the sacrificial layer material and the contact layer material are oxide, an etch may be performed with vapor hydrofluoric acid (VHF). As a result, aMEMS device 96 is formed underside 14 of thesemiconductor substrate 10. - It is noted that
FIGS. 7-12 describe a surface machining process for forming the MEMS device. A surface machining process uses a succession of thin film deposition and selective etching. Alternatively, a bulk machining process may be used. For example,FIGS. 13-15 illustrate a bulk machining process. A bulk micromachining process defines structures by selectively etching inside a substrate. Whereas surface micromachining creates structures on top of a substrate, bulk micromachining produces structures inside a substrate. - In
FIG. 13 , the structure ofFIG. 6 is flipped andside 14 is recessed to surface 58, similar to the process ofFIG. 7 . Again,arrow 56 is considered to point downward for the purposes of this description despite the actual orientation of thesemiconductor substrate 10 during processing. InFIG. 13 , aMEMS device layer 110 is bonded to the recessedsurface 58. For example, theMEMS device layer 110 may include anintermediate layer 112 and asemiconductor layer 114. An exemplaryintermediate layer 112 is a conductive material such as gold, aluminum, an alloy thereof or another conventional alloy for eutectic bonding. Anexemplary semiconductor layer 114 is silicon. - In
FIG. 14 , aconductive layer 116 is formed under thesemiconductor layer 114. For example, a metal such as copper, tungsten, or aluminum or alloys thereof may be deposited, such as by PVD. Masks may be sequentially formed and patterned to etch the metal to form theconductive layer 116 and to etchopenings 120 through thesemiconductor layer 114. Then, the intermediate layer exposed by theopenings 120 may be removed by an etch process such as an etch with vapor hydrofluoric acid (VHF). Then,trenches 126 may be etched through theconductive layer 116, thesemiconductor layer 114 andintermediate layer 112 and filled with a conductive material to formconductive pads 128. An exemplary conductive material is aluminum. - In
FIG. 15 , theopenings 120 are filled with athin film 130. For example, a plasma enhanced chemical vapor deposition (PECVD) process may be performed to deposit a thin film material, such as for example silicon oxide or amorphous silicon. As a result, aMEMS device 96 is formed in theMEMS device layer 110 underside 14 ofsemiconductor substrate 10. - Cross-referencing
FIGS. 12 and 15 , it is noted that anexemplary MEMS device 96 is a radiofrequency (RF) MEMS device. TheMEMS device 96 may be a switch, variable capacitor, surface acoustic wave (SAW) filter, bulk acoustic wave (BAW) filter, film bulk acoustic resonator (FBAR) filter, or other non-RF MEMS device such as a pressure sensor, optical device, microfluidic device, or other device as desired. - Further, the
MEMS device 96 may be selectively electrically connected with theCMOS devices 30 formed overside 12 of thesemiconductor substrate 10. Specifically, eachelectrode MEMS device 96 may be connected through selectedconductive pads interconnect 26, throughcontact plug 40, and throughconductive lines 44 toCMOS devices 30. As shown, the structure in each ofFIGS. 12 and 15 forms an integrated MEMS-CMOS device 100. - As described in
FIGS. 1-12 and 13-15 , the methods provide for fabrication of at least one CMOS device on one side of a semiconductor substrate and of at least one MEMS device on the opposite side of the semiconductor substrate. Thus, the CMOS device(s) and MEMS device(s) are vertically aligned. The distance between the CMOS device(s) and MEMS device(s) includes the thickness of thesemiconductor substrate 10, i.e., the distance between the surface of each side of the semiconductor substrate. Further, the semiconductor substrate may be provided as high resistivity silicon, thereby further inhibiting cross talk between MEMS and CMOS devices. Also, due to the vertical alignment of the CMOS device(s) and MEMS device(s), the integrated MEMS-CMOS device takes up less chip size as compared to conventional side-by-side structures. - While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration as claimed in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the exemplary embodiment or exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope herein as set forth in the appended claims and the legal equivalents thereof
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