US20170110641A1 - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereof Download PDFInfo
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- US20170110641A1 US20170110641A1 US15/394,464 US201615394464A US2017110641A1 US 20170110641 A1 US20170110641 A1 US 20170110641A1 US 201615394464 A US201615394464 A US 201615394464A US 2017110641 A1 US2017110641 A1 US 2017110641A1
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- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000002955 isolation Methods 0.000 claims description 41
- 238000000059 patterning Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 45
- 238000000034 method Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 230000003247 decreasing effect Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
- H10N10/80—Constructional details
- H10N10/81—Structural details of the junction
- H10N10/817—Structural details of the junction the junction being non-separable, e.g. being cemented, sintered or soldered
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J5/02—Constructional details
- G01J5/0225—Shape of the cavity itself or of elements contained in or suspended over the cavity
- G01J5/024—Special manufacturing steps or sacrificial layers or layer structures
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- G—PHYSICS
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- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J5/02—Constructional details
- G01J5/04—Casings
- G01J5/041—Mountings in enclosures or in a particular environment
- G01J5/045—Sealings; Vacuum enclosures; Encapsulated packages; Wafer bonding structures; Getter arrangements
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
- G01J5/20—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L31/1876—Particular processes or apparatus for batch treatment of the devices
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
- H10N10/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
- H10N10/80—Constructional details
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
- H10N10/80—Constructional details
- H10N10/82—Connection of interconnections
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
Definitions
- the present invention relates to a semiconductor package and a manufacturing method of the semiconductor package. More particularly, the present invention relates to a semiconductor package having a detecting function and a manufacturing method of the semiconductor package.
- MEMS micro-electro mechanical systems
- FIG. 1 A detecting type semiconductor package 1 is shown in FIG. 1 .
- the semiconductor package 1 has a chip 10 and a glass sheet 12 that is stacked on the chip 10 .
- the chip 10 has an operating surface 10 a and a non-operating surface 10 b.
- the operating surface 10 a has a light sensor 100 , and the glass sheet 12 is disposed on the operating surface 10 a by a dam layer 11 , such that a space P is formed between the glass sheet 12 and the light sensor 100 .
- the volume of the chip 10 is large, so that noise is more apt to occur.
- the use of the semiconductor package 1 is limited, and the semiconductor package 1 is difficult to be matched with the requirement of multiple functions, thereby reducing product competitiveness.
- An aspect of the present invention is to provide a semiconductor package.
- a semiconductor package includes a substrate, at least one support, a cover, and a plate.
- the substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface.
- the light sensor or the thermal sensor is disposed on the first surface.
- the second surface of the substrate has an opening to expose the light sensor or the thermal sensor.
- the support is disposed on the first surface of the substrate.
- the cover is disposed on the support, such that the cover is above the light sensor or the thermal sensor, and a first space is formed between the cover and the light sensor or between the cover and the thermal sensor.
- the plate is placed on the second surface of the substrate to cover the opening, such that a second space is formed between the plate and the light sensor or between the plate and the thermal sensor.
- An aspect of the present invention is to provide a manufacturing method of a semiconductor package.
- a manufacturing method of a semiconductor package includes the following steps.
- a wafer that has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface is provided, and the light sensor or the thermal sensor is disposed on the first surface.
- a cover is disposed on the first surface of the wafer by at least one support, such that the cover is above the light sensor or the thermal sensor, and a first space is formed between the cover and the light sensor or between the cover and the thermal sensor.
- An opening is formed in the second surface of the wafer to expose the light sensor or the thermal sensor.
- a plate is placed on the second surface of the substrate to cover the opening, such that a second space is formed between the plate and the light sensor or between the plate and the thermal sensor.
- the second space may be formed between the plate and the light sensor or between the plate and the thermal sensor.
- the volume of the substrate of the semiconductor package may be reduced, so that signal noise can be decreased, and the detecting capability of the light sensor or the thermal sensor (e.g., infrared ray detecting capability) is improved. Therefore, the use of the semiconductor package of the present invention is expanded and the purpose of multiple functions is achieved, thereby improving product competitiveness.
- An aspect of the present invention is to provide a semiconductor package.
- a semiconductor package includes a substrate, at least one support, a cover, an isolation layer, and a redistribution layer.
- the substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface.
- the first surface has a recess and an electrical connecting pad.
- the light sensor or the thermal sensor is disposed on the first surface and covers the recess.
- the support is disposed on the first surface of the substrate.
- the cover is located on the support, such that a space is formed between the cover and the light sensor or between the cover and the thermal sensor.
- the isolation layer is located on the second surface of the substrate.
- the redistribution layer is located on the isolation layer and electrically connected to the electrical connecting pad.
- An aspect of the present invention is to provide a manufacturing method of a semiconductor package.
- a manufacturing method of a semiconductor package includes the following steps.
- a wafer that has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface is provided, and the light sensor or the thermal sensor is disposed on the first surface and covers a recess of the first surface.
- a cover is disposed on the first surface of the wafer by at least one support, such that the cover is above the light sensor or the thermal sensor, and a space is formed between the cover and the light sensor or between the cover and the thermal sensor.
- a through hole is formed in the second surface of the wafer to expose the support and an electrical connecting pad of the wafer.
- An isolation layer is formed on the second surface of the wafer and a wall surface that surrounds the through hole.
- a redistribution layer is formed on the isolation layer, and the redistribution layer is electrically connected to the electrical connecting pad.
- the volume of the substrate of the semiconductor package may be reduced.
- signal noise can be decreased, and the detecting capability of the light sensor or the thermal sensor (e.g., infrared ray detecting capability) is improved. Therefore, the use of the semiconductor package of the present invention is expanded and the purpose of multiple functions is achieved, thereby improving product competitiveness.
- FIG. 1 is a cross-sectional view of a conventional semiconductor package
- FIGS. 2A to 2J are cross-sectional views of a manufacturing method of a semiconductor package according to one embodiment of the present invention.
- FIGS. 3A to 3E are cross-sectional views of a manufacturing method of a semiconductor package according to one embodiment of the present invention.
- FIGS. 4A to 4D are cross-sectional views of a manufacturing method of a semiconductor package according to one embodiment of the present invention.
- a semiconductor package after being stacked, packaged, and diced may be used in various micro electro mechanical systems (MEMS), such as an image sensor capable of detecting through an electrical variation or a capacitive variation, and a detecting-type semiconductor package manufactured in wafer scale package process (WSP) and having image sensors, RF circuits, accelerators, gyroscopes, micro actuators, or pressure sensors.
- MEMS micro electro mechanical systems
- WSP wafer scale package process
- FIGS. 2A to 2J are cross-sectional views of a manufacturing method of a semiconductor package 2 (see FIG. 2J ) according to one embodiment of the present invention.
- a wafer 20 having at least one light sensor or thermal sensor 200 , a first surface 20 a, and a second surface 20 b opposite to the first surface 20 a is provided.
- the light sensor or the thermal sensor 200 is disposed on the first surface 20 a.
- the light sensor or the thermal sensor 200 may be located on first surface 20 a or in the first surface 20 a, the light sensor or the thermal sensor 200 may protrude from the first surface 20 a , the light sensor or the thermal sensor 200 and the first surface 20 a may be at the same level, the light sensor or the thermal sensor 200 may be recessed in the light sensor or the thermal sensor 200 , and the present invention is not limited in this regard.
- the first surface 20 a of the wafer 20 has a plurality of electrical connecting pads 201 .
- the size of the wafer 20 may be 6 inches, 8 inches, 12 inches, etc., and the present invention is not limited in this regard.
- the light sensor or the thermal sensor 200 may be used to detect an infrared ray (IR), but the present invention is not limited thereto.
- At least one support 21 is formed on the first surface 20 a of the wafer 20 .
- the support 21 is a dam layer and located on a portion of a surface of the electrical connecting pad 201 .
- a cover 22 is disposed on the support 21 , such that the cover 22 is above the light sensor or the thermal sensor 200 , and a first space P 1 is formed between the cover 22 and the light sensor 200 or between the cover 22 and the thermal sensor 200 .
- the cover 22 is made of silicon or quartz, and the thickness t of the cover 22 may be 300 ⁇ m, but the thinner, the better.
- An infrared ray may pass through the cover 22 , such that the light sensor or the thermal sensor 200 may detect the infrared ray, but the present invention is not limited to the infrared ray.
- the first space P 1 is in a vacuum state, and the height h of the first space P 1 may be in a range form 30 ⁇ m to 50 ⁇ m, such as 40 ⁇ m.
- the cover 22 is made of light impermeable material (e.g., silicon or quartz). Therefore, an optical alignment process may not be used.
- the support 21 is disposed on the first surface 20 a of the wafer 20 , and thereafter the cover 22 is used to cover the wafer 20 , such that the alignment problem of the cover 22 (or the support 21 ) is prevented.
- the support 21 when the cover 22 is made of light permeable material (e.g., glass), the support 21 may be disposed on cover 22 , and next the support 21 and the cover 22 may be disposed on the first surface 20 a of the wafer 20 by an alignment method, such as optical alignment by utilizing the light transmittance of glass.
- an alignment method such as optical alignment by utilizing the light transmittance of glass.
- the thickness of the wafer 20 is reduced from the second surface 20 b, and a through hole 202 is formed in the second surface 20 b of the wafer 20 to expose the support 21 and the electrical connecting pad 201 .
- the thickness d of the wafer 20 may be in a range from 100 ⁇ m to 400 ⁇ m.
- an isolation layer 23 is formed on the second surface 20 b of the wafer 20 , and through hole 202 is filled with the isolation layer 23 . Thereafter, an opening region 230 that is aligned with the light sensor or the thermal sensor 200 on the isolation layer 23 is formed, such that a portion of the second surface 20 b of the wafer 20 is exposed through the opening region 230 .
- an opening 203 is formed in the second surface 20 b of the wafer 20 in the opening region 230 to expose the light sensor or the thermal sensor 200 .
- the opening 203 is formed by and etching process.
- a plate 24 is placed on the second surface 20 b of the wafer 20 to cover the opening 203 , such that a second space P 2 is formed between the plate 24 and the light sensor 200 or between the plate 24 and the thermal sensor 200 .
- the plate 24 may support the wafer 20 to enhance structure strength.
- the plate 24 may be made of silicon or glass, and the plate 24 is disposed on the isolation layer 23 and the through hole 202 . Moreover, the thickness r of the plate 24 may be in a range from 100 ⁇ m to 300 ⁇ m, such as 200 ⁇ m.
- the second space P 2 is in a vacuum state.
- an via hole 240 communicated with the through hole 202 is formed in the plate 24 , and the isolation layer 23 and the support 21 are removed from the through hole 202 , such that the support 21 and a side surface of the electrical connecting pad 201 .
- a redistribution layer 25 is formed on the plate 24 , the sidewall of the via hole 240 , and the sidewall of the through hole 202 , such that the redistribution layer 25 is electrically connected to the electrical connecting pad 201 .
- the redistribution layer 25 includes a dielectric layer 250 and a conductive layer 251 that is formed on the dielectric layer 250 .
- the dielectric layer 250 is formed on the plate 24 , the sidewall of the via hole 240 , and the sidewall of the through hole 202 .
- a protection layer 26 is formed on the plate 24 and the redistribution layer 25 , and an opening hole 260 is formed in the protection layer 26 , such that a portion of a surface of the redistribution layer 251 on the plate 24 is exposed through the opening hole 260 .
- the protection layer 26 may be made of solder mask material.
- a conductive protrusion 27 may be a solder ball, a protruding block, or a structure that is known in the industry, and the shape of the conductive protrusion 27 may be round, elliptical, square, and rectangular, but the present invention is not limited in this regard.
- a dicing process is performed, and a cutting path S of the dicing process is along the through hole 202 and the via hole 240 , such that a plurality of semiconductor packages shown in FIG. 2J are formed.
- the conductive protrusion 27 may be formed on the redistribution layer 251 in the opening hole 260 .
- a chip such as a substrate 20 shown in FIG. 2J , may be referred to as the wafer 20 after being diced.
- the second space P 2 can prevent a light signal or a thermal signal of the light sensor 200 or a light signal or a thermal signal of the thermal sensor 200 from dissipating through the substrate 20 to affect a detecting result.
- the second space may be formed between the plate and the light sensor or between the plate and the thermal sensor.
- the volume of the substrate of the semiconductor package may be reduced, so that signal noise can be decreased, and the detecting capability of the light sensor or the thermal sensor (e.g., infrared ray detecting capability) is improved.
- FIGS. 3A to 3E are cross-sectional views of a manufacturing method of a semiconductor package 3 (see FIG. 3E ) according to one embodiment of the present invention.
- the wafer 20 that has at least one light sensor or thermal sensor 200 , the first surface 20 a, and the second surface 20 b opposite to the first surface 20 a is provided.
- the light sensor or the thermal sensor 200 is disposed on the first surface 20 a and covers a recess 204 of the first surface 20 a.
- the cover 22 may be disposed on the first surface 20 a of the wafer 20 by at least one support 21 , such that the cover 22 is above the light sensor or the thermal sensor 200 , and a space P′ is formed between the cover 22 and the light sensor 200 or between the cover 22 and the thermal sensor 200 . Thereafter, the second surface 20 b of the wafer 20 may be ground.
- the through hole 202 may be formed in the second surface 20 b of the wafer 20 to expose the support 21 and the electrical connecting pad 201 of the wafer 20 .
- an isolation layer 23 a may be formed on the second surface 20 b of the wafer 20 and a wall surface 20 c that surrounds the through hole 202 .
- the isolation layer 23 a may cover the through hole 202 , and a knife is used to form a notch 202 a in the isolation layer 23 a in the through hole 202 , such that the isolation layer 23 a is located on the wall surface of the wafer 20 surrounding the through hole 202 . Thereafter, a redistribution layer 25 a is formed on the isolation layer 23 a and electrically connected to the electrical connecting pad 201 , such that the structure shown in FIG. 3C may be obtained.
- the protection layer 26 may be formed on the isolation layer 23 a and the redistribution layer 25 a. Afterwards, the protection layer 26 is patterned to form the opening hole 260 to expose the redistribution layer 25 a. After the opening hole 260 of the protection layer 26 is formed, the conductive protrusion 27 may be formed on the redistribution layer 25 a in the opening hole 260 , such that the conductive protrusion 27 may be conducted with the electrical connecting pad 201 through the redistribution layer 25 a.
- the cover 22 , the support 21 , and the wafer 20 may be vertically diced along the through hole 202 (i.e., along the cutting path S), such that the semiconductor package 3 is obtained.
- the substrate 20 shown in FIG. 3E is the diced wafer 20 .
- the semiconductor package 3 includes the substrate 20 , at least one support 21 , the cover 22 , the isolation layer 23 a, the redistribution layer 25 a, the protection layer 26 , and the conductive protrusion 27 .
- the substrate 20 has at least one light sensor or thermal sensor 200 , the first surface 20 a and the second surface 20 b that is opposite to the first surface 20 a.
- the first surface 20 a has the recess 204 and the electrical connecting pad 201 .
- the recess 204 can prevent a light signal or a thermal signal of the light sensor 200 or a light signal or a thermal signal of the thermal sensor 200 from dissipating through the substrate 20 to affect a detecting result.
- the light sensor or the thermal sensor 200 is disposed on the first surface 20 a and covers the recess 204 .
- the support 21 is disposed on the first surface 20 a of the substrate 20 .
- the cover 22 is located on the support 21 , such that the space P′ is formed between the cover 22 and the light sensor 200 or between the cover 22 and the thermal sensor 200 .
- the isolation layer 23 a is located on the second surface 20 b of the substrate 20 .
- the redistribution layer 25 a is located on the isolation layer 23 a and electrically connected to the electrical connecting pad 201 .
- the protection layer 26 is located on the isolation layer 23 a and the redistribution layer 25 a, and the protection layer 26 has the opening hole 260 to expose a portion of a surface of the redistribution layer 25 a.
- the conductive protrusion 27 is located on the redistribution layer 25 a that is in the opening hole 260 .
- the substrate 20 has the wall surface 20 c adjacent to the electrical connecting pad 201 and the second surface 20 b, and the isolation layer 23 a is located on the wall surface 20 c. Furthermore, an obtuse angle is included between the wall surface 20 c and the second surface 20 b.
- the volume of the substrate of the semiconductor package may be reduced.
- signal noise can be decreased, and the detecting capability of the light sensor or the thermal sensor (e.g., infrared ray detecting capability) is improved. Therefore, the use of the semiconductor package is expanded and the purpose of multiple functions is achieved, thereby improving product competitiveness.
- FIGS. 4A to 4D are cross-sectional views of a manufacturing method of a semiconductor package 4 (see FIG. 4D ) according to one embodiment of the present invention.
- the wafer 20 that has at least one light sensor or thermal sensor 200 , the first surface 20 a, and the second surface 20 b opposite to the first surface 20 a is provided.
- the light sensor or the thermal sensor 200 is disposed on the first surface 20 a and covers the recess 204 of the first surface 20 a.
- the cover 22 may be disposed on the first surface 20 a of the wafer 20 by at least one support 21 , such that the cover 22 is above the light sensor or the thermal sensor 200 , and the space P′ is formed between the cover 22 and the light sensor 200 or between the cover 22 and the thermal sensor 200 . Thereafter, the second surface 20 b of the wafer 20 may be ground.
- the through hole 202 may be formed in the second surface 20 b of the wafer 20 to expose the support 21 and the electrical connecting pad 201 of the wafer 20 .
- an isolation layer 23 b may be formed on the second surface 20 b of the wafer 20 and a wall surface 20 d that surrounds the through hole 202 .
- the wall surface 20 d is perpendicular to the second surface 20 b and the electrical connecting pad 201 .
- the isolation layer 23 b may be patterned to expose the electrical connecting pad 201 .
- the redistribution layer 25 a may be formed on the isolation layer 23 b, such that the redistribution layer 25 a is electrically connected to the electrical connecting pad 201 .
- the protection layer 26 may be formed on the isolation layer 23 b and the redistribution layer 25 a. Afterwards, the protection layer 26 is patterned to form the opening hole 260 to expose the redistribution layer 25 a.
- the conductive protrusion 27 may be formed on the redistribution layer 25 a in the opening hole 260 , such that the conductive protrusion 27 may be conducted with the electrical connecting pad 201 through the redistribution layer 25 a, and the structure shown in FIG. 4C is obtained.
- a portion of the protection layer 26 is located in the through hole 202 , such that a void is formed between the protection layer 26 and the electrical connecting pad 201 .
- the cover 22 , the support 21 , and the wafer 20 may be vertically diced along the cutting path S, such that the semiconductor package 4 is obtained.
- the substrate 20 shown in FIG. 4D is the diced wafer 20 .
- the semiconductor package 4 includes the substrate 20 , at least one support 21 , the cover 22 , the isolation layer 23 b, the redistribution layer 25 a, the protection layer 26 , and the conductive protrusion 27 .
- the substrate 20 has at least one light sensor or thermal sensor 200 , the first surface 20 a and the second surface 20 b that is opposite to the first surface 20 a.
- the first surface 20 a has the recess 204 and the electrical connecting pad 201 .
- the recess 204 can prevent a light signal or a thermal signal of the light sensor 200 or a light signal or a thermal signal of the thermal sensor 200 from dissipating through the substrate 20 to affect a detecting result.
- the light sensor or the thermal sensor 200 is disposed on the first surface 20 a and covers the recess 204 .
- the support 21 is disposed on the first surface 20 a of the substrate 20 .
- the cover 22 is located on the support 21 , such that the space P′ is formed between the cover 22 and the light sensor 200 or between the cover 22 and the thermal sensor 200 .
- the isolation layer 23 b is located on the second surface 20 b of the substrate 20 .
- the redistribution layer 25 a is located on the isolation layer 23 b and electrically connected to the electrical connecting pad 201 .
- the protection layer 26 is located on the isolation layer 23 b and the redistribution layer 25 a, and the protection layer 26 has the opening hole 260 to expose a portion of a surface of the redistribution layer 25 a.
- the conductive protrusion 27 is located on the redistribution layer 25 a that is in the opening hole 260 .
- the substrate 20 has the wall surface 20 d adjacent to the electrical connecting pad 201 and the second surface 20 b, and the isolation layer 23 b is located on the wall surface 20 d. Furthermore, the wall surface 20 d is perpendicular to the second surface 20 b and the electrical connecting pad 201 , and the protection layer 26 is located in the through hole 202 .
- the volume of the substrate of the semiconductor package may be reduced.
- signal noise can be decreased, and the detecting capability of the light sensor or the thermal sensor (e.g., infrared ray detecting capability) is improved. Therefore, the use of the semiconductor package is expanded and the purpose of multiple functions is achieved, thereby improving product competitiveness.
Abstract
A semiconductor package includes a substrate, at lest one support, a cover, and a plate. The substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface. The light sensor or the thermal sensor is disposed on the first surface. The second surface has an opening to expose the light sensor (or the thermal sensor). The support is disposed on the first surface. The cover is disposed on the support, such that the cover is above the light sensor (or the thermal sensor) to form a first space between the cover and the light sensor (or the thermal sensor). The plate is placed on the second surface to cover the opening, such that a second space is formed between the plate and the light sensor (or the thermal sensor).
Description
- The present application is a Divisional Application of the U.S. application Ser. No. 14/570,949, filed Dec. 15, 2014, which claims priority to Taiwan Application Serial Number 103136492, filed Oct. 22, 2014, all of which are herein incorporated by reference.
- Field of Invention
- The present invention relates to a semiconductor package and a manufacturing method of the semiconductor package. More particularly, the present invention relates to a semiconductor package having a detecting function and a manufacturing method of the semiconductor package.
- Description of Related Art
- Along with the progress and development in electronic industry, the requirement for functions of electronic products is increased. In order to achieve the requirement of multiple functions for users, semiconductor packages and electronic components having multiple functions need to be disposed on the printed circuit boards of the electronic products. According to the requirements of miniaturization, semiconductor packages are integrated with the electronic products to form micro-electro mechanical systems (MEMS) utilizing the improvement of integration. As a result, not only the layout space of the printed circuit board may be reduced, but also the requirement of multiple functions may be maintained.
- Recently, technology for stacking wafers is a new development in the art, such that plural homogeneous or heterogeneous wafers may be stacked in the development to reach the purpose of multiple functions. Therefore, the bottleneck of miniaturization in the technology of semiconductor flat package may be solved. That is to say, the requirement of miniaturization may be achieved by integration.
- A detecting type semiconductor package 1 is shown in
FIG. 1 . The semiconductor package 1 has achip 10 and aglass sheet 12 that is stacked on thechip 10. Thechip 10 has anoperating surface 10 a and anon-operating surface 10 b. Theoperating surface 10 a has alight sensor 100, and theglass sheet 12 is disposed on theoperating surface 10 a by adam layer 11, such that a space P is formed between theglass sheet 12 and thelight sensor 100. - However, in the conventional semiconductor package 1 having a detecting function, the volume of the
chip 10 is large, so that noise is more apt to occur. As a result, the use of the semiconductor package 1 is limited, and the semiconductor package 1 is difficult to be matched with the requirement of multiple functions, thereby reducing product competitiveness. - An aspect of the present invention is to provide a semiconductor package.
- According to an embodiment of the present invention, a semiconductor package includes a substrate, at least one support, a cover, and a plate. The substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface. The light sensor or the thermal sensor is disposed on the first surface. The second surface of the substrate has an opening to expose the light sensor or the thermal sensor. The support is disposed on the first surface of the substrate. The cover is disposed on the support, such that the cover is above the light sensor or the thermal sensor, and a first space is formed between the cover and the light sensor or between the cover and the thermal sensor. The plate is placed on the second surface of the substrate to cover the opening, such that a second space is formed between the plate and the light sensor or between the plate and the thermal sensor.
- An aspect of the present invention is to provide a manufacturing method of a semiconductor package.
- According to an embodiment of the present invention, a manufacturing method of a semiconductor package includes the following steps. A wafer that has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface is provided, and the light sensor or the thermal sensor is disposed on the first surface. A cover is disposed on the first surface of the wafer by at least one support, such that the cover is above the light sensor or the thermal sensor, and a first space is formed between the cover and the light sensor or between the cover and the thermal sensor. An opening is formed in the second surface of the wafer to expose the light sensor or the thermal sensor. A plate is placed on the second surface of the substrate to cover the opening, such that a second space is formed between the plate and the light sensor or between the plate and the thermal sensor.
- In the aforementioned embodiments of the present invention, since the second surface of the substrate of the semiconductor package of the present invention has the opening, the second space may be formed between the plate and the light sensor or between the plate and the thermal sensor. As a result, the volume of the substrate of the semiconductor package may be reduced, so that signal noise can be decreased, and the detecting capability of the light sensor or the thermal sensor (e.g., infrared ray detecting capability) is improved. Therefore, the use of the semiconductor package of the present invention is expanded and the purpose of multiple functions is achieved, thereby improving product competitiveness.
- An aspect of the present invention is to provide a semiconductor package.
- According to an embodiment of the present invention, a semiconductor package includes a substrate, at least one support, a cover, an isolation layer, and a redistribution layer. The substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface. The first surface has a recess and an electrical connecting pad. The light sensor or the thermal sensor is disposed on the first surface and covers the recess. The support is disposed on the first surface of the substrate. The cover is located on the support, such that a space is formed between the cover and the light sensor or between the cover and the thermal sensor. The isolation layer is located on the second surface of the substrate. The redistribution layer is located on the isolation layer and electrically connected to the electrical connecting pad.
- An aspect of the present invention is to provide a manufacturing method of a semiconductor package.
- According to an embodiment of the present invention, a manufacturing method of a semiconductor package includes the following steps. A wafer that has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface is provided, and the light sensor or the thermal sensor is disposed on the first surface and covers a recess of the first surface. A cover is disposed on the first surface of the wafer by at least one support, such that the cover is above the light sensor or the thermal sensor, and a space is formed between the cover and the light sensor or between the cover and the thermal sensor. A through hole is formed in the second surface of the wafer to expose the support and an electrical connecting pad of the wafer. An isolation layer is formed on the second surface of the wafer and a wall surface that surrounds the through hole. A redistribution layer is formed on the isolation layer, and the redistribution layer is electrically connected to the electrical connecting pad.
- In the aforementioned embodiments of the present invention, since the first surface of the substrate of the semiconductor package of the present invention has the recess, the volume of the substrate of the semiconductor package may be reduced. As a result, signal noise can be decreased, and the detecting capability of the light sensor or the thermal sensor (e.g., infrared ray detecting capability) is improved. Therefore, the use of the semiconductor package of the present invention is expanded and the purpose of multiple functions is achieved, thereby improving product competitiveness.
- It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.
- The invention can be more fully understood by reading the following detailed description of the embodiments, with reference made to the accompanying drawings as follows:
-
FIG. 1 is a cross-sectional view of a conventional semiconductor package; -
FIGS. 2A to 2J are cross-sectional views of a manufacturing method of a semiconductor package according to one embodiment of the present invention; -
FIGS. 3A to 3E are cross-sectional views of a manufacturing method of a semiconductor package according to one embodiment of the present invention; and -
FIGS. 4A to 4D are cross-sectional views of a manufacturing method of a semiconductor package according to one embodiment of the present invention. - Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
- In the present invention, a semiconductor package after being stacked, packaged, and diced may be used in various micro electro mechanical systems (MEMS), such as an image sensor capable of detecting through an electrical variation or a capacitive variation, and a detecting-type semiconductor package manufactured in wafer scale package process (WSP) and having image sensors, RF circuits, accelerators, gyroscopes, micro actuators, or pressure sensors.
- As shown in
FIGS. 2A to 2J ,FIGS. 2A to 2J are cross-sectional views of a manufacturing method of a semiconductor package 2 (seeFIG. 2J ) according to one embodiment of the present invention. - As shown in
FIG. 2A , awafer 20 having at least one light sensor orthermal sensor 200, afirst surface 20 a, and asecond surface 20 b opposite to thefirst surface 20 a is provided. The light sensor or thethermal sensor 200 is disposed on thefirst surface 20 a. For example, the light sensor or thethermal sensor 200 may be located onfirst surface 20 a or in thefirst surface 20 a, the light sensor or thethermal sensor 200 may protrude from thefirst surface 20 a, the light sensor or thethermal sensor 200 and thefirst surface 20 a may be at the same level, the light sensor or thethermal sensor 200 may be recessed in the light sensor or thethermal sensor 200, and the present invention is not limited in this regard. Moreover, thefirst surface 20 a of thewafer 20 has a plurality of electrical connectingpads 201. - In this embodiment, the size of the
wafer 20 may be 6 inches, 8 inches, 12 inches, etc., and the present invention is not limited in this regard. The light sensor or thethermal sensor 200 may be used to detect an infrared ray (IR), but the present invention is not limited thereto. - As shown in
FIG. 2B , at least onesupport 21 is formed on thefirst surface 20 a of thewafer 20. In this embodiment, thesupport 21 is a dam layer and located on a portion of a surface of the electrical connectingpad 201. - As shown in
FIG. 2C , acover 22 is disposed on thesupport 21, such that thecover 22 is above the light sensor or thethermal sensor 200, and a first space P1 is formed between thecover 22 and thelight sensor 200 or between thecover 22 and thethermal sensor 200. - In this embodiment, the
cover 22 is made of silicon or quartz, and the thickness t of thecover 22 may be 300 μm, but the thinner, the better. An infrared ray may pass through thecover 22, such that the light sensor or thethermal sensor 200 may detect the infrared ray, but the present invention is not limited to the infrared ray. - Furthermore, the first space P1 is in a vacuum state, and the height h of the first space P1 may be in a range form 30 μm to 50 μm, such as 40 μm.
- In addition, the
cover 22 is made of light impermeable material (e.g., silicon or quartz). Therefore, an optical alignment process may not be used. As a result, thesupport 21 is disposed on thefirst surface 20 a of thewafer 20, and thereafter thecover 22 is used to cover thewafer 20, such that the alignment problem of the cover 22 (or the support 21) is prevented. - In another embodiment, when the
cover 22 is made of light permeable material (e.g., glass), thesupport 21 may be disposed oncover 22, and next thesupport 21 and thecover 22 may be disposed on thefirst surface 20 a of thewafer 20 by an alignment method, such as optical alignment by utilizing the light transmittance of glass. - As shown in
FIG. 2D , the thickness of thewafer 20 is reduced from thesecond surface 20 b, and a throughhole 202 is formed in thesecond surface 20 b of thewafer 20 to expose thesupport 21 and the electrical connectingpad 201. - In this embodiment, after a process for reducing the thickness of the
wafer 20 is performed, the thickness d of thewafer 20 may be in a range from 100 μm to 400 μm. - As shown in
FIG. 2E , anisolation layer 23 is formed on thesecond surface 20 b of thewafer 20, and throughhole 202 is filled with theisolation layer 23. Thereafter, anopening region 230 that is aligned with the light sensor or thethermal sensor 200 on theisolation layer 23 is formed, such that a portion of thesecond surface 20 b of thewafer 20 is exposed through theopening region 230. - As shown in
FIG. 2F , anopening 203 is formed in thesecond surface 20 b of thewafer 20 in theopening region 230 to expose the light sensor or thethermal sensor 200. In this embodiment, theopening 203 is formed by and etching process. - As shown in
FIG. 2G , aplate 24 is placed on thesecond surface 20 b of thewafer 20 to cover theopening 203, such that a second space P2 is formed between theplate 24 and thelight sensor 200 or between theplate 24 and thethermal sensor 200. Theplate 24 may support thewafer 20 to enhance structure strength. - In this embodiment, the
plate 24 may be made of silicon or glass, and theplate 24 is disposed on theisolation layer 23 and the throughhole 202. Moreover, the thickness r of theplate 24 may be in a range from 100 μm to 300 μm, such as 200 μm. - In addition, the second space P2 is in a vacuum state.
- As shown in
FIG. 2H , an viahole 240 communicated with the throughhole 202 is formed in theplate 24, and theisolation layer 23 and thesupport 21 are removed from the throughhole 202, such that thesupport 21 and a side surface of the electrical connectingpad 201. - As shown in
FIG. 21 , aredistribution layer 25 is formed on theplate 24, the sidewall of the viahole 240, and the sidewall of the throughhole 202, such that theredistribution layer 25 is electrically connected to the electrical connectingpad 201. - In this embodiment, the
redistribution layer 25 includes adielectric layer 250 and aconductive layer 251 that is formed on thedielectric layer 250. Thedielectric layer 250 is formed on theplate 24, the sidewall of the viahole 240, and the sidewall of the throughhole 202. - Thereafter, a
protection layer 26 is formed on theplate 24 and theredistribution layer 25, and anopening hole 260 is formed in theprotection layer 26, such that a portion of a surface of theredistribution layer 251 on theplate 24 is exposed through theopening hole 260. - In this embodiment, the
protection layer 26 may be made of solder mask material. Aconductive protrusion 27 may be a solder ball, a protruding block, or a structure that is known in the industry, and the shape of theconductive protrusion 27 may be round, elliptical, square, and rectangular, but the present invention is not limited in this regard. - Afterwards, a dicing process is performed, and a cutting path S of the dicing process is along the through
hole 202 and the viahole 240, such that a plurality of semiconductor packages shown inFIG. 2J are formed. Moreover, theconductive protrusion 27 may be formed on theredistribution layer 251 in theopening hole 260. A chip, such as asubstrate 20 shown inFIG. 2J , may be referred to as thewafer 20 after being diced. The second space P2 can prevent a light signal or a thermal signal of thelight sensor 200 or a light signal or a thermal signal of thethermal sensor 200 from dissipating through thesubstrate 20 to affect a detecting result. - Since the second surface of the substrate of the semiconductor package has the opening, the second space may be formed between the plate and the light sensor or between the plate and the thermal sensor. As a result, the volume of the substrate of the semiconductor package may be reduced, so that signal noise can be decreased, and the detecting capability of the light sensor or the thermal sensor (e.g., infrared ray detecting capability) is improved.
- Therefore, the use of the semiconductor package is expanded and the purpose of multiple functions is achieved, thereby improving product competitiveness.
- It is to be noted that the materials of the elements described above will not be repeated in the following description. In the following description, other semiconductor packages and manufacturing methods thereof will be described.
-
FIGS. 3A to 3E are cross-sectional views of a manufacturing method of a semiconductor package 3 (seeFIG. 3E ) according to one embodiment of the present invention. As shown inFIG. 3A , thewafer 20 that has at least one light sensor orthermal sensor 200, thefirst surface 20 a, and thesecond surface 20 b opposite to thefirst surface 20 a is provided. The light sensor or thethermal sensor 200 is disposed on thefirst surface 20 a and covers arecess 204 of thefirst surface 20 a. Thecover 22 may be disposed on thefirst surface 20 a of thewafer 20 by at least onesupport 21, such that thecover 22 is above the light sensor or thethermal sensor 200, and a space P′ is formed between thecover 22 and thelight sensor 200 or between thecover 22 and thethermal sensor 200. Thereafter, thesecond surface 20 b of thewafer 20 may be ground. - As shown in
FIG. 3A andFIG. 3B , after thecover 22 covers the light sensor or thethermal sensor 200, the throughhole 202 may be formed in thesecond surface 20 b of thewafer 20 to expose thesupport 21 and the electrical connectingpad 201 of thewafer 20. Next, anisolation layer 23 a may be formed on thesecond surface 20 b of thewafer 20 and awall surface 20 c that surrounds the throughhole 202. - As shown in
FIG. 3B andFIG. 3C , in this embodiment, theisolation layer 23 a may cover the throughhole 202, and a knife is used to form anotch 202 a in theisolation layer 23 a in the throughhole 202, such that theisolation layer 23 a is located on the wall surface of thewafer 20 surrounding the throughhole 202. Thereafter, aredistribution layer 25 a is formed on theisolation layer 23 a and electrically connected to the electrical connectingpad 201, such that the structure shown inFIG. 3C may be obtained. - As shown in
FIG. 3C andFIG. 3D , after theredistribution layer 25 a is formed, theprotection layer 26 may be formed on theisolation layer 23 a and theredistribution layer 25 a. Afterwards, theprotection layer 26 is patterned to form theopening hole 260 to expose theredistribution layer 25 a. After theopening hole 260 of theprotection layer 26 is formed, theconductive protrusion 27 may be formed on theredistribution layer 25 a in theopening hole 260, such that theconductive protrusion 27 may be conducted with the electrical connectingpad 201 through theredistribution layer 25 a. - As shown in
FIG. 3D and 3E , after the structure shown inFIG. 3D is obtained, thecover 22, thesupport 21, and thewafer 20 may be vertically diced along the through hole 202 (i.e., along the cutting path S), such that thesemiconductor package 3 is obtained. Thesubstrate 20 shown inFIG. 3E is the dicedwafer 20. - The
semiconductor package 3 includes thesubstrate 20, at least onesupport 21, thecover 22, theisolation layer 23 a, theredistribution layer 25 a, theprotection layer 26, and theconductive protrusion 27. Thesubstrate 20 has at least one light sensor orthermal sensor 200, thefirst surface 20 a and thesecond surface 20 b that is opposite to thefirst surface 20 a. Thefirst surface 20 a has therecess 204 and the electrical connectingpad 201. Therecess 204 can prevent a light signal or a thermal signal of thelight sensor 200 or a light signal or a thermal signal of thethermal sensor 200 from dissipating through thesubstrate 20 to affect a detecting result. The light sensor or thethermal sensor 200 is disposed on thefirst surface 20 a and covers therecess 204. Thesupport 21 is disposed on thefirst surface 20 a of thesubstrate 20. Thecover 22 is located on thesupport 21, such that the space P′ is formed between thecover 22 and thelight sensor 200 or between thecover 22 and thethermal sensor 200. Theisolation layer 23 a is located on thesecond surface 20 b of thesubstrate 20. Theredistribution layer 25 a is located on theisolation layer 23 a and electrically connected to the electrical connectingpad 201. Theprotection layer 26 is located on theisolation layer 23 a and theredistribution layer 25 a, and theprotection layer 26 has theopening hole 260 to expose a portion of a surface of theredistribution layer 25 a. Theconductive protrusion 27 is located on theredistribution layer 25 a that is in theopening hole 260. - In this embodiment, the
substrate 20 has thewall surface 20 c adjacent to the electrical connectingpad 201 and thesecond surface 20 b, and theisolation layer 23 a is located on thewall surface 20 c. Furthermore, an obtuse angle is included between thewall surface 20 c and thesecond surface 20 b. - Since the first surface of the substrate of the semiconductor package has the recess, the volume of the substrate of the semiconductor package may be reduced. As a result, signal noise can be decreased, and the detecting capability of the light sensor or the thermal sensor (e.g., infrared ray detecting capability) is improved. Therefore, the use of the semiconductor package is expanded and the purpose of multiple functions is achieved, thereby improving product competitiveness.
-
FIGS. 4A to 4D are cross-sectional views of a manufacturing method of a semiconductor package 4 (seeFIG. 4D ) according to one embodiment of the present invention. As shown inFIG. 4A , thewafer 20 that has at least one light sensor orthermal sensor 200, thefirst surface 20 a, and thesecond surface 20 b opposite to thefirst surface 20 a is provided. The light sensor or thethermal sensor 200 is disposed on thefirst surface 20 a and covers therecess 204 of thefirst surface 20 a. Thecover 22 may be disposed on thefirst surface 20 a of thewafer 20 by at least onesupport 21, such that thecover 22 is above the light sensor or thethermal sensor 200, and the space P′ is formed between thecover 22 and thelight sensor 200 or between thecover 22 and thethermal sensor 200. Thereafter, thesecond surface 20 b of thewafer 20 may be ground. - As shown in
FIG. 4A andFIG. 4B , after thecover 22 covers the light sensor or thethermal sensor 200, the throughhole 202 may be formed in thesecond surface 20 b of thewafer 20 to expose thesupport 21 and the electrical connectingpad 201 of thewafer 20. Next, anisolation layer 23 b may be formed on thesecond surface 20 b of thewafer 20 and awall surface 20 d that surrounds the throughhole 202. In this embodiment, thewall surface 20 d is perpendicular to thesecond surface 20 b and the electrical connectingpad 201. Moreover, theisolation layer 23 b may be patterned to expose the electrical connectingpad 201. - As shown in
FIG. 4B andFIG. 4C , thereafter, theredistribution layer 25 a may be formed on theisolation layer 23 b, such that theredistribution layer 25 a is electrically connected to the electrical connectingpad 201. After theredistribution layer 25 a is formed, theprotection layer 26 may be formed on theisolation layer 23 b and theredistribution layer 25 a. Afterwards, theprotection layer 26 is patterned to form theopening hole 260 to expose theredistribution layer 25 a. After theopening hole 260 of theprotection layer 26 is formed, theconductive protrusion 27 may be formed on theredistribution layer 25 a in theopening hole 260, such that theconductive protrusion 27 may be conducted with the electrical connectingpad 201 through theredistribution layer 25 a, and the structure shown inFIG. 4C is obtained. - In this embodiment, a portion of the
protection layer 26 is located in the throughhole 202, such that a void is formed between theprotection layer 26 and the electrical connectingpad 201. - As shown in
FIG. 4C andFIG. 4D , after the structure shown inFIG. 4C is obtained, thecover 22, thesupport 21, and thewafer 20 may be vertically diced along the cutting path S, such that thesemiconductor package 4 is obtained. Thesubstrate 20 shown inFIG. 4D is the dicedwafer 20. - The
semiconductor package 4 includes thesubstrate 20, at least onesupport 21, thecover 22, theisolation layer 23 b, theredistribution layer 25 a, theprotection layer 26, and theconductive protrusion 27. Thesubstrate 20 has at least one light sensor orthermal sensor 200, thefirst surface 20 a and thesecond surface 20 b that is opposite to thefirst surface 20 a. Thefirst surface 20 a has therecess 204 and the electrical connectingpad 201. Therecess 204 can prevent a light signal or a thermal signal of thelight sensor 200 or a light signal or a thermal signal of thethermal sensor 200 from dissipating through thesubstrate 20 to affect a detecting result. The light sensor or thethermal sensor 200 is disposed on thefirst surface 20 a and covers therecess 204. Thesupport 21 is disposed on thefirst surface 20 a of thesubstrate 20. Thecover 22 is located on thesupport 21, such that the space P′ is formed between thecover 22 and thelight sensor 200 or between thecover 22 and thethermal sensor 200. Theisolation layer 23 b is located on thesecond surface 20 b of thesubstrate 20. Theredistribution layer 25 a is located on theisolation layer 23 b and electrically connected to the electrical connectingpad 201. Theprotection layer 26 is located on theisolation layer 23 b and theredistribution layer 25 a, and theprotection layer 26 has theopening hole 260 to expose a portion of a surface of theredistribution layer 25 a. Theconductive protrusion 27 is located on theredistribution layer 25 a that is in theopening hole 260. - In this embodiment, the
substrate 20 has thewall surface 20 d adjacent to the electrical connectingpad 201 and thesecond surface 20 b, and theisolation layer 23 b is located on thewall surface 20 d. Furthermore, thewall surface 20 d is perpendicular to thesecond surface 20 b and the electrical connectingpad 201, and theprotection layer 26 is located in the throughhole 202. - Since the first surface of the substrate of the semiconductor package has the recess, the volume of the substrate of the semiconductor package may be reduced. As a result, signal noise can be decreased, and the detecting capability of the light sensor or the thermal sensor (e.g., infrared ray detecting capability) is improved. Therefore, the use of the semiconductor package is expanded and the purpose of multiple functions is achieved, thereby improving product competitiveness.
- Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.
Claims (11)
1. A semiconductor package, comprising:
a substrate having at least one light sensor or at least one thermal sensor, a first surface, and a second surface opposite to the first surface, wherein the first surface has a recess and an electrical connecting pad, and the at least one light sensor or the at least one thermal sensor is disposed on the first surface and covers the recess;
at least one support disposed on the first surface of the substrate;
a cover located on the at least one support, such that a space is formed between the cover and the at least one light sensor or between the cover and the at least one thermal sensor;
an isolation layer located on the second surface of the substrate; and
a redistribution layer located on the isolation layer and electrically connected to the electrical connecting pad.
2. The semiconductor package of claim 1 , further comprising:
a protection layer located on the isolation layer and the redistribution layer, wherein the protection layer has an opening hole for exposing a portion of a surface of the redistribution layer.
3. The semiconductor package of claim 2 , further comprising:
a conductive protrusion located on the redistribution layer in the opening hole.
4. The semiconductor package of claim 1 , wherein the substrate has a wall surface adjacent to the electrical connecting pad and the second surface, and the isolation layer is located on the wall surface.
5. The semiconductor package of claim 4 , wherein an obtuse angle is included between the wall surface and the second surface.
6. The semiconductor package of claim 4 , wherein the wall surface is perpendicular to the second surface and the electrical connecting pad.
7. A manufacturing method of a semiconductor package, comprising:
providing a wafer that has at least one light sensor or at least one thermal sensor, a first surface, and a second surface opposite to the first surface, wherein the at least one light sensor or the at least one thermal sensor is disposed on the first surface and covers a recess of the first surface;
disposing a cover on the first surface of the wafer by at least one support, such that the cover is above the at least one light sensor or the at least one thermal sensor, and a space is formed between the cover and the at least one light sensor or between the cover and the at least one thermal sensor;
forming a through hole in the second surface of the wafer for exposing the at least one support and an electrical connecting pad of the wafer;
forming an isolation layer on the second surface of the wafer and a wall surface that surrounds the through hole; and
forming a redistribution layer on the isolation layer, wherein the redistribution layer is electrically connected to the electrical connecting pad.
8. The manufacturing method of the semiconductor package of claim 7 , forming the isolation layer on the second surface of the wafer and the wall surface that surrounds the through hole further comprising:
using the isolation layer to cover the through hole; and
forming a notch in the isolation layer in the through hole, such that the isolation layer is located on the wall surface of the wafer surrounding the through hole.
9. The manufacturing method of the semiconductor package of claim 7 , further comprising:
forming a protection layer on the isolation layer and the redistribution layer; and
patterning the protection layer to form an opening hole for exposing the redistribution layer.
10. The manufacturing method of the semiconductor package of claim 9 , further comprising:
forming a conductive protrusion on the redistribution layer in the opening hole.
11. The manufacturing method of the semiconductor package of claim 7 , further comprising:
vertically dicing the cover, the at least one support, and the wafer along the through hole.
Priority Applications (1)
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US15/394,464 US20170110641A1 (en) | 2014-10-22 | 2016-12-29 | Semiconductor package and manufacturing method thereof |
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TW103136492 | 2014-10-22 | ||
TW103136492A TWI569427B (en) | 2014-10-22 | 2014-10-22 | Semiconductor package and manufacturing method thereof |
US14/570,949 US9570633B2 (en) | 2014-10-22 | 2014-12-15 | Semiconductor package and manufacturing method thereof |
US15/394,464 US20170110641A1 (en) | 2014-10-22 | 2016-12-29 | Semiconductor package and manufacturing method thereof |
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US14/570,949 Division US9570633B2 (en) | 2014-10-22 | 2014-12-15 | Semiconductor package and manufacturing method thereof |
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US20170110641A1 true US20170110641A1 (en) | 2017-04-20 |
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US15/394,464 Abandoned US20170110641A1 (en) | 2014-10-22 | 2016-12-29 | Semiconductor package and manufacturing method thereof |
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TWI600125B (en) * | 2015-05-01 | 2017-09-21 | 精材科技股份有限公司 | Chip package and manufacturing method thereof |
US11069729B2 (en) * | 2018-05-01 | 2021-07-20 | Canon Kabushiki Kaisha | Photoelectric conversion device, and equipment |
CN112313799A (en) * | 2018-06-29 | 2021-02-02 | 索尼半导体解决方案公司 | Solid-state imaging device, electronic apparatus, and method of manufacturing solid-state imaging device |
US11121031B2 (en) * | 2018-11-01 | 2021-09-14 | Xintec Inc. | Manufacturing method of chip package and chip package |
DE102019211371A1 (en) * | 2019-07-30 | 2021-02-04 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method of manufacturing an electronic circuit component and electronic circuit component |
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Also Published As
Publication number | Publication date |
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US20160118506A1 (en) | 2016-04-28 |
US9570633B2 (en) | 2017-02-14 |
TWI569427B (en) | 2017-02-01 |
TW201616642A (en) | 2016-05-01 |
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