US20170062353A1 - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- US20170062353A1 US20170062353A1 US14/840,808 US201514840808A US2017062353A1 US 20170062353 A1 US20170062353 A1 US 20170062353A1 US 201514840808 A US201514840808 A US 201514840808A US 2017062353 A1 US2017062353 A1 US 2017062353A1
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Definitions
- Electronic equipments using semiconductor devices are essential for many modern applications.
- the semiconductor devices are applied for a variety of high-density electronics applications.
- the electronic equipment is getting more complicated with greater functionality and greater amounts of integrated circuitry, while are becoming increasingly smaller in size.
- Due to the miniaturized scale of the electronic equipment various types and dimensions of semiconductor devices perfoiming different functionalities are integrated and packaged into a single module.
- numerous manufacturing operations are implemented for integration of various types of semiconductor devices.
- the manufacturing and integration of the semiconductor devices involve many complicated steps and operations.
- the integration of the semiconductor devices in such low profile and high density becomes more complicated.
- An increase in a complexity of manufacturing and integration of the semiconductor devices may cause deficiencies such as contamination, poor electrical interconnection, noise coupling, delamination of the components or high yield loss.
- the semiconductor devices are integrated and produced in an undesired configuration, which would further exacerbate materials wastage and thus increase the manufacturing cost. Since more different components with different materials are involved, complexity of the manufacturing and integration operations of the semiconductor devices is increased. There are more challenges to modify a structure of the semiconductor device and improve the manufacturing operations. As such, there is a continuous need to improve the manufacturing the semiconductor devices and solve the above deficiencies.
- FIG. 1 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 2 is a schematic cross sectional view of a semiconductor structure along AA′ of FIG. 1 in accordance with some embodiments of the present disclosure.
- FIG. 3 is a schematic cross sectional view of a semiconductor structure along BB′ of FIG. 1 in accordance with some embodiments of the present disclosure.
- FIG. 4 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 5 is a schematic cross sectional view of a semiconductor structure along CC′ of FIG. 4 in accordance with some embodiments of the present disclosure.
- FIG. 6 is a schematic cross sectional view of a semiconductor structure along DD′ of FIG. 4 in accordance with some embodiments of the present disclosure.
- FIG. 7 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 8 is a schematic cross sectional view of a semiconductor structure along EE′ of FIG. 7 in accordance with some embodiments of the present disclosure.
- FIG. 9 is a schematic cross sectional view of a semiconductor structure along FF′ of FIG. 7 in accordance with some embodiments of the present disclosure.
- FIG. 10 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 11 is a schematic cross sectional view of a semiconductor structure along GG′ of FIG. 10 in accordance with some embodiments of the present disclosure.
- FIG. 12 is a schematic cross sectional view of a semiconductor structure along HH′ of FIG. 10 in accordance with some embodiments of the present disclosure.
- FIG. 13 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 14 is a schematic cross sectional view of a semiconductor structure along II′ of FIG. 13 in accordance with some embodiments of the present disclosure.
- FIG. 15 is a schematic cross sectional view of a semiconductor structure along JJ′ of FIG. 13 in accordance with some embodiments of the present disclosure.
- FIG. 16 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 17 is a schematic cross sectional view of a semiconductor structure along KK′ of FIG. 16 in accordance with some embodiments of the present disclosure.
- FIG. 18 is a schematic cross sectional view of a semiconductor structure along LL′ of FIG. 16 in accordance with some embodiments of the present disclosure.
- FIG. 19 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 20 is a schematic cross sectional view of a semiconductor structure along MM′ of FIG. 19 in accordance with some embodiments of the present disclosure.
- FIG. 21 is a schematic cross sectional view of a semiconductor structure along NN′ of FIG. 19 in accordance with some embodiments of the present disclosure.
- FIG. 22 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 23 is a schematic cross sectional view of a semiconductor structure along OO′ of FIG. 22 in accordance with some embodiments of the present disclosure.
- FIG. 24 is a schematic cross sectional view of a semiconductor structure along PP′ of FIG. 22 in accordance with some embodiments of the present disclosure.
- FIG. 25 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 26 is a schematic cross sectional view of a semiconductor structure along QQ′ of FIG. 25 in accordance with some embodiments of the present disclosure.
- FIG. 27 is a schematic cross sectional view of a semiconductor structure along RR′ of FIG. 25 in accordance with some embodiments of the present disclosure.
- FIG. 28 is a schematic exploded view of a semiconductor structure of FIGS. 25-27 in accordance with some embodiments of the present disclosure.
- FIG. 29 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIGS. 30A-30I are schematic views of manufacturing a semiconductor structure by a method of FIG. 29 in accordance with some embodiments of the present disclosure.
- FIG. 31 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIGS. 32A-32G are schematic views of manufacturing a semiconductor structure by a method of FIG. 31 in accordance with some embodiments of the present disclosure.
- FIG. 33 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIGS. 34A-34G are schematic views of manufacturing a semiconductor structure by a method of FIG. 33 in accordance with some embodiments of the present disclosure.
- FIG. 35 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIGS. 36A-36O are schematic views of manufacturing a semiconductor structure by a method of FIG. 35 in accordance with some embodiments of the present disclosure.
- FIG. 37 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIGS. 38A-38O are schematic views of manufacturing a semiconductor structure by a method of FIG. 37 in accordance with some embodiments of the present disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- An electronic equipment including various semiconductor devices is manufactured by a number of operations. During the manufacturing, the semiconductor devices with different functionalities and dimensions are integrated into a single system. Circuitries of the semiconductor devices are integrated and connected through conductive traces and a substrate. After integration of the semiconductor devices, the semiconductor devices are encapsulated by a mold in order to protect the semiconductor devices from damages of the circuitries and environmental contamination. Also, a through silicon vias (TSV) is formed along a periphery of the semiconductor device to isolate the semiconductor devices from each other.
- TSV through silicon vias
- the semiconductor device may include a source emitting a radio wave in a radio frequency (RF).
- RF radio frequency
- Such source requires isolation from external electromagnetic interference to prevent noise coupling.
- the source has to be isolated from another source in order to prevent interference of the radio waves from the sources and noise affecting each other.
- a leakage of radio wave out of the semiconductor device shall be prevented.
- the TSV is provided around the source for absorbing the radio wave and reducing interference of the radio waves between the source and another source. However, absorption of the radio wave in a particular frequency by the TSV could not be performed. Lack of selectivity of the frequency being absorbed would limit functionality and application of the semiconductor device.
- an improved semiconductor structure includes a die at least partially enclosed by a seal ring or a redistribution layer (RDL).
- the seal ring or the RDL is configured for grounding or is connectable to ground in order to isolate the die from other components. Since the seal ring and the RDL occupy less space and thus more space can be used for electrical routing. The grounding of the seal ring or the RDL could reduce or prevent noise coupling.
- the semiconductor structure includes a source emitting an electromagnetic radiation such as radio wave in a radio frequency (RF), and a RDL configured to absorb the electromagnetic radiation from the source.
- the RDL can be configured to selectively absorb the electromagnetic radiation in a predetermined radio frequency.
- the RDL could isolate the source from other components and reduce electromagnetic interference between the electromagnetic radiation from the source and electromagnetic radiation from other components, such that noise can be minimized or prevented.
- An overall performance and reliability of the semiconductor structure could be improved.
- FIGS. 1-3 are an embodiment of a semiconductor structure 100 .
- FIG. 1 is a schematic top view of the semiconductor structure 100 .
- FIG. 2 is a schematic cross sectional view of the semiconductor structure 100 along AA′ of FIG. 1 .
- FIG. 3 is a schematic cross sectional view of the semiconductor structure 100 along BB′ of FIG. 1 .
- the semiconductor structure 100 includes a substrate 101 , a die 102 , a polymeric layer 103 , a molding 104 and a redistribution layer (RDL) 105 .
- the semiconductor structure 100 is a fan out wafer level package, that input/output (I/O) terminals of a die are routed out and not limited to be disposed over a surface area of the die. The I/O terminals can be disposed outside the surface area of the die.
- the substrate 101 includes semiconductive material such as silicon, germanium, gallium, arsenic, and combinations thereof. In some embodiments, the substrate 101 is a silicon substrate. In some embodiments, the substrate 101 includes a variety of electrical components formed over or within the substrate 101 by several fabrication operations. The electrical components can be various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, diodes or the like. The electrical components may be interconnected to perform one or more functions.
- NMOS n-type metal-oxide semiconductor
- PMOS p-type metal-oxide semiconductor
- the die 102 is disposed over the substrate 101 . In some embodiments, the die 102 is disposed over a front side of the substrate 101 . In some embodiments, the die 102 is disposed and attached to the substrate 101 by an adhesive 102 d such as a die attach film (DAF), a tape or the like. In some embodiments, the die 102 is a small piece including semiconductive material such as silicon and is fabricated with a predetermined functional circuit within the die 102 produced by photolithography operations. In some embodiments, the die 102 is singulated from a silicon wafer by a mechanical or laser blade and then is placed over the substrate 101 for subsequent manufacturing operations. In some embodiments, the die 102 is in a quadrilateral, a rectangular or a square shape.
- DAF die attach film
- the die 102 includes a die pad 102 a , a seal ring 102 b and a passivation 102 c .
- the die pad 102 a is disposed over the die 102 .
- the die pad 102 a is disposed over an active surface or a top surface of the die 102 .
- the die pad 102 a is configured to electrically connect with a circuitry external to the die 102 , so that a circuitry internal to the die 102 electrically connects with the circuitry external to the die 102 through the die pad 102 a .
- the die pad 102 a includes aluminum, copper, nickel, tungsten, gold, silver, palladium and/or alloys thereof.
- the die pad 102 a is partially covered by the passivation 102 c . In some embodiments, the die pad 102 a is surrounded by the passivation 102 c , and a portion of the die pad 102 a is exposed from the passivation 102 c . In some embodiments, the portion of the die pad 102 a exposed from the passivation 102 c is configured to subsequently receive a conductive structure such as a conductive trace. As such, the die pad 102 a can electrically connect with a circuitry external to the die 102 . In some embodiments, the passivation 102 c is configured to provide an electrical insulation and a moisture protection for the die 102 , so that the die 102 is isolated from ambient environment. In some embodiments, the passivation 102 c includes dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, spin-on glass (SOG), or the like.
- SOG spin-on glass
- the seal ring 102 b is disposed over or within the die 102 . As the die 102 may be potentially damaged upon fabrication and singulation operations, the seal ring 102 b is configured to protect the die 102 . In some embodiments, the seal ring 102 b is served as a barrier for preventing contaminants such as moisture, chemicals, corrosive material or etc. from penetrating into the die 102 and preventing cracks from propagating into the die 102 upon singulation operations. In some embodiments, the seal ring 102 b includes conductive material (such as aluminum, copper, silver, etc.) disposed within a dielectric material (such as silicon oxide, silicon oxynitride, silicon nitride, etc.) of the die 102 .
- conductive material such as aluminum, copper, silver, etc.
- dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, etc.
- the seal ring 102 b includes several stacked conductive layers interconnected by several of via layers. In some embodiments, the stacked conductive layers and the via layers are disposed alternatively. In some embodiments, the seal ring 102 b is electrically connected with the die pad 102 a . In some embodiments, a portion of the conductive layers of the seal ring 102 b is coupled and electrically connected with the die pad 102 a.
- the seal ring 102 b is disposed at a periphery of the die 102 . In some embodiments, the seal ring 102 b extends along the periphery of the die 102 to at least partially enclose a central portion of the die 102 . In some embodiments as illustrated in FIG. 1 , the seal ring 102 b encloses the central portion of the die 120 . In some embodiments, the conductive layers of the seal ring 102 b extend within the dielectric material of the die 102 along the periphery of the die 102 . In some embodiments, the seal ring 102 b is in rectangular, quadrilateral or other suitable shapes. In some embodiments, the seal ring 102 b surrounds components and interconnections disposed over or within the die 102 , such that contamination and damage of the die 102 would be prevented.
- the seal ring 102 b is configured for grounding or is connectable to ground. In some embodiments as illustrated in FIG. 1 , the seal ring 102 b is electrically grounded or connected to ground. As such, the die pad 102 a is also electrically grounded when the seal ring 102 b is electrically grounded or connected to ground. The grounding of the seal ring 102 b can provide isolation of the die 102 from other dies, circuitries or electrical components. In some embodiments, the die 102 would be isolated and thus would not electrically or electromagnetically interfere with other dies, circuitries or electrical components upon an operation of the die 102 .
- a via 106 is disposed over the die pad 102 a and the passivation 102 c . In some embodiments, the via 106 is electrically connected with the die pad 102 a . In some embodiments, the via 106 is extended through the passivation 102 c to the die pad 102 a . In some embodiments, the portion of the die pad 102 a exposed from the passivation 102 c is coupled with the via 106 . In some embodiments, the via 106 includes conductive material such as copper, aluminum, silver or etc. In some embodiments, the via 106 is electrically connected with the die pad 102 a and the seal ring 102 b.
- the polymeric layer 103 is disposed over the die 102 . In some embodiments, the polymeric layer 103 is disposed over the passivation 102 c . In some embodiments, the polymeric layer 103 surrounds the via 106 . In some embodiments, the via 106 is at least partially covered by the polymeric layer 103 . In some embodiments, the polymeric layer 103 includes polymeric material such as epoxy, polyimide, polybenzoxazole (PBO), solder resist (SR), ABF film, or the like. In some embodiments, the polymeric layer 103 is patterned to provide a path for a conductive structure passing through and electrically connecting with the via 106 and the die pad 102 a .
- the polymeric layer 103 includes a recess 103 a disposed over the via 106 and the die pad 102 a .
- the recess 103 a exposes a portion of the via 106 , so that the via 106 can electrically connect with a conductive structure.
- the molding 104 is disposed over the substrate 101 and surrounds the die 102 and the polymeric layer 103 . In some embodiments, the molding 104 encapsulates the die 102 , the passivation 102 c and the polymeric layer 103 . In some embodiments, the molding 104 includes a molding compound.
- the molding compound can be a single layer film or a composite stack.
- the molding compound includes various materials, for example, one or more of epoxy resins, phenolic hardeners, silicas, catalysts, pigments, mold release agents, and the like. Each of the materials for forming a molding compound has a high thermal conductivity, a low moisture absorption rate, a high flexural strength at board-mounting temperatures, or a combination of these.
- the RDL 105 is disposed over the die 102 and the molding 104 . In some embodiments, the RDL 105 is a layer for routing the I/O terminals out from the die 102 . In some embodiments, the RDL 105 includes an interconnect structure 105 a and a dielectric layer 105 d surrounding the interconnect structure 105 a . In some embodiments, the interconnect structure 105 a includes conductive material such as copper, aluminum, silver, gold or etc. In some embodiments, the dielectric layer 105 d includes dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, etc.
- the interconnect structure 105 a electrically connects with the via 106 , the die pad 102 a and the seal ring 102 b . In some embodiments, the interconnect structure 105 a is disposed over the polymeric layer 103 and conformal to the recess 103 a to couple with the via 106 . In some embodiments, the interconnect structure 105 a includes a via portion 105 b and a land portion 105 c coupled with the via portion 105 b . In some embodiments, the via portion 105 b extends through the polymeric layer 103 and couples with the via 106 . In some embodiments, the land portion 105 c is disposed over the polymeric layer 103 .
- the land portion 105 c extends along the dielectric layer 105 d and over the central portion of the die 102 .
- the interconnect structure 105 a of the RDL 105 is electrically grounded, as the interconnect structure 105 a is electrically connected with the seal ring 102 b through the die pad 102 a and the via 106 .
- the interconnect structure 105 a of the RDL 105 is configured for grounding or is connectable to ground.
- the seal ring 102 b , the die pad 102 a , the via 106 and the interconnect structure 105 a of the RDL 105 are cooperatively configured, so that the die 102 is electrically isolated from other electrical components or circuitries, and thus electrical or electromagnetic interference between the die 102 and other electrical components or circuitries could be minimized or prevented.
- FIGS. 4-6 are an embodiment of a semiconductor structure 200 .
- FIG. 4 is a schematic top view of the semiconductor structure 200 .
- FIG. 5 is a schematic cross sectional view of the semiconductor structure 200 along CC′ of FIG. 4 .
- FIG. 6 is a schematic cross sectional view of the semiconductor structure 100 along DD′ of FIG. 4 .
- the semiconductor structure 200 includes a substrate 101 , a die 102 , a polymeric layer 103 and a molding 104 , which have similar configuration as described above or illustrated in FIGS. 1-3 .
- the semiconductor structure 200 includes a RDL 105 disposed over the molding 104 and the polymeric layer 103 .
- the RDL 105 includes an interconnect structure 105 a and a dielectric layer 105 d surrounding the interconnect structure 105 a .
- the interconnect structure 105 a of the RDL 105 is electrically grounded, as the interconnect structure 105 a is electrically connected with the seal ring 102 b through the die pad 102 a and the via 106 .
- the interconnect structure 105 a of the RDL 105 is configured for grounding or is connectable to ground.
- the RDL 105 can be in various configurations.
- the interconnect structure 105 a includes a via portion 105 b and a land portion 105 c coupled with the via portion 105 b .
- the land portion 105 c extends over the polymeric layer 103 .
- the land portion 105 c extends over periphery of the die 102 , a central portion of the die 102 or a portion of the seal ring 102 b .
- the land portion 105 c partially encloses the central portion of the die 102 .
- the land portion 105 c is in a strip, a frame, a C shape or any other suitable shapes.
- FIGS. 7-9 are an embodiment of a semiconductor structure 300 .
- FIG. 7 is a schematic top view of the semiconductor structure 300 .
- FIG. 8 is a schematic cross sectional view of the semiconductor structure 300 along EE′ of FIG. 7 .
- FIG. 9 is a schematic cross sectional view of the semiconductor structure 300 along FF′ of FIG. 7 .
- the semiconductor structure 300 includes a substrate 101 , a first die 102 , a second die 302 , a first polymeric layer 103 , a second polymeric layer 303 , a molding 104 and a redistribution layer (RDL) 105 .
- the first die 102 and the second die 302 are integrated and packaged to become a semiconductor package.
- the semiconductor structure 300 is a fan out wafer level package. Although only two dies ( 102 and 302 ) are described below, the semiconductor structure 300 can include one or more dies. It is not intended to limit to two dies. Any number of dies in the semiconductor structure is also fallen into our intended scope, without departing from the spirit and scope of the present disclosure.
- the first die 102 and the second die 302 are disposed over the substrate 101 .
- the substrate 101 is a silicon substrate. In some embodiments, the substrate 101 has similar configuration as described above or illustrated in any one of FIGS. 1-6 .
- the first die 102 or the second die 302 includes semiconductive material such as silicon. In some embodiments, the first die 102 and the second die 302 have similar configuration as the die 102 described above or illustrated in any one of FIGS. 1-6 . In some embodiments, the first die 102 is substantially same as or different from the second die 302 . In some embodiments, the first die 102 and the second die 302 are different in applications, functions, structures, sizes, dimensions, shapes or etc.
- the first die 102 and the second die 302 perform different functions, or the first die 102 has a size same as or larger than the second die 302 , or a thickness of the first die 102 is same as or greater than a thickness of the second die 302 .
- the first die 102 is disposed adjacent to the second die 302 .
- the first die 102 is attached over a surface of the substrate 101 by a first adhesive 102 d
- the second die 302 is attached over the surface of the substrate 101 by a second adhesive 302 d .
- the first adhesive 102 d or the second adhesive 302 has similar configuration as the adhesive 102 d described above or illustrated in any one of FIGS. 1-6 .
- the first die 102 includes a first die pad 102 a disposed over the first die 102 and a first seal ring 102 b disposed within the first die 102 .
- a first passivation 102 c is disposed over the first die 102 and covers a portion of the first die pad 102 a .
- a first via 106 is disposed over and electrically connected with the first die pad 102 a .
- a first polymeric layer 103 is disposed over the first die 102 and surrounds the first via 106 .
- the first seal ring 102 b is configured for grounding or is connectable to ground.
- the first die pad 102 a , the first seal ring 102 b , the first passivation 102 c , the first via 106 and the first polymeric layer 103 have similar configuration as the die pad 102 a , the seal ring 102 b , the passivation 102 c , the via 106 and the polymeric layer 103 respectively described above or illustrated in any one of FIGS. 1-6 .
- the second die 302 includes a second die pad 302 a disposed over the second die 302 and a second seal ring 302 b disposed within the second die 302 .
- a second passivation 302 c is disposed over the second die 302 and covers a portion of the second die pad 302 a .
- the second die pad 302 a is electrically connected with the second seal ring 302 b .
- the second seal ring 302 b extends along a periphery of the second die 302 and at least partially encloses a central portion of the second die 302 .
- a second via 306 is disposed over and electrically connected with the second die pad 302 a .
- a second polymeric layer 303 is disposed over the second die 302 and surrounds the second via 306 .
- the second die pad 302 a , the second seal ring 302 b , the second passivation 302 c , the second via 306 and the second polymeric layer 303 are in similar configuration as the first die pad 102 a , the first seal ring 102 b , the first passivation 102 c , the first via 106 and the first polymeric layer 103 respectively.
- the first passivation 102 c and the first polymeric layer 103 are substantially same as the second passivation 302 c and the second polymeric layer 303 .
- the molding 104 is disposed over the substrate 101 and surrounds the first die 102 , the first passivation 102 c , the first polymeric layer 103 , the second die 302 , the second passivation 302 c and the second polymeric layer 303 . In some embodiments, a portion of the molding 104 is disposed between the first die 102 and the second die 302 . In some embodiments, the molding 104 has similar configuration as described above or illustrated in any one of FIGS. 1-6 .
- the RDL 105 is disposed over the molding 104 , the first die 102 and the second die 302 . In embodiments, the RDL 105 is disposed over the molding 104 , the first polymeric layer 103 and the second polymeric layer 303 . In some embodiments, the RDL 105 includes an interconnect structure 105 a and a dielectric layer 105 d surrounding the interconnect structure 105 a . In some embodiments, the interconnect structure 105 a includes a via portion 105 b coupled with the first via 106 and a land portion 105 c extending over the first die 102 . In some embodiments, the RDL 105 has similar configuration as described above or illustrated in any one of FIGS. 1-6 .
- the interconnect structure 105 a of the RDL 105 , the first via 106 , the first die pad 102 a and the first seal ring 102 b are electrically connected and thus are electrically grounded when the first seal ring 102 b is electrically grounded.
- the first seal ring 102 b , the first die pad 102 a , the first via 106 and the interconnect structure 105 a are cooperatively configured, so that the first die 102 is electrically isolated from the second die 302 , and thus electrical and electromagnetic interference between the first die 102 and the second die 302 could be minimized or prevented.
- FIGS. 10-12 are an embodiment of a semiconductor structure 400 .
- FIG. 10 is a schematic top view of the semiconductor structure 400 .
- FIG. 11 is a schematic cross sectional view of the semiconductor structure 400 along GG′ of FIG. 10 .
- FIG. 12 is a schematic cross sectional view of the semiconductor structure 400 along HH′ of FIG. 10 .
- the semiconductor structure 400 is in similar configuration as the semiconductor structure 300 illustrated in any one of FIGS. 7-9 .
- the RDL 105 can be in various configurations.
- the interconnect structure 105 a includes a via portion 105 b and a land portion 105 c coupled with the via portion 105 b .
- the land portion 105 c extends over the first polymeric layer 103 .
- the land portion 105 c extends over a periphery of the first die 102 , a central portion of the first die 102 or a portion of the first seal ring 102 b .
- the land portion 105 c partially encloses the central portion of the first die 102 .
- the land portion 105 c is in a strip, a frame, a C shape or any other suitable shapes.
- the RDL 105 of the semiconductor structure 400 has similar configuration as the RDL 105 of the semiconductor structure 300 described above or illustrated in any one of FIGS. 7-9 .
- FIGS. 13-15 are an embodiment of a semiconductor structure 500 .
- FIG. 13 is a schematic top view of the semiconductor structure 500 .
- FIG. 14 is a schematic cross sectional view of the semiconductor structure 500 along II′ of FIG. 13 .
- FIG. 15 is a schematic cross sectional view of the semiconductor structure 500 along JJ′ of FIG. 13 .
- the semiconductor structure 500 includes a substrate 101 , a first die 102 , a first polymeric layer 103 , a second die 302 , a second polymeric layer 303 , a molding 104 and a package seal ring 502 .
- the first die 102 and the second die 302 are disposed over the substrate 101 , and the molding 104 surrounds the first die 102 and the second die 302 .
- the first die 102 includes a first die pad 102 a disposed over the first die 102 .
- a first passivation 102 c is disposed over the first die 102 and covers a portion of the first die pad 102 a .
- the first polymeric layer 103 is disposed over the first die 102 .
- a first via 106 is disposed over and electrically connects the first die pad 102 a .
- the first polymeric layer 103 surrounds the first via 106 .
- the first die pad 102 a , the first passivation 102 c , the first via 106 and the first polymeric layer 103 have similar configuration as the die pad 102 a , the passivation 102 c , the via 106 and the polymeric layer 103 respectively described above or illustrated in any one of FIGS. 1-6 .
- the first die pad 102 a , the first passivation 102 c , the first via 106 and the first polymeric layer 103 have similar configuration as described above or illustrated in any one of FIGS. 7-12 .
- an electrical component 501 is disposed over the first die 102 .
- the second die 302 includes a second die pad 302 a disposed over the second die 302 .
- a second passivation 302 c is disposed over the second die 302 and covers a portion of the second die pad 302 a .
- the second polymeric layer 303 is disposed over the second die 302 .
- a second via 306 is disposed over and electrically connects the second die pad 302 a .
- the second t polymeric layer 303 surrounds the second via 306 .
- the second die pad 302 a , the second passivation 302 c , the second via 306 and the second polymeric layer 303 have similar configuration as the first die pad 102 a , the first passivation 102 c , the first via 106 and the first polymeric layer 103 respectively described above or illustrated in any one of FIGS. 1-12 .
- the second die pad 302 a , the second passivation 302 c , the second via 306 and the second polymeric layer 303 have similar configuration as described above or illustrated in any one of FIGS. 7-12 .
- the package seal ring 502 is disposed over the molding 104 . In some embodiments, the package seal ring 502 is disposed within a dielectric layer and is extended along a periphery of the semiconductor structure 500 . In some embodiments, the package seal ring 502 is at least partially around the first die 102 and the second die 302 . In some embodiments, the package seal ring 502 is disposed between the first die 102 and the second die 302 . In some embodiments, the package seal ring 502 includes conductive material such as copper, aluminum, silver, etc. In some embodiments, the package seal ring 502 is configured for grounding or is connectable to ground. Thus, the package seal ring 502 can electrically isolate the first die 102 from the second die 302 . An electrical or electromagnetic interference between the first die 102 and the second die 302 could be minimized or prevented.
- FIGS. 16-18 are an embodiment of a semiconductor structure 600 .
- FIG. 16 is a schematic top view of the semiconductor structure 600 .
- FIG. 17 is a schematic cross sectional view of the semiconductor structure 600 along KK′ of FIG. 16 .
- FIG. 18 is a schematic cross sectional view of the semiconductor structure 600 along LL′ of FIG. 16 .
- the semiconductor structure 600 includes a substrate 101 , a first die 102 , a first die pad 102 a , a first polymeric layer 103 , a first via 106 , a second die 302 , a second die pad 302 a , a second polymeric layer 303 , a second via 306 and a molding 104 , which have similar configuration as described above or illustrated in any one of FIGS. 13-15 .
- the semiconductor structure 600 includes a package redistribution layer (RDL) 601 disposed over the molding 104 .
- the package RDL 601 is disposed within a dielectric layer and is extended along a periphery of the semiconductor structure 600 .
- the package RDL 601 is at least partially around the first die 102 and the second die 302 .
- the package RDL 601 is disposed between the first die 102 and the second die 302 .
- the package RDL 601 includes conductive material such as copper, aluminum, silver, etc.
- the package RDL 601 is configured for grounding or is connectable to ground.
- the package RDL 601 can electrically isolate the first die 102 from the second die 302 . An electrical or electromagnetic interference between the first die 102 and the second die 302 could be minimized or prevented.
- FIGS. 19-21 are an embodiment of a semiconductor structure 700 .
- FIG. 19 is a schematic top view of the semiconductor structure 700 .
- FIG. 20 is a schematic cross sectional view of the semiconductor structure 700 along MM′ of FIG. 19 .
- FIG. 21 is a schematic cross sectional view of the semiconductor structure 700 along NN′ of FIG. 19 .
- the semiconductor structure 700 includes a substrate 101 . In some embodiments, the first die 102 and the second die 302 are disposed over the substrate 101 . In some embodiments, the substrate 101 includes a first RDL 701 . In some embodiments, the first RDL 701 includes a first interconnect structure 701 a and a dielectric layer surrounding the first interconnect structure 701 a . In some embodiments, the first interconnect structure 701 a includes conductive material such as copper, aluminum, silver, etc. In some embodiments, the first interconnect structure 701 a includes a via portion 701 b and a land portion 701 c coupled with the via portion 701 b .
- the land portion 701 c is extended along a periphery of the semiconductor structure 700 .
- the via portion 701 b is extended through the dielectric layer of the first RDL 701 .
- the first interconnect structure 701 a is configured for grounding or is connectable to ground.
- the semiconductor structure 700 includes a first die 102 , a first die pad 102 a , a first polymeric layer 103 , a first via 106 , a second die 302 , a second die pad 302 a , a second polymeric layer 303 , a second via 306 and a molding 104 , which have similar configuration as described above or illustrated in any one of FIGS. 13-18 .
- the semiconductor structure 700 includes a through via 703 extending within the molding 104 .
- the through via 703 extends from and electrically connected with the first interconnect structure 701 a of the first RDL 701 .
- the through via 703 is disposed over and electrically connected with the via portion 701 b of the first interconnect structure 701 a of the first RDL 701 .
- the through via is a through integrated fan out via (TIV).
- the through via 703 includes conductive material such as copper, aluminum, silver, etc.
- the through via 703 is disposed adjacent to the periphery of the semiconductor structure 700 .
- the through via 703 extends from the first RDL 701 to a second RDL 702 disposed over the molding 104 , the first die 102 and the second die 302 .
- the second RDL 702 includes a second interconnect structure 702 a and a dielectric layer surrounding the second interconnect structure 702 a .
- the second interconnect structure 702 a includes conductive material such as copper, aluminum, silver, etc.
- the second interconnect structure 702 a includes a via portion 702 b and a land portion 702 c coupled with the via portion 702 b .
- the land portion 702 c is extended along the periphery of the semiconductor structure 700 .
- the via portion 702 b is extended through the dielectric layer of the second RDL 702 .
- the via portion 701 b of the second RDL 702 is disposed over the through via 703 .
- the through via 703 extends from the via portion 701 b of the first RDL 701 to the via portion 702 b of the second RDL 702 , such that the first interconnect structure 701 a is electrically connected with the second interconnect structure 702 a through the through via 703 .
- the second interconnect structure 702 a is electrically grounded when the first interconnect structure 701 a is electrically grounded or connected to ground, as the second interconnect structure 702 a is electrically connected with the first interconnect structure 701 a .
- the first interconnect structure 701 a of the first RDL 701 and the second interconnect structure 702 b of the second RDL 702 are in cooperation to electrically isolate the first die 102 from the second die 302 .
- An electrical or electromagnetic interference between the first die 102 and the second die 302 could be minimized or prevented.
- FIGS. 22-24 are an embodiment of a semiconductor structure 800 .
- FIG. 22 is a schematic top view of the semiconductor structure 800 .
- FIG. 23 is a schematic cross sectional view of the semiconductor structure 800 along OO′ of FIG. 22 .
- FIG. 21 is a schematic cross sectional view of the semiconductor structure 800 along PP of FIG. 22 .
- the semiconductor structure 800 includes a first RDL 801 , a via 802 , a second RDL 803 , a die 804 , a source 805 and a molding 806 .
- the first RDL 801 includes a first interconnect structure 801 a and a first dielectric layer 801 b . In some embodiments, the first interconnect structure 801 a is surrounded by the first dielectric layer 801 b . In some embodiments, the first interconnect structure 801 a includes conductive material such as copper, aluminum or etc. In some embodiments, the first interconnect structure 801 includes a via portion 801 c and a land portion 801 d coupled with the via portion 801 c . In some embodiments, the via portion 801 c extends from the land portion 801 d through the first dielectric layer 801 b . In some embodiments, the land portion 801 d extends within the first dielectric layer 801 b . In some embodiments, the land portion 801 d is extended in various shapes such as a strip, a frame, an annular shape, C shape, etc.
- the via 802 is disposed over, extended from and electrically connected with the via portion 801 c of the first RDL 801 . In some embodiments, the via 802 extends through a third dielectric layer 802 a disposed over the first RDL 801 . In some embodiments, the via 802 electrically connects with the first interconnect structure 801 a of the first RDL 801 and extends through the third dielectric layer 802 a . In some embodiments, the via 802 includes conductive material such as copper, etc. In some embodiments, the via 802 is a through integrated fan out via. In some embodiments, the via 802 has a height of about 500 um or a diameter of about 100 um.
- the second RDL 803 includes a second interconnect structure 803 a and a second dielectric layer 803 b .
- the second interconnect structure 803 a is surrounded by the second dielectric layer 803 b .
- the second dielectric layer 803 b is disposed over the third dielectric layer 802 a and the via 802 .
- the second interconnect structure 803 a includes conductive material such as copper, aluminum or etc.
- the second interconnect structure 803 includes a via portion 803 c and a land portion 803 d coupled with the via portion 803 c .
- the via portion 803 c extends from the land portion 803 d through the second dielectric layer 803 b .
- the land portion 803 d extends within the second dielectric layer 803 b .
- the land portion 803 d is extended in various shapes such as a strip, a frame, an annular shape, C shape, etc.
- the first interconnect structure 801 a is substantially same or different from the second interconnect structure 803 a .
- the first dielectric layer 801 b is substantially same or different from the second dielectric layer 803 b or the third dielectric layer 802 a.
- the second interconnect structure 803 a electrically connects with the first conductive structure 801 a by the via 802 .
- the via 802 extends between the first RDL 801 and the second RDL 803 .
- the via 802 electrically connects the first interconnect structure 801 a with the second interconnect structure 803 a .
- the first interconnect structure 801 a and the second interconnect structure 803 a are aligned and disposed opposite to each other.
- the first interconnect structure 801 a and the second interconnect structure 803 a are configured in substantially same dimension and shape.
- the die 804 is disposed over the second RDL 803 , the via 802 or the first RDL 801 .
- the die 804 includes semiconductive material such as silicon and is fabricated with a predetermined functional circuit within the die 804 produced by photolithography operations.
- the die 804 is singulated from a silicon wafer by a mechanical or laser blade and then is disposed over the second dielectric layer 803 b .
- the die 804 is in a quadrilateral, a rectangular or a square shape.
- the molding 806 is disposed over the second RDL 803 and covers the die 804 .
- the source 805 is disposed within the die 804 and the second RDL 803 or is disposed within the first RDL 801 , the second RDL 803 and the third dielectric layer 802 a and the die 804 . In some embodiments, the source 805 is electrically connected with the die 804 . In some embodiments, the source 805 extends from the die 804 to the first RDL 801 or the second RDL 803 . In some embodiments, the source 805 extends from the die 804 to the first RDL 801 through the second RDL 803 and the third dielectric layer 802 a .
- a first portion of the source 805 is partially or wholly surrounded by the first interconnect structure 801 a of the first RDL 801 .
- a second portion of the source 805 is partially or wholly surrounded by the second interconnect structure 803 a of the second RDL 803 .
- the source 805 is configured to emit an electromagnetic radiation such as radio wave.
- the source 805 emits the electromagnetic radiation in a radio frequency (RF) such as lower than about 300 GHz, a range of about 3 kHz to about 300 GHz, etc. for wireless communication.
- RF radio frequency
- the source 805 is in a patch shape, spiral shape or other suitable shapes.
- the first interconnect structure 801 a of the first RDL 801 and the second interconnect structure 803 a of the second RDL 803 are configured to absorb an electromagnetic radiation.
- the first interconnect structure 801 a and the second interconnect structure 803 a are in cooperation to absorb the electromagnetic radiation in a predetermined frequency.
- the electromagnetic radiation emitted from the source 805 can be absorbed by the first interconnect structure 801 a and the second interconnect structure 803 a .
- the first interconnect structure 801 a and the second interconnect structure 803 a can absorb the electromagnetic radiation in the radio frequency emitted from the source 805 .
- the first interconnect structure 801 a and the second interconnect structure 803 a can absorb the electromagnetic radiation in the frequency of about 5 GHz to about 15 GHz emitted from the source 805 .
- the first interconnect structure 801 a and the second interconnect structure 803 a are configured to optimize an absorption of the electromagnetic radiation in the predetermined frequency, such that an electrical interference between the source 805 and other electrical component or source is in a minimal, and therefore a noise is reduced or prevented and a performance of the semiconductor structure 800 is improved.
- FIGS. 25-27 are an embodiment of a semiconductor structure 900 .
- FIG. 25 is a schematic top view of the semiconductor structure 900 .
- FIG. 26 is a schematic cross sectional view of the semiconductor structure 900 along QQ′ of FIG. 25 .
- FIG. 27 is a schematic cross sectional view of the semiconductor structure 900 along RR′ of FIG. 25 .
- the semiconductor structure 900 includes a first RDL 801 , a via 802 , a second RDL 803 , a first die 804 , a second die 807 , a source 805 , a component 808 and a molding 806 .
- FIG. 28 is a schematic exploded view of the semiconductor structure 900 including the first interconnect structure 801 a , the second interconnect structure 803 a and the via 802 coupling the first interconnect structure 801 a with the second interconnect structure 803 a.
- the first RDL 801 includes a first interconnect structure 801 a and a first dielectric layer 801 b .
- the first interconnect structure 801 a is surrounded by the first dielectric layer 801 b .
- the first interconnect structure 801 a includes conductive material such as copper, aluminum or etc.
- the first interconnect structure 801 includes several via portions 801 c and a land portion 801 d coupled with the via portions 801 c .
- each of the via portions 801 c extends from the land portion 801 d through the first dielectric layer 801 b .
- the land portion 801 d extends within the first dielectric layer 801 b .
- the land portion 801 d is extended in various shapes such as a strip, a frame, an annular shape, C shape, closed loop shape, etc.
- the vias 802 are disposed over, extended from and electrically connected with the via portions 801 c of the first RDL 801 respectively.
- the vias 802 extend through a third dielectric layer 802 a disposed over the first RDL 801 .
- the vias 802 electrically connects with the first interconnect structure 801 a of the first RDL 801 .
- the via 802 includes conductive material such as copper, etc.
- the via 802 is a through integrated fan out via.
- the via 802 has a height of about 500 um or a diameter of about 100 um.
- the second RDL 803 includes a second interconnect structure 803 a and a second dielectric layer 803 b .
- the second interconnect structure 803 a is surrounded by the second dielectric layer 803 b .
- the second dielectric layer 803 b is disposed over the third dielectric layer 802 a and the via 802 .
- the second interconnect structure 803 a includes conductive material such as copper, aluminum or etc.
- the second interconnect structure 803 includes several via portions 803 c and more than one land portions 803 d coupled with the via portions 803 c .
- the via portion 803 c extends from the land portion 803 d through the second dielectric layer 803 b .
- the land portion 803 d extends within the second dielectric layer 803 b .
- the land portion 803 d is extended in various shapes such as a strip, a frame, an annular shape, C shape, etc.
- the land portion 803 d includes two portions distanced from each other in a distance D of about 75 um to about 300 um. In some embodiments, the distance between the two portions of the land portion 803 d is about 175 um. In some embodiments, the land portions 803 d are in two half C shapes.
- the first interconnect structure 801 a is substantially same or different from the second interconnect structure 803 a .
- the first dielectric layer 801 b is substantially same or different from the second dielectric layer 803 b or the third dielectric layer 802 a.
- the second interconnect structure 803 a electrically connects with the first conductive structure 801 a by the vias 802 .
- the vias 802 extend between the first RDL 801 and the second RDL 803 .
- the vias 802 electrically connects the first interconnect structure 801 a with the second interconnect structure 803 a .
- the first interconnect structure 801 a and the second interconnect structure 803 a are aligned and disposed opposite to each other.
- the first die 804 and the second die 807 are disposed over the second RDL 803 .
- the first die 804 and the second die 807 include semiconductive material such as silicon and are fabricated with predetermined functional circuits.
- the first die 804 or the second die 807 is singulated from a silicon wafer by a mechanical or laser blade and then is disposed over the second dielectric layer 803 b .
- the first die 804 or the second die 807 is in a quadrilateral, a rectangular or a square shape.
- the molding 806 is disposed over the second RDL 803 and covers the first die 804 and the second die 807 .
- the source 805 is disposed within the first die 804 and the second RDL 803 or is disposed within the first RDL 801 , the second RDL 803 and the third dielectric layer 802 a and the first die 804 .
- the component 808 is disposed within the second die 807 and the second RDL 803 or is disposed within the first RDL 801 , the second RDL 803 and the third dielectric layer 802 a and the second die 807 .
- the source 805 and the component 808 are electrically connected with the first die 804 and the second die 807 respectively.
- a first portion of the source 805 and a first portion of the component 807 are surrounded by the first interconnect structure 801 a of the first RDL 801 .
- a second portion of the source 805 and a second portion of the component 808 are partially surrounded by the second interconnect structure 803 a of the second RDL 803 .
- the source 805 is configured to emit an electromagnetic radiation such as radio wave.
- the source 805 emit the electromagnetic radiation in a radio frequency (RF) such as lower than about 300 GHz, a range of about 3 kHz to about 300 GHz, etc. for wireless communication.
- RF radio frequency
- the source 805 is in a patch shape, spiral shape or other suitable shapes.
- the first interconnect structure 801 a of the first RDL 801 and the second interconnect structure 803 a of the second RDL 803 are configured to absorb the electromagnetic radiation emitted from the source 805 .
- the first interconnect structure 801 a and the second interconnect structure 803 a are in cooperation to absorb the electromagnetic radiation emitted from the source 805 in a predetermined frequency. In some embodiments, the first interconnect structure 801 a and the second interconnect structure 803 a can absorb the electromagnetic radiation in the predetermined frequency of about 5 GHz to about 15 GHz emitted from the source 805 .
- the first interconnect structure 801 a and the second interconnect structure 803 a are configured to optimize an absorption of the electromagnetic radiation emitted from the source 805 in the predetermined frequency, such that an electrical interference between the source 805 and the component 808 is in a minimal, and therefore a noise is reduced or prevented and a performance of the semiconductor structure 900 is improved.
- the source 805 and the component 808 are configured to emit an electromagnetic radiation such as radio wave respectively.
- the source 805 and the component 808 emit the electromagnetic radiation in a radio frequency (RF) such as lower than about 300 GHz, a range of about 3 kHz to about 300 GHz, etc. for wireless communication.
- the source 805 emits the electromagnetic radiation in the frequency substantially same or different from the frequency of the electromagnetic radiation emitted by the component 808 .
- the first interconnect structure 801 a and the second interconnect structure 803 a are configured to absorb the electromagnetic radiation emitted from the source 805 and the component 808 , such that the electromagnetic radiation emitted from the source 805 would not electrically interfere with the electromagnetic radiation emitted from the components 808 .
- the first interconnect structure 801 a and the second interconnect structure 803 a are configured to absorb the electromagnetic radiation of the predetermined frequency emitted from the source 805 or the component 808 .
- the electromagnetic radiation of the predetermined frequency emitted from the source 805 or the component 808 would not electromagnetically interfere or affect the source 805 or the component 808 .
- a method of manufacturing a semiconductor structure is also disclosed.
- a semiconductor structure ( 100 , 200 , 300 or 400 ) is formed by a method 1000 .
- FIG. 29 is an embodiment of the method 1000 of manufacturing the semiconductor structure ( 100 , 200 , 300 or 400 ).
- the method 1000 includes a number of operations ( 1001 , 1002 , 1003 , 1004 , 1005 , 1006 and 1007 ).
- the method 1000 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.
- a substrate 101 is received or provided as shown in FIG. 30A .
- the substrate 101 includes semiconductive material such as silicon, germanium, gallium, arsenic, and combinations thereof.
- the substrate 101 is a silicon substrate.
- the substrate 101 includes a variety of electrical components formed over or within the substrate 101 by several fabrication operations.
- the substrate 101 has similar configuration as described above or illustrated in any one of FIGS. 1-12 .
- a die (a first die 102 or a second die 302 ) is disposed over the substrate 101 as shown in FIG. 30B .
- the first die 102 is disposed over the substrate 101 by a first adhesive 102 d
- the second die 302 is disposed over the substrate 101 by a second adhesive 302 d .
- the first die 102 and the second die 302 are disposed simultaneously, or the second die 302 is disposed after disposing the first die 102 or vice versa.
- the first die 102 and the second die 302 include semiconductive material such as silicon.
- the first die 102 and the second die 302 are same or different from each other in various aspects such as size, dimension, shapes, functions, circuitries, etc. In some embodiments, the first die 102 and the second die 302 are fabricated to include same or different electrical components and structures to perform same or different functions.
- the first die 102 includes a first die pad 102 a disposed over the substrate 101 and a first seal ring 102 b formed at a periphery of the first die 102 and electrically connected with the first die pad 102 a .
- a first passivation 102 c is disposed over the first die 102 and covers a portion of the first die pad 102 a .
- the second die 302 includes a second die pad 302 a disposed over the substrate 101 and a second seal ring 302 b formed at a periphery of the second die 302 and electrically connected with the second die pad 302 a .
- a second passivation 302 c is disposed over the second die 302 and covers a portion of the second t die pad 302 a .
- the die (the first die 102 or the second die 302 ) has similar configuration as described above or illustrated in any one of FIGS. 1-12 .
- a via (a first via 106 or a second via 306 ) is formed over the die (the first die 102 or the second die 302 ) as shown in FIG. 30C .
- the first via 106 is disposed over the first die pad 102 a of the first die 102 .
- the second via 306 is disposed over the second die pad 302 a of the second die 302 .
- the via is formed by any suitable operations such as sputtering, electroplating, etc.
- the via (a first via 106 or a second via 306 ) is formed by disposing a conductive material over the first die pad 102 a .
- the first via 106 is substantially same or different from the second via 306 .
- the first via 106 and the second via 306 are formed simultaneously or one by one.
- the first via 106 is electrically connected with the first die pad 102 a and the first seal ring 102 b .
- the second via 306 is electrically connected with the second die pad 302 a and the second seal ring 102 b .
- the via (the first via 106 or the second via 306 ) has similar configuration as described above or illustrated in any one of FIGS. 1-12 .
- a polymeric layer (a first polymeric layer 103 or a second polymeric layer 303 ) is disposed over the die (the first die 102 or the second die 302 ) as shown in FIG. 30D .
- the first polymeric layer 103 is disposed over the first die 102 and covers the first via 106 .
- the second polymeric layer 303 is disposed over the second die 302 and covers the second via 306 .
- the first polymeric layer 103 and the second polymeric layer 303 are same or different from each other in various aspects such as materials.
- the first polymeric layer 103 and the second polymeric layer 303 are disposed simultaneously or one by one.
- the first polymeric layer 103 is patterned to form a recess 103 a .
- the recess 103 a exposes a portion of the first via 106 for receiving a conductive structure in subsequent operations.
- the recess 103 a is formed by photolithography and etching operations.
- the polymeric layer (the first polymeric layer 103 or the second polymeric layer 303 ) has similar configuration as described above or illustrated in any one of FIGS. 1-12 .
- a molding 104 is disposed over the substrate 101 as shown in FIG. 30E .
- the molding 104 is disposed over the substrate and surrounds the die (the first die 102 or the second die 302 ).
- the molding 104 has similar configuration as described above or illustrated in any one of FIGS. 1-12 .
- a redistribution layer (RDL) 105 is formed as shown in FIGS. 30F and 30G or 30H and 30I .
- the RDL 105 is disposed over the die (the first die 102 or the second die 302 ).
- the RDL 105 includes an interconnect structure 105 a and a dielectric layer 105 d surrounding the interconnect structure 105 a .
- the dielectric layer 105 d covers the molding 104 , the polymeric layer (the first polymeric layer 103 or the second polymeric layer 303 ) and the interconnect structure 105 a .
- the interconnect structure 105 a is formed over and electrically connected with the first via 106 so that the interconnect structure 105 a , the first via 106 , the first die pad 102 and the first seal ring 102 b are electrically connected.
- the interconnect structure 105 a includes a via portion 105 b and a land portion 105 c coupled with the via portion 105 b .
- the via portion 105 b contacts with the portion of the first via 106 exposed from the first polymeric layer 103 .
- the land portion 105 c extends within the dielectric layer 105 d and over a central portion of the first die 102 as shown in FIG. 30G (a top view of FIG.
- the RDL 105 has similar configuration as described above or illustrated in any one of FIGS. 1-12 .
- the first seal ring 102 b is configured for grounding or is connectable to ground as shown in FIGS. 30F and 30G or 30H and 30I .
- the first seal ring 102 b is connected to ground.
- the interconnect structure 105 a of the RDL 105 is connected to ground.
- the interconnect structure 105 a , the first via 106 , the first die pad 102 a are electrically grounded when the first seal ring 102 b is electrically grounded or connected to ground.
- a method of manufacturing a semiconductor structure 500 is also disclosed.
- a semiconductor structure 500 is formed by a method 2000 .
- FIG. 31 is an embodiment of the method 2000 of manufacturing the semiconductor structure 500 .
- the method 2000 includes a number of operations ( 2001 , 2002 , 2003 , 2004 , 2005 , 2006 and 2007 ).
- the method 2000 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.
- a substrate 101 is received or provided as shown in FIG. 32A .
- the operation 2001 is similar to the operation 1001 .
- a die (a first die 102 or a second die 302 ) is disposed over the substrate 101 as shown in FIG. 32B .
- the operation 2002 is similar to the operation 1002 .
- a via (a first via 106 or a second via 306 ) is formed over the die (the first die 102 or the second die 302 ) as shown in FIG. 32C .
- the operation 2003 is similar to the operation 1003 .
- a polymeric layer (a first polymeric layer 103 or a second polymeric layer 303 ) is disposed over the die (the first die 102 or the second die 302 ) as shown in FIG. 32D .
- the operation 2004 is similar to the operation 1004 .
- a molding 104 is disposed over the substrate 101 as shown in FIG. 32E .
- the operation 2005 is similar to the operation 1005 .
- a package seal ring is formed as shown in FIGS. 32F and 32G .
- the package seal ring 502 is formed over the molding 104 .
- the package seal ring 502 is disposed within a dielectric layer and is extended along a periphery of a semiconductor structure 500 .
- the package seal ring 502 at least partially surrounds the first die 102 and the second die 302 .
- the package seal ring 502 is disposed between the first die 102 and the second die 302 .
- the package seal ring 502 includes conductive material such as copper, aluminum, silver, etc.
- the package seal ring 502 is configured for grounding or is connectable to ground. In some embodiments, the package seal ring 502 is connected to ground (as illustrated in FIG. 32G which is a top view of FIG. 32F ). Thus, the package seal ring 502 can electrically isolate the first die 102 from the second die 302 . An electrical or electromagnetic interference between the first die 102 and the second die 302 could be minimized or prevented. In some embodiments, an electrical component 501 is disposed over the first die 102 .
- a method of manufacturing a semiconductor structure 600 is also disclosed.
- a semiconductor structure 600 is formed by a method 3000 .
- FIG. 33 is an embodiment of the method 3000 of manufacturing the semiconductor structure 600 .
- the method 3000 includes a number of operations ( 3001 , 3002 , 3003 , 3004 , 3005 , 3006 and 3007 ).
- the method 3000 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.
- a substrate 101 is received or provided as shown in FIG. 34A .
- the operation 3001 is similar to the operation 1001 or 2001 .
- a die (a first die 102 or a second die 302 ) is disposed over the substrate 101 as shown in FIG. 34B .
- the operation 3002 is similar to the operation 1002 or 2002 .
- a via (a first via 106 or a second via 306 ) is formed over the die (the first die 102 or the second die 302 ) as shown in FIG. 34C .
- the operation 3003 is similar to the operation 1003 or 2003 .
- a polymeric layer (a first polymeric layer 103 or a second polymeric layer 303 ) is disposed over the die (the first die 102 or the second die 302 ) as shown in FIG. 34D .
- the operation 3004 is similar to the operation 1004 or 2004 .
- a molding 104 is disposed over the substrate 101 as shown in FIG. 34E .
- the operation 3005 is similar to the operation 1005 or 2005 .
- a package RDL 601 is formed as shown in FIGS. 34F and 34G .
- the package RDL 601 is disposed over the molding 104 .
- the package RDL 601 is disposed within a dielectric layer and is extended along a periphery of a semiconductor structure 600 .
- the package RDL 601 at least partially surrounds the first die 102 and the second die 302 .
- the package RDL 601 is disposed between the first die 102 and the second die 302 .
- the package RDL 601 includes conductive material such as copper, aluminum, silver, etc.
- the package RDL 601 is formed by any suitable operations such as sputtering, electroplating, etc. In some embodiments, the package RDL 601 is configured for grounding or is connectable to ground. In some embodiments, the package RDL 601 is connected to ground (as illustrated in FIG. 34G which is a top view of FIG. 34F ). Thus, the package RDL 601 can electrically isolate the first die 102 from the second die 302 . An electrical or electromagnetic interference between the first die 102 and the second die 302 could be minimized or prevented.
- a method of manufacturing a semiconductor structure 700 is also disclosed.
- a semiconductor structure 700 is formed by a method 4000 .
- FIG. 35 is an embodiment of the method 4000 of manufacturing the semiconductor structure 700 .
- the method 4000 includes a number of operations ( 4001 , 4002 , 4003 , 4004 , 4005 , 4006 , 4007 and 4008 ).
- the method 4000 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.
- a substrate 101 is received or provided as shown in FIGS. 36A-36C .
- FIG. 36B is a schematic cross sectional view of FIG. 36A along MM′
- FIG. 36C is a schematic cross sectional view of FIG. 36C along NN′.
- the substrate 101 includes a first RDL 701 .
- the first RDL 701 includes a first interconnect structure 701 a and a dielectric layer surrounding the first interconnect structure 701 a .
- the first interconnect structure 701 a includes a via portion 701 b and a land portion 701 c coupled with the via portion 701 b .
- the land portion 701 c is extended along a periphery of the substrate 101 .
- the via portion 701 b is extended through the dielectric layer of the first RDL 701 .
- a die (a first die 102 or a second die 302 ) is disposed over the substrate 101 as shown in FIGS. 36D-36F .
- FIG. 36E is a schematic cross sectional view of FIG. 36D along MM′
- FIG. 36F is a schematic cross sectional view of FIG. 36D along NN′.
- the operation 4002 is similar to the operation 1002 , 2002 or 3002 .
- a via (a first via 106 or a second via 306 ) is formed over the die (the first die 102 or the second die 302 ) as shown in FIGS. 36D-36F .
- the operation 4003 is similar to the operation 1003 , 2003 or 3003 .
- a polymeric layer (a first polymeric layer 103 or a second polymeric layer 303 ) is disposed over the die (the first die 102 or the second die 302 ) as shown in FIGS. 36D-36F .
- the operation 4004 is similar to the operation 1004 , 2004 or 3004 .
- a molding 104 is disposed over the substrate 101 as shown in FIGS. 36G-36I .
- FIG. 36H is a schematic cross sectional view of FIG. 36G along MM′
- FIG. 36I is a schematic cross sectional view of FIG. 36G along NN′.
- the operation 4005 is similar to the operation 1005 , 2005 or 3005 .
- a through via 703 is formed as shown in FIGS. 36J-36L .
- FIG. 36K is a schematic cross sectional view of FIG. 36J along MM′
- FIG. 36L is a schematic cross sectional view of FIG. 36J along NN′.
- the through via 703 is formed by removing a portion of the molding 104 to form an opening and filling a conductive material within the opening.
- the through via 703 extends from the via portion 701 b of the first RDL 701 through the molding 104 , so that the first interconnect structure 701 a of the first RDL 701 is electrically connected with the through via 703 .
- the through via 703 is disposed adjacent to the periphery of the substrate 101 .
- a second RDL 702 is formed as shown in FIGS. 36M-36O .
- FIG. 36N is a schematic cross sectional view of FIG. 36M along MM′
- FIG. 36O is a schematic cross sectional view of FIG. 36M along NN′.
- the second RDL 702 is formed over the molding 104 , the first die 102 and the second die 302 .
- the second RDL 702 includes a second interconnect structure 702 a and a dielectric layer surrounding the second interconnect structure 702 a .
- the second interconnect structure 702 a includes a via portion 702 b and a land portion 702 c coupled with the via portion 702 b .
- the land portion 702 c is extended along the periphery of the substrate 101 or a semiconductor structure 700 .
- the via portion 702 b is extended through the dielectric layer of the second RDL 702 and contacts with the through via 703 .
- the first interconnect structure 701 a of the first RDL 701 is electrically connected with the second interconnect structure 702 a of the second RDL 702 by the through via 703 .
- the first RDL 701 is configured for grounding or is connectable to ground as shown in FIGS. 36M-36O .
- the first interconnect structure 701 a is electrically grounded or electrically connected to ground.
- the through via 703 and the second interconnect structure 702 a are electrically connected with the first interconnect structure 701 a and thus are also electrically grounded when the first interconnect structure 701 a is electrically grounded or is connected to ground.
- the first interconnect structure 701 a of the first RDL 701 , the through via 703 and the second interconnect structure 702 b of the second RDL 702 are in cooperation to electrically isolate the first die 102 from the second die 302 . An electrical or electromagnetic interference between the first die 102 and the second die 302 could be minimized or prevented.
- a method of manufacturing a semiconductor structure ( 800 or 900 ) is also disclosed.
- a semiconductor structure ( 800 or 900 ) is formed by a method 5000 .
- FIG. 37 is an embodiment of the method 5000 of manufacturing the semiconductor structure ( 800 or 900 ).
- the method 5000 includes a number of operations ( 5001 , 5002 , 5003 , 5004 , 5005 , 5006 , 5007 and 5008 ).
- the method 5000 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.
- a first RDL 801 is formed as shown in FIGS. 38A-38C .
- FIG. 38B is a schematic cross sectional view of FIG. 38A along QQ′
- FIG. 38C is a schematic cross sectional view of FIG. 38A along RR′.
- the first RDL 801 includes a first interconnect structure 801 a and a first dielectric layer 801 b .
- the first interconnect structure 801 a is surrounded by the first dielectric layer 801 b .
- the first interconnect structure 801 includes a via portion 801 c and a land portion 801 d coupled with the via portion 801 c .
- the via portion 801 c extends from the land portion 801 d through the first dielectric layer 801 b .
- the land portion 801 d extends within the first dielectric layer 801 b .
- the first interconnect structure 801 a is in a closed loop shape.
- a via 802 is formed over the first RDL 801 as shown in FIGS. 38D-38F .
- FIG. 38E is a schematic cross sectional view of FIG. 38D along QQ′
- FIG. 38F is a schematic cross sectional view of FIG. 38D along RR′.
- the via 802 is disposed over, extended from and electrically connected with the via portion 801 c of the first RDL 801 .
- the via 802 extends through a third dielectric layer 802 a disposed over the first RDL 801 .
- the via 802 electrically connects with the first interconnect structure 801 a of the first RDL 801 and extends through the third dielectric layer 802 a .
- the via 802 is formed by removing a portion of the third dielectric layer 802 a to form an opening and filling a conductive material within the opening.
- a portion of a source 805 and a portion of a component 808 are formed through the third dielectric layer 802 a and extended from the first RDL 801 .
- a second RDL 803 is formed as shown in FIGS. 38G-38I .
- FIG. 38 H is a schematic cross sectional view of FIG. 38G along QQ′
- FIG. 38I is a schematic cross sectional view of FIG. 38G along RR′.
- the second RDL 803 includes a second interconnect structure 803 a and a second dielectric layer 803 b .
- the second interconnect structure 803 a is surrounded by the second dielectric layer 803 b .
- the second dielectric layer 803 b is disposed over the third dielectric layer 802 a and the via 802 .
- the second interconnect structure 803 includes a via portion 803 c and a land portion 803 d coupled with the via portion 803 c .
- the via portion 803 c extends from the land portion 803 d through the second dielectric layer 803 b .
- the land portion 803 d extends within the second dielectric layer 803 b .
- the second interconnect structure 803 a is in a C shape or a flipped C shape.
- the first interconnect structure 801 a and the second interconnect structure 803 a are electrically connected by the via 802 .
- a portion of the source 805 and a portion of the component 808 are formed through the second dielectric layer 803 b and extended from the third dielectric layer 802 a.
- a die (a first die 804 or a second die 807 ) is disposed over the second RDL 803 as shown in FIGS. 38J-38L .
- FIG. 38K is a schematic cross sectional view of FIG. 38J along QQ′
- FIG. 38L is a schematic cross sectional view of FIG. 38J along RR′.
- the first die 804 is disposed over the source 805 .
- the second die 807 is disposed over the component 808 .
- the first die 804 and the second die 807 are disposed over the second RDL 803 simultaneously or one by one.
- the first die 804 is electrically connected to the source 805 .
- the second die 807 is electrically connected to the component 808 .
- the first interconnect structure 801 a and the second interconnect structure 803 a are configured to absorb an electromagnetic radiation of a predetermined frequency emitted from the source 805 or the component 808 , such that the source 805 or the component 808 would not electrically interfere with each other.
- a molding 806 is disposed over the die (the first die 804 or the second die 807 ) as shown in FIGS. 38M-38O .
- FIG. 38N is a schematic cross sectional view of FIG. 38M along QQ′
- FIG. 38O is a schematic cross sectional view of FIG. 38M along RR′.
- the molding 806 is disposed over the second RDL 803 and covers the die (the first die 804 or the second die 807 ).
- an improved semiconductor structure includes a die at least partially enclosed by a seal ring or a redistribution layer (RDL).
- the seal ring or the RDL is configured for grounding or is connectable to ground in order to isolate the die from other components.
- the semiconductor structure includes a source emitting an electromagnetic radiation such as a radio wave in a radio frequency (RF), and a RDL configured to absorb the electromagnetic radiation from the source.
- RF radio frequency
- the RDL can be configured to selectively absorb the electromagnetic radiation in a predetermined radio frequency.
- the RDL could isolate the source from other components and reduce electromagnetic interference between the electromagnetic radiation from the source and electromagnetic radiation from other components.
- a semiconductor structure includes a substrate, a die disposed over the substrate, and including a die pad disposed over the die and a seal ring disposed at a periphery of the die and electrically connected with the die pad, a polymeric layer disposed over the die, a via extending through the polymeric layer and electrically connected with the die pad, and a molding disposed over the substrate and surrounding the die and the polymeric layer, wherein the seal ring is configured for grounding.
- the seal ring extends along the periphery of the die to at least partially enclose a central portion of the die. In some embodiments, the seal ring is connectable to ground. In some embodiments, the via is disposed over the die pad and surrounded by the polymeric layer. In some embodiments, the semiconductor structure further includes a redistribution layer (RDL) disposed over the die and the molding, and including an interconnect structure electrically connecting with the via, the die pad and the seal ring. In some embodiments, the interconnect structure of the RDL is configured for grounding or is connectable to ground.
- RDL redistribution layer
- a semiconductor structure includes a first redistribution layer (RDL) including a first interconnect structure, a dielectric layer disposed over the first RDL, a via electrically connected with the first interconnect structure and extending through the dielectric layer, a second redistribution layer (RDL) disposed over the dielectric layer and the via, and including a second interconnect structure electrically connected with the first interconnect structure by the via, a die disposed over the second RDL, and a source electrically connected with the die, configured to emit an electromagnetic radiation, and disposed between the die and the first RDL, wherein the first interconnect structure of the first RDL and the second interconnect structure of the second RDL are configured to absorb the electromagnetic radiation of a predetermined frequency.
- RDL redistribution layer
- the first interconnect structure surrounds a first portion of the source, or the second interconnect structure partially surrounds a second portion of the source.
- the via extends between the first RDL and the second RDL and electrically connects the first interconnect structure with the second interconnect structure.
- the second interconnect structure is in a C shape, or the first interconnect structure is in an annular or a closed loop shape.
- the source extends from the die to the first RDL or the second RDL.
- the first interconnect structure and the second interconnect structure are aligned and disposed opposite to each other.
- the first interconnect structure and the second interconnect structure are configured in substantially same dimension and shape.
- the semiconductor structure further includes a molding disposed over the second RDL and covering the die.
- a method of manufacturing a semiconductor structure includes receiving a substrate, disposing a die over the substrate, wherein the die includes a die pad disposed over the substrate and a seal ring formed at a periphery of the die and electrically connected with the die pad, forming a via over the die pad of the die, disposing a polymeric layer over the die, disposing a molding over the substrate and surrounding the die and the polymeric layer, wherein the seal ring is configured for grounding.
- the seal ring is electrically connected with the via through the die pad.
- the via and the die pad are electrically grounded by grounding the seal ring.
- forming the via includes disposing a conductive material over the die pad.
- the method further includes forming a redistribution layer (RDL) over the polymeric layer, wherein the RDL includes an interconnect structure disposed within the RDL, electrically connected with the via, the die pad and the seal ring, and configured for grounding.
- the interconnect structure of the RDL extends along the periphery of the die or extends over a central portion of the die.
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor structure includes a substrate, a die disposed over the substrate, and including a die pad disposed over the die and a seal ring disposed at a periphery of the die and electrically connected with the die pad, a polymeric layer disposed over the die, a via extending through the polymeric layer and electrically connected with the die pad, and a molding disposed over the substrate and surrounding the die and the polymeric layer, wherein the seal ring is configured for grounding.
Description
- Electronic equipments using semiconductor devices are essential for many modern applications. The semiconductor devices are applied for a variety of high-density electronics applications. With the advancement of electronic technology, the electronic equipment is getting more complicated with greater functionality and greater amounts of integrated circuitry, while are becoming increasingly smaller in size. Due to the miniaturized scale of the electronic equipment, various types and dimensions of semiconductor devices perfoiming different functionalities are integrated and packaged into a single module. Furthermore, numerous manufacturing operations are implemented for integration of various types of semiconductor devices.
- However, the manufacturing and integration of the semiconductor devices involve many complicated steps and operations. The integration of the semiconductor devices in such low profile and high density becomes more complicated. An increase in a complexity of manufacturing and integration of the semiconductor devices may cause deficiencies such as contamination, poor electrical interconnection, noise coupling, delamination of the components or high yield loss.
- The semiconductor devices are integrated and produced in an undesired configuration, which would further exacerbate materials wastage and thus increase the manufacturing cost. Since more different components with different materials are involved, complexity of the manufacturing and integration operations of the semiconductor devices is increased. There are more challenges to modify a structure of the semiconductor device and improve the manufacturing operations. As such, there is a continuous need to improve the manufacturing the semiconductor devices and solve the above deficiencies.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 2 is a schematic cross sectional view of a semiconductor structure along AA′ ofFIG. 1 in accordance with some embodiments of the present disclosure. -
FIG. 3 is a schematic cross sectional view of a semiconductor structure along BB′ ofFIG. 1 in accordance with some embodiments of the present disclosure. -
FIG. 4 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 5 is a schematic cross sectional view of a semiconductor structure along CC′ ofFIG. 4 in accordance with some embodiments of the present disclosure. -
FIG. 6 is a schematic cross sectional view of a semiconductor structure along DD′ ofFIG. 4 in accordance with some embodiments of the present disclosure. -
FIG. 7 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 8 is a schematic cross sectional view of a semiconductor structure along EE′ ofFIG. 7 in accordance with some embodiments of the present disclosure. -
FIG. 9 is a schematic cross sectional view of a semiconductor structure along FF′ ofFIG. 7 in accordance with some embodiments of the present disclosure. -
FIG. 10 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 11 is a schematic cross sectional view of a semiconductor structure along GG′ ofFIG. 10 in accordance with some embodiments of the present disclosure. -
FIG. 12 is a schematic cross sectional view of a semiconductor structure along HH′ ofFIG. 10 in accordance with some embodiments of the present disclosure. -
FIG. 13 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 14 is a schematic cross sectional view of a semiconductor structure along II′ ofFIG. 13 in accordance with some embodiments of the present disclosure. -
FIG. 15 is a schematic cross sectional view of a semiconductor structure along JJ′ ofFIG. 13 in accordance with some embodiments of the present disclosure. -
FIG. 16 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 17 is a schematic cross sectional view of a semiconductor structure along KK′ ofFIG. 16 in accordance with some embodiments of the present disclosure. -
FIG. 18 is a schematic cross sectional view of a semiconductor structure along LL′ ofFIG. 16 in accordance with some embodiments of the present disclosure. -
FIG. 19 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 20 is a schematic cross sectional view of a semiconductor structure along MM′ ofFIG. 19 in accordance with some embodiments of the present disclosure. -
FIG. 21 is a schematic cross sectional view of a semiconductor structure along NN′ ofFIG. 19 in accordance with some embodiments of the present disclosure. -
FIG. 22 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 23 is a schematic cross sectional view of a semiconductor structure along OO′ ofFIG. 22 in accordance with some embodiments of the present disclosure. -
FIG. 24 is a schematic cross sectional view of a semiconductor structure along PP′ ofFIG. 22 in accordance with some embodiments of the present disclosure. -
FIG. 25 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 26 is a schematic cross sectional view of a semiconductor structure along QQ′ ofFIG. 25 in accordance with some embodiments of the present disclosure. -
FIG. 27 is a schematic cross sectional view of a semiconductor structure along RR′ ofFIG. 25 in accordance with some embodiments of the present disclosure. -
FIG. 28 is a schematic exploded view of a semiconductor structure ofFIGS. 25-27 in accordance with some embodiments of the present disclosure. -
FIG. 29 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIGS. 30A-30I are schematic views of manufacturing a semiconductor structure by a method ofFIG. 29 in accordance with some embodiments of the present disclosure. -
FIG. 31 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIGS. 32A-32G are schematic views of manufacturing a semiconductor structure by a method ofFIG. 31 in accordance with some embodiments of the present disclosure. -
FIG. 33 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIGS. 34A-34G are schematic views of manufacturing a semiconductor structure by a method ofFIG. 33 in accordance with some embodiments of the present disclosure. -
FIG. 35 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIGS. 36A-36O are schematic views of manufacturing a semiconductor structure by a method ofFIG. 35 in accordance with some embodiments of the present disclosure. -
FIG. 37 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIGS. 38A-38O are schematic views of manufacturing a semiconductor structure by a method ofFIG. 37 in accordance with some embodiments of the present disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- An electronic equipment including various semiconductor devices is manufactured by a number of operations. During the manufacturing, the semiconductor devices with different functionalities and dimensions are integrated into a single system. Circuitries of the semiconductor devices are integrated and connected through conductive traces and a substrate. After integration of the semiconductor devices, the semiconductor devices are encapsulated by a mold in order to protect the semiconductor devices from damages of the circuitries and environmental contamination. Also, a through silicon vias (TSV) is formed along a periphery of the semiconductor device to isolate the semiconductor devices from each other. However, the formation of the TSV would occupy large area and thus reduce space for electrical routing and lower a design freedom. The isolation by the TSV is unsatisfactory.
- Further, the semiconductor device may include a source emitting a radio wave in a radio frequency (RF). Such source requires isolation from external electromagnetic interference to prevent noise coupling. For example, the source has to be isolated from another source in order to prevent interference of the radio waves from the sources and noise affecting each other. Also, a leakage of radio wave out of the semiconductor device shall be prevented. The TSV is provided around the source for absorbing the radio wave and reducing interference of the radio waves between the source and another source. However, absorption of the radio wave in a particular frequency by the TSV could not be performed. Lack of selectivity of the frequency being absorbed would limit functionality and application of the semiconductor device.
- In the present disclosure, an improved semiconductor structure is disclosed. The semiconductor structure includes a die at least partially enclosed by a seal ring or a redistribution layer (RDL). The seal ring or the RDL is configured for grounding or is connectable to ground in order to isolate the die from other components. Since the seal ring and the RDL occupy less space and thus more space can be used for electrical routing. The grounding of the seal ring or the RDL could reduce or prevent noise coupling. Further, the semiconductor structure includes a source emitting an electromagnetic radiation such as radio wave in a radio frequency (RF), and a RDL configured to absorb the electromagnetic radiation from the source. The RDL can be configured to selectively absorb the electromagnetic radiation in a predetermined radio frequency. The RDL could isolate the source from other components and reduce electromagnetic interference between the electromagnetic radiation from the source and electromagnetic radiation from other components, such that noise can be minimized or prevented. An overall performance and reliability of the semiconductor structure could be improved.
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FIGS. 1-3 are an embodiment of asemiconductor structure 100.FIG. 1 is a schematic top view of thesemiconductor structure 100.FIG. 2 is a schematic cross sectional view of thesemiconductor structure 100 along AA′ ofFIG. 1 .FIG. 3 is a schematic cross sectional view of thesemiconductor structure 100 along BB′ ofFIG. 1 . - In some embodiments, the
semiconductor structure 100 includes asubstrate 101, adie 102, apolymeric layer 103, amolding 104 and a redistribution layer (RDL) 105. In some embodiments, thesemiconductor structure 100 is a fan out wafer level package, that input/output (I/O) terminals of a die are routed out and not limited to be disposed over a surface area of the die. The I/O terminals can be disposed outside the surface area of the die. - In some embodiments, the
substrate 101 includes semiconductive material such as silicon, germanium, gallium, arsenic, and combinations thereof. In some embodiments, thesubstrate 101 is a silicon substrate. In some embodiments, thesubstrate 101 includes a variety of electrical components formed over or within thesubstrate 101 by several fabrication operations. The electrical components can be various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, diodes or the like. The electrical components may be interconnected to perform one or more functions. - In some embodiments, the
die 102 is disposed over thesubstrate 101. In some embodiments, thedie 102 is disposed over a front side of thesubstrate 101. In some embodiments, thedie 102 is disposed and attached to thesubstrate 101 by an adhesive 102 d such as a die attach film (DAF), a tape or the like. In some embodiments, thedie 102 is a small piece including semiconductive material such as silicon and is fabricated with a predetermined functional circuit within thedie 102 produced by photolithography operations. In some embodiments, thedie 102 is singulated from a silicon wafer by a mechanical or laser blade and then is placed over thesubstrate 101 for subsequent manufacturing operations. In some embodiments, thedie 102 is in a quadrilateral, a rectangular or a square shape. - In some embodiments, the
die 102 includes adie pad 102 a, aseal ring 102 b and apassivation 102 c. In some embodiments, thedie pad 102 a is disposed over thedie 102. In some embodiments, thedie pad 102 a is disposed over an active surface or a top surface of thedie 102. In some embodiments, thedie pad 102 a is configured to electrically connect with a circuitry external to thedie 102, so that a circuitry internal to the die 102 electrically connects with the circuitry external to the die 102 through thedie pad 102 a. In some embodiments, thedie pad 102 a includes aluminum, copper, nickel, tungsten, gold, silver, palladium and/or alloys thereof. - In some embodiments, the
die pad 102 a is partially covered by thepassivation 102 c. In some embodiments, thedie pad 102 a is surrounded by thepassivation 102 c, and a portion of thedie pad 102 a is exposed from thepassivation 102 c. In some embodiments, the portion of thedie pad 102 a exposed from thepassivation 102 c is configured to subsequently receive a conductive structure such as a conductive trace. As such, thedie pad 102 a can electrically connect with a circuitry external to thedie 102. In some embodiments, thepassivation 102 c is configured to provide an electrical insulation and a moisture protection for thedie 102, so that thedie 102 is isolated from ambient environment. In some embodiments, thepassivation 102 c includes dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, spin-on glass (SOG), or the like. - In some embodiments, the
seal ring 102 b is disposed over or within thedie 102. As thedie 102 may be potentially damaged upon fabrication and singulation operations, theseal ring 102 b is configured to protect thedie 102. In some embodiments, theseal ring 102 b is served as a barrier for preventing contaminants such as moisture, chemicals, corrosive material or etc. from penetrating into thedie 102 and preventing cracks from propagating into thedie 102 upon singulation operations. In some embodiments, theseal ring 102 b includes conductive material (such as aluminum, copper, silver, etc.) disposed within a dielectric material (such as silicon oxide, silicon oxynitride, silicon nitride, etc.) of thedie 102. In some embodiments, theseal ring 102 b includes several stacked conductive layers interconnected by several of via layers. In some embodiments, the stacked conductive layers and the via layers are disposed alternatively. In some embodiments, theseal ring 102 b is electrically connected with thedie pad 102 a. In some embodiments, a portion of the conductive layers of theseal ring 102 b is coupled and electrically connected with thedie pad 102 a. - In some embodiments, the
seal ring 102 b is disposed at a periphery of thedie 102. In some embodiments, theseal ring 102 b extends along the periphery of the die 102 to at least partially enclose a central portion of thedie 102. In some embodiments as illustrated inFIG. 1 , theseal ring 102 b encloses the central portion of the die 120. In some embodiments, the conductive layers of theseal ring 102 b extend within the dielectric material of thedie 102 along the periphery of thedie 102. In some embodiments, theseal ring 102 b is in rectangular, quadrilateral or other suitable shapes. In some embodiments, theseal ring 102 b surrounds components and interconnections disposed over or within thedie 102, such that contamination and damage of thedie 102 would be prevented. - In some embodiments, the
seal ring 102 b is configured for grounding or is connectable to ground. In some embodiments as illustrated inFIG. 1 , theseal ring 102 b is electrically grounded or connected to ground. As such, thedie pad 102 a is also electrically grounded when theseal ring 102 b is electrically grounded or connected to ground. The grounding of theseal ring 102 b can provide isolation of the die 102 from other dies, circuitries or electrical components. In some embodiments, thedie 102 would be isolated and thus would not electrically or electromagnetically interfere with other dies, circuitries or electrical components upon an operation of thedie 102. - In some embodiments, a via 106 is disposed over the
die pad 102 a and thepassivation 102 c. In some embodiments, the via 106 is electrically connected with thedie pad 102 a. In some embodiments, the via 106 is extended through thepassivation 102 c to thedie pad 102 a. In some embodiments, the portion of thedie pad 102 a exposed from thepassivation 102 c is coupled with the via 106. In some embodiments, the via 106 includes conductive material such as copper, aluminum, silver or etc. In some embodiments, the via 106 is electrically connected with thedie pad 102 a and theseal ring 102 b. - In some embodiments, the
polymeric layer 103 is disposed over thedie 102. In some embodiments, thepolymeric layer 103 is disposed over thepassivation 102 c. In some embodiments, thepolymeric layer 103 surrounds the via 106. In some embodiments, the via 106 is at least partially covered by thepolymeric layer 103. In some embodiments, thepolymeric layer 103 includes polymeric material such as epoxy, polyimide, polybenzoxazole (PBO), solder resist (SR), ABF film, or the like. In some embodiments, thepolymeric layer 103 is patterned to provide a path for a conductive structure passing through and electrically connecting with the via 106 and thedie pad 102 a. In some embodiments, thepolymeric layer 103 includes arecess 103 a disposed over the via 106 and thedie pad 102 a. In some embodiments, therecess 103 a exposes a portion of the via 106, so that the via 106 can electrically connect with a conductive structure. - In some embodiments, the
molding 104 is disposed over thesubstrate 101 and surrounds thedie 102 and thepolymeric layer 103. In some embodiments, themolding 104 encapsulates thedie 102, thepassivation 102 c and thepolymeric layer 103. In some embodiments, themolding 104 includes a molding compound. The molding compound can be a single layer film or a composite stack. The molding compound includes various materials, for example, one or more of epoxy resins, phenolic hardeners, silicas, catalysts, pigments, mold release agents, and the like. Each of the materials for forming a molding compound has a high thermal conductivity, a low moisture absorption rate, a high flexural strength at board-mounting temperatures, or a combination of these. - In some embodiments, the
RDL 105 is disposed over thedie 102 and themolding 104. In some embodiments, theRDL 105 is a layer for routing the I/O terminals out from thedie 102. In some embodiments, theRDL 105 includes aninterconnect structure 105 a and adielectric layer 105 d surrounding theinterconnect structure 105 a. In some embodiments, theinterconnect structure 105 a includes conductive material such as copper, aluminum, silver, gold or etc. In some embodiments, thedielectric layer 105 d includes dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, etc. - In some embodiments, the
interconnect structure 105 a electrically connects with the via 106, thedie pad 102 a and theseal ring 102 b. In some embodiments, theinterconnect structure 105 a is disposed over thepolymeric layer 103 and conformal to therecess 103 a to couple with the via 106. In some embodiments, theinterconnect structure 105 a includes a viaportion 105 b and aland portion 105 c coupled with the viaportion 105 b. In some embodiments, the viaportion 105 b extends through thepolymeric layer 103 and couples with the via 106. In some embodiments, theland portion 105 c is disposed over thepolymeric layer 103. In some embodiments, theland portion 105 c extends along thedielectric layer 105 d and over the central portion of thedie 102. In some embodiments, theinterconnect structure 105 a of theRDL 105 is electrically grounded, as theinterconnect structure 105 a is electrically connected with theseal ring 102 b through thedie pad 102 a and thevia 106. In some embodiments, theinterconnect structure 105 a of theRDL 105 is configured for grounding or is connectable to ground. - In some embodiments, the
seal ring 102 b, thedie pad 102 a, the via 106 and theinterconnect structure 105 a of theRDL 105 are cooperatively configured, so that thedie 102 is electrically isolated from other electrical components or circuitries, and thus electrical or electromagnetic interference between the die 102 and other electrical components or circuitries could be minimized or prevented. -
FIGS. 4-6 are an embodiment of asemiconductor structure 200.FIG. 4 is a schematic top view of thesemiconductor structure 200.FIG. 5 is a schematic cross sectional view of thesemiconductor structure 200 along CC′ ofFIG. 4 .FIG. 6 is a schematic cross sectional view of thesemiconductor structure 100 along DD′ ofFIG. 4 . - In some embodiments, the
semiconductor structure 200 includes asubstrate 101, adie 102, apolymeric layer 103 and amolding 104, which have similar configuration as described above or illustrated inFIGS. 1-3 . In some embodiments, thesemiconductor structure 200 includes aRDL 105 disposed over themolding 104 and thepolymeric layer 103. In some embodiments, theRDL 105 includes aninterconnect structure 105 a and adielectric layer 105 d surrounding theinterconnect structure 105 a. In some embodiments, theinterconnect structure 105 a of theRDL 105 is electrically grounded, as theinterconnect structure 105 a is electrically connected with theseal ring 102 b through thedie pad 102 a and thevia 106. In some embodiments, theinterconnect structure 105 a of theRDL 105 is configured for grounding or is connectable to ground. - The
RDL 105 can be in various configurations. In some embodiments, theinterconnect structure 105 a includes a viaportion 105 b and aland portion 105 c coupled with the viaportion 105 b. In some embodiments, theland portion 105 c extends over thepolymeric layer 103. In some embodiments theland portion 105 c extends over periphery of thedie 102, a central portion of the die 102 or a portion of theseal ring 102 b. In some embodiments, theland portion 105 c partially encloses the central portion of thedie 102. In some embodiments, theland portion 105 c is in a strip, a frame, a C shape or any other suitable shapes. -
FIGS. 7-9 are an embodiment of asemiconductor structure 300.FIG. 7 is a schematic top view of thesemiconductor structure 300.FIG. 8 is a schematic cross sectional view of thesemiconductor structure 300 along EE′ ofFIG. 7 .FIG. 9 is a schematic cross sectional view of thesemiconductor structure 300 along FF′ ofFIG. 7 . - In some embodiments, the
semiconductor structure 300 includes asubstrate 101, afirst die 102, asecond die 302, afirst polymeric layer 103, asecond polymeric layer 303, amolding 104 and a redistribution layer (RDL) 105. In some embodiments, thefirst die 102 and thesecond die 302 are integrated and packaged to become a semiconductor package. In some embodiments, thesemiconductor structure 300 is a fan out wafer level package. Although only two dies (102 and 302) are described below, thesemiconductor structure 300 can include one or more dies. It is not intended to limit to two dies. Any number of dies in the semiconductor structure is also fallen into our intended scope, without departing from the spirit and scope of the present disclosure. - In some embodiments, the
first die 102 and thesecond die 302 are disposed over thesubstrate 101. In some embodiments, thesubstrate 101 is a silicon substrate. In some embodiments, thesubstrate 101 has similar configuration as described above or illustrated in any one ofFIGS. 1-6 . In some embodiments, thefirst die 102 or thesecond die 302 includes semiconductive material such as silicon. In some embodiments, thefirst die 102 and thesecond die 302 have similar configuration as thedie 102 described above or illustrated in any one ofFIGS. 1-6 . In some embodiments, thefirst die 102 is substantially same as or different from thesecond die 302. In some embodiments, thefirst die 102 and thesecond die 302 are different in applications, functions, structures, sizes, dimensions, shapes or etc. For example, thefirst die 102 and thesecond die 302 perform different functions, or thefirst die 102 has a size same as or larger than thesecond die 302, or a thickness of thefirst die 102 is same as or greater than a thickness of thesecond die 302. - In some embodiments, the
first die 102 is disposed adjacent to thesecond die 302. In some embodiments, thefirst die 102 is attached over a surface of thesubstrate 101 by afirst adhesive 102 d, and thesecond die 302 is attached over the surface of thesubstrate 101 by asecond adhesive 302 d. In some embodiments, thefirst adhesive 102 d or thesecond adhesive 302 has similar configuration as the adhesive 102 d described above or illustrated in any one ofFIGS. 1-6 . - In some embodiments, the
first die 102 includes afirst die pad 102 a disposed over thefirst die 102 and afirst seal ring 102 b disposed within thefirst die 102. In some embodiments, afirst passivation 102 c is disposed over thefirst die 102 and covers a portion of thefirst die pad 102 a. In some embodiments, a first via 106 is disposed over and electrically connected with thefirst die pad 102 a. In some embodiments, afirst polymeric layer 103 is disposed over thefirst die 102 and surrounds the first via 106. In some embodiments, thefirst seal ring 102 b is configured for grounding or is connectable to ground. In some embodiments, thefirst die pad 102 a, thefirst seal ring 102 b, thefirst passivation 102 c, the first via 106 and thefirst polymeric layer 103 have similar configuration as thedie pad 102 a, theseal ring 102 b, thepassivation 102 c, the via 106 and thepolymeric layer 103 respectively described above or illustrated in any one ofFIGS. 1-6 . - In some embodiments, the
second die 302 includes asecond die pad 302 a disposed over thesecond die 302 and asecond seal ring 302 b disposed within thesecond die 302. In some embodiments, asecond passivation 302 c is disposed over thesecond die 302 and covers a portion of thesecond die pad 302 a. In some embodiments, thesecond die pad 302 a is electrically connected with thesecond seal ring 302 b. In some embodiments, thesecond seal ring 302 b extends along a periphery of thesecond die 302 and at least partially encloses a central portion of thesecond die 302. In some embodiments, a second via 306 is disposed over and electrically connected with thesecond die pad 302 a. In some embodiments, asecond polymeric layer 303 is disposed over thesecond die 302 and surrounds the second via 306. In some embodiments, thesecond die pad 302 a, thesecond seal ring 302 b, thesecond passivation 302 c, the second via 306 and thesecond polymeric layer 303 are in similar configuration as thefirst die pad 102 a, thefirst seal ring 102 b, thefirst passivation 102 c, the first via 106 and thefirst polymeric layer 103 respectively. In some embodiments, thefirst passivation 102 c and thefirst polymeric layer 103 are substantially same as thesecond passivation 302 c and thesecond polymeric layer 303. - In some embodiments, the
molding 104 is disposed over thesubstrate 101 and surrounds thefirst die 102, thefirst passivation 102 c, thefirst polymeric layer 103, thesecond die 302, thesecond passivation 302 c and thesecond polymeric layer 303. In some embodiments, a portion of themolding 104 is disposed between thefirst die 102 and thesecond die 302. In some embodiments, themolding 104 has similar configuration as described above or illustrated in any one ofFIGS. 1-6 . - In some embodiments, the
RDL 105 is disposed over themolding 104, thefirst die 102 and thesecond die 302. In embodiments, theRDL 105 is disposed over themolding 104, thefirst polymeric layer 103 and thesecond polymeric layer 303. In some embodiments, theRDL 105 includes aninterconnect structure 105 a and adielectric layer 105 d surrounding theinterconnect structure 105 a. In some embodiments, theinterconnect structure 105 a includes a viaportion 105 b coupled with the first via 106 and aland portion 105 c extending over thefirst die 102. In some embodiments, theRDL 105 has similar configuration as described above or illustrated in any one ofFIGS. 1-6 . - In some embodiments, the
interconnect structure 105 a of theRDL 105, the first via 106, thefirst die pad 102 a and thefirst seal ring 102 b are electrically connected and thus are electrically grounded when thefirst seal ring 102 b is electrically grounded. Thefirst seal ring 102 b, thefirst die pad 102 a, the first via 106 and theinterconnect structure 105 a are cooperatively configured, so that thefirst die 102 is electrically isolated from thesecond die 302, and thus electrical and electromagnetic interference between thefirst die 102 and thesecond die 302 could be minimized or prevented. -
FIGS. 10-12 are an embodiment of asemiconductor structure 400.FIG. 10 is a schematic top view of thesemiconductor structure 400.FIG. 11 is a schematic cross sectional view of thesemiconductor structure 400 along GG′ ofFIG. 10 .FIG. 12 is a schematic cross sectional view of thesemiconductor structure 400 along HH′ ofFIG. 10 . In some embodiments, thesemiconductor structure 400 is in similar configuration as thesemiconductor structure 300 illustrated in any one ofFIGS. 7-9 . - In some embodiments, the
RDL 105 can be in various configurations. In some embodiments, theinterconnect structure 105 a includes a viaportion 105 b and aland portion 105 c coupled with the viaportion 105 b. In some embodiments, theland portion 105 c extends over thefirst polymeric layer 103. In some embodiments theland portion 105 c extends over a periphery of thefirst die 102, a central portion of thefirst die 102 or a portion of thefirst seal ring 102 b. In some embodiments, theland portion 105 c partially encloses the central portion of thefirst die 102. In some embodiments, theland portion 105 c is in a strip, a frame, a C shape or any other suitable shapes. In some embodiments, theRDL 105 of thesemiconductor structure 400 has similar configuration as theRDL 105 of thesemiconductor structure 300 described above or illustrated in any one ofFIGS. 7-9 . -
FIGS. 13-15 are an embodiment of asemiconductor structure 500.FIG. 13 is a schematic top view of thesemiconductor structure 500.FIG. 14 is a schematic cross sectional view of thesemiconductor structure 500 along II′ ofFIG. 13 .FIG. 15 is a schematic cross sectional view of thesemiconductor structure 500 along JJ′ ofFIG. 13 . - In some embodiments, the
semiconductor structure 500 includes asubstrate 101, afirst die 102, afirst polymeric layer 103, asecond die 302, asecond polymeric layer 303, amolding 104 and apackage seal ring 502. In some embodiments, thefirst die 102 and thesecond die 302 are disposed over thesubstrate 101, and themolding 104 surrounds thefirst die 102 and thesecond die 302. - In some embodiments, the
first die 102 includes afirst die pad 102 a disposed over thefirst die 102. In some embodiments, afirst passivation 102 c is disposed over thefirst die 102 and covers a portion of thefirst die pad 102 a. In some embodiments, thefirst polymeric layer 103 is disposed over thefirst die 102. In some embodiments, a first via 106 is disposed over and electrically connects thefirst die pad 102 a. In some embodiments, thefirst polymeric layer 103 surrounds the first via 106. In some embodiments, thefirst die pad 102 a, thefirst passivation 102 c, the first via 106 and thefirst polymeric layer 103 have similar configuration as thedie pad 102 a, thepassivation 102 c, the via 106 and thepolymeric layer 103 respectively described above or illustrated in any one ofFIGS. 1-6 . In some embodiments, thefirst die pad 102 a, thefirst passivation 102 c, the first via 106 and thefirst polymeric layer 103 have similar configuration as described above or illustrated in any one ofFIGS. 7-12 . In some embodiments, anelectrical component 501 is disposed over thefirst die 102. - In some embodiments, the
second die 302 includes asecond die pad 302 a disposed over thesecond die 302. In some embodiments, asecond passivation 302 c is disposed over thesecond die 302 and covers a portion of thesecond die pad 302 a. In some embodiments, thesecond polymeric layer 303 is disposed over thesecond die 302. In some embodiments, a second via 306 is disposed over and electrically connects thesecond die pad 302 a. In some embodiments, the secondt polymeric layer 303 surrounds the second via 306. In some embodiments, thesecond die pad 302 a, thesecond passivation 302 c, the second via 306 and thesecond polymeric layer 303 have similar configuration as thefirst die pad 102 a, thefirst passivation 102 c, the first via 106 and thefirst polymeric layer 103 respectively described above or illustrated in any one ofFIGS. 1-12 . In some embodiments, thesecond die pad 302 a, thesecond passivation 302 c, the second via 306 and thesecond polymeric layer 303 have similar configuration as described above or illustrated in any one ofFIGS. 7-12 . - In some embodiments, the
package seal ring 502 is disposed over themolding 104. In some embodiments, thepackage seal ring 502 is disposed within a dielectric layer and is extended along a periphery of thesemiconductor structure 500. In some embodiments, thepackage seal ring 502 is at least partially around thefirst die 102 and thesecond die 302. In some embodiments, thepackage seal ring 502 is disposed between thefirst die 102 and thesecond die 302. In some embodiments, thepackage seal ring 502 includes conductive material such as copper, aluminum, silver, etc. In some embodiments, thepackage seal ring 502 is configured for grounding or is connectable to ground. Thus, thepackage seal ring 502 can electrically isolate thefirst die 102 from thesecond die 302. An electrical or electromagnetic interference between thefirst die 102 and thesecond die 302 could be minimized or prevented. -
FIGS. 16-18 are an embodiment of asemiconductor structure 600.FIG. 16 is a schematic top view of thesemiconductor structure 600.FIG. 17 is a schematic cross sectional view of thesemiconductor structure 600 along KK′ ofFIG. 16 .FIG. 18 is a schematic cross sectional view of thesemiconductor structure 600 along LL′ ofFIG. 16 . - In some embodiments, the
semiconductor structure 600 includes asubstrate 101, afirst die 102, afirst die pad 102 a, afirst polymeric layer 103, a first via 106, asecond die 302, asecond die pad 302 a, asecond polymeric layer 303, a second via 306 and amolding 104, which have similar configuration as described above or illustrated in any one ofFIGS. 13-15 . - In some embodiments, the
semiconductor structure 600 includes a package redistribution layer (RDL) 601 disposed over themolding 104. In some embodiments, thepackage RDL 601 is disposed within a dielectric layer and is extended along a periphery of thesemiconductor structure 600. In some embodiments, thepackage RDL 601 is at least partially around thefirst die 102 and thesecond die 302. In some embodiments, thepackage RDL 601 is disposed between thefirst die 102 and thesecond die 302. In some embodiments, thepackage RDL 601 includes conductive material such as copper, aluminum, silver, etc. In some embodiments, thepackage RDL 601 is configured for grounding or is connectable to ground. Thus, thepackage RDL 601 can electrically isolate thefirst die 102 from thesecond die 302. An electrical or electromagnetic interference between thefirst die 102 and thesecond die 302 could be minimized or prevented. -
FIGS. 19-21 are an embodiment of asemiconductor structure 700.FIG. 19 is a schematic top view of thesemiconductor structure 700.FIG. 20 is a schematic cross sectional view of thesemiconductor structure 700 along MM′ ofFIG. 19 .FIG. 21 is a schematic cross sectional view of thesemiconductor structure 700 along NN′ ofFIG. 19 . - In some embodiments, the
semiconductor structure 700 includes asubstrate 101. In some embodiments, thefirst die 102 and thesecond die 302 are disposed over thesubstrate 101. In some embodiments, thesubstrate 101 includes afirst RDL 701. In some embodiments, thefirst RDL 701 includes afirst interconnect structure 701 a and a dielectric layer surrounding thefirst interconnect structure 701 a. In some embodiments, thefirst interconnect structure 701 a includes conductive material such as copper, aluminum, silver, etc. In some embodiments, thefirst interconnect structure 701 a includes a viaportion 701 b and aland portion 701 c coupled with the viaportion 701 b. In some embodiments, theland portion 701 c is extended along a periphery of thesemiconductor structure 700. In some embodiments, the viaportion 701 b is extended through the dielectric layer of thefirst RDL 701. In some embodiments, thefirst interconnect structure 701 a is configured for grounding or is connectable to ground. - In some embodiments, the
semiconductor structure 700 includes afirst die 102, afirst die pad 102 a, afirst polymeric layer 103, a first via 106, asecond die 302, asecond die pad 302 a, asecond polymeric layer 303, a second via 306 and amolding 104, which have similar configuration as described above or illustrated in any one ofFIGS. 13-18 . - In some embodiments, the
semiconductor structure 700 includes a through via 703 extending within themolding 104. In some embodiments, the through via 703 extends from and electrically connected with thefirst interconnect structure 701 a of thefirst RDL 701. In some embodiments, the through via 703 is disposed over and electrically connected with the viaportion 701 b of thefirst interconnect structure 701 a of thefirst RDL 701. In some embodiments, the through via is a through integrated fan out via (TIV). In some embodiments, the through via 703 includes conductive material such as copper, aluminum, silver, etc. In some embodiments, the through via 703 is disposed adjacent to the periphery of thesemiconductor structure 700. - In some embodiments, the through via 703 extends from the
first RDL 701 to asecond RDL 702 disposed over themolding 104, thefirst die 102 and thesecond die 302. In some embodiments, thesecond RDL 702 includes asecond interconnect structure 702 a and a dielectric layer surrounding thesecond interconnect structure 702 a. In some embodiments, thesecond interconnect structure 702 a includes conductive material such as copper, aluminum, silver, etc. In some embodiments, thesecond interconnect structure 702 a includes a viaportion 702 b and aland portion 702 c coupled with the viaportion 702 b. In some embodiments, theland portion 702 c is extended along the periphery of thesemiconductor structure 700. In some embodiments, the viaportion 702 b is extended through the dielectric layer of thesecond RDL 702. - In some embodiments, the via
portion 701 b of thesecond RDL 702 is disposed over the through via 703. In some embodiments, the through via 703 extends from the viaportion 701 b of thefirst RDL 701 to the viaportion 702 b of thesecond RDL 702, such that thefirst interconnect structure 701 a is electrically connected with thesecond interconnect structure 702 a through the through via 703. In some embodiments, thesecond interconnect structure 702 a is electrically grounded when thefirst interconnect structure 701 a is electrically grounded or connected to ground, as thesecond interconnect structure 702 a is electrically connected with thefirst interconnect structure 701 a. Therefore, thefirst interconnect structure 701 a of thefirst RDL 701 and thesecond interconnect structure 702 b of thesecond RDL 702 are in cooperation to electrically isolate thefirst die 102 from thesecond die 302. An electrical or electromagnetic interference between thefirst die 102 and thesecond die 302 could be minimized or prevented. -
FIGS. 22-24 are an embodiment of asemiconductor structure 800.FIG. 22 is a schematic top view of thesemiconductor structure 800.FIG. 23 is a schematic cross sectional view of thesemiconductor structure 800 along OO′ ofFIG. 22 .FIG. 21 is a schematic cross sectional view of thesemiconductor structure 800 along PP ofFIG. 22 . In some embodiments, thesemiconductor structure 800 includes afirst RDL 801, a via 802, asecond RDL 803, adie 804, asource 805 and amolding 806. - In some embodiments, the
first RDL 801 includes afirst interconnect structure 801 a and a firstdielectric layer 801 b. In some embodiments, thefirst interconnect structure 801 a is surrounded by thefirst dielectric layer 801 b. In some embodiments, thefirst interconnect structure 801 a includes conductive material such as copper, aluminum or etc. In some embodiments, thefirst interconnect structure 801 includes a viaportion 801 c and aland portion 801 d coupled with the viaportion 801 c. In some embodiments, the viaportion 801 c extends from theland portion 801 d through thefirst dielectric layer 801 b. In some embodiments, theland portion 801 d extends within thefirst dielectric layer 801 b. In some embodiments, theland portion 801 d is extended in various shapes such as a strip, a frame, an annular shape, C shape, etc. - In some embodiments, the via 802 is disposed over, extended from and electrically connected with the via
portion 801 c of thefirst RDL 801. In some embodiments, the via 802 extends through a thirddielectric layer 802 a disposed over thefirst RDL 801. In some embodiments, the via 802 electrically connects with thefirst interconnect structure 801 a of thefirst RDL 801 and extends through the thirddielectric layer 802 a. In some embodiments, the via 802 includes conductive material such as copper, etc. In some embodiments, the via 802 is a through integrated fan out via. In some embodiments, the via 802 has a height of about 500 um or a diameter of about 100 um. - In some embodiments, the
second RDL 803 includes asecond interconnect structure 803 a and asecond dielectric layer 803 b. In some embodiments, thesecond interconnect structure 803 a is surrounded by thesecond dielectric layer 803 b. In some embodiments, thesecond dielectric layer 803 b is disposed over the thirddielectric layer 802 a and thevia 802. In some embodiments, thesecond interconnect structure 803 a includes conductive material such as copper, aluminum or etc. In some embodiments, thesecond interconnect structure 803 includes a viaportion 803 c and aland portion 803 d coupled with the viaportion 803 c. In some embodiments, the viaportion 803 c extends from theland portion 803 d through thesecond dielectric layer 803 b. In some embodiments, theland portion 803 d extends within thesecond dielectric layer 803 b. In some embodiments, theland portion 803 d is extended in various shapes such as a strip, a frame, an annular shape, C shape, etc. In some embodiments, thefirst interconnect structure 801 a is substantially same or different from thesecond interconnect structure 803 a. In some embodiments, thefirst dielectric layer 801 b is substantially same or different from thesecond dielectric layer 803 b or the thirddielectric layer 802 a. - In some embodiments, the
second interconnect structure 803 a electrically connects with the firstconductive structure 801 a by thevia 802. In some embodiments, the via 802 extends between thefirst RDL 801 and thesecond RDL 803. In some embodiments, the via 802 electrically connects thefirst interconnect structure 801 a with thesecond interconnect structure 803 a. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a are aligned and disposed opposite to each other. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a are configured in substantially same dimension and shape. - In some embodiments, the
die 804 is disposed over thesecond RDL 803, the via 802 or thefirst RDL 801. In some embodiments, thedie 804 includes semiconductive material such as silicon and is fabricated with a predetermined functional circuit within thedie 804 produced by photolithography operations. In some embodiments, thedie 804 is singulated from a silicon wafer by a mechanical or laser blade and then is disposed over thesecond dielectric layer 803 b. In some embodiments, thedie 804 is in a quadrilateral, a rectangular or a square shape. In some embodiments, themolding 806 is disposed over thesecond RDL 803 and covers thedie 804. - In some embodiments, the
source 805 is disposed within thedie 804 and thesecond RDL 803 or is disposed within thefirst RDL 801, thesecond RDL 803 and the thirddielectric layer 802 a and thedie 804. In some embodiments, thesource 805 is electrically connected with thedie 804. In some embodiments, thesource 805 extends from thedie 804 to thefirst RDL 801 or thesecond RDL 803. In some embodiments, thesource 805 extends from thedie 804 to thefirst RDL 801 through thesecond RDL 803 and the thirddielectric layer 802 a. In some embodiments, a first portion of thesource 805 is partially or wholly surrounded by thefirst interconnect structure 801 a of thefirst RDL 801. In some embodiments, a second portion of thesource 805 is partially or wholly surrounded by thesecond interconnect structure 803 a of thesecond RDL 803. In some embodiments, thesource 805 is configured to emit an electromagnetic radiation such as radio wave. In some embodiments, thesource 805 emits the electromagnetic radiation in a radio frequency (RF) such as lower than about 300 GHz, a range of about 3 kHz to about 300 GHz, etc. for wireless communication. In some embodiments, thesource 805 is in a patch shape, spiral shape or other suitable shapes. - In some embodiments, the
first interconnect structure 801 a of thefirst RDL 801 and thesecond interconnect structure 803 a of thesecond RDL 803 are configured to absorb an electromagnetic radiation. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a are in cooperation to absorb the electromagnetic radiation in a predetermined frequency. In some embodiments, the electromagnetic radiation emitted from thesource 805 can be absorbed by thefirst interconnect structure 801 a and thesecond interconnect structure 803 a. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a can absorb the electromagnetic radiation in the radio frequency emitted from thesource 805. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a can absorb the electromagnetic radiation in the frequency of about 5 GHz to about 15 GHz emitted from thesource 805. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a are configured to optimize an absorption of the electromagnetic radiation in the predetermined frequency, such that an electrical interference between thesource 805 and other electrical component or source is in a minimal, and therefore a noise is reduced or prevented and a performance of thesemiconductor structure 800 is improved. -
FIGS. 25-27 are an embodiment of asemiconductor structure 900.FIG. 25 is a schematic top view of thesemiconductor structure 900.FIG. 26 is a schematic cross sectional view of thesemiconductor structure 900 along QQ′ ofFIG. 25 .FIG. 27 is a schematic cross sectional view of thesemiconductor structure 900 along RR′ ofFIG. 25 . In some embodiments, thesemiconductor structure 900 includes afirst RDL 801, a via 802, asecond RDL 803, afirst die 804, asecond die 807, asource 805, acomponent 808 and amolding 806.FIG. 28 is a schematic exploded view of thesemiconductor structure 900 including thefirst interconnect structure 801 a, thesecond interconnect structure 803 a and the via 802 coupling thefirst interconnect structure 801 a with thesecond interconnect structure 803 a. - In some embodiments, the
first RDL 801 includes afirst interconnect structure 801 a and a firstdielectric layer 801 b. In some embodiments, thefirst interconnect structure 801 a is surrounded by thefirst dielectric layer 801 b. In some embodiments, thefirst interconnect structure 801 a includes conductive material such as copper, aluminum or etc. In some embodiments, thefirst interconnect structure 801 includes several viaportions 801 c and aland portion 801 d coupled with the viaportions 801 c. In some embodiments, each of the viaportions 801 c extends from theland portion 801 d through thefirst dielectric layer 801 b. In some embodiments, theland portion 801 d extends within thefirst dielectric layer 801 b. In some embodiments, theland portion 801 d is extended in various shapes such as a strip, a frame, an annular shape, C shape, closed loop shape, etc. - In some embodiments,
several vias 802 are disposed over, extended from and electrically connected with the viaportions 801 c of thefirst RDL 801 respectively. In some embodiments, thevias 802 extend through a thirddielectric layer 802 a disposed over thefirst RDL 801. In some embodiments, thevias 802 electrically connects with thefirst interconnect structure 801 a of thefirst RDL 801. In some embodiments, the via 802 includes conductive material such as copper, etc. In some embodiments, the via 802 is a through integrated fan out via. In some embodiments, the via 802 has a height of about 500 um or a diameter of about 100 um. - In some embodiments, the
second RDL 803 includes asecond interconnect structure 803 a and asecond dielectric layer 803 b. In some embodiments, thesecond interconnect structure 803 a is surrounded by thesecond dielectric layer 803 b. In some embodiments, thesecond dielectric layer 803 b is disposed over the thirddielectric layer 802 a and thevia 802. In some embodiments, thesecond interconnect structure 803 a includes conductive material such as copper, aluminum or etc. In some embodiments, thesecond interconnect structure 803 includes several viaportions 803 c and more than oneland portions 803 d coupled with the viaportions 803 c. In some embodiments, the viaportion 803 c extends from theland portion 803 d through thesecond dielectric layer 803 b. In some embodiments, theland portion 803 d extends within thesecond dielectric layer 803 b. In some embodiments, theland portion 803 d is extended in various shapes such as a strip, a frame, an annular shape, C shape, etc. In some embodiments, theland portion 803 d includes two portions distanced from each other in a distance D of about 75 um to about 300 um. In some embodiments, the distance between the two portions of theland portion 803 d is about 175 um. In some embodiments, theland portions 803 d are in two half C shapes. In some embodiments, thefirst interconnect structure 801 a is substantially same or different from thesecond interconnect structure 803 a. In some embodiments, thefirst dielectric layer 801 b is substantially same or different from thesecond dielectric layer 803 b or the thirddielectric layer 802 a. - In some embodiments, the
second interconnect structure 803 a electrically connects with the firstconductive structure 801 a by thevias 802. In some embodiments, thevias 802 extend between thefirst RDL 801 and thesecond RDL 803. In some embodiments, thevias 802 electrically connects thefirst interconnect structure 801 a with thesecond interconnect structure 803 a. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a are aligned and disposed opposite to each other. - In some embodiments, the
first die 804 and thesecond die 807 are disposed over thesecond RDL 803. In some embodiments, thefirst die 804 and thesecond die 807 include semiconductive material such as silicon and are fabricated with predetermined functional circuits. In some embodiments, thefirst die 804 or thesecond die 807 is singulated from a silicon wafer by a mechanical or laser blade and then is disposed over thesecond dielectric layer 803 b. In some embodiments, thefirst die 804 or thesecond die 807 is in a quadrilateral, a rectangular or a square shape. In some embodiments, themolding 806 is disposed over thesecond RDL 803 and covers thefirst die 804 and thesecond die 807. - In some embodiments, the
source 805 is disposed within thefirst die 804 and thesecond RDL 803 or is disposed within thefirst RDL 801, thesecond RDL 803 and the thirddielectric layer 802 a and thefirst die 804. In some embodiments, thecomponent 808 is disposed within thesecond die 807 and thesecond RDL 803 or is disposed within thefirst RDL 801, thesecond RDL 803 and the thirddielectric layer 802 a and thesecond die 807. In some embodiments, thesource 805 and thecomponent 808 are electrically connected with thefirst die 804 and thesecond die 807 respectively. In some embodiments, a first portion of thesource 805 and a first portion of thecomponent 807 are surrounded by thefirst interconnect structure 801 a of thefirst RDL 801. In some embodiments, a second portion of thesource 805 and a second portion of thecomponent 808 are partially surrounded by thesecond interconnect structure 803 a of thesecond RDL 803. - In some embodiments, the
source 805 is configured to emit an electromagnetic radiation such as radio wave. In some embodiments, thesource 805 emit the electromagnetic radiation in a radio frequency (RF) such as lower than about 300 GHz, a range of about 3 kHz to about 300 GHz, etc. for wireless communication. In some embodiments, thesource 805 is in a patch shape, spiral shape or other suitable shapes. In some embodiments, thefirst interconnect structure 801 a of thefirst RDL 801 and thesecond interconnect structure 803 a of thesecond RDL 803 are configured to absorb the electromagnetic radiation emitted from thesource 805. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a are in cooperation to absorb the electromagnetic radiation emitted from thesource 805 in a predetermined frequency. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a can absorb the electromagnetic radiation in the predetermined frequency of about 5 GHz to about 15 GHz emitted from thesource 805. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a are configured to optimize an absorption of the electromagnetic radiation emitted from thesource 805 in the predetermined frequency, such that an electrical interference between thesource 805 and thecomponent 808 is in a minimal, and therefore a noise is reduced or prevented and a performance of thesemiconductor structure 900 is improved. - In some embodiments, the
source 805 and thecomponent 808 are configured to emit an electromagnetic radiation such as radio wave respectively. In some embodiments, thesource 805 and thecomponent 808 emit the electromagnetic radiation in a radio frequency (RF) such as lower than about 300 GHz, a range of about 3 kHz to about 300 GHz, etc. for wireless communication. In some embodiments, thesource 805 emits the electromagnetic radiation in the frequency substantially same or different from the frequency of the electromagnetic radiation emitted by thecomponent 808. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a are configured to absorb the electromagnetic radiation emitted from thesource 805 and thecomponent 808, such that the electromagnetic radiation emitted from thesource 805 would not electrically interfere with the electromagnetic radiation emitted from thecomponents 808. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a are configured to absorb the electromagnetic radiation of the predetermined frequency emitted from thesource 805 or thecomponent 808. Thus, the electromagnetic radiation of the predetermined frequency emitted from thesource 805 or thecomponent 808 would not electromagnetically interfere or affect thesource 805 or thecomponent 808. - In the present disclosure, a method of manufacturing a semiconductor structure (100, 200, 300 or 400) is also disclosed. In some embodiments, a semiconductor structure (100, 200, 300 or 400) is formed by a
method 1000.FIG. 29 is an embodiment of themethod 1000 of manufacturing the semiconductor structure (100, 200, 300 or 400). Themethod 1000 includes a number of operations (1001, 1002, 1003, 1004, 1005, 1006 and 1007). Themethod 1000 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations. - In
operation 1001, asubstrate 101 is received or provided as shown inFIG. 30A . In some embodiments, thesubstrate 101 includes semiconductive material such as silicon, germanium, gallium, arsenic, and combinations thereof. In some embodiments, thesubstrate 101 is a silicon substrate. In some embodiments, thesubstrate 101 includes a variety of electrical components formed over or within thesubstrate 101 by several fabrication operations. In some embodiments, thesubstrate 101 has similar configuration as described above or illustrated in any one ofFIGS. 1-12 . - In
operation 1002, a die (afirst die 102 or a second die 302) is disposed over thesubstrate 101 as shown inFIG. 30B . In some embodiments, thefirst die 102 is disposed over thesubstrate 101 by afirst adhesive 102 d, or thesecond die 302 is disposed over thesubstrate 101 by asecond adhesive 302 d. In some embodiments, thefirst die 102 and thesecond die 302 are disposed simultaneously, or thesecond die 302 is disposed after disposing thefirst die 102 or vice versa. In some embodiments, thefirst die 102 and thesecond die 302 include semiconductive material such as silicon. In some embodiments, thefirst die 102 and thesecond die 302 are same or different from each other in various aspects such as size, dimension, shapes, functions, circuitries, etc. In some embodiments, thefirst die 102 and thesecond die 302 are fabricated to include same or different electrical components and structures to perform same or different functions. - In some embodiments, the
first die 102 includes afirst die pad 102 a disposed over thesubstrate 101 and afirst seal ring 102 b formed at a periphery of thefirst die 102 and electrically connected with thefirst die pad 102 a. In some embodiments, afirst passivation 102 c is disposed over thefirst die 102 and covers a portion of thefirst die pad 102 a. In some embodiments, thesecond die 302 includes asecond die pad 302 a disposed over thesubstrate 101 and asecond seal ring 302 b formed at a periphery of thesecond die 302 and electrically connected with thesecond die pad 302 a. In some embodiments, asecond passivation 302 c is disposed over thesecond die 302 and covers a portion of the secondt die pad 302 a. In some embodiments, the die (thefirst die 102 or the second die 302) has similar configuration as described above or illustrated in any one ofFIGS. 1-12 . - In
operation 1003, a via (a first via 106 or a second via 306) is formed over the die (thefirst die 102 or the second die 302) as shown inFIG. 30C . In some embodiments, the first via 106 is disposed over thefirst die pad 102 a of thefirst die 102. In some embodiments, the second via 306 is disposed over thesecond die pad 302 a of thesecond die 302. In some embodiments, the via (the first via 106 or the second via 306) is formed by any suitable operations such as sputtering, electroplating, etc. In some embodiments, the via (a first via 106 or a second via 306) is formed by disposing a conductive material over thefirst die pad 102 a. In some embodiments, the first via 106 is substantially same or different from the second via 306. In some embodiments, the first via 106 and the second via 306 are formed simultaneously or one by one. In some embodiments, the first via 106 is electrically connected with thefirst die pad 102 a and thefirst seal ring 102 b. In some embodiments, the second via 306 is electrically connected with thesecond die pad 302 a and thesecond seal ring 102 b. In some embodiments, the via (the first via 106 or the second via 306) has similar configuration as described above or illustrated in any one ofFIGS. 1-12 . - In
operation 1004, a polymeric layer (afirst polymeric layer 103 or a second polymeric layer 303) is disposed over the die (thefirst die 102 or the second die 302) as shown inFIG. 30D . In some embodiments, thefirst polymeric layer 103 is disposed over thefirst die 102 and covers the first via 106. In some embodiments, thesecond polymeric layer 303 is disposed over thesecond die 302 and covers the second via 306. In some embodiments, thefirst polymeric layer 103 and thesecond polymeric layer 303 are same or different from each other in various aspects such as materials. In some embodiments, thefirst polymeric layer 103 and thesecond polymeric layer 303 are disposed simultaneously or one by one. In some embodiments, thefirst polymeric layer 103 is patterned to form arecess 103 a. Therecess 103 a exposes a portion of the first via 106 for receiving a conductive structure in subsequent operations. In some embodiments, therecess 103 a is formed by photolithography and etching operations. In some embodiments, the polymeric layer (thefirst polymeric layer 103 or the second polymeric layer 303) has similar configuration as described above or illustrated in any one ofFIGS. 1-12 . - In
operation 1005, amolding 104 is disposed over thesubstrate 101 as shown inFIG. 30E . In some embodiments, themolding 104 is disposed over the substrate and surrounds the die (thefirst die 102 or the second die 302). In some embodiments, themolding 104 has similar configuration as described above or illustrated in any one ofFIGS. 1-12 . - In
operation 1006, a redistribution layer (RDL) 105 is formed as shown inFIGS. 30F and 30G or 30H and 30I . In some embodiments, theRDL 105 is disposed over the die (thefirst die 102 or the second die 302). In some embodiments, theRDL 105 includes aninterconnect structure 105 a and adielectric layer 105 d surrounding theinterconnect structure 105 a. In some embodiments, thedielectric layer 105 d covers themolding 104, the polymeric layer (thefirst polymeric layer 103 or the second polymeric layer 303) and theinterconnect structure 105 a. In some embodiments, theinterconnect structure 105 a is formed over and electrically connected with the first via 106 so that theinterconnect structure 105 a, the first via 106, thefirst die pad 102 and thefirst seal ring 102 b are electrically connected. In some embodiments, theinterconnect structure 105 a includes a viaportion 105 b and aland portion 105 c coupled with the viaportion 105 b. In some embodiments, the viaportion 105 b contacts with the portion of the first via 106 exposed from thefirst polymeric layer 103. In some embodiments, theland portion 105 c extends within thedielectric layer 105 d and over a central portion of thefirst die 102 as shown inFIG. 30G (a top view ofFIG. 30F ) or along a periphery of thefirst die 102 as shown inFIG. 30I (a top view ofFIG. 30H ). In some embodiments, theRDL 105 has similar configuration as described above or illustrated in any one ofFIGS. 1-12 . - In
operation 1007, thefirst seal ring 102 b is configured for grounding or is connectable to ground as shown inFIGS. 30F and 30G or 30H and 30I . In some embodiments, thefirst seal ring 102 b is connected to ground. In some embodiments, theinterconnect structure 105 a of theRDL 105 is connected to ground. In some embodiments, theinterconnect structure 105 a, the first via 106, thefirst die pad 102 a are electrically grounded when thefirst seal ring 102 b is electrically grounded or connected to ground. - In the present disclosure, a method of manufacturing a
semiconductor structure 500 is also disclosed. In some embodiments, asemiconductor structure 500 is formed by amethod 2000.FIG. 31 is an embodiment of themethod 2000 of manufacturing thesemiconductor structure 500. Themethod 2000 includes a number of operations (2001, 2002, 2003, 2004, 2005, 2006 and 2007). Themethod 2000 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations. - In
operation 2001, asubstrate 101 is received or provided as shown inFIG. 32A . In some embodiments, theoperation 2001 is similar to theoperation 1001. Inoperation 2002, a die (afirst die 102 or a second die 302) is disposed over thesubstrate 101 as shown inFIG. 32B . In some embodiments, theoperation 2002 is similar to theoperation 1002. Inoperation 2003, a via (a first via 106 or a second via 306) is formed over the die (thefirst die 102 or the second die 302) as shown inFIG. 32C . In some embodiments, theoperation 2003 is similar to theoperation 1003. Inoperation 2004, a polymeric layer (afirst polymeric layer 103 or a second polymeric layer 303) is disposed over the die (thefirst die 102 or the second die 302) as shown inFIG. 32D . In some embodiments, theoperation 2004 is similar to theoperation 1004. Inoperation 2005, amolding 104 is disposed over thesubstrate 101 as shown inFIG. 32E . In some embodiments, theoperation 2005 is similar to theoperation 1005. - In
operation 2006, a package seal ring is formed as shown inFIGS. 32F and 32G . In some embodiments, thepackage seal ring 502 is formed over themolding 104. In some embodiments, thepackage seal ring 502 is disposed within a dielectric layer and is extended along a periphery of asemiconductor structure 500. In some embodiments, thepackage seal ring 502 at least partially surrounds thefirst die 102 and thesecond die 302. In some embodiments, thepackage seal ring 502 is disposed between thefirst die 102 and thesecond die 302. In some embodiments, thepackage seal ring 502 includes conductive material such as copper, aluminum, silver, etc. In some embodiments, thepackage seal ring 502 is configured for grounding or is connectable to ground. In some embodiments, thepackage seal ring 502 is connected to ground (as illustrated inFIG. 32G which is a top view ofFIG. 32F ). Thus, thepackage seal ring 502 can electrically isolate thefirst die 102 from thesecond die 302. An electrical or electromagnetic interference between thefirst die 102 and thesecond die 302 could be minimized or prevented. In some embodiments, anelectrical component 501 is disposed over thefirst die 102. - In the present disclosure, a method of manufacturing a
semiconductor structure 600 is also disclosed. In some embodiments, asemiconductor structure 600 is formed by amethod 3000.FIG. 33 is an embodiment of themethod 3000 of manufacturing thesemiconductor structure 600. Themethod 3000 includes a number of operations (3001, 3002, 3003, 3004, 3005, 3006 and 3007). Themethod 3000 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations. - In
operation 3001, asubstrate 101 is received or provided as shown inFIG. 34A . In some embodiments, theoperation 3001 is similar to theoperation operation 3002, a die (afirst die 102 or a second die 302) is disposed over thesubstrate 101 as shown inFIG. 34B . In some embodiments, theoperation 3002 is similar to theoperation operation 3003, a via (a first via 106 or a second via 306) is formed over the die (thefirst die 102 or the second die 302) as shown inFIG. 34C . In some embodiments, theoperation 3003 is similar to theoperation operation 3004, a polymeric layer (afirst polymeric layer 103 or a second polymeric layer 303) is disposed over the die (thefirst die 102 or the second die 302) as shown inFIG. 34D . In some embodiments, theoperation 3004 is similar to theoperation operation 3005, amolding 104 is disposed over thesubstrate 101 as shown inFIG. 34E . In some embodiments, theoperation 3005 is similar to theoperation - In
operation 3006, apackage RDL 601 is formed as shown inFIGS. 34F and 34G . Thepackage RDL 601 is disposed over themolding 104. In some embodiments, thepackage RDL 601 is disposed within a dielectric layer and is extended along a periphery of asemiconductor structure 600. In some embodiments, thepackage RDL 601 at least partially surrounds thefirst die 102 and thesecond die 302. In some embodiments, thepackage RDL 601 is disposed between thefirst die 102 and thesecond die 302. In some embodiments, thepackage RDL 601 includes conductive material such as copper, aluminum, silver, etc. In some embodiments, thepackage RDL 601 is formed by any suitable operations such as sputtering, electroplating, etc. In some embodiments, thepackage RDL 601 is configured for grounding or is connectable to ground. In some embodiments, thepackage RDL 601 is connected to ground (as illustrated inFIG. 34G which is a top view ofFIG. 34F ). Thus, thepackage RDL 601 can electrically isolate thefirst die 102 from thesecond die 302. An electrical or electromagnetic interference between thefirst die 102 and thesecond die 302 could be minimized or prevented. - In the present disclosure, a method of manufacturing a
semiconductor structure 700 is also disclosed. In some embodiments, asemiconductor structure 700 is formed by amethod 4000.FIG. 35 is an embodiment of themethod 4000 of manufacturing thesemiconductor structure 700. Themethod 4000 includes a number of operations (4001, 4002, 4003, 4004, 4005, 4006, 4007 and 4008). Themethod 4000 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations. - In
operation 4001, asubstrate 101 is received or provided as shown inFIGS. 36A-36C .FIG. 36B is a schematic cross sectional view ofFIG. 36A along MM′, andFIG. 36C is a schematic cross sectional view ofFIG. 36C along NN′. In some embodiments, thesubstrate 101 includes afirst RDL 701. In some embodiments, thefirst RDL 701 includes afirst interconnect structure 701 a and a dielectric layer surrounding thefirst interconnect structure 701 a. In some embodiments, thefirst interconnect structure 701 a includes a viaportion 701 b and aland portion 701 c coupled with the viaportion 701 b. In some embodiments, theland portion 701 c is extended along a periphery of thesubstrate 101. In some embodiments, the viaportion 701 b is extended through the dielectric layer of thefirst RDL 701. - In
operation 4002, a die (afirst die 102 or a second die 302) is disposed over thesubstrate 101 as shown inFIGS. 36D-36F .FIG. 36E is a schematic cross sectional view ofFIG. 36D along MM′, andFIG. 36F is a schematic cross sectional view ofFIG. 36D along NN′. In some embodiments, theoperation 4002 is similar to theoperation operation 4003, a via (a first via 106 or a second via 306) is formed over the die (thefirst die 102 or the second die 302) as shown inFIGS. 36D-36F . In some embodiments, theoperation 4003 is similar to theoperation operation 4004, a polymeric layer (afirst polymeric layer 103 or a second polymeric layer 303) is disposed over the die (thefirst die 102 or the second die 302) as shown inFIGS. 36D-36F . In some embodiments, theoperation 4004 is similar to theoperation operation 4005, amolding 104 is disposed over thesubstrate 101 as shown inFIGS. 36G-36I .FIG. 36H is a schematic cross sectional view ofFIG. 36G along MM′, andFIG. 36I is a schematic cross sectional view ofFIG. 36G along NN′. In some embodiments, theoperation 4005 is similar to theoperation - In
operation 4006, a through via 703 is formed as shown inFIGS. 36J-36L .FIG. 36K is a schematic cross sectional view ofFIG. 36J along MM′, andFIG. 36L is a schematic cross sectional view ofFIG. 36J along NN′. In some embodiments, the through via 703 is formed by removing a portion of themolding 104 to form an opening and filling a conductive material within the opening. In some embodiments, the through via 703 extends from the viaportion 701 b of thefirst RDL 701 through themolding 104, so that thefirst interconnect structure 701 a of thefirst RDL 701 is electrically connected with the through via 703. In some embodiments, the through via 703 is disposed adjacent to the periphery of thesubstrate 101. - In
operation 4007, asecond RDL 702 is formed as shown inFIGS. 36M-36O .FIG. 36N is a schematic cross sectional view ofFIG. 36M along MM′, andFIG. 36O is a schematic cross sectional view ofFIG. 36M along NN′. In some embodiments, thesecond RDL 702 is formed over themolding 104, thefirst die 102 and thesecond die 302. In some embodiments, thesecond RDL 702 includes asecond interconnect structure 702 a and a dielectric layer surrounding thesecond interconnect structure 702 a. In some embodiments, thesecond interconnect structure 702 a includes a viaportion 702 b and aland portion 702 c coupled with the viaportion 702 b. In some embodiments, theland portion 702 c is extended along the periphery of thesubstrate 101 or asemiconductor structure 700. In some embodiments, the viaportion 702 b is extended through the dielectric layer of thesecond RDL 702 and contacts with the through via 703. As such, thefirst interconnect structure 701 a of thefirst RDL 701 is electrically connected with thesecond interconnect structure 702 a of thesecond RDL 702 by the through via 703. - In
operation 4008, thefirst RDL 701 is configured for grounding or is connectable to ground as shown inFIGS. 36M-36O . In some embodiments, thefirst interconnect structure 701 a is electrically grounded or electrically connected to ground. In some embodiments, the through via 703 and thesecond interconnect structure 702 a are electrically connected with thefirst interconnect structure 701 a and thus are also electrically grounded when thefirst interconnect structure 701 a is electrically grounded or is connected to ground. Thefirst interconnect structure 701 a of thefirst RDL 701, the through via 703 and thesecond interconnect structure 702 b of thesecond RDL 702 are in cooperation to electrically isolate thefirst die 102 from thesecond die 302. An electrical or electromagnetic interference between thefirst die 102 and thesecond die 302 could be minimized or prevented. - In the present disclosure, a method of manufacturing a semiconductor structure (800 or 900) is also disclosed. In some embodiments, a semiconductor structure (800 or 900) is formed by a
method 5000.FIG. 37 is an embodiment of themethod 5000 of manufacturing the semiconductor structure (800 or 900). Themethod 5000 includes a number of operations (5001, 5002, 5003, 5004, 5005, 5006, 5007 and 5008). Themethod 5000 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations. - In
operation 5001, afirst RDL 801 is formed as shown inFIGS. 38A-38C .FIG. 38B is a schematic cross sectional view ofFIG. 38A along QQ′, andFIG. 38C is a schematic cross sectional view ofFIG. 38A along RR′. In some embodiments, thefirst RDL 801 includes afirst interconnect structure 801 a and a firstdielectric layer 801 b. In some embodiments, thefirst interconnect structure 801 a is surrounded by thefirst dielectric layer 801 b. In some embodiments, thefirst interconnect structure 801 includes a viaportion 801 c and aland portion 801 d coupled with the viaportion 801 c. In some embodiments, the viaportion 801 c extends from theland portion 801 d through thefirst dielectric layer 801 b. In some embodiments, theland portion 801 d extends within thefirst dielectric layer 801 b. In some embodiments, thefirst interconnect structure 801 a is in a closed loop shape. - In
operation 5002, a via 802 is formed over thefirst RDL 801 as shown inFIGS. 38D-38F .FIG. 38E is a schematic cross sectional view ofFIG. 38D along QQ′, andFIG. 38F is a schematic cross sectional view ofFIG. 38D along RR′. In some embodiments, the via 802 is disposed over, extended from and electrically connected with the viaportion 801 c of thefirst RDL 801. In some embodiments, the via 802 extends through a thirddielectric layer 802 a disposed over thefirst RDL 801. In some embodiments, the via 802 electrically connects with thefirst interconnect structure 801 a of thefirst RDL 801 and extends through the thirddielectric layer 802 a. In some embodiments, the via 802 is formed by removing a portion of the thirddielectric layer 802 a to form an opening and filling a conductive material within the opening. In some embodiments, a portion of asource 805 and a portion of acomponent 808 are formed through the thirddielectric layer 802 a and extended from thefirst RDL 801. - In
operation 5003, asecond RDL 803 is formed as shown inFIGS. 38G-38I . FIG. 38H is a schematic cross sectional view ofFIG. 38G along QQ′, andFIG. 38I is a schematic cross sectional view ofFIG. 38G along RR′. In some embodiments, thesecond RDL 803 includes asecond interconnect structure 803 a and asecond dielectric layer 803 b. In some embodiments, thesecond interconnect structure 803 a is surrounded by thesecond dielectric layer 803 b. In some embodiments, thesecond dielectric layer 803 b is disposed over the thirddielectric layer 802 a and thevia 802. In some embodiments, thesecond interconnect structure 803 includes a viaportion 803 c and aland portion 803 d coupled with the viaportion 803 c. In some embodiments, the viaportion 803 c extends from theland portion 803 d through thesecond dielectric layer 803 b. In some embodiments, theland portion 803 d extends within thesecond dielectric layer 803 b. In some embodiments, thesecond interconnect structure 803 a is in a C shape or a flipped C shape. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a are electrically connected by thevia 802. In some embodiments, a portion of thesource 805 and a portion of thecomponent 808 are formed through thesecond dielectric layer 803 b and extended from the thirddielectric layer 802 a. - In
operation 5004, a die (afirst die 804 or a second die 807) is disposed over thesecond RDL 803 as shown inFIGS. 38J-38L .FIG. 38K is a schematic cross sectional view ofFIG. 38J along QQ′, andFIG. 38L is a schematic cross sectional view ofFIG. 38J along RR′. In some embodiments, thefirst die 804 is disposed over thesource 805. In some embodiments, thesecond die 807 is disposed over thecomponent 808. In some embodiments, thefirst die 804 and thesecond die 807 are disposed over thesecond RDL 803 simultaneously or one by one. In some embodiments, thefirst die 804 is electrically connected to thesource 805. In some embodiments, thesecond die 807 is electrically connected to thecomponent 808. In some embodiments, thefirst interconnect structure 801 a and thesecond interconnect structure 803 a are configured to absorb an electromagnetic radiation of a predetermined frequency emitted from thesource 805 or thecomponent 808, such that thesource 805 or thecomponent 808 would not electrically interfere with each other. - In
operation 5005, amolding 806 is disposed over the die (thefirst die 804 or the second die 807) as shown inFIGS. 38M-38O .FIG. 38N is a schematic cross sectional view ofFIG. 38M along QQ′, andFIG. 38O is a schematic cross sectional view ofFIG. 38M along RR′. In some embodiments, themolding 806 is disposed over thesecond RDL 803 and covers the die (thefirst die 804 or the second die 807). - In the present disclosure, an improved semiconductor structure is disclosed. The semiconductor structure includes a die at least partially enclosed by a seal ring or a redistribution layer (RDL). The seal ring or the RDL is configured for grounding or is connectable to ground in order to isolate the die from other components. Further, the semiconductor structure includes a source emitting an electromagnetic radiation such as a radio wave in a radio frequency (RF), and a RDL configured to absorb the electromagnetic radiation from the source. The RDL can be configured to selectively absorb the electromagnetic radiation in a predetermined radio frequency. The RDL could isolate the source from other components and reduce electromagnetic interference between the electromagnetic radiation from the source and electromagnetic radiation from other components.
- In some embodiments, a semiconductor structure includes a substrate, a die disposed over the substrate, and including a die pad disposed over the die and a seal ring disposed at a periphery of the die and electrically connected with the die pad, a polymeric layer disposed over the die, a via extending through the polymeric layer and electrically connected with the die pad, and a molding disposed over the substrate and surrounding the die and the polymeric layer, wherein the seal ring is configured for grounding.
- In some embodiments, the seal ring extends along the periphery of the die to at least partially enclose a central portion of the die. In some embodiments, the seal ring is connectable to ground. In some embodiments, the via is disposed over the die pad and surrounded by the polymeric layer. In some embodiments, the semiconductor structure further includes a redistribution layer (RDL) disposed over the die and the molding, and including an interconnect structure electrically connecting with the via, the die pad and the seal ring. In some embodiments, the interconnect structure of the RDL is configured for grounding or is connectable to ground.
- In some embodiments, a semiconductor structure includes a first redistribution layer (RDL) including a first interconnect structure, a dielectric layer disposed over the first RDL, a via electrically connected with the first interconnect structure and extending through the dielectric layer, a second redistribution layer (RDL) disposed over the dielectric layer and the via, and including a second interconnect structure electrically connected with the first interconnect structure by the via, a die disposed over the second RDL, and a source electrically connected with the die, configured to emit an electromagnetic radiation, and disposed between the die and the first RDL, wherein the first interconnect structure of the first RDL and the second interconnect structure of the second RDL are configured to absorb the electromagnetic radiation of a predetermined frequency.
- In some embodiments, the first interconnect structure surrounds a first portion of the source, or the second interconnect structure partially surrounds a second portion of the source. In some embodiments, the via extends between the first RDL and the second RDL and electrically connects the first interconnect structure with the second interconnect structure. In some embodiments, the second interconnect structure is in a C shape, or the first interconnect structure is in an annular or a closed loop shape. In some embodiments, the source extends from the die to the first RDL or the second RDL. In some embodiments, the first interconnect structure and the second interconnect structure are aligned and disposed opposite to each other. In some embodiments, the first interconnect structure and the second interconnect structure are configured in substantially same dimension and shape. In some embodiments, the semiconductor structure further includes a molding disposed over the second RDL and covering the die.
- In some embodiments, a method of manufacturing a semiconductor structure includes receiving a substrate, disposing a die over the substrate, wherein the die includes a die pad disposed over the substrate and a seal ring formed at a periphery of the die and electrically connected with the die pad, forming a via over the die pad of the die, disposing a polymeric layer over the die, disposing a molding over the substrate and surrounding the die and the polymeric layer, wherein the seal ring is configured for grounding.
- In some embodiments, the seal ring is electrically connected with the via through the die pad. In some embodiments, the via and the die pad are electrically grounded by grounding the seal ring. In some embodiments, forming the via includes disposing a conductive material over the die pad. In some embodiments, the method further includes forming a redistribution layer (RDL) over the polymeric layer, wherein the RDL includes an interconnect structure disposed within the RDL, electrically connected with the via, the die pad and the seal ring, and configured for grounding. In some embodiments, the interconnect structure of the RDL extends along the periphery of the die or extends over a central portion of the die.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. A semiconductor structure, comprising:
a substrate;
a die disposed over the substrate, and including
a die pad disposed over the die and
a seal ring embeddedly arranged within the die at an upper periphery region thereof and electrically connected with the die pad;
a polymeric layer disposed over the die;
a via extending through the polymeric layer and electrically connected with the die pad; and
a molding disposed over the substrate and surrounding the die and the polymeric layer,
wherein the seal ring is configured for grounding.
2. The semiconductor structure of claim 1 , wherein the seal ring extends along the periphery of the die to at least partially enclose a central portion of the die.
3. The semiconductor structure of claim 1 , wherein the seal ring is connectable to ground.
4. The semiconductor structure of claim 1 , wherein the via is disposed over the die pad and surrounded by the polymeric layer.
5. The semiconductor structure of claim 1 , further comprising a redistribution layer (RDL) disposed over the die and the molding and including an interconnect structure electrically connecting with the via, the die pad and the seal ring.
6. The semiconductor structure of claim 5 , wherein the interconnect structure of the RDL is configured for grounding or is connectable to ground.
7. A semiconductor structure, comprising:
a first redistribution layer (RDL) including a first interconnect structure;
a dielectric layer disposed over the first RDL;
a via electrically connected with the first interconnect structure and extending through the dielectric layer;
a second redistribution layer (RDL) disposed over the dielectric layer and the via, and including a second interconnect structure electrically connected with the first interconnect structure by the via;
a die disposed over the second RDL; and
a source electrically connected with the die, configured to emit an electromagnetic radiation, at least partially disposed within the die and disposed between the die and the first RDL,
wherein the first interconnect structure of the first RDL and the second interconnect structure of the second RDL are configured to absorb the electromagnetic radiation of a predetermined frequency.
8. The semiconductor structure of claim 7 , wherein the first interconnect structure surrounds a first portion of the source, or the second interconnect structure partially surrounds a second portion of the source.
9. The semiconductor structure of claim 7 , wherein the via extends between the first RDL and the second RDL and electrically connects the first interconnect structure with the second interconnect structure.
10. The semiconductor structure of claim 7 , wherein the second interconnect structure is in a C shape, or the first interconnect structure is in an annular or a closed loop shape.
11. The semiconductor structure of claim 7 , wherein the source extends from the die to the first RDL or the second RDL.
12. The semiconductor structure of claim 7 , wherein the first interconnect structure and the second interconnect structure are aligned and disposed opposite to each other.
13. The semiconductor structure of claim 7 , wherein the first interconnect structure and the second interconnect structure are configured in substantially same dimension and shape.
14. The semiconductor structure of claim 7 , further comprising a molding disposed over the second RDL and covering the die.
15. A method of manufacturing a semiconductor structure, comprising:
receiving a substrate;
disposing a die over the substrate, wherein the die includes a die pad disposed over the substrate and a seal ring embeddedly arranged within the die at an upper periphery region thereof and electrically connected with the die pad;
forming a via over the die pad of the die;
disposing a polymeric layer over the die;
disposing a molding over the substrate and surrounding the die and the polymeric layer,
wherein the seal ring is configured for grounding.
16. The method of claim 15 , wherein the seal ring is electrically connected with the via through the die pad.
17. The method of claim 15 , wherein the via and the die pad are electrically grounded by grounding the seal ring.
18. The method of claim 15 , wherein forming the via includes disposing a conductive material over the die pad.
19. The method of claim 15 , further comprising:
forming a redistribution layer (RDL) over the polymeric layer, wherein the RDL includes an interconnect structure disposed within the RDL, electrically connected with the via, the die pad and the seal ring, and configured for grounding.
20. The method of claim 19 , wherein the interconnect structure of the RDL extends along the periphery of the die or extends over a central portion of the die.
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US9793227B1 (en) * | 2016-04-21 | 2017-10-17 | Peregrine Semiconductor San Diego | Switchable die seal connection |
US20180332151A1 (en) * | 2015-12-22 | 2018-11-15 | Intel Corporation | Microelectronic devices designed with integrated antennas on a substrate |
US11004812B2 (en) * | 2018-09-18 | 2021-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming the same |
US11569173B2 (en) * | 2017-12-29 | 2023-01-31 | Intel Corporation | Bridge hub tiling architecture |
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US10074618B1 (en) | 2017-08-14 | 2018-09-11 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
US11075173B2 (en) | 2018-10-31 | 2021-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming same |
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GB2288286A (en) * | 1994-03-30 | 1995-10-11 | Plessey Semiconductors Ltd | Ball grid array arrangement |
US8168529B2 (en) * | 2009-01-26 | 2012-05-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming seal ring in an integrated circuit die |
US7977783B1 (en) * | 2009-08-27 | 2011-07-12 | Amkor Technology, Inc. | Wafer level chip size package having redistribution layers |
US9718678B2 (en) * | 2014-09-25 | 2017-08-01 | Infineon Technologies Ag | Package arrangement, a package, and a method of manufacturing a package arrangement |
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US20180332151A1 (en) * | 2015-12-22 | 2018-11-15 | Intel Corporation | Microelectronic devices designed with integrated antennas on a substrate |
US10887439B2 (en) * | 2015-12-22 | 2021-01-05 | Intel Corporation | Microelectronic devices designed with integrated antennas on a substrate |
US9793227B1 (en) * | 2016-04-21 | 2017-10-17 | Peregrine Semiconductor San Diego | Switchable die seal connection |
US20170309581A1 (en) * | 2016-04-21 | 2017-10-26 | Peregrine Semiconductor Corporation | Switchable Die Seal Connection |
US11569173B2 (en) * | 2017-12-29 | 2023-01-31 | Intel Corporation | Bridge hub tiling architecture |
US11004812B2 (en) * | 2018-09-18 | 2021-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming the same |
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