US20170054032A1 - Non-volatile memory having individually optimized silicide contacts and process therefor - Google Patents
Non-volatile memory having individually optimized silicide contacts and process therefor Download PDFInfo
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- US20170054032A1 US20170054032A1 US14/593,694 US201514593694A US2017054032A1 US 20170054032 A1 US20170054032 A1 US 20170054032A1 US 201514593694 A US201514593694 A US 201514593694A US 2017054032 A1 US2017054032 A1 US 2017054032A1
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- 230000015654 memory Effects 0.000 title claims abstract description 225
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 84
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title claims description 37
- 230000008569 process Effects 0.000 title description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 112
- 239000002184 metal Substances 0.000 claims abstract description 112
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 53
- 229920005591 polysilicon Polymers 0.000 claims description 53
- 230000002093 peripheral effect Effects 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 20
- 238000000137 annealing Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000005457 optimization Methods 0.000 abstract description 2
- 210000004027 cell Anatomy 0.000 description 61
- 210000003850 cellular structure Anatomy 0.000 description 31
- 238000003860 storage Methods 0.000 description 11
- 238000002955 isolation Methods 0.000 description 6
- 238000003491 array Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000011370 conductive nanoparticle Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012782 phase change material Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
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- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
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- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
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Definitions
- This application relates generally to two- or three-dimensional nonvolatile memory integrated circuits such as semiconductor flash memory and its fabrication, and more specifically, to ones having different low resistance metal silicide contacts optimized for different portions of the integrated circuits.
- Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products.
- RAM random access memory
- flash memory is non-volatile, and retains its stored data even after power is turned off.
- ROM read only memory
- flash memory is rewritable similar to a disk storage device. In spite of the higher cost, flash memory is increasingly being used in mass storage applications.
- the floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window.
- the size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate.
- the threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
- Nonvolatile memory devices are also manufactured from memory cells with a dielectric layer for storing charge. Instead of the conductive floating gate elements described earlier, a dielectric layer is used. Such memory devices utilizing dielectric storage element have been described by Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545.
- An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source.
- U.S. Pat. Nos. 5,768,192 and 6,011,725 disclose a nonvolatile memory cell having a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.
- DRAM dynamic random access memory
- SRAM static random access memory
- non-volatile memory devices such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magneto-resistive random access memory (“MRAM”), and other semiconductor elements capable of storing information.
- ReRAM resistive random access memory
- EEPROM electrically erasable programmable read only memory
- FRAM ferroelectric random access memory
- MRAM magneto-resistive random access memory
- each type of memory device may have different configurations.
- flash memory devices may be configured in a NAND or a NOR configuration.
- NAND devices contain memory elements (e.g., devices containing a charge storage region) connected in series.
- a NAND memory array may be configured so that the array is composed of multiple strings of memory in which each string is composed of multiple memory elements sharing a single bit line and accessed as a group.
- memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array.
- NOR memory array One of skill in the art will recognize that the NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.
- the semiconductor memory elements of a single device may be distributed in two or three dimensions, such as a two dimensional array structure or a three dimensional array structure.
- the memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arranged in non-regular or non-orthogonal configurations as understood by one of skill in the art.
- the memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.
- a three dimensional memory array is organized so that memory elements occupy multiple planes or multiple device levels, forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).
- each plane in a three dimensional memory array structure may be physically located in two dimensions (one memory level) with multiple two dimensional memory levels to form a three dimensional memory array structure.
- a three dimensional memory array may be physically structured as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate in the y direction) having multiple elements in each column and therefore having elements spanning several vertically stacked memory planes.
- the columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, thereby resulting in a three dimensional arrangement of memory elements.
- One of skill in the art will understand that other configurations of memory elements in three dimensions will also constitute a three dimensional memory array.
- the memory elements may be connected together to form a NAND string within a single horizontal (e.g., x-z) plane.
- the memory elements may be connected together to extend through multiple horizontal planes.
- Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which extend through multiple memory levels.
- Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
- a monolithic three dimensional memory array is one in which multiple memory levels are formed above and/or within a single substrate, such as a semiconductor wafer.
- the layers of each level of the array are formed on the layers of each underlying level of the array.
- layers of adjacent levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory levels.
- two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device.
- non-monolithic stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other.
- the substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed separately and then packaged together to form a stacked-chip memory device.
- Semiconductor devices typically have one or more polysilicon layer as gate electrode material for devices.
- a polysilicon gate's electrical conductivity may be increased by depositing a metal (such as tungsten) or a metal silicide (such as tungsten silicide) over the gate.
- Polysilicon may also be employed as a conductor or as an ohmic contact for shallow junctions, with the desired electrical conductivity attained by doping the polysilicon material.
- memory cells and other circuit elements are formed on the same wafer.
- depositions of polysilicon/metal silicide/metal contact are performed across the wafer.
- a configuration of polysilicon/metal silicide/metal contact may be optimized for the memory cells but not for the other circuit elements. This may result in higher than optimal resistances in the metal contacts of the other circuit elements.
- the thicker silicide layer in the non-memory cell region is accomplished by a self-aligned silicide process.
- the process includes using a mask layer to open a trench in the non-memory cell region that extends from the upper first poly layer to the lower poly layer, depositing a second poly layer, etching back the second poly layer to the mask layer, depositing a first metal layer and annealing to form a first silicide layer between the first metal layer and the second poly layer, removing the first metal layer and the mask layer to expose the first poly layer, and depositing a second metal layer and annealing to form a second silicide layer between the second metal layer and the first poly layer.
- regions masked by the mask layer have the second silicide layer and regions unmasked by the mask layer has a combined first and second silicide layer.
- the non-memory cell region includes a component with a slit contact.
- the step of etching back the second poly layer to the mask layer to expose the first poly layer also expose a portion the lower poly layer.
- FIG. 1 illustrates a host in communication with a memory device in which the features of the present invention are embodied.
- FIG. 2 illustrates an example memory organization in the NAND configuration in which a page of memory cells is sensed or programmed in parallel.
- FIG. 3 illustrates schematically a conventional semiconductor structure for realizing the example NAND memory of FIG. 2 .
- FIG. 4 illustrates schematically an example of a conventional slit contact for the peripheral circuits.
- FIG. 5 illustrates schematically a further modification to the slit contact shown in FIG. 4 .
- FIG. 6 illustrates a memory device with the metal silicide layer being of different thickness for the different types of device element.
- FIG. 7 is a cross-sectional view of a slab, which constitutes the gross structure after the first part of the fabrication.
- FIG. 8 is a cross-sectional view of the slab, illustrating the process of cutting trenches in the slab for poly plugs formation later.
- FIG. 9 is a cross-sectional view of the slab, illustrating the process of depositing a layer of CG 2 poly 410 .
- FIG. 10 is a cross-sectional view of the slab, illustrating the process of forming the poly plug in the select transistor region.
- FIG. 11 is a cross-sectional view of the slab, illustrating the process of depositing a layer of metal 360 on top of the poly plug and the slit.
- FIG. 12 is a cross-sectional view of the slab, illustrating the process of forming a first silicide layer 350 and followed by removing the metal layer 360 .
- FIG. 13 is a cross-sectional view of the slab, illustrating the process of removing the mask 400 .
- FIG. 14 is a cross-sectional view of the slab, illustrating the process of depositing a layer of metal by sputtering.
- FIG. 15 is a cross-sectional view of the slab after, illustrating the process of segmenting the slab along the x-direction to provide isolation between memory cells and devices.
- FIG. 1 illustrates a host in communication with a memory device in which the features of the present invention are embodied.
- the host 10 typically sends data to be stored at the memory device 20 or retrieves data by reading the memory device 20 .
- the memory device 20 includes one or more memory chip 30 managed by a memory controller 40 .
- the memory chip 30 includes a memory array 100 of memory cells with each cell capable of being configured as a multi-level cell (“MLC”) for storing multiple bits of data, as well as capable of being configured as a single-level cell (“SLC”) for storing 1 bit of data.
- MLC multi-level cell
- SLC single-level cell
- the memory chip also includes peripheral circuits 50 such as row and column decoders, sense modules, data latches and I/O circuits.
- An on-chip control circuitry 60 controls low-level memory operations of each chip.
- the control circuitry 60 is an on-chip controller that cooperates with the peripheral circuits 50 to perform memory operations on the memory array 100 .
- the host 10 communicates and interacts with the memory chip 30 via the memory controller 40 .
- the controller 40 co-operates with the memory chip and controls and manages higher level memory operations.
- a firmware 42 provides codes to implement the functions of the controller 40 .
- An error correction code (“ECC”) processor (not shown) in the controller processes ECC during operations of the memory device 20 .
- the host 10 sends data to be written to the memory array 100 in logical sectors allocated from a file system of the host's operating system.
- a memory block management system implemented in the controller stages the sectors and maps and stores them to the physical structure of the memory array.
- a preferred block management system is disclosed in United States Patent Application Publication Number: US-2010-0172180-A1, the entire disclosure of which is incorporated herein by reference.
- a “page” of memory cells are read or programmed together.
- a row typically contains several interleaved pages or it may constitute one page. All memory cells of a page will be read or programmed together.
- Flash a block of memory cells organized in pages is erased as a unit.
- the block is sometimes referred to as a “flash” block and a memory with block erase structure is referred to as a “flash” memory.
- FIG. 2 illustrates an example memory organization in the NAND configuration in which a page of memory cells is sensed or programmed in parallel.
- FIG. 2 essentially shows a row of NAND strings 110 in the memory array 100 of FIG. 1 .
- Each NAND string 110 is a series of memory transistors 120 daisy-chained by their sources and drains to form a source terminal and a drain terminal respective at its two ends.
- a pair of select transistors 130 , 140 controls the memory transistors chain's connection to the external via the NAND string's source terminal and drain terminal respectively.
- the source select transistor 130 is turned on via a source select line SGS 132
- the source terminal is coupled to a source line 150 .
- the drain select transistor 140 is turned on via the drain select line SGD 142
- the drain terminal of the NAND string 110 is coupled to a bit line 160 of the memory array.
- Each memory transistor 120 in the NAND string 110 acts as a memory cell 120 .
- the memory cell 120 has a charge storage element 122 , such as a floating gate, to store a given amount of charge so as to represent an intended memory state.
- a control gate 124 of each memory transistor allows control over read and write operations.
- the control gates 124 of corresponding memory transistors 120 among the row of NAND strings are all connected to the same word line 170 (such as one of WL 0 , WL 1 , . . . ).
- control gates 134 , 144 corresponding to the select transistors 130 , 140 (accessed via select lines SGS 132 and SGD 142 respectively) provide control access to the NAND string 110 via its source terminal and drain terminal respectively.
- a “page” such as the page 180 is a group of memory cells 120 enabled to be sensed or programmed in parallel via a row of bit lines 160 . This is accomplished in the peripheral circuits 50 by a corresponding page of sense amplifiers 52 . The sensed results are latches in a corresponding set of data latches 54 .
- Each sense amplifier can be coupled to a NAND string, such as NAND string 110 via a bit line, such as bit line 160 .
- the page 180 is along a row and is sensed by a sensing voltage applied to the control gates 124 of the memory cells 120 of the page connected in common to the word line WL 3 .
- each memory cell such as memory cell 120 is accessible by a sense amplifier via a bit line.
- the page 180 referred to above is a physical page memory cells or sense amplifiers. Depending on context, in the case where each cell is storing multi-bit data, each physical page has multiple data pages.
- FIG. 3 illustrates schematically a conventional semiconductor structure for realizing the example NAND memory of FIG. 2 .
- Semiconducting devices comprising different types of components are typically formed on a silicon substrate 300 .
- memory cell components such as memory cells 120 and other type of non-memory cell components, such as select transistors 130 , 140 and a device element 56 in peripheral circuits 50 .
- FIG. 3 illustrates a NAND string with four memory cells 120 .
- the individual memory cells 120 of the NAND are isolated with oxide in between (not shown).
- essentially the FG poly layer 330 forms the floating gate 122 .
- the CG 1 poly layer 340 , the silicide layer 350 and the metal layer 360 form the control gate 124 .
- each memory cell 120 is basically a field-effect transistor whose field is further modified by charges programmed into the floating gate 122 .
- Channel regions are formed in the substrate 300 by doping source and drain regions 310 .
- a layer of oxide 320 provides insulation from the channel region. This is followed by a layer of FG poly 330 to implement a floating gate 122 .
- a gate oxide layer 322 insulates the floating gate 330 from above. Then a layer of CG 1 poly 340 acting as a control gate electrode is placed on top of the gate oxide 322 .
- a composite control gate 124 with improved conductivity is achieved by a layer of metal 360 , such as tungsten on top of the CG 1 poly 340 . Furthermore, the resistance of the metal contact 360 to the control gate electrode 340 is significantly reduced with an interfacing metal silicide layer 350 .
- peripheral circuits 50 include field-effect transistors.
- a poly plug 374 constituting from the CG 2 poly 410 filling is employed to form an electrical connection between the existing FG poly layer 330 330 (i.e., the floating gate poly) and the control gate to form a gross control or select gate 56 .
- the lower the metal contact resistance to the control gate electrode the better is the speed performance of the memory device.
- an interfacing metal silicide layer 350 between the metal layer 360 and the CG 1 poly 340 significantly reduces the contact resistance.
- the thicker the metal silicide layer 350 the lower is the contact resistance.
- the metal silicide layer 350 is formed after deposition of the CG 1 poly layer 340 and the metal layer 360 by annealing under elevated temperature to form the silicide layer 350 at their common interface.
- each layer constituting a memory cell 120 requires a certain thickness for optimum functioning and performance.
- the metal layer 360 needs to be of sufficient thickness to be robust and of low resistance.
- the thickness 352 of the metal silicide layer 350 as well as that of the metal layer 360 each has an upper limit predetermined by consideration of the geometry of the memory cell (memory cell components) during fabrication, which by extension also imposes the same limit on the non-memory cell components as the deposition of each of the CG 1 poly layer 340 and the metal layer 360 is performed across the substrate at the same time.
- U.S. Pat. No. 8,338,365 B2 discloses a similar slit contact in which the metal layer 360 and the silicide layer 350 drop into a trench or “slit” to make contact with structures closer to or underneath the substrate.
- FIG. 4 illustrates schematically an example of a conventional slit contact for the peripheral circuits.
- a trench or slit is open to access the FG Poly layer 330 .
- the metal layer 360 and the silicide layer 350 are dropped into and around the trench to form a slit contact 58 .
- contact resistance is reduced owing to the increased contact area.
- the slit contact 58 improves over the poly plug 374 shown in FIG. 3 .
- FIG. 5 illustrates schematically a further modification to the slit contact shown in FIG. 4 .
- the slit contact 58 improves over the poly plug 374 .
- the contact resistance could be further improved if the silicide layer 350 has a thickness 356 that is greater than the previous thickness 352 shown in FIG. 3 and FIG. 4 .
- this is infeasible because the previous thickness 352 is already optimized and limited by considerations in fabricating the memory cells portion of the chip.
- the select transistors are dependent on low contact resistance to switch an entire NAND string. Similar, the performance of the peripheral circuits could improve with lower contact resistance. A lower resistance in the circuits generally improves on the operating speed of the memory.
- a memory device has a semiconductor structure comprising multiple layers on a substrate.
- the multiple layers including a floating gate layer, a control gate layer, a metal silicide layer and a metal layer.
- the semiconductor structure comprises memory cell components and non-memory cell components.
- the memory cell components include non-volatile memory cells.
- Each memory cell has a floating gate layer, a control gate layer, a metal layer and a metal silicide layer interfacing between the control gate layer and the metal layer.
- the non-memory cell components include select transistors with individual ones sharing similar layer structure as the first type of device element but also with its floating gate electrically connected to its control gate by a connecting plug.
- the non-memory cell components also include peripheral circuits, with individual ones sharing similar layer structure as the first type of device element but also with a slit contact that has the metal layer dips into the floating gate layer.
- the non-memory cell components are characterized by a metal silicide layer having additional thickness compared to that of the memory cell components. In this way, the metal silicide layers for the two types of components are independently optimized. In the case of the select transistors, the additional thickness in metal silicide layer improves the conductance between the metal layer and the control gate and connected floating gate layers. In the case of the peripheral devices, the conductance between the metal layer and the floating gate layer is improved.
- FIG. 6 illustrates a memory device with the metal silicide layer being of different thickness for the different types of device element.
- the memory device 30 has a semiconductor structure comprising multiple layers on a substrate 300 .
- the multiple layers including a floating gate layer, such as a doped polysilicon layer, FG Poly 330 , a control gate layer, such as a doped polysilicon layer, CG1 Poly 340 , a metal silicide layer 350 and a metal layer 360 , such as titanium.
- the semiconductor structure comprises memory cell components and non-memory cell components.
- the memory cell components include a non-volatile memory cell 120 , having the floating gate layer FG Poly 330 , the control gate layer CG1 Poly 340 , the metal layer 360 and the metal silicide layer 350 interfacing between the control gate layer 340 and the metal layer 360 .
- the non-memory cell components include a select transistor 140 , sharing similar layer structure as the memory cell components but with its floating gate 330 electrically connected to its control gate 340 by a connector plug 372 .
- the non-memory cell components also include the peripheral circuits 50 .
- the device element of the peripheral circuits shares similar layer structure as the memory cell components but with a slit contact 58 that has the metal layer 360 dips into the floating gate layer 330 .
- the non-memory cell components are characterized by having a metal silicide layer 350 of additional thickness compared to that of the memory cell components.
- the metal silicide layer 350 ′ has a thickness 352 ′, which is thicker than that of the metal silicide layer 350 for the first type of device.
- the metal silicide layer 350 ′ has a thickness 352 ′, which is thicker than that of the metal silicide layer 350 for the memory cell components.
- the additional thickness in metal silicide layer 350 ′ of the non-memory cell components improve the conductance between the metal layer to the connector plug 372 for the select transistor 140 or to the floating gate for the device element of the peripheral circuits 50 .
- the metal silicide layers 350 and 350 ′ for the two types of components coexisting on the same substrate 300 are independently optimized.
- FIG. 7 to FIG. 15 illustrate a self-aligned silicide process of forming independently optimized metal silicide layer in the structure illustrated in FIG. 6 .
- a NAND memory device is fabricated on top of a semiconductor substrate to form a memory device chip.
- the fabrication comprises of two parts.
- the first part is the formation of a gross structure of the memory device, which includes the memory cell components (e.g., NAND memory cells), and the non-memory cell components.
- the gross structure and therefore the silicide thickness are primarily dictated by the requirements of forming the memory cell components (e.g., NAND memory cells).
- additional process steps allow thicker silicide layers to be formed in the non-memory cell components compared to that in the first-type devices.
- FIG. 7 is a cross-sectional view of a slab, which constitutes the gross structure after the first part of the fabrication.
- a slab has been formed comprising of multiple layers that correspond to the gross structure of the NAND memory.
- diffusion regions 310 are formed in the substrate 300 for the sources and drains of the memory cells. Then the following layers are deposited in turn on top of each other.
- a first layer of insulating oxide 320 is formed on top of the substrate 300 .
- a layer of FG (floating gate) poly 330 is formed on top of the oxide 320 .
- a second layer of oxide 322 is formed on top of the FG poly 330 .
- a layer of CG 1 Poly 340 is formed on top of the second layer of oxide 322 .
- a layer of oxide mask 400 is formed on top of the layer of CG 1 Poly.
- FIG. 8 is a cross-sectional view of the slab, illustrating the process of cutting trenches in the slab for poly plugs formation later. This is accomplished by unmasking the oxide mask 400 where these poly plugs are to be formed, the sites of select transistor and slit contacts of the peripheral circuits. The trenches runs along the x-direction (not shown explicitly) and are spaced apart in the y-direction. Anisotropic etching cut the trenches to a depth reaching the FG poly 330 .
- FIG. 9 is a cross-sectional view of the slab, illustrating the process of depositing a layer of CG 2 poly 410 .
- FIG. 10 is a cross-sectional view of the slab, illustrating the process of forming the poly plug in the select transistor region. This is accomplished by etching back the CG 2 poly 410 to the metal layer 360 . This basically leaves a poly plug in the select transistor region and a slit in the slit contact region of the peripheral circuits.
- FIG. 11 is a cross-sectional view of the slab, illustrating the process of depositing a first layer of metal 360 ′ on top of the poly plug and the slit.
- FIG. 12 is a cross-sectional view of the slab, illustrating the process of forming a first silicide layer 350 and followed by removing the first metal layer 360 ′.
- the silicide layer 350 is formed at the interface between the first metal layer 360 ′ and the poly plug filled with CG 2 Poly 410 .
- the silicide layer 350 is formed at the interface between the first metal layer 360 ′ and the CG 2 Poly 410 and FG Poly 330 .
- the silicide layer 350 is formed by annealing at elevated temperature so that the poly reacts with the metal to form the silicide.
- the silicide layer 350 has a thickness commensurate with the oxide mask 400 .
- FIG. 13 is a cross-sectional view of the slab, illustrating the process of removing the mask 400 . This will expose the CG 1 poly layer 340 .
- FIG. 14 is a cross-sectional view of the slab, illustrating the process of depositing a second metal layer by sputtering. This is followed by a process of forming a silicide layer between the second metal layer 360 and the CG 1 poly layer 340 by annealing.
- FIG. 15 is a cross-sectional view of the slab after, illustrating the process of segmenting the slab along the x-direction to provide isolation between memory cells and devices. Isolation trenches spaced apart in the y-direction are cut along the x-directions to form individual memory cells of each NAND string. Isolation trenches spaced apart in the x-direction and along the y-direction are cut to form individual NAND strings. These isolation trenches are eventually filled with isolation oxide (not shown).
- the above-described process has silicide of a predetermined thickness 350 formed in the memory cell regions while a thicker silicide layer 350 ′ is formed in the select device region and the peripheral circuit regions of the chip.
- the thickness of the silicide layers among the various regions of the chip can be independently optimized.
- the thickness of the silicide layer 350 ′ for the slit contacts in the peripheral circuits can be increased independent of the silicide layer 350 of the memory cells.
- the silicide layer 350 ′ in the select transistor region is independent increased with respect to the silicide layer 350 of the memory cells. In this case, the conductivity of the thinner metal layer is not significantly reduced because of the larger metal line there compared with those at the memory cells.
Abstract
In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically restricted by consideration of integrated-circuit fabrication geometry for each memory cell not to exceed a predetermined aspect ratio. The present implementation allows independent optimization of the thickness of silicide layer in the memory cells region and the non-memory cell region. In particular, in the non-memory cell region, a thicker silicide layer significantly improves the contact resistance of a slit contact for components having the upper poly layer in contact with a lower poly layer (a floating gate poly).
Description
- This application relates generally to two- or three-dimensional nonvolatile memory integrated circuits such as semiconductor flash memory and its fabrication, and more specifically, to ones having different low resistance metal silicide contacts optimized for different portions of the integrated circuits.
- Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, and retains its stored data even after power is turned off. Also, unlike ROM (read only memory), flash memory is rewritable similar to a disk storage device. In spite of the higher cost, flash memory is increasingly being used in mass storage applications.
- Flash EEPROM is similar to EEPROM (electrically erasable and programmable read-only memory) in that it is a non-volatile memory that can be erased and have new data written or “programmed” into their memory cells. Both utilize a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions. Flash memory such as Flash EEPROM allows entire blocks of memory cells to be erased at the same time.
- The floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
- Nonvolatile memory devices are also manufactured from memory cells with a dielectric layer for storing charge. Instead of the conductive floating gate elements described earlier, a dielectric layer is used. Such memory devices utilizing dielectric storage element have been described by Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. For example, U.S. Pat. Nos. 5,768,192 and 6,011,725 disclose a nonvolatile memory cell having a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.
- There are many commercially successful semiconductor memory devices being used today. These semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magneto-resistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Furthermore, each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.
- The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles or a charge storage dielectric material.
- Multiple memory elements may be configured so that they are connected in series or such that each element is individually accessible. By way of non-limiting example, NAND devices contain memory elements (e.g., devices containing a charge storage region) connected in series. For example, a NAND memory array may be configured so that the array is composed of multiple strings of memory in which each string is composed of multiple memory elements sharing a single bit line and accessed as a group. In contrast, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. One of skill in the art will recognize that the NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.
- The semiconductor memory elements of a single device, such as elements located within and/or over the same substrate or in a single die, may be distributed in two or three dimensions, such as a two dimensional array structure or a three dimensional array structure.
- In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or single memory device level. Typically, in a two dimensional memory structure, memory elements are located in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over which the layers of the memory elements are deposited and/or in which memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed.
- The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arranged in non-regular or non-orthogonal configurations as understood by one of skill in the art. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.
- A three dimensional memory array is organized so that memory elements occupy multiple planes or multiple device levels, forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).
- As a non-limiting example, each plane in a three dimensional memory array structure may be physically located in two dimensions (one memory level) with multiple two dimensional memory levels to form a three dimensional memory array structure. As another non-limiting example, a three dimensional memory array may be physically structured as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate in the y direction) having multiple elements in each column and therefore having elements spanning several vertically stacked memory planes. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, thereby resulting in a three dimensional arrangement of memory elements. One of skill in the art will understand that other configurations of memory elements in three dimensions will also constitute a three dimensional memory array.
- By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be connected together to form a NAND string within a single horizontal (e.g., x-z) plane. Alternatively, the memory elements may be connected together to extend through multiple horizontal planes. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which extend through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
- A monolithic three dimensional memory array is one in which multiple memory levels are formed above and/or within a single substrate, such as a semiconductor wafer. In a monolithic three-dimensional array the layers of each level of the array are formed on the layers of each underlying level of the array. One of skill in the art will understand that layers of adjacent levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory levels. In contrast, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device. For example, non-monolithic stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other. The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed separately and then packaged together to form a stacked-chip memory device.
- Semiconductor devices typically have one or more polysilicon layer as gate electrode material for devices. A polysilicon gate's electrical conductivity may be increased by depositing a metal (such as tungsten) or a metal silicide (such as tungsten silicide) over the gate. Polysilicon may also be employed as a conductor or as an ohmic contact for shallow junctions, with the desired electrical conductivity attained by doping the polysilicon material.
- For example, in a NAND memory device, memory cells and other circuit elements are formed on the same wafer. Typically, depositions of polysilicon/metal silicide/metal contact are performed across the wafer. A configuration of polysilicon/metal silicide/metal contact may be optimized for the memory cells but not for the other circuit elements. This may result in higher than optimal resistances in the metal contacts of the other circuit elements.
- Thus, there is a need to provide a memory device and processing method where the configuration of silicide is independently optimized for the memory cells and for the other circuit elements to provide lower contact resistance for the other circuit elements.
- In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper or first poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically restricted by consideration of integrated-circuit fabrication geometry for each memory cell not to exceed a predetermined aspect ratio. The present implementation allows independent optimization of the thickness of silicide layer in the memory cells region and the non-memory cell region. In particular, in the non-memory cell region, a thicker silicide layer significantly improves the contact resistance of a slit contact for components having the upper poly layer in contact with a lower poly layer (a floating gate poly).
- The thicker silicide layer in the non-memory cell region is accomplished by a self-aligned silicide process. The process includes using a mask layer to open a trench in the non-memory cell region that extends from the upper first poly layer to the lower poly layer, depositing a second poly layer, etching back the second poly layer to the mask layer, depositing a first metal layer and annealing to form a first silicide layer between the first metal layer and the second poly layer, removing the first metal layer and the mask layer to expose the first poly layer, and depositing a second metal layer and annealing to form a second silicide layer between the second metal layer and the first poly layer. In this way, regions masked by the mask layer have the second silicide layer and regions unmasked by the mask layer has a combined first and second silicide layer.
- The non-memory cell region includes a component with a slit contact. The step of etching back the second poly layer to the mask layer to expose the first poly layer also expose a portion the lower poly layer. The step of depositing a second metal layer and annealing to form a second silicide layer between the second metal layer and the first poly layer and also between the second metal layer and the lower poly layer.
- Various aspects, advantages, features and embodiments are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.
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FIG. 1 illustrates a host in communication with a memory device in which the features of the present invention are embodied. -
FIG. 2 illustrates an example memory organization in the NAND configuration in which a page of memory cells is sensed or programmed in parallel. -
FIG. 3 illustrates schematically a conventional semiconductor structure for realizing the example NAND memory ofFIG. 2 . -
FIG. 4 illustrates schematically an example of a conventional slit contact for the peripheral circuits. -
FIG. 5 illustrates schematically a further modification to the slit contact shown inFIG. 4 . -
FIG. 6 illustrates a memory device with the metal silicide layer being of different thickness for the different types of device element. -
FIG. 7 is a cross-sectional view of a slab, which constitutes the gross structure after the first part of the fabrication. -
FIG. 8 is a cross-sectional view of the slab, illustrating the process of cutting trenches in the slab for poly plugs formation later. -
FIG. 9 is a cross-sectional view of the slab, illustrating the process of depositing a layer ofCG 2poly 410. -
FIG. 10 is a cross-sectional view of the slab, illustrating the process of forming the poly plug in the select transistor region. -
FIG. 11 is a cross-sectional view of the slab, illustrating the process of depositing a layer ofmetal 360 on top of the poly plug and the slit. -
FIG. 12 is a cross-sectional view of the slab, illustrating the process of forming afirst silicide layer 350 and followed by removing themetal layer 360. -
FIG. 13 is a cross-sectional view of the slab, illustrating the process of removing themask 400. -
FIG. 14 is a cross-sectional view of the slab, illustrating the process of depositing a layer of metal by sputtering. -
FIG. 15 is a cross-sectional view of the slab after, illustrating the process of segmenting the slab along the x-direction to provide isolation between memory cells and devices. -
FIG. 1 illustrates a host in communication with a memory device in which the features of the present invention are embodied. Thehost 10 typically sends data to be stored at thememory device 20 or retrieves data by reading thememory device 20. Thememory device 20 includes one ormore memory chip 30 managed by amemory controller 40. Thememory chip 30 includes amemory array 100 of memory cells with each cell capable of being configured as a multi-level cell (“MLC”) for storing multiple bits of data, as well as capable of being configured as a single-level cell (“SLC”) for storing 1 bit of data. The memory chip also includesperipheral circuits 50 such as row and column decoders, sense modules, data latches and I/O circuits. An on-chip control circuitry 60 controls low-level memory operations of each chip. Thecontrol circuitry 60 is an on-chip controller that cooperates with theperipheral circuits 50 to perform memory operations on thememory array 100. Thecontrol circuitry 60 typically includes astate machine 62 to provide chip level control of memory operations via data, control andaddress buses 61. - In many implementations, the
host 10 communicates and interacts with thememory chip 30 via thememory controller 40. Thecontroller 40 co-operates with the memory chip and controls and manages higher level memory operations. Afirmware 42 provides codes to implement the functions of thecontroller 40. An error correction code (“ECC”) processor (not shown) in the controller processes ECC during operations of thememory device 20. - For example, in a host write, the
host 10 sends data to be written to thememory array 100 in logical sectors allocated from a file system of the host's operating system. A memory block management system implemented in the controller stages the sectors and maps and stores them to the physical structure of the memory array. A preferred block management system is disclosed in United States Patent Application Publication Number: US-2010-0172180-A1, the entire disclosure of which is incorporated herein by reference. - In order to improve read and program performance, multiple memory cells or memory transistors in the memory array are read or programmed in parallel. Thus, a “page” of memory cells are read or programmed together. In existing memory architectures, a row typically contains several interleaved pages or it may constitute one page. All memory cells of a page will be read or programmed together.
- Similar, to improve erase performance, a block of memory cells organized in pages is erased as a unit. The block is sometimes referred to as a “flash” block and a memory with block erase structure is referred to as a “flash” memory.
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FIG. 2 illustrates an example memory organization in the NAND configuration in which a page of memory cells is sensed or programmed in parallel.FIG. 2 essentially shows a row of NAND strings 110 in thememory array 100 ofFIG. 1 . - Each
NAND string 110 is a series ofmemory transistors 120 daisy-chained by their sources and drains to form a source terminal and a drain terminal respective at its two ends. A pair ofselect transistors select transistor 130 is turned on via a sourceselect line SGS 132, the source terminal is coupled to asource line 150. Similarly, when the drainselect transistor 140 is turned on via the drainselect line SGD 142, the drain terminal of theNAND string 110 is coupled to abit line 160 of the memory array. Eachmemory transistor 120 in theNAND string 110 acts as amemory cell 120. Thememory cell 120 has acharge storage element 122, such as a floating gate, to store a given amount of charge so as to represent an intended memory state. Acontrol gate 124 of each memory transistor allows control over read and write operations. Thecontrol gates 124 ofcorresponding memory transistors 120 among the row of NAND strings are all connected to the same word line 170 (such as one of WL0, WL1, . . . ). Similarly,control gates select transistors 130, 140 (accessed viaselect lines SGS 132 andSGD 142 respectively) provide control access to theNAND string 110 via its source terminal and drain terminal respectively. - A “page” such as the
page 180, is a group ofmemory cells 120 enabled to be sensed or programmed in parallel via a row of bit lines 160. This is accomplished in theperipheral circuits 50 by a corresponding page ofsense amplifiers 52. The sensed results are latches in a corresponding set of data latches 54. Each sense amplifier can be coupled to a NAND string, such asNAND string 110 via a bit line, such asbit line 160. For example, thepage 180 is along a row and is sensed by a sensing voltage applied to thecontrol gates 124 of thememory cells 120 of the page connected in common to the word line WL3. Along each column, each memory cell such asmemory cell 120 is accessible by a sense amplifier via a bit line. Data in the data latches 54 are toggled in from or out to thememory controller 40 via thebuses 61. Thepage 180 referred to above is a physical page memory cells or sense amplifiers. Depending on context, in the case where each cell is storing multi-bit data, each physical page has multiple data pages. -
FIG. 3 illustrates schematically a conventional semiconductor structure for realizing the example NAND memory ofFIG. 2 . Semiconducting devices comprising different types of components are typically formed on asilicon substrate 300. In this case, there are memory cell components such asmemory cells 120 and other type of non-memory cell components, such asselect transistors device element 56 inperipheral circuits 50. -
FIG. 3 illustrates a NAND string with fourmemory cells 120. Theindividual memory cells 120 of the NAND are isolated with oxide in between (not shown). Referring also toFIG. 2 , for thememory cell 120, essentially theFG poly layer 330 forms the floatinggate 122. TheCG 1poly layer 340, thesilicide layer 350 and themetal layer 360 form thecontrol gate 124. - For the memory cell components, each
memory cell 120 is basically a field-effect transistor whose field is further modified by charges programmed into the floatinggate 122. Channel regions are formed in thesubstrate 300 by doping source and drainregions 310. A layer ofoxide 320 provides insulation from the channel region. This is followed by a layer ofFG poly 330 to implement a floatinggate 122. Agate oxide layer 322 insulates the floatinggate 330 from above. Then a layer ofCG 1poly 340 acting as a control gate electrode is placed on top of thegate oxide 322. Acomposite control gate 124 with improved conductivity is achieved by a layer ofmetal 360, such as tungsten on top of theCG 1poly 340. Furthermore, the resistance of themetal contact 360 to thecontrol gate electrode 340 is significantly reduced with an interfacingmetal silicide layer 350. - For the non-memory cell components, such as the
select transistors FG poly layer 330 that forms the floatinggate 122. Thus, for the non-memory cell components, the existingFG poly layer 330 is electrically incorporated into the select gate, such asselect gate composite control gate 124 directly to theFG poly layer 330 by aconductive poly plug 372. The poly plug is effected by aCG 2poly 410 filling that effectively incorporates the FG poly layer 330 (i.e., the floating gate poly) as part of a device control gate orselect gate - Similarly for other non-memory cell components, such the
peripheral circuits 50, they include field-effect transistors. Thus, apoly plug 374 constituting from theCG 2poly 410 filling is employed to form an electrical connection between the existingFG poly layer 330 330 (i.e., the floating gate poly) and the control gate to form a gross control orselect gate 56. - Generally, the lower the metal contact resistance to the control gate electrode, the better is the speed performance of the memory device. Earlier, it has been described that an interfacing
metal silicide layer 350 between themetal layer 360 and theCG 1poly 340 significantly reduces the contact resistance. Typically, the thicker themetal silicide layer 350, the lower is the contact resistance. Themetal silicide layer 350 is formed after deposition of theCG 1poly layer 340 and themetal layer 360 by annealing under elevated temperature to form thesilicide layer 350 at their common interface. - While it is desirable to have a
thicker silicide layer 350, however, the memory cell geometry places a limitation on the thickness. As can be seen fromFIG. 3 , each layer constituting amemory cell 120 requires a certain thickness for optimum functioning and performance. For example, themetal layer 360 needs to be of sufficient thickness to be robust and of low resistance. When all the layers are tallied, the memory cell already has a column structure with an aspect ratio beyond which “word line collapse” is liable to occur. Thus, thethickness 352 of themetal silicide layer 350 as well as that of themetal layer 360 each has an upper limit predetermined by consideration of the geometry of the memory cell (memory cell components) during fabrication, which by extension also imposes the same limit on the non-memory cell components as the deposition of each of theCG 1poly layer 340 and themetal layer 360 is performed across the substrate at the same time. - For the peripheral circuits among the non-memory cell components, without the option of further increasing the thickness of the
metal silicide layer 350, one way of reducing the resistance of the metal contact resistance to the control gate electrode is to form a “slit contact”. U.S. Pat. No. 8,338,365 B2 discloses a similar slit contact in which themetal layer 360 and thesilicide layer 350 drop into a trench or “slit” to make contact with structures closer to or underneath the substrate. -
FIG. 4 illustrates schematically an example of a conventional slit contact for the peripheral circuits. A trench or slit is open to access theFG Poly layer 330. Themetal layer 360 and thesilicide layer 350 are dropped into and around the trench to form aslit contact 58. In this way, contact resistance is reduced owing to the increased contact area. Theslit contact 58 improves over thepoly plug 374 shown inFIG. 3 . -
FIG. 5 illustrates schematically a further modification to the slit contact shown inFIG. 4 . As described with regard toFIG. 4 , theslit contact 58 improves over thepoly plug 374. Still, the contact resistance could be further improved if thesilicide layer 350 has athickness 356 that is greater than theprevious thickness 352 shown inFIG. 3 andFIG. 4 . However, as explained earlier, this is infeasible because theprevious thickness 352 is already optimized and limited by considerations in fabricating the memory cells portion of the chip. The select transistors are dependent on low contact resistance to switch an entire NAND string. Similar, the performance of the peripheral circuits could improve with lower contact resistance. A lower resistance in the circuits generally improves on the operating speed of the memory. - According, it is desirable to have a memory device with a semiconductor structure in which the different types of device element are independently optimized.
- Silicide in the Memory Cells not Impacted by Thicker Silicide in other Devices on the Same Chip
- A memory device has a semiconductor structure comprising multiple layers on a substrate. The multiple layers including a floating gate layer, a control gate layer, a metal silicide layer and a metal layer. The semiconductor structure comprises memory cell components and non-memory cell components.
- The memory cell components include non-volatile memory cells. Each memory cell has a floating gate layer, a control gate layer, a metal layer and a metal silicide layer interfacing between the control gate layer and the metal layer.
- The non-memory cell components include select transistors with individual ones sharing similar layer structure as the first type of device element but also with its floating gate electrically connected to its control gate by a connecting plug.
- The non-memory cell components also include peripheral circuits, with individual ones sharing similar layer structure as the first type of device element but also with a slit contact that has the metal layer dips into the floating gate layer. The non-memory cell components are characterized by a metal silicide layer having additional thickness compared to that of the memory cell components. In this way, the metal silicide layers for the two types of components are independently optimized. In the case of the select transistors, the additional thickness in metal silicide layer improves the conductance between the metal layer and the control gate and connected floating gate layers. In the case of the peripheral devices, the conductance between the metal layer and the floating gate layer is improved.
-
FIG. 6 illustrates a memory device with the metal silicide layer being of different thickness for the different types of device element. Thememory device 30 has a semiconductor structure comprising multiple layers on asubstrate 300. The multiple layers including a floating gate layer, such as a doped polysilicon layer,FG Poly 330, a control gate layer, such as a doped polysilicon layer,CG1 Poly 340, ametal silicide layer 350 and ametal layer 360, such as titanium. - The semiconductor structure comprises memory cell components and non-memory cell components.
- The memory cell components include a
non-volatile memory cell 120, having the floating gatelayer FG Poly 330, the control gatelayer CG1 Poly 340, themetal layer 360 and themetal silicide layer 350 interfacing between thecontrol gate layer 340 and themetal layer 360. - The non-memory cell components include a
select transistor 140, sharing similar layer structure as the memory cell components but with its floatinggate 330 electrically connected to itscontrol gate 340 by aconnector plug 372. - The non-memory cell components also include the
peripheral circuits 50. The device element of the peripheral circuits shares similar layer structure as the memory cell components but with aslit contact 58 that has themetal layer 360 dips into the floatinggate layer 330. - The non-memory cell components are characterized by having a
metal silicide layer 350 of additional thickness compared to that of the memory cell components. In the case of the select transistors, themetal silicide layer 350′ has athickness 352′, which is thicker than that of themetal silicide layer 350 for the first type of device. In the case of the device element of the peripheral devices, themetal silicide layer 350′ has athickness 352′, which is thicker than that of themetal silicide layer 350 for the memory cell components. The additional thickness inmetal silicide layer 350′ of the non-memory cell components improve the conductance between the metal layer to theconnector plug 372 for theselect transistor 140 or to the floating gate for the device element of theperipheral circuits 50. As can be seen fromFIG. 6 , themetal silicide layers same substrate 300 are independently optimized. -
FIG. 7 toFIG. 15 illustrate a self-aligned silicide process of forming independently optimized metal silicide layer in the structure illustrated inFIG. 6 . - For example, a NAND memory device is fabricated on top of a semiconductor substrate to form a memory device chip. The fabrication comprises of two parts. In the first part is the formation of a gross structure of the memory device, which includes the memory cell components (e.g., NAND memory cells), and the non-memory cell components. The gross structure and therefore the silicide thickness are primarily dictated by the requirements of forming the memory cell components (e.g., NAND memory cells). In the second part, additional process steps allow thicker silicide layers to be formed in the non-memory cell components compared to that in the first-type devices.
-
FIG. 7 is a cross-sectional view of a slab, which constitutes the gross structure after the first part of the fabrication. Essentially, a slab has been formed comprising of multiple layers that correspond to the gross structure of the NAND memory. First,diffusion regions 310 are formed in thesubstrate 300 for the sources and drains of the memory cells. Then the following layers are deposited in turn on top of each other. A first layer of insulatingoxide 320 is formed on top of thesubstrate 300. A layer of FG (floating gate)poly 330 is formed on top of theoxide 320. A second layer ofoxide 322 is formed on top of theFG poly 330. A layer ofCG 1Poly 340 is formed on top of the second layer ofoxide 322. A layer ofoxide mask 400 is formed on top of the layer ofCG 1 Poly. -
FIG. 8 is a cross-sectional view of the slab, illustrating the process of cutting trenches in the slab for poly plugs formation later. This is accomplished by unmasking theoxide mask 400 where these poly plugs are to be formed, the sites of select transistor and slit contacts of the peripheral circuits. The trenches runs along the x-direction (not shown explicitly) and are spaced apart in the y-direction. Anisotropic etching cut the trenches to a depth reaching theFG poly 330. -
FIG. 9 is a cross-sectional view of the slab, illustrating the process of depositing a layer ofCG 2poly 410. -
FIG. 10 is a cross-sectional view of the slab, illustrating the process of forming the poly plug in the select transistor region. This is accomplished by etching back theCG 2poly 410 to themetal layer 360. This basically leaves a poly plug in the select transistor region and a slit in the slit contact region of the peripheral circuits. -
FIG. 11 is a cross-sectional view of the slab, illustrating the process of depositing a first layer ofmetal 360′ on top of the poly plug and the slit. -
FIG. 12 is a cross-sectional view of the slab, illustrating the process of forming afirst silicide layer 350 and followed by removing thefirst metal layer 360′. In the select transistor region, thesilicide layer 350 is formed at the interface between thefirst metal layer 360′ and the poly plug filled withCG 2Poly 410. In the peripheral circuits region, thesilicide layer 350 is formed at the interface between thefirst metal layer 360′ and theCG 2Poly 410 andFG Poly 330. Thesilicide layer 350 is formed by annealing at elevated temperature so that the poly reacts with the metal to form the silicide. Thesilicide layer 350 has a thickness commensurate with theoxide mask 400. -
FIG. 13 is a cross-sectional view of the slab, illustrating the process of removing themask 400. This will expose theCG 1poly layer 340. -
FIG. 14 is a cross-sectional view of the slab, illustrating the process of depositing a second metal layer by sputtering. This is followed by a process of forming a silicide layer between thesecond metal layer 360 and theCG 1poly layer 340 by annealing. -
FIG. 15 is a cross-sectional view of the slab after, illustrating the process of segmenting the slab along the x-direction to provide isolation between memory cells and devices. Isolation trenches spaced apart in the y-direction are cut along the x-directions to form individual memory cells of each NAND string. Isolation trenches spaced apart in the x-direction and along the y-direction are cut to form individual NAND strings. These isolation trenches are eventually filled with isolation oxide (not shown). - It can be seen that the above-described process has silicide of a
predetermined thickness 350 formed in the memory cell regions while athicker silicide layer 350′ is formed in the select device region and the peripheral circuit regions of the chip. In this way, the thickness of the silicide layers among the various regions of the chip can be independently optimized. In particular, the thickness of thesilicide layer 350′ for the slit contacts in the peripheral circuits can be increased independent of thesilicide layer 350 of the memory cells. Similarly, thesilicide layer 350′ in the select transistor region is independent increased with respect to thesilicide layer 350 of the memory cells. In this case, the conductivity of the thinner metal layer is not significantly reduced because of the larger metal line there compared with those at the memory cells. - The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the above to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to explain the principles involved and its practical application, to thereby enable others to best utilize the various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.
Claims (20)
1. A memory integrated circuit, comprising:
channels regions formed on a substrate;
a floating gate polysilicon layer above and isolated from the channel regions;
a first polysilicon layer above and isolated from the floating gate polysilicon layer;
a first metal silicide layer above and in electric contact with the first polysilicon layer; and
a metal layer above and in electric contact with the metal silicide layer; and wherein:
in a first region of said memory integrated circuit where nonvolatile memory elements are formed, said first metal silicide layer has a first thickness; and
in a second region of said memory integrated circuit where other circuit elements are formed with contacts below said first metal layer, a second metal silicide layer is formed below the first metal layer, said second metal silicide layer has a second thickness that exceeds the first thickness by a predetermined amount.
2. The memory integrated circuit as in claim 1 , wherein in said first region:
individual portions of said first polysilicon layer serves as control gates for the nonvolatile memory elements.
3. The memory integrated circuit as in claim 1 , wherein in said second region:
individual portions of said first polysilicon layer serve as control gates for select transistors for the nonvolatile memory elements in said first region;
each select transistor having an individual polysilicon plug electrically connecting between a corresponding individual portion of said first polysilicon layer and a corresponding portion of said floating gate polysilicon layer.
4. The memory integrated circuit as in claim 1 , wherein:
said second region includes non-memory components with slit contacts to the metal layer;
each slit contact enables the metal layer to dip down to make contact with the floating gate polysilicon layer;
said second metal silicide layer is between the metal layer and the floating gate polysilicon layer.
5. The memory integrated circuit as in claim 1 , wherein the first polysilicon layer and the metal layer have a uniform thickness across the first and second regions.
6. The memory integrated circuit as in claim 1 , wherein the nonvolatile memory elements are organized as NAND type memory.
7. The memory integrated circuit as in claim 1 , wherein the nonvolatile memory elements are organized in a two-dimensional array.
8. The memory integrated circuit as in claim 1 , wherein the nonvolatile memory elements are part of a three-dimensional array.
9. The memory integrated circuit as in claim 1 , wherein each of the nonvolatile memory elements each stores more than one bit of data.
10. A method of forming a memory, comprising:
forming a multi-layer slab on top of a semiconductor substrate with layers corresponding to structures of an array of NAND strings, and wherein the layers includes a first region for forming memory cells of the NAND strings and a second region for forming select transistors and peripheral circuits components, and wherein a first polysilicon layer is deposited as a top layer of the multi-layer slab;
masking the first polysilicon layer with a mask layer that leaves unmasked areas in designated areas among the second region;
etching trenches in the unmasked areas;
depositing a second polysilicon layer in the trenches;
etching back the second polysilicon layer to the mask layer;
depositing a first metal layer;
annealing to form a first silicide layer between the first metal layer and the second polysilicon layers interfacing with the first metal layer;
removing the first metal layer;
removing the mask layer to expose the first polysilicon layer;
depositing a second metal layer; and
annealing to form a second silicide layer between the second metal layer and the first polysilicon layer.
11. The method as in claim 10 , wherein:
the peripheral circuits components include slit contacts;
said etching back the second polysilicon layer to the mask layer also creates at each slit contact an exposed portion of a floating gate polysilicon below the first polysilicon layer; and
said annealing to form a first silicide layer between the first metal layer and the second polysilicon layers interfacing with the first metal layer also has the first silicide layer formed between the first metal layer and the exposed floating gate polysilicon.
12. The method as in claim 10 , wherein:
the first and second metal layers are tungsten.
13. The method as in claim 10 , wherein:
the first polysilicon layer is for forming a portion of the control gates of the memory cells.
14. The method as in claim 10 , wherein:
the first polysilicon layer is doped.
15. The method as in claim 10 , wherein:
the second polysilicon layer is for forming poly plugs that connect between the first polysilicon layer and a floating-gate polysilicon layer.
16. A method of forming a memory having memory cells arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions, said method comprising:
forming a multi-layer slab on top of a semiconductor substrate in an x-y plane, the layers of the multi-layer slab being stacked in the z-direction and corresponding to structures of an array in the x-y plane of NAND memory cells, and wherein the layers includes a first region for forming memory cells of the NAND strings and a second region for forming select transistors and peripheral circuits components, and wherein a first polysilicon layer is deposited as a top layer of the multi-layer slab;
masking the first polysilicon layer with a mask layer that leaves unmasked areas in designated areas among the second region;
etching trenches in the unmasked areas;
depositing a second polysilicon layer in the trenches;
etching back the second polysilicon layer to the mask layer;
depositing a first metal layer;
annealing to form a first silicide layer between the first metal layer and the second polysilicon layers interfacing with the first metal layer;
removing the first metal layer;
removing the mask layer to expose the first polysilicon layer;
depositing a second metal layer; and
annealing to form a second silicide layer between the second metal layer and the first polysilicon layer.
17. The method as in claim 16 , wherein:
the peripheral circuits components include slit contacts;
said etching back the second polysilicon layer to the mask layer also creates at each slit contact an exposed portion of a floating gate polysilicon below the first polysilicon layer; and
said annealing to form a first silicide layer between the first metal layer and the second polysilicon layers interfacing with the first metal layer also has the first silicide layer formed between the first metal layer and the exposed floating gate polysilicon.
18. The method as in claim 16 , wherein:
the first and second metal layers are tungsten.
19. The method as in claim 16 , wherein:
the first polysilicon layer is for forming a portion of the control gates of the memory cells.
20. The method as in claim 16 , wherein:
the second polysilicon layer is for forming poly plugs that connect between the first polysilicon layer and a floating-gate polysilicon layer.
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200311512A1 (en) * | 2018-07-24 | 2020-10-01 | Sandisk Technologies Llc | Realization of binary neural networks in nand memory arrays |
US11328204B2 (en) * | 2018-07-24 | 2022-05-10 | Sandisk Technologies Llc | Realization of binary neural networks in NAND memory arrays |
US11462260B2 (en) * | 2016-08-04 | 2022-10-04 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices |
US11568200B2 (en) | 2019-10-15 | 2023-01-31 | Sandisk Technologies Llc | Accelerating sparse matrix multiplication in storage class memory-based convolutional neural network inference |
US11625586B2 (en) | 2019-10-15 | 2023-04-11 | Sandisk Technologies Llc | Realization of neural networks with ternary inputs and ternary weights in NAND memory arrays |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11837601B2 (en) * | 2021-05-10 | 2023-12-05 | Sandisk Technologies Llc | Transistor circuits including fringeless transistors and method of making the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010030342A1 (en) * | 2000-04-14 | 2001-10-18 | Kazuhiro Ohnishi | Semiconductor device and process for producing the same |
US20110260235A1 (en) * | 2010-04-22 | 2011-10-27 | Takashi Whitney Orimoto | P-type control gate in non-volatile storage and methods for forming same |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5768192A (en) | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
CN101535492A (en) | 2005-02-11 | 2009-09-16 | 南加州大学 | Method of expressing proteins with disulfide bridges |
JP2009130137A (en) * | 2007-11-22 | 2009-06-11 | Toshiba Corp | Semiconductor memory device and manufacturing method thereof |
JP2010028084A (en) * | 2008-06-17 | 2010-02-04 | Toshiba Corp | Method of manufacturing semiconductor device |
JP4764461B2 (en) * | 2008-09-17 | 2011-09-07 | 株式会社東芝 | Semiconductor device |
JP2010080498A (en) * | 2008-09-24 | 2010-04-08 | Toshiba Corp | Non-volatile semiconductor memory device and its manufacturing method |
JP2010153481A (en) * | 2008-12-24 | 2010-07-08 | Toshiba Corp | Semiconductor memory device |
US8094500B2 (en) | 2009-01-05 | 2012-01-10 | Sandisk Technologies Inc. | Non-volatile memory and method with write cache partitioning |
JP2012038835A (en) * | 2010-08-05 | 2012-02-23 | Toshiba Corp | Nonvolatile semiconductor memory device and method of manufacturing the same |
JP2012038934A (en) * | 2010-08-06 | 2012-02-23 | Toshiba Corp | Nonvolatile semiconductor memory device and method for manufacturing the same |
KR101093967B1 (en) * | 2010-10-06 | 2011-12-15 | 주식회사 하이닉스반도체 | Nand flash memory device and manufacturing method of the same |
KR102001228B1 (en) * | 2012-07-12 | 2019-10-21 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
US20140264531A1 (en) * | 2013-03-15 | 2014-09-18 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory |
US9041114B2 (en) * | 2013-05-20 | 2015-05-26 | Kabushiki Kaisha Toshiba | Contact plug penetrating a metallic transistor |
-
2015
- 2015-01-09 US US14/593,694 patent/US20170054032A1/en not_active Abandoned
-
2017
- 2017-04-05 US US15/479,508 patent/US10056262B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010030342A1 (en) * | 2000-04-14 | 2001-10-18 | Kazuhiro Ohnishi | Semiconductor device and process for producing the same |
US20110260235A1 (en) * | 2010-04-22 | 2011-10-27 | Takashi Whitney Orimoto | P-type control gate in non-volatile storage and methods for forming same |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11462260B2 (en) * | 2016-08-04 | 2022-10-04 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices |
US11942140B2 (en) | 2016-08-04 | 2024-03-26 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices |
US20200311512A1 (en) * | 2018-07-24 | 2020-10-01 | Sandisk Technologies Llc | Realization of binary neural networks in nand memory arrays |
US11328204B2 (en) * | 2018-07-24 | 2022-05-10 | Sandisk Technologies Llc | Realization of binary neural networks in NAND memory arrays |
US11568200B2 (en) | 2019-10-15 | 2023-01-31 | Sandisk Technologies Llc | Accelerating sparse matrix multiplication in storage class memory-based convolutional neural network inference |
US11625586B2 (en) | 2019-10-15 | 2023-04-11 | Sandisk Technologies Llc | Realization of neural networks with ternary inputs and ternary weights in NAND memory arrays |
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