US20160372600A1 - Contact-first field-effect transistors - Google Patents
Contact-first field-effect transistors Download PDFInfo
- Publication number
- US20160372600A1 US20160372600A1 US14/744,147 US201514744147A US2016372600A1 US 20160372600 A1 US20160372600 A1 US 20160372600A1 US 201514744147 A US201514744147 A US 201514744147A US 2016372600 A1 US2016372600 A1 US 2016372600A1
- Authority
- US
- United States
- Prior art keywords
- contact
- fin
- gate electrode
- layer
- device structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000005669 field effect Effects 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 50
- 239000000463 material Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims description 53
- 230000008569 process Effects 0.000 claims description 33
- 239000003989 dielectric material Substances 0.000 claims description 17
- 239000002019 doping agent Substances 0.000 claims description 15
- 239000012212 insulator Substances 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 238000005530 etching Methods 0.000 description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 239000004020 conductor Substances 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000000615 nonconductor Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
Definitions
- the present invention relates to semiconductor device fabrication and, more specifically, to device structures for fin-type field-effect transistor (FinFET) integrated circuit technologies, as well as methods of fabricating device structures in FinFET integrated circuit technologies.
- FinFET fin-type field-effect transistor
- FinFETs are non-planar devices that are capable of being more densely packed in an integrated circuit than planar complementary metal-oxide-semiconductor (CMOS) transistors. In addition to the increase in packing density, FinFETs also offer superior short channel scalability, reduced threshold voltage swing, higher mobility, and the ability to operate at lower supply voltages than traditional planar CMOS transistors.
- Each FinFET features a narrow vertical fin of semiconductor material and a gate electrode that intersects a central channel of the fin.
- a thin gate dielectric layer separates the gate electrode from the fin.
- Heavily-doped source and drain regions are formed at opposite ends of the fin and the central channel is located between the source and drain regions.
- a method for forming a device structure.
- a first contact, a second contact, and a gate electrode are formed on a fin comprised of a semiconductor material.
- the second contact is spaced along a length of the fin from the first contact.
- the gate electrode is positioned along the length of the fin between the first contact and the second contact.
- a device structure includes a first contact on the fin, a second contact on the fin, and a gate electrode on a fin comprised of a semiconductor material.
- the second contact is spaced along a length of the fin from the first contact.
- the gate electrode is positioned along the length of the fin between the first contact and the second contact.
- FIGS. 1-6 are side views of a portion of a substrate at successive fabrication stages of a processing method for forming a device structure from fins in accordance with an embodiment of the invention.
- FIG. 1A is a cross-sectional view taken generally along line 1 A- 1 A in FIG. 1 .
- FIG. 2A is a cross-sectional view taken generally along line 2 A- 2 A in FIG. 2 .
- FIG. 3A is a cross-sectional view taken generally along line 3 A- 3 A in FIG. 3 .
- FIG. 4A is a cross-sectional view taken generally along line 4 A- 4 A in FIG. 4 .
- FIG. 5A is a cross-sectional view taken generally along line 5 A- 5 A in FIG. 5 .
- FIG. 6A is a cross-sectional view taken generally along line 6 A- 6 A in FIG. 6 .
- a plurality of fins 10 , 12 , 14 are formed from the device layer 18 of a semiconductor-on-insulator (SOI) substrate 16 .
- SOI substrate 16 further includes a buried insulator layer 20 comprised of an electrical insulator and a handle wafer 22 .
- the device layer 18 is separated from the handle wafer 22 by the intervening buried insulator layer 20 and is in direct contact along a planar interface with a top surface 20 a of the buried insulator layer 20 .
- the buried insulator layer 20 electrically isolates the handle wafer 22 from the device layer 18 , which is considerably thinner than the handle wafer 22 .
- the device layer 18 and the handle wafer 22 may be comprised of a semiconductor material, such as single crystal silicon, and the semiconductor material of the device layer 18 may be device quality.
- the buried insulator layer 20 may be a buried oxide layer comprised of silicon dioxide (SiO 2 ).
- Each of fins 10 , 12 , 14 is defined by a three-dimensional body of semiconductor material originating from the device layer 18 .
- the fins 10 , 12 , 14 are positioned on the top surface 20 a adjacent to each other, are laterally spaced apart across the top surface 20 a , and may be aligned parallel with each other with a length L.
- Each of the fins 10 , 12 , 14 may have a bottom surface that is in direct contact with the top surface 20 a of the buried insulator layer 20 along the interface between the device layer 18 and the buried insulator layer 20 .
- the fins 10 , 12 , 14 may be formed by photolithography and subtractive etching processes. To that end, the fins 10 , 12 , 14 may be formed, for example, using a sidewall image transfer (SIT) process that promotes dense packing. To that end, a cap layer and a sacrificial layer comprised of, for example, polysilicon may be serially deposited on the top surface of the device layer 18 and the sacrificial layer patterned to define mandrels in the region of the device layer 18 used to form the fins 10 , 12 , 14 . Spacers are then formed on the sidewalls of the mandrels.
- SIT sidewall image transfer
- the mandrels are arranged such that the spacers are formed at the intended locations for the fins 10 , 12 , 14 .
- the mandrels are then selectively removed relative to the spacers using an etching process, such as RIE.
- the cap layer and the device layer 18 are patterned with an etching process, such as RIE, using one or more etching chemistries while each spacer operates as an individual etch mask for one of the fins 10 , 12 , 14 .
- the etching process may stop on a top surface 20 a of the buried insulator layer 20 .
- the spacers and cap layer may be removed subsequent to the etching process so that the sidewalls of the fins 10 , 12 , 14 are exposed.
- the fins 10 , 12 , 14 may be formed from a bulk substrate (i.e., a non-SOI substrate) in a bulk process flow.
- a bulk substrate i.e., a non-SOI substrate
- the subsequent fabrication stages for fins 10 , 12 , 14 formed using the device layer 18 of the SOI substrate 16 apply equally to the bulk substrate in this alternative embodiment.
- contacts 24 , 26 may be formed that partially wrap around the opposite ends of the fins 10 , 12 , 14 and that cover respective portions of their exterior surfaces 10 a , 12 a , 14 a .
- the contacts 24 , 26 are also in direct contact with the top surface 20 a of the buried insulator layer 20 .
- the contacts 24 , 26 are electrically and physically coupled with the fins 10 , 12 , 14 .
- the gap between the confronting sidewalls or side surfaces 24 a , 26 a of the contacts 24 , 26 defines a space in which the gate electrode of the device structure is subsequently formed and defines the physical gate length GL of the device structure.
- the portions of the fins 10 , 12 , 14 that are contacted by the contacts 24 , 26 comprise source/drain regions 13 of the device structure 50 .
- the contacts 24 , 26 may be comprised of a conductor layer 25 and a liner layer 28 .
- the liner layer 28 is positioned between the conductor layer 25 and the respective exterior surfaces 10 a , 12 a , 14 a of the fins 10 , 12 , 14 .
- the conductor layer 25 may be comprised of a metal, such as tungsten (W), that is deposited by, for example, physical vapor deposition (PVD).
- the liner layer 28 may be comprised of a metal, such as titanium (Ti) or tantalum (Ta), that is deposited by, for example, chemical vapor deposition (CVD).
- a mask layer 29 may be applied on a top surface of the metal layers and patterned with photolithography.
- the mask layer 29 may comprise a light-sensitive material, such as a photoresist, that is applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to define an etch mask. Sections of the mask layer 29 cover the metal layer at the intended locations of the contacts 24 , 26 .
- etching process is then used, with the mask layer 29 present, to pattern the conductor layer 25 and liner layer 28 .
- the conductor layer 25 and liner layer 28 may be patterned at a gate pitch when forming the contacts 24 , 26 .
- the etching process may be selected to remove the material of the conductor layer 25 and liner layer 28 selective to the semiconductor material of the fins 10 , 12 , 14 .
- the term “selective” in reference to a material removal process denotes that, with an appropriate etchant choice, the material removal rate for the targeted material is greater than the removal rate for at least another material exposed to the material removal process.
- the etching process may be conducted in a single etching step or multiple steps, and may rely on one or more etch chemistries.
- the mask layer 29 may be removed following the conclusion of the etching process. If comprised of a photoresist, the mask layer 29 may be removed by ashing or solvent stripping, followed by a cleaning process.
- the metal forming the contacts 24 , 26 may be doped during deposition in order to provide a solid-state diffusion source for doping the fins 10 , 12 , 14 and/or to improve the contact resistance.
- the liner layer 28 may function as part of the contacts 24 , 26 to reduce the contact resistance with the fins 10 , 12 , 14 .
- the liner layer 28 may be omitted from the construction of the device structure.
- spacers 30 , 32 are formed on the side surfaces 24 a , 26 a of the contacts 24 , 26 .
- the spacers 30 , 32 may be formed by depositing a conformal layer comprised of an electrical insulator and shaping the conformal layer with an anisotropic etching process, such as a RIE process, that preferentially removes the conformal layer from horizontal surfaces.
- an anisotropic etching process such as a RIE process
- the spacers 30 , 32 may be comprised of, for example, silicon nitride (Si 3 N 4 ) or silicon dioxide deposited by chemical vapor deposition.
- the spacers 30 , 32 are separated by gap g 1 , which is less than the physical gate length GL of the device structure between the contacts 24 , 26 by the spacer thickness.
- the spacers 30 , 32 on the side surfaces 24 a , 26 a of the contacts 24 , 26 may be comprised of a material, such as a phosphorous-doped silicate glass (PSG), an arsenic-doped silicate glass (ASG), or a boron-doped silicate glass (BSG), that contains a dopant.
- PSG phosphorous-doped silicate glass
- ASG arsenic-doped silicate glass
- BSG boron-doped silicate glass
- Dopant originating from the solid-state dopant source represented by the spacers 30 , 32 can be caused to diffuse locally from the spacers 30 , 32 into the fins 10 , 12 , 14 by, for example, a thermal anneal process at a given temperature and over a given duration.
- These doped portions of the fins 10 , 12 , 14 may function to provide link-up extensions in the constituent semiconductor material between the source/drain regions 13 and channel
- a gate dielectric 34 and a gate electrode 36 are formed on the fins 10 , 12 , 14 over their respective exterior surfaces 10 a , 12 a , 14 a .
- the gate dielectric 34 and gate electrode 36 are located in the gap g 1 between the spacers 30 , 32 , and cover that respective portion of the exterior surfaces 10 a , 12 a , 14 a .
- the portion of the fins 10 , 12 , 14 covered by the gate electrode 36 may define a channel of the device structure.
- the gate dielectric 34 may be comprised of an electrical insulator with a dielectric constant (e.g., a permittivity) characteristic of a dielectric material.
- the gate dielectric 34 may be comprised of silicon dioxide, silicon oxynitride, a high-k dielectric material such as hafnium oxide, or layered combinations of these dielectric materials, deposited by v, atomic layer deposition (ALD), etc.
- the gate electrode 36 is comprised of a metal, a silicide, polycrystalline silicon (e.g., polysilicon), or a combination of these materials deposited by physical vapor deposition, chemical vapor deposition, etc.
- the gate dielectric 34 and gate electrode 36 may be formed by patterning a deposited layer stack of their constituent materials using photolithography and etching processes.
- a mask layer may be applied on a top surface of the layer stack and patterned with photolithography.
- the mask layer may comprise a photosensitive material, such as a photoresist, that is applied by spin coating, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer.
- a section of the mask layer covers the layer stack at the intended location of the gate electrode 36 and functions as an etch mask. An etching process is used, with the mask layer present, to form the gate dielectric 34 and the gate electrode 36 from the layer stack.
- the etching process may be selected to remove the materials of the layer stack selective to the respective materials of the fins 10 , 12 , 14 and contacts 24 , 26 .
- the etching process may be conducted in a single etching step or multiple steps, and may rely on one or more etch chemistries.
- the mask layer may be removed following the etching process. If comprised of a photoresist, the mask layer may be removed by ashing or solvent stripping, followed by a cleaning process.
- a planarization process such as chemical-mechanical polishing (CMP) is employed to planarize the top surfaces of the gate electrode 36 and the contacts 24 , 26 .
- the gate dielectric 34 is positioned between the gate electrode 36 and a channel in the fins 10 , 12 , 14 , which is itself located between the source/drain regions 13 .
- the spacers 30 , 32 which flank the opposite sidewalls of the gate electrode 36 , are positioned between the contacts 24 , 26 and the gate electrode 36 as intervening structures.
- the gate electrode 36 is formed in a self-aligned manner with the channel as constrained by the presence of the contacts 24 , 26 that are formed before the gate electrode 36 is formed.
- the contacts 24 , 26 are not dummy structures comprised of a sacrificial material that is removed after the gate electrode 36 is formed and exist as elements in the final device structure 50 .
- the complexity of the processing method producing the device structure 50 is reduced in comparison with the complexity of fabricating conventional device structures.
- the device structure 50 has the form of a fin-type field effect transistor in which the physical gate length of the device structure 50 is determined by the contact-to-contact spacing between contacts 24 , 26 .
- Gate lithography is eliminated because the gate electrode 36 is formed between the contacts 24 , 26 in a self-aligned manner.
- a positive lithographic step is not needed to establish the channel length of the device structure 50 , which eliminates limitations of on the minimum gate length that is achievable in conventional device structures.
- the contacts 24 , 26 are formed as metal pillars as an initial step and at earlier fabrication stage in the processing flow than in the fabrication of convention device structures. Another consequence of the process flow is that enabling technologies for low-temperature transistor formation, such as for three-dimensional monolithic integration (nanosecond laser anneal, etc.), may be utilized to form the field-effect transistor after the contacts 24 , 26 are formed.
- the contacts 24 , 26 may provide improved contact metallurgy by eliminating protective liners (generally of lower conductivity) normally used to fill contact holes for prevent interaction of the metal deposition process.
- the elimination of the protective liners may be effective to reduce the contact resistance.
- the device structure 50 can be formed without a contact etch-stop layer on top of the gate electrode, and the contacts 24 , 26 do not have to be etched selectively to maintain self-alignment.
- the spacers 30 , 32 may be removed using an etching process that is selective to the materials of the contacts 24 , 26 and the gate electrode 36 .
- the exterior surfaces 10 a , 12 a , 14 a of the fins 10 , 12 , 14 between the side surfaces 24 a , 26 a of contacts 24 , 26 and confronting side surfaces of the gate electrode 36 are exposed. Sections of the fins 10 , 12 , 14 are accessible to be doped by, for example, plasma emersion or ion implantation to define link-up extensions.
- the semiconductor material of the fins 10 , 12 , 14 may be doped by introducing a p-type dopant species selected from Group III of the Periodic Table (e.g., boron) that is effective to impart p-type conductivity.
- a p-type dopant species selected from Group III of the Periodic Table (e.g., boron) that is effective to impart p-type conductivity.
- the semiconductor material of the fins 10 , 12 , 14 may be doped by introducing an electrically-active dopant, such as an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P) or arsenic (As)) that is effective to impart n-type conductivity.
- P phosphorus
- As arsenic
- the spacers 30 , 32 may remain in the gaps between the contacts 24 , 26 and the gate electrode 36 . If not removed and replaced, then the spacers 30 , 32 will be present in the device structure 50 following its fabrication. In an embodiment, the spacers 30 , 32 may not be removed and replaced if dopant is outdiffused from the spacers 30 , 32 , as discussed herein above, to dope sections of the fins 10 , 12 , 14 and thereby provide the link-up extensions.
- spacers 40 , 42 are formed inside the gaps between the contacts 24 , 26 and gate electrode 36 .
- the spacers 40 , 42 may be formed from the same dielectric material (e.g., silicon nitride or silicon dioxide) as originally used in spacers 30 , 32 or may be formed using a different dielectric material than original used in spacers 30 , 32 .
- the spacers 40 , 42 may be formed from a dielectric material having a lower relative permittivity or dielectric constant than the spacers 30 , 32 .
- the spacers 40 , 42 may be comprised of a low-k dielectric material characterized by a relative permittivity less than the relative permittivity for silicon dioxide of roughly 3.9.
- suitable low-k dielectric materials for spacers 40 , 42 include, but are not limited to, porous and nonporous spun-on inorganic and organic low-k dielectrics (e.g., hydrogen-enriched silicon oxycarbide (SiCOH)).
- Spacers 40 , 42 may be deposited by any number of techniques including, but not limited to, sputtering, spin-on application, or chemical vapor deposition.
- the top surface 36 a of the gate electrode 36 may be recessed below a plane containing the top surfaces 40 a , 42 a of the spacers 40 , 42 if the spacers 30 , 32 are removed and replaced and a plane containing the top surfaces 24 b , 26 b of the contacts 24 , 26 to define a cavity 44 .
- An etching process may be used that removes the material of the gate electrode 36 selective to the materials of the spacers 40 , 42 and contacts 24 , 26 .
- the etching process may be conducted in a single etching step or multiple steps, and may rely on one or more etch chemistries. If the spacers 30 , 32 are not removed and replaced by spacers 40 , 42 , the top surfaces of the spacers 30 , 32 may provide the reference plane for the recession of the gate electrode 36 .
- the cavity 44 may be filled with a dielectric layer 46 comprised of a dielectric material differing in composition from the conductive material comprising the gate electrode 36 .
- the cavity 44 may be filled during middle-of-line (MOL) processing.
- MOL middle-of-line
- the cavity 44 may be filled during local interconnect formation with an electrical insulator, such as silicon dioxide (SiO 2 ), deposited by CVD and subsequently planarized using a chemical mechanical polishing process that eliminates topography.
- the replacement of a portion of the gate electrode 36 with dielectric material may be effective to reduce the capacitance of the device structure 50 .
- the methods as described above are used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
- the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- references herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference.
- the term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation.
- the terms “vertical” and “normal” refers to a direction perpendicular to the horizontal, as just defined.
- the term “lateral” refers to a dimension within the horizontal plane.
- a feature may be “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present.
- a feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent.
- a feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
Abstract
Description
- The present invention relates to semiconductor device fabrication and, more specifically, to device structures for fin-type field-effect transistor (FinFET) integrated circuit technologies, as well as methods of fabricating device structures in FinFET integrated circuit technologies.
- FinFETs are non-planar devices that are capable of being more densely packed in an integrated circuit than planar complementary metal-oxide-semiconductor (CMOS) transistors. In addition to the increase in packing density, FinFETs also offer superior short channel scalability, reduced threshold voltage swing, higher mobility, and the ability to operate at lower supply voltages than traditional planar CMOS transistors. Each FinFET features a narrow vertical fin of semiconductor material and a gate electrode that intersects a central channel of the fin. A thin gate dielectric layer separates the gate electrode from the fin. Heavily-doped source and drain regions are formed at opposite ends of the fin and the central channel is located between the source and drain regions.
- Improved device structures and fabrication methods are needed for FinFET integrated circuit technologies.
- According to one embodiment of the present invention, a method is provided for forming a device structure. A first contact, a second contact, and a gate electrode are formed on a fin comprised of a semiconductor material. The second contact is spaced along a length of the fin from the first contact. The gate electrode is positioned along the length of the fin between the first contact and the second contact.
- According to another embodiment of the present invention, a device structure includes a first contact on the fin, a second contact on the fin, and a gate electrode on a fin comprised of a semiconductor material. The second contact is spaced along a length of the fin from the first contact. The gate electrode is positioned along the length of the fin between the first contact and the second contact.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
-
FIGS. 1-6 are side views of a portion of a substrate at successive fabrication stages of a processing method for forming a device structure from fins in accordance with an embodiment of the invention. -
FIG. 1A is a cross-sectional view taken generally alongline 1A-1A inFIG. 1 . -
FIG. 2A is a cross-sectional view taken generally alongline 2A-2A inFIG. 2 . -
FIG. 3A is a cross-sectional view taken generally alongline 3A-3A inFIG. 3 . -
FIG. 4A is a cross-sectional view taken generally alongline 4A-4A inFIG. 4 . -
FIG. 5A is a cross-sectional view taken generally alongline 5A-5A inFIG. 5 . -
FIG. 6A is a cross-sectional view taken generally alongline 6A-6A inFIG. 6 . - With reference to
FIGS. 1, 1A and in accordance with an embodiment of the invention, a plurality offins substrate 16. TheSOI substrate 16 further includes a buriedinsulator layer 20 comprised of an electrical insulator and ahandle wafer 22. The device layer 18 is separated from thehandle wafer 22 by the intervening buriedinsulator layer 20 and is in direct contact along a planar interface with atop surface 20 a of the buriedinsulator layer 20. The buriedinsulator layer 20 electrically isolates the handle wafer 22 from the device layer 18, which is considerably thinner than thehandle wafer 22. The device layer 18 and thehandle wafer 22 may be comprised of a semiconductor material, such as single crystal silicon, and the semiconductor material of the device layer 18 may be device quality. The buriedinsulator layer 20 may be a buried oxide layer comprised of silicon dioxide (SiO2). - Each of
fins fins top surface 20 a adjacent to each other, are laterally spaced apart across thetop surface 20 a, and may be aligned parallel with each other with a length L. Each of thefins top surface 20 a of the buriedinsulator layer 20 along the interface between the device layer 18 and the buriedinsulator layer 20. - The
fins fins fins fins fins top surface 20 a of the buriedinsulator layer 20. The spacers and cap layer may be removed subsequent to the etching process so that the sidewalls of thefins - In an alternative embodiment, the
fins fins SOI substrate 16 apply equally to the bulk substrate in this alternative embodiment. - Following the formation of the
fins contacts fins exterior surfaces contacts top surface 20 a of the buriedinsulator layer 20. Thecontacts fins side surfaces contacts fins contacts drain regions 13 of thedevice structure 50. - The
contacts conductor layer 25 and aliner layer 28. Theliner layer 28 is positioned between theconductor layer 25 and the respectiveexterior surfaces fins conductor layer 25 may be comprised of a metal, such as tungsten (W), that is deposited by, for example, physical vapor deposition (PVD). Theliner layer 28 may be comprised of a metal, such as titanium (Ti) or tantalum (Ta), that is deposited by, for example, chemical vapor deposition (CVD). - The
conductor layer 25 andliner layer 28 are subsequently patterned to formcontacts mask layer 29 may be applied on a top surface of the metal layers and patterned with photolithography. Themask layer 29 may comprise a light-sensitive material, such as a photoresist, that is applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to define an etch mask. Sections of themask layer 29 cover the metal layer at the intended locations of thecontacts - An etching process is then used, with the
mask layer 29 present, to pattern theconductor layer 25 andliner layer 28. Theconductor layer 25 andliner layer 28 may be patterned at a gate pitch when forming thecontacts conductor layer 25 andliner layer 28 selective to the semiconductor material of thefins - The
mask layer 29 may be removed following the conclusion of the etching process. If comprised of a photoresist, themask layer 29 may be removed by ashing or solvent stripping, followed by a cleaning process. - In an alternative embodiment, the metal forming the
contacts fins liner layer 28 may function as part of thecontacts fins liner layer 28 may be omitted from the construction of the device structure. - With reference to
FIGS. 2, 2A in which like reference numerals refer to like features inFIGS. 1, 1A and at a subsequent fabrication stage, spacers 30, 32 are formed on the side surfaces 24 a, 26 a of thecontacts spacers spacers spacers spacers contacts - In an alternative embodiment, the
spacers contacts spacers spacers fins fins drain regions 13 and channel of the device structure at locations beneath thespacers - With reference to
FIGS. 3, 3A in which like reference numerals refer to like features inFIGS. 2, 2A and at a subsequent fabrication stage, agate dielectric 34 and agate electrode 36 are formed on thefins gate dielectric 34 andgate electrode 36 are located in the gap g1 between thespacers fins gate electrode 36 may define a channel of the device structure. - The
gate dielectric 34 may be comprised of an electrical insulator with a dielectric constant (e.g., a permittivity) characteristic of a dielectric material. For example, thegate dielectric 34 may be comprised of silicon dioxide, silicon oxynitride, a high-k dielectric material such as hafnium oxide, or layered combinations of these dielectric materials, deposited by v, atomic layer deposition (ALD), etc. Thegate electrode 36 is comprised of a metal, a silicide, polycrystalline silicon (e.g., polysilicon), or a combination of these materials deposited by physical vapor deposition, chemical vapor deposition, etc. - The
gate dielectric 34 andgate electrode 36 may be formed by patterning a deposited layer stack of their constituent materials using photolithography and etching processes. To provide the patterning, a mask layer may be applied on a top surface of the layer stack and patterned with photolithography. The mask layer may comprise a photosensitive material, such as a photoresist, that is applied by spin coating, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. A section of the mask layer covers the layer stack at the intended location of thegate electrode 36 and functions as an etch mask. An etching process is used, with the mask layer present, to form thegate dielectric 34 and thegate electrode 36 from the layer stack. The etching process may be selected to remove the materials of the layer stack selective to the respective materials of thefins contacts - A planarization process, such as chemical-mechanical polishing (CMP), is employed to planarize the top surfaces of the
gate electrode 36 and thecontacts gate dielectric 34 is positioned between thegate electrode 36 and a channel in thefins drain regions 13. Thespacers gate electrode 36, are positioned between thecontacts gate electrode 36 as intervening structures. Thegate electrode 36 is formed in a self-aligned manner with the channel as constrained by the presence of thecontacts gate electrode 36 is formed. Thecontacts gate electrode 36 is formed and exist as elements in thefinal device structure 50. - The complexity of the processing method producing the
device structure 50 is reduced in comparison with the complexity of fabricating conventional device structures. Thedevice structure 50 has the form of a fin-type field effect transistor in which the physical gate length of thedevice structure 50 is determined by the contact-to-contact spacing betweencontacts gate electrode 36 is formed between thecontacts device structure 50, which eliminates limitations of on the minimum gate length that is achievable in conventional device structures. - In the process flow of fabrication stages, the
contacts contacts - The
contacts device structure 50 can be formed without a contact etch-stop layer on top of the gate electrode, and thecontacts - With reference to
FIGS. 4, 4A in which like reference numerals refer to like features inFIGS. 3, 3A and in accordance with an alternative embodiment, thespacers contacts gate electrode 36. Once removed, the exterior surfaces 10 a, 12 a, 14 a of thefins contacts gate electrode 36 are exposed. Sections of thefins fins fins - The
spacers contacts gate electrode 36. If not removed and replaced, then thespacers device structure 50 following its fabrication. In an embodiment, thespacers spacers fins - With reference to
FIGS. 5, 5A in which like reference numerals refer to like features inFIGS. 4, 4A and at a subsequent fabrication stage, spacers 40, 42 are formed inside the gaps between thecontacts gate electrode 36. Thespacers spacers spacers spacers spacers spacers spacers Spacers - With reference to
FIGS. 6, 6A in which like reference numerals refer to like features inFIGS. 5, 5A and in accordance with an alternative embodiment, thetop surface 36 a of thegate electrode 36 may be recessed below a plane containing thetop surfaces spacers spacers top surfaces contacts cavity 44. An etching process may be used that removes the material of thegate electrode 36 selective to the materials of thespacers contacts spacers spacers spacers gate electrode 36. - The
cavity 44 may be filled with adielectric layer 46 comprised of a dielectric material differing in composition from the conductive material comprising thegate electrode 36. In one embodiment, thecavity 44 may be filled during middle-of-line (MOL) processing. For example, during middle-of-line processing thecavity 44 may be filled during local interconnect formation with an electrical insulator, such as silicon dioxide (SiO2), deposited by CVD and subsequently planarized using a chemical mechanical polishing process that eliminates topography. The replacement of a portion of thegate electrode 36 with dielectric material may be effective to reduce the capacitance of thedevice structure 50. - The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refers to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a dimension within the horizontal plane.
- A feature may be “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/744,147 US20160372600A1 (en) | 2015-06-19 | 2015-06-19 | Contact-first field-effect transistors |
US16/670,894 US11101367B2 (en) | 2015-06-19 | 2019-10-31 | Contact-first field-effect transistors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/744,147 US20160372600A1 (en) | 2015-06-19 | 2015-06-19 | Contact-first field-effect transistors |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/670,894 Division US11101367B2 (en) | 2015-06-19 | 2019-10-31 | Contact-first field-effect transistors |
Publications (1)
Publication Number | Publication Date |
---|---|
US20160372600A1 true US20160372600A1 (en) | 2016-12-22 |
Family
ID=57588459
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/744,147 Abandoned US20160372600A1 (en) | 2015-06-19 | 2015-06-19 | Contact-first field-effect transistors |
US16/670,894 Active US11101367B2 (en) | 2015-06-19 | 2019-10-31 | Contact-first field-effect transistors |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/670,894 Active US11101367B2 (en) | 2015-06-19 | 2019-10-31 | Contact-first field-effect transistors |
Country Status (1)
Country | Link |
---|---|
US (2) | US20160372600A1 (en) |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5989966A (en) * | 1997-12-15 | 1999-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and a deep sub-micron field effect transistor structure for suppressing short channel effects |
US6160299A (en) * | 1997-08-29 | 2000-12-12 | Texas Instruments Incorporated | Shallow-implant elevated source/drain doping from a sidewall dopant source |
US6372589B1 (en) * | 2000-04-19 | 2002-04-16 | Advanced Micro Devices, Inc. | Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer |
US20050202618A1 (en) * | 2004-03-10 | 2005-09-15 | Atsushi Yagishita | Semiconductor device and manufacturing method of the same |
US20060197111A1 (en) * | 2005-03-02 | 2006-09-07 | Kazuya Matsuzawa | Semiconductor LSI circuit and a method for fabricating the semiconductor LSI circuit |
US20080251779A1 (en) * | 2007-04-11 | 2008-10-16 | Infineon Technologies Ag | Apparatus of memory array using finfets |
US20130020613A1 (en) * | 2011-07-19 | 2013-01-24 | Semiconductor Manufacturing International (Beijing) Corporation | Semiconductor device and manufacturing method thereof |
US20130134522A1 (en) * | 2011-11-30 | 2013-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid Fin Field-Effect Transistors |
US20130187229A1 (en) * | 2012-01-20 | 2013-07-25 | International Business Machines Corporation | Semiconductor device with a low-k spacer and method of forming the same |
US20140001569A1 (en) * | 2012-06-28 | 2014-01-02 | Walid M. Hafez | High voltage three-dimensional devices having dielectric liners |
US20140110755A1 (en) * | 2012-10-24 | 2014-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and Method for Forming Semiconductor Contacts |
US20140154846A1 (en) * | 2012-11-30 | 2014-06-05 | International Business Machines Corporation | Semiconductor device with raised source/drain and replacement metal gate |
US20150243769A1 (en) * | 2014-02-24 | 2015-08-27 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
US20160093692A1 (en) * | 2013-10-02 | 2016-03-31 | International Business Machines Corporation | Finfet semiconductor devices with replacement gate structures |
Family Cites Families (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5545579A (en) | 1995-04-04 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains |
US5960270A (en) | 1997-08-11 | 1999-09-28 | Motorola, Inc. | Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions |
US5856225A (en) | 1997-11-24 | 1999-01-05 | Chartered Semiconductor Manufacturing Ltd | Creation of a self-aligned, ion implanted channel region, after source and drain formation |
US6787424B1 (en) | 2001-02-09 | 2004-09-07 | Advanced Micro Devices, Inc. | Fully depleted SOI transistor with elevated source and drain |
US6689650B2 (en) | 2001-09-27 | 2004-02-10 | International Business Machines Corporation | Fin field effect transistor with self-aligned gate |
US6642119B1 (en) * | 2002-08-08 | 2003-11-04 | Advanced Micro Devices, Inc. | Silicide MOSFET architecture and method of manufacture |
US6864540B1 (en) | 2004-05-21 | 2005-03-08 | International Business Machines Corp. | High performance FET with elevated source/drain region |
JP4796329B2 (en) * | 2004-05-25 | 2011-10-19 | 三星電子株式会社 | Manufacturing method of multi-bridge channel type MOS transistor |
KR100652381B1 (en) * | 2004-10-28 | 2006-12-01 | 삼성전자주식회사 | Multi bridge channel field effect transistor comprising nano-wire channels and method of manufacturing the same |
US7488650B2 (en) | 2005-02-18 | 2009-02-10 | Infineon Technologies Ag | Method of forming trench-gate electrode for FinFET device |
KR100594327B1 (en) * | 2005-03-24 | 2006-06-30 | 삼성전자주식회사 | Semiconductor device comprising nanowire having rounded section and method for manufacturing the same |
KR100618900B1 (en) * | 2005-06-13 | 2006-09-01 | 삼성전자주식회사 | Mos field effect transistor having a plurality of channels and method of fabricating the same |
KR101155176B1 (en) * | 2005-07-12 | 2012-06-11 | 삼성전자주식회사 | Fabrication method of orientation controlled simgle-crystalline wire and transistor adopting the wire |
US7223650B2 (en) | 2005-10-12 | 2007-05-29 | Intel Corporation | Self-aligned gate isolation |
KR100763542B1 (en) * | 2006-10-30 | 2007-10-05 | 삼성전자주식회사 | Method of manufacturing semiconductor device having multiple channels mos transistor |
KR100906154B1 (en) * | 2007-12-05 | 2009-07-03 | 한국전자통신연구원 | Semiconductor nanowire sensor device and method for manufacturing the same |
WO2009150999A1 (en) * | 2008-06-09 | 2009-12-17 | 独立行政法人産業技術総合研究所 | Nano-wire field effect transistor, method of manufacturing the transistor, and integrated circuit including the transistor |
US7884004B2 (en) * | 2009-02-04 | 2011-02-08 | International Business Machines Corporation | Maskless process for suspending and thinning nanowires |
US8422273B2 (en) * | 2009-05-21 | 2013-04-16 | International Business Machines Corporation | Nanowire mesh FET with multiple threshold voltages |
US8216902B2 (en) * | 2009-08-06 | 2012-07-10 | International Business Machines Corporation | Nanomesh SRAM cell |
US9029834B2 (en) * | 2010-07-06 | 2015-05-12 | International Business Machines Corporation | Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric |
KR20120100630A (en) * | 2011-03-04 | 2012-09-12 | 삼성전자주식회사 | Semiconductor device, method of manufacturing the same and electronic device including semiconductor device |
US8551833B2 (en) * | 2011-06-15 | 2013-10-08 | International Businesss Machines Corporation | Double gate planar field effect transistors |
US8952355B2 (en) * | 2011-09-29 | 2015-02-10 | Intel Corporation | Electropositive metal containing layers for semiconductor applications |
US9590089B2 (en) * | 2011-12-30 | 2017-03-07 | Intel Corporation | Variable gate width for gate all-around transistors |
US8648330B2 (en) * | 2012-01-05 | 2014-02-11 | International Business Machines Corporation | Nanowire field effect transistors |
US9190419B2 (en) * | 2013-02-07 | 2015-11-17 | International Business Machines Corporation | Diode structure and method for FINFET technologies |
US9006087B2 (en) * | 2013-02-07 | 2015-04-14 | International Business Machines Corporation | Diode structure and method for wire-last nanomesh technologies |
US8927397B2 (en) * | 2013-02-07 | 2015-01-06 | International Business Machines Corporation | Diode structure and method for gate all around silicon nanowire technologies |
US8778768B1 (en) * | 2013-03-12 | 2014-07-15 | International Business Machines Corporation | Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain |
US8912609B2 (en) * | 2013-05-08 | 2014-12-16 | International Business Machines Corporation | Low extension resistance III-V compound fin field effect transistor |
US9252016B2 (en) * | 2013-09-04 | 2016-02-02 | Globalfoundries Inc. | Stacked nanowire |
US9048262B2 (en) * | 2013-09-20 | 2015-06-02 | International Business Machines Corporation | Multi-fin finFETs with merged-fin source/drains and replacement gates |
US9917240B2 (en) * | 2014-07-24 | 2018-03-13 | Samsung Electronics Co., Ltd. | Thermoelectric element, method of manufacturing the same and semiconductor device including the same |
US20160141360A1 (en) * | 2014-11-19 | 2016-05-19 | International Business Machines Corporation | Iii-v semiconductor devices with selective oxidation |
US9853101B2 (en) * | 2015-10-07 | 2017-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained nanowire CMOS device and method of forming |
US9431301B1 (en) * | 2015-12-10 | 2016-08-30 | International Business Machines Corporation | Nanowire field effect transistor (FET) and method for fabricating the same |
US10074730B2 (en) * | 2016-01-28 | 2018-09-11 | International Business Machines Corporation | Forming stacked nanowire semiconductor device |
KR102413610B1 (en) * | 2016-03-02 | 2022-06-24 | 삼성전자주식회사 | Layout design system, Semiconductor device and method for fabricating the same using the design system |
US10134905B2 (en) * | 2016-06-30 | 2018-11-20 | International Business Machines Corporation | Semiconductor device including wrap around contact, and method of forming the semiconductor device |
US9704863B1 (en) * | 2016-09-09 | 2017-07-11 | International Business Machines Corporation | Forming a hybrid channel nanosheet semiconductor structure |
US10069015B2 (en) * | 2016-09-26 | 2018-09-04 | International Business Machines Corporation | Width adjustment of stacked nanowires |
US10177226B2 (en) * | 2016-11-03 | 2019-01-08 | International Business Machines Corporation | Preventing threshold voltage variability in stacked nanosheets |
US9972542B1 (en) * | 2017-01-04 | 2018-05-15 | International Business Machines Corporation | Hybrid-channel nano-sheet FETs |
US10490559B1 (en) * | 2018-06-27 | 2019-11-26 | International Business Machines Corporation | Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions |
-
2015
- 2015-06-19 US US14/744,147 patent/US20160372600A1/en not_active Abandoned
-
2019
- 2019-10-31 US US16/670,894 patent/US11101367B2/en active Active
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6160299A (en) * | 1997-08-29 | 2000-12-12 | Texas Instruments Incorporated | Shallow-implant elevated source/drain doping from a sidewall dopant source |
US5989966A (en) * | 1997-12-15 | 1999-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and a deep sub-micron field effect transistor structure for suppressing short channel effects |
US6372589B1 (en) * | 2000-04-19 | 2002-04-16 | Advanced Micro Devices, Inc. | Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer |
US20050202618A1 (en) * | 2004-03-10 | 2005-09-15 | Atsushi Yagishita | Semiconductor device and manufacturing method of the same |
US20060197111A1 (en) * | 2005-03-02 | 2006-09-07 | Kazuya Matsuzawa | Semiconductor LSI circuit and a method for fabricating the semiconductor LSI circuit |
US20080251779A1 (en) * | 2007-04-11 | 2008-10-16 | Infineon Technologies Ag | Apparatus of memory array using finfets |
US20130020613A1 (en) * | 2011-07-19 | 2013-01-24 | Semiconductor Manufacturing International (Beijing) Corporation | Semiconductor device and manufacturing method thereof |
US20130134522A1 (en) * | 2011-11-30 | 2013-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid Fin Field-Effect Transistors |
US20130187229A1 (en) * | 2012-01-20 | 2013-07-25 | International Business Machines Corporation | Semiconductor device with a low-k spacer and method of forming the same |
US20140001569A1 (en) * | 2012-06-28 | 2014-01-02 | Walid M. Hafez | High voltage three-dimensional devices having dielectric liners |
US20140110755A1 (en) * | 2012-10-24 | 2014-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and Method for Forming Semiconductor Contacts |
US20140154846A1 (en) * | 2012-11-30 | 2014-06-05 | International Business Machines Corporation | Semiconductor device with raised source/drain and replacement metal gate |
US20160093692A1 (en) * | 2013-10-02 | 2016-03-31 | International Business Machines Corporation | Finfet semiconductor devices with replacement gate structures |
US20150243769A1 (en) * | 2014-02-24 | 2015-08-27 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
US20200066871A1 (en) | 2020-02-27 |
US11101367B2 (en) | 2021-08-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10971601B2 (en) | Replacement metal gate structures | |
US10269983B2 (en) | Stacked nanosheet field-effect transistor with air gap spacers | |
US10580704B2 (en) | Semiconductor devices with sidewall spacers of equal thickness | |
US9972495B1 (en) | Low-K dielectric spacer for a gate cut | |
US10636890B2 (en) | Chamfered replacement gate structures | |
TWI645513B (en) | Interconnects for vertical-transport field-effect transistors | |
TWI609459B (en) | Semiconductor device and formation method thereof | |
US20160172356A1 (en) | Inter-level dielectric layer in replacement metal gates and resistor fabrication | |
US11437286B2 (en) | Middle of line structures | |
US10084053B1 (en) | Gate cuts after metal gate formation | |
US10340362B2 (en) | Spacers for tight gate pitches in field effect transistors | |
TW202127584A (en) | Air spacer structures | |
US7998813B2 (en) | Methods of fabricating an access transistor having a polysilicon-comprising plug on individual of opposing sides of gate material | |
TW202013607A (en) | Intergrated circuits with capacitors | |
US11101367B2 (en) | Contact-first field-effect transistors | |
US20180350607A1 (en) | Semiconductor structure | |
CN109494249B (en) | Semiconductor device and method for manufacturing the same | |
JP2003209190A (en) | Method for manufacturing semiconductor element |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOOK, TERENCE B.;NA, MYUNG-HEE;PRANATHARTHIHARAN, BALASUBRAMANIAN;AND OTHERS;SIGNING DATES FROM 20150603 TO 20150610;REEL/FRAME:035946/0561 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: ADVISORY ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |