US20160276426A1 - MIM Capacitor and Method Forming the Same - Google Patents
MIM Capacitor and Method Forming the Same Download PDFInfo
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- US20160276426A1 US20160276426A1 US14/659,000 US201514659000A US2016276426A1 US 20160276426 A1 US20160276426 A1 US 20160276426A1 US 201514659000 A US201514659000 A US 201514659000A US 2016276426 A1 US2016276426 A1 US 2016276426A1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 85
- 238000000034 method Methods 0.000 title claims description 33
- 229920000642 polymer Polymers 0.000 claims abstract description 112
- 239000012212 insulator Substances 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims description 16
- 150000001875 compounds Chemical class 0.000 claims description 9
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- 238000000059 patterning Methods 0.000 claims description 7
- 238000007667 floating Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 186
- 229910052751 metal Inorganic materials 0.000 description 26
- 239000002184 metal Substances 0.000 description 26
- 230000008569 process Effects 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000002161 passivation Methods 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 239000006117 anti-reflective coating Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
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- 239000010949 copper Substances 0.000 description 3
- 229920002577 polybenzoxazole Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
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- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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- 239000010937 tungsten Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Definitions
- Metal-Insulator-Metal (MIM) capacitors have been widely used in functional circuits such as mixed signal circuits, analog circuits, Radio Frequency (RF) circuits, Dynamic Random Access Memories (DRAMs), embedded DRAMs, and logic operation circuits.
- RF Radio Frequency
- DRAMs Dynamic Random Access Memories
- embedded DRAMs and logic operation circuits.
- different capacitors for different functional circuits have to be integrated on a same chip to serve different purposes.
- capacitors are used as decoupling capacitors and high-frequency noise filters.
- DRAM and embedded DRAM circuits capacitors are used for memory storage, while for RF circuits, capacitors are used in oscillators and phase-shift networks for coupling and/or bypassing purposes.
- microprocessors capacitors are used for decoupling. The traditional way to combine these capacitors on a same chip is to fabricate them in different metal layers.
- Decoupling capacitors are used to decouple some parts of electrical networks from others. Noise caused by certain circuit elements is shunted through the decoupling capacitors, hence reducing the effect of the noise-generating circuit elements on adjacent circuits.
- Decoupling capacitors are also used in power supplies, so that the power supplies may accommodate the variations in current-draw, so that the variation in power supply voltage is minimized. When the current-draw in a device changes, the power supply itself cannot respond to the change instantaneously.
- the decoupling capacitors thus may act as power storages to maintain power supply voltages in response to the current-draw at frequencies ranging from hundreds of kilo-hertz to hundreds of mega-hertz.
- FIG. 1 illustrates a cross-sectional view of a package in accordance with some embodiments, wherein a capacitor is formed in a top polymer layer in the package;
- FIG. 2 illustrates a cross-sectional view of a package in accordance with some embodiments, wherein a capacitor is formed in a polymer layer underlying the top polymer layer in the package;
- FIGS. 3 through 14 illustrate cross-sectional views and a top view of intermediate stages in the formation of package in accordance with some embodiments.
- FIG. 15 illustrates a process flow for forming a capacitor in a polymer layer in accordance with some embodiments.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- a package and the method of forming the same are provided in accordance with various exemplary embodiments.
- the intermediate stages of forming the package are illustrated.
- the variations of the embodiments are discussed.
- like reference numbers are used to designate like elements.
- wafer 2 which includes semiconductor substrate 10 .
- Semiconductor substrate 10 may be a bulk silicon substrate or a silicon-on-insulator substrate. Alternatively, other semiconductor materials that include group III, group IV, and/or group V elements may also be used, which may include silicon germanium, silicon carbon, and/or III-V compound semiconductor materials.
- Integrated circuit devices such as transistors (schematically illustrated as 12 ) are formed at a surface of semiconductor substrate 10 .
- Wafer 2 may further include Inter-Layer Dielectric (ILD) 14 and interconnect structure 16 over semiconductor substrate 10 .
- Interconnect structure 16 includes metal lines 20 and vias 22 , which are formed in dielectric layers 18 .
- interconnect structure 16 may include a plurality of metal layers that are interconnected through vias 22 .
- Metal lines 20 and vias 22 may be formed of copper or copper alloys, although they can also be formed of other metals.
- dielectric layers 18 comprise low-k dielectric materials.
- the dielectric constants (k values) of the low-k dielectric materials may be lower than about 3.0, or lower than about 2.5, for example.
- Metal pads 30 are formed over interconnect structure 16 , and may be electrically couple to integrated circuit devices 12 through metal lines 20 and vias 22 .
- Metal pads 30 may be aluminum pads or aluminum-copper pads, and hence are alternatively referred to as aluminum pads 30 hereinafter, while other metallic materials may be used.
- metal pads 30 may have an aluminum (atomic) percentage between about 99.5 percent and about 99.9 percent, and a copper percentage between about 0.1 percent and about 0.5 percent.
- metal pads 30 are in physical contact with the underlying metal lines (or pads) in the top metal layer in interconnect structure 16 .
- metal pads 30 have bottom surfaces in contact with the top surfaces of metal pads 29 .
- passivation layer 32 is formed over interconnect structure 16 .
- Passivation layer 32 has a k value greater than 3 . 8 , and is formed using a non-low-k dielectric material.
- passivation layer 32 is a composite layer comprising a silicon oxide layer (not shown), and a silicon nitride layer (not shown) over the silicon oxide layer.
- Passivation layer 32 may also be formed of other non-porous dielectric materials such as Un-doped Silicate Glass (USG), silicon oxynitride, and/or the like.
- USG Un-doped Silicate Glass
- Passivation layer 32 is patterned, so that some portions of passivation layer 32 cover the edge portions of aluminum pads 30 , and the central portions of aluminum pads 30 are exposed through the openings in passivation layer 32 .
- Passivation layer 32 and metal pads 30 have some portions level with each other in accordance with some embodiments of the present disclosure.
- Polymer layer 36 is formed over metal pads 30 and passivation layer 32 . Polymer layer 36 is also patterned to form openings, with the central portions of metal pads 30 exposed through the openings in polymer layer 36 .
- polymer layer 36 is formed of polybenzoxazole (PBO).
- polymer layer 36 is formed of other polymers such as polyimide, benzocyclobutene (BCB), or the like.
- the material of polymer layer 36 may be photo sensitive, although non-photo-sensitive materials may also be used.
- Post-Passivation Interconnect (PPI) 38 is formed to have line portions 38 A (referred to as PPI lines) over polymer layer 36 , and via portions 38 B (referred to as PPI vias) extending into polymer layer 36 . PPI lines 38 A are thus electrically connected to metal pads 30 .
- Dielectric layers 40 and polymer layer 42 are formed over polymer layer 36 and PPI 38 .
- dielectric layers 40 are formed of inorganic dielectric materials including silicon oxide, silicon carbide, silicon oxycarbide, silicon nitride, or the like.
- dielectric layers 40 may include two or more layers formed of different materials.
- dielectric layers 40 may be formed of a silicon carbide layer and a silicon oxide layer over the silicon carbide layer.
- Polymer layer 42 is formed over dielectric layer 40 , and is also patterned to form openings, with vias 44 formed in the openings.
- polymer layer 42 is formed of PBO.
- polymer layer 42 is formed of other polymers such as polyimide, BCB, or the like.
- the material of polymer layer 36 may be photo sensitive, although non-photo-sensitive materials may also be used.
- Polymer layer 42 and polymer layer 36 may be formed of a same type of polymer, or may be formed of different types of polymers.
- capacitor 46 and alignment mark 48 are embedded in polymer layer 42 .
- the bottom surfaces of capacitor 46 and alignment mark 48 may be in contact with the top surface of dielectric layers 40 .
- Capacitor 46 and alignment mark 48 may have a same layered structure, with each of the layers in capacitor 46 having a corresponding layer in alignment mark 48 , and vice versa.
- Alignment mark 48 may be electrically floating.
- capacitor 46 is a decoupling capacitor, with the top electrode and the bottom electrode of capacitor 46 being electrically coupled to power supply lines such as VDD and VSS, respectively.
- capacitor 46 is used to filter noise and also used as a power storage for reducing the voltage variation resulted from the current-drawn from the power source.
- the top electrode and the bottom electrode of capacitor 46 are connected to signal lines, and capacitor 46 is used to filter noise.
- the top electrode and the bottom electrode of capacitor 46 are connected to vias 44 , which extend to the top surface of polymer layer 42 .
- PPI 50 is formed over polymer layer 42 , and is electrically connected to vias 44 .
- PPI 50 includes a plurality of redistribution lines.
- PPI 50 and PPI 38 differ in structures.
- PPI 38 includes PPI lines 38 A and vias 38 B, which are formed simultaneously using the same material(s). Accordingly, PPI lines 38 A are continuously connected to the respective vias 38 B, with no distinguishable interfaces between PPI lines 38 A and the respective vias 38 B.
- PPI lines 38 A and vias 38 B form conformal features, with thickness TP 1 of PPI lines 38 A and thickness TP 2 of vias 38 B substantially equal to each other, for example, with difference smaller than about 20 percent.
- the entireties (or substantially entireties) of PPI 50 may be over polymer layer 42 .
- PPI 50 and vias 44 are formed in different processes, and may be formed of different materials. Accordingly, there may be distinguishable interfaces between PPI 50 and the respective connecting vias 44 .
- the top surfaces of PPI vias 38 B are not flat, and may include portions lower than the top surfaces of PPI lines 38 A, or even lower than the top surface of polymer layer 36 .
- the top surfaces of PPI 50 are substantially planar.
- the difference in the structures of PPI 38 and PPI 50 are resulted from their difference in formation processes.
- the formation of PPI 38 may include forming a blanket seed layer (not shown) over polymer layer 36 and extending into the openings in polymer layer 36 , forming a mask (not shown) to cover some portions of the blanket seed layer, and performing a plating. After the plating, the mask layer is removed, and the portions of the seed layer covered by the mask layer are removed, leaving PPI 38 .
- the top surface of PPI 38 thus has a topology following the topology of polymer layer 36 and the openings in polymer layer 36 .
- vias 44 and PPI 50 are formed separately, as shown in FIGS. 13A and 14 , and hence vias 44 have top surfaces substantially level with the top surface of polymer layer 42 . As a result, PPI 50 can have substantially planar top surfaces.
- PPI 50 is in molding compound 52 , which encircles PPI 50 , and contacts the top surface of polymer layer 42 .
- the top surfaces and sidewalls of PPI 50 may also be in physical contact with molding compound 52 .
- electrical connectors 54 are formed to electrically connect to PPI 50 .
- Electrical connectors 54 may include metal regions, which may include solder balls placed on PPI 50 .
- Electrical connectors 54 may also include metal pillars.
- electrical connectors 54 include solder, the solder may be placed or plated, and the plating of solder may be similar to the formation of PPI 38 .
- Electrical connectors 54 have upper portions over the top surface of molding compound 52 , and lower portions embedded in molding compound 52 .
- wafer 2 may be sawed into individual packages 56 , each including one capacitor 46 and integrated circuit device 12 .
- FIG. 2 illustrates a cross-sectional view of wafer 2 in accordance with alternative embodiments of the present disclosure.
- the materials and the formation methods of the components in these embodiments are essentially the same as the like components, which are denoted by like reference numerals in the embodiments shown in FIG. 1 .
- the details regarding the formation process and the materials of the components shown in FIG. 2 may thus be found in the discussion of the embodiments shown in FIG. 1 .
- the wafer 2 as shown in FIG. 2 differs from the wafer 2 in FIG. 1 in that capacitor 46 and alignment mark 48 are formed in polymer layer 36 , rather than in polymer layer 42 . Accordingly, dielectric layers 40 are formed underlying polymer layer 36 , rather than underlying polymer layer 42 . The top surface of polymer layer 36 may be in contact with the bottom surface of polymer layer 42 in these embodiments.
- Capacitor 46 has a bottom surface in contact with the top surface of dielectric layers 40 . Furthermore, capacitor 46 is encircled by, and is also covered by, polymer layer 36 . Some of vias 44 are formed in polymer layer 36 to connect to the top electrode and the bottom electrode of capacitor 46 . Additional vias 44 are formed to extend into both dielectric layers 40 and polymer layer 36 to electrically connect to metal pads 30 .
- PPI 50 and PPI 38 also differ in structures.
- PPI 50 includes PPI lines 50 A and vias 50 B, which are formed simultaneously using the same material(s). Accordingly, PPI lines 50 A are continuously connected to the respective vias 50 B, with no distinguishable interfaces between PPI lines 50 A and the respective vias 50 B.
- the entireties of PPI 38 (which includes a plurality of redistribution lines) may be over polymer layer 36 .
- PPI 38 and vias 44 are formed in different processes, and may be formed of different materials. Accordingly, there may be distinguishable interfaces between PPI 38 and the respective connecting vias 44 .
- top surfaces of PPI vias 50 B are not planar, and may include portions lower than the top surfaces of PPI lines 50 A, or even lower than the top surface of polymer layer 42 .
- the top surfaces of vias 44 are substantially planar.
- FIGS. 3 through 14 illustrate the cross-sectional views and a top view of intermediate stages in the formation of some portions of wafer 2 in accordance with some embodiments.
- the portions shown in FIGS. 3 through 14 include the portions of capacitor 46 , alignment mark 48 , and some overlying and underling portions.
- the steps shown in FIG. 3 through 14 are also illustrated schematically in the process flow shown in FIG. 15 . In the subsequent discussion, the process steps shown in FIGS. 3 through 14 are discussed referring to the process steps in FIG. 15 .
- wafer 2 includes capacitor region 100 for forming a capacitor therein, logic region 200 for forming the electrical connections connected to logic (core) devices 12 ( FIGS. 1 and 2 ), and alignment mark region 300 for forming an alignment mark therein.
- Conductive features 30 / 38 are provided. The portions of wafer 2 underlying or coplanar with conductive features 30 / 38 are not illustrated. In the embodiments shown in FIG. 1 , conductive features 30 / 38 are portions of PPI 38 . In the embodiments in FIG. 2 , conductive features 30 / 38 are portions of metal pads 30 .
- Dielectric layers 40 are formed over conductive features 30 / 38 . The respective step is shown as step 402 in process flow 400 illustrated in FIG. 15 . It is appreciated that although FIG. 3 illustrates that dielectric layers 40 are planar layers, dielectric layers 40 may actually have the topology as shown in FIG. 1 or 2 . Dielectric layers 40 include dielectric layer 40 A and dielectric layer 40 B over dielectric layer 40 A. Dielectric layers 40 A and 40 B are formed of different materials, which may be inorganic materials in accordance with some embodiments. For example, dielectric layer 40 A may be formed of SiC. Thickness T 1 of dielectric layer 40 A may be in the range between about 400 ⁇ and about 700 ⁇ . Dielectric layer 40 B may be formed of silicon oxide.
- Thickness T 2 of dielectric layer 40 B may be in the range between about 800 ⁇ and about 1,200 ⁇ .
- Dielectric layers 40 A and 40 B may be formed using Plasma Enhance Chemical Vapor Deposition (PECVD), Low-Pressure Chemical Vapor Deposition (LPCVD), Atomic Layer Deposition (ALD), or the like.
- PECVD Plasma Enhance Chemical Vapor Deposition
- LPCVD Low-Pressure Chemical Vapor Deposition
- ALD Atomic Layer Deposition
- a portion of dielectric layer 40 B is etched to form recess 64 .
- the respective step is shown as step 404 in process flow 400 illustrated in FIG. 15 .
- Dielectric layer 40 A is used as the etch stop layer, and hence a top surface of dielectric layer 40 A is exposed to recess 64 .
- the top-view of recess 64 may have a shape that can be easily identified, wherein the available shapes include cross, triangle, hexagon, or the like.
- conductive layer 66 is formed of TiN, which has thickness T 3 in the range between about 300 ⁇ and about 500 ⁇ .
- Dielectric layer 68 may be formed of stacked layers ZrO 2 /Al 2 O 3 /ZrO 2 (ZAZ), which has thickness T 4 in the range between about 80 ⁇ and about 120 ⁇ .
- ZAZ has the advantageous feature of having a low equivalent oxide thickness, and hence the capacitance value of the resulting capacitor is high.
- Conductive layer 70 may be formed of TiN, which has thickness T 5 in the range between about 300 ⁇ and about 500 ⁇ .
- Layer 72 which is an anti-reflective coating, may be formed of SiON, which has thickness T 6 in the range between about 250 ⁇ and about 350 ⁇ . Stacked layers 66 , 68 , 70 , and 72 extend into recess 64 ( FIG. 4 ), and hence stacked layers 66 , 68 , 70 , and 72 form recess 74 in alignment mark region 300 .
- Layers 70 and 72 are patterned in a photolithography process to form a top electrode.
- the respective step is shown as step 408 in process flow 400 illustrated in FIG. 15 .
- the patterned layers 70 and 72 have remaining portions 70 A and 72 A, respectively, in capacitor region 100 .
- the patterned layers 70 and 72 further have remaining portions 70 B and 72 B, respectively, in alignment mark region 300 .
- layer 72 may be used as an anti-reflective coating.
- recess 74 as shown in FIG. 5 is used as an alignment mark to align the position of the photolithography mask, and the position of the patterned portions 70 A and 72 A is determined using the alignment mark.
- dielectric layers 76 and 78 are formed.
- the respective step is shown as step 410 in process flow 400 illustrated in FIG. 15 .
- dielectric layer 76 is formed of silicon oxide, which has thickness T 7 in the range between about 150 ⁇ and about 250 ⁇ .
- Dielectric layer 78 may be formed of SiN, which has thickness T 8 in the range between about 400 ⁇ and about 600 ⁇ .
- FIG. 8 illustrates the further patterning of layers 66 , 68 , 76 , and 78 .
- the respective step is shown as step 412 in process flow 400 illustrated in FIG. 15 .
- the patterned layers in capacitor region 100 thus form capacitor 46 .
- layers 66 , 68 , and 70 A are the bottom capacitor electrode, capacitor insulator, and the top capacitor electrode, respectively.
- Capacitor 46 is thus a Metal-Insulator-Metal (MIM) capacitor.
- MIM Metal-Insulator-Metal
- alignment mark 48 is formed. Since alignment mark 48 is formed simultaneously as capacitor 46 , capacitor 46 and alignment mark 48 may have same number of layers, with each layer in capacitor 46 corresponding to one of the layers in alignment mark 48 , and vice versa. Furthermore, alignment mark 48 may have a first bottom surface in contact with a top surface of dielectric layer 40 B, and a second bottom surface in contact with a top surface of dielectric layer 40 A, with a portion of alignment mark 48 penetrating through dielectric layer 40 A. The resulting alignment mark 48 is formed as an isolated feature isolated from other conductive features.
- Polymer layer 84 is formed.
- Polymer layer 84 may be the lower portion of the polymer layer 42 in the embodiments shown in FIG. 1 , or the lower portion of polymer layer 36 in the embodiments shown in FIG. 2 .
- Alignment mark 48 is fully embedded in dielectric layers including polymer layer 84 and dielectric layers 40 , and is electrically floating.
- Polymer layer 84 may have a thickness in the range between about 2 k ⁇ and about 5 k ⁇ .
- Over polymer layer 84 is further formed of hard mask layer 80 and anti-reflective coating 82 .
- hard mask layer 80 is formed of SiN, and has a thickness in the range between about 400 ⁇ and about 600 ⁇ .
- Anti-reflective coating 82 may be formed of SiON, and may have a thickness in the range between about 500 ⁇ and about 700 ⁇ .
- Hard mask layer 80 is then patterned, followed by the removal of anti-reflective coating 82 .
- the resulting structure is shown in FIG. 10 .
- Openings 81 are thus formed in hard mask layer 80 , exposing the underlying polymer layer 84 .
- polymer layer 86 is formed in a subsequent step, as shown in FIG. 11 .
- the steps shown in FIGS. 9 through 11 are shown as step 414 in process flow 400 illustrated in FIG. 15 .
- Polymer layer 86 may have a thickness in the range between about 25 k ⁇ and about 45 k ⁇ .
- Polymer layers 84 and 86 may be formed of the same polymer or different polymers.
- Anti-reflective coating 88 is formed over polymer layer 86 , and may be formed of SiON, with a thickness in the range between about 500 ⁇ and about 700 ⁇ .
- a photo lithography process is performed.
- Anti-reflective coating 88 , polymer 86 , hard mask layer 80 , and polymer layer 84 are patterned to form trenches 90 in polymer layer 86 and via openings 92 (including 92 A, 92 B, and 92 C) in polymer layer 84 .
- the patterns of via openings 92 are defined by the patterns of hard mask layer 80 , and are defined by the sizes and the locations of openings 81 ( FIG. 10 ). Accordingly, trenches 90 and via openings 92 may be formed in the same patterning process.
- Top electrode 70 A and bottom electrode 66 are exposed to via openings 92 A and 92 B, respectively.
- One of conductive features 30 / 38 in logic region 200 is exposed to opening 92 C.
- FIG. 13A illustrates the formation of conductive vias 44 A, 44 B, and 44 C, which are formed by filling trenches 90 and via openings 92 with a conductive material such as copper, aluminum, tungsten, cobalt, or alloys thereof.
- the respective step is shown as step 402 in process flow 400 illustrated in FIG. 15 .
- the filling may be performed by a selective plating such as electro-less plating.
- the top surfaces of vias 44 A, 44 B, and 44 C may be level with, slightly higher than, or slightly lower than, the top surface of polymer layer 86 or the top surface of layer 88 .
- Conductive vias 44 A, 44 B, and 44 C are thus electrically connected to top electrode 70 A, bottom electrode 66 , and conductive feature 30 / 38 , respectively.
- via 44 A includes upper portion 94 A in polymer layer 86 and lower portion 94 B in polymer layer 84 , with lower portion 94 B smaller than upper portion 94 A.
- the upper portion 94 A may further penetrate through hard mask layer 80 and extend into polymer layer 84 slightly.
- lower portion 94 B penetrates through hard mask layer 80 and polymer layer 84 , while upper portion 94 A stops on the top surface of hard mask layer 80 .
- Vias 44 B and 44 C have similar structures as vias 44 A, except they extend deeper than via 44 A. Via 44 further penetrates through dielectric layers 40 A and 40 B to contact the top surface of conductive feature 30 / 38 .
- FIG. 13B illustrates a top view of the structure shown in FIG. 13A , wherein the top view shapes of via portions 94 A and 94 B may be rectangles, circles, hexagons, or the like.
- the upper portions 94 A of all vias 44 throughout the entire wafer 2 are used for interconnecting the respective lower portions 94 B to the overlying RDLs, and are not used for electrical routing laterally.
- Polymer layers 84 and 86 are in combination referred to as a two-step polymer layer, which is either the polymer layer 42 in the embodiments shown in FIG. 1 , or the polymer layer 36 in the embodiments shown in FIG. 2 .
- PPI 38 / 50 After the formation of the structure in FIG. 14 , further process may be performed to form PPI 38 / 50 , as shown in FIG. 14 .
- PPI 38 / 50 is PPI 50
- PPI 38 / 50 is PPI 38 .
- PPI 38 / 50 hs the function of lateral routing, unlike vias 44 A, 44 B, and 44 C.
- the redistribution lines of PPI 38 / 50 may be connected to power supplies such as VDD and VSS.
- capacitors such as decoupling capacitors in polymer layers
- the formation of the capacitors may be integrated with the process of wafer level chip-scale package.
- a package inorganic dielectric layer, and a capacitor.
- the capacitor includes a bottom electrode having a top surface in contact with a top surface of the inorganic dielectric layer, an insulator over the bottom electrode, and a top electrode over the insulator.
- the package further includes a polymer layer covering the capacitor, with a portion of the polymer layer being coplanar with the capacitor and encircling the capacitor. The polymer contacts the top surface of the inorganic dielectric layer.
- a package in accordance with alternative embodiments of the present disclosure, includes a capacitor, which includes a bottom electrode, an insulator over the bottom electrode, and a top electrode over the insulator.
- a polymer layer covers the capacitor, with a portion of the polymer layer being coplanar with the capacitor and encircling the capacitor.
- An alignment mark has an upper portion in the polymer layer, wherein the alignment mark has same layers formed of same materials as the capacitor. The alignment mark is electrically floating.
- a method includes forming a first conductive layer over a first dielectric layer, forming an insulator layer over the first conductive layer, and forming a second conductive layer over the insulator.
- the insulator layer and the second conductive layer are patterned, with each having a portion remaining.
- a dielectric layer is formed to cover the patterned insulator layer and the patterned second conductive layer.
- the first conductive layer is then patterned, with remaining portions of the second conductive layer, the insulator layer, and the first conductive layer forming a top electrode, a capacitor insulator, and a bottom electrode, respectively, of a capacitor.
- a polymer layer is disposed to cover the capacitor, with the first polymer layer including a portion level with the capacitor.
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Abstract
Description
- Metal-Insulator-Metal (MIM) capacitors have been widely used in functional circuits such as mixed signal circuits, analog circuits, Radio Frequency (RF) circuits, Dynamic Random Access Memories (DRAMs), embedded DRAMs, and logic operation circuits. In system-on-chip applications, different capacitors for different functional circuits have to be integrated on a same chip to serve different purposes. For example, in mixed-signal circuits, capacitors are used as decoupling capacitors and high-frequency noise filters. For DRAM and embedded DRAM circuits, capacitors are used for memory storage, while for RF circuits, capacitors are used in oscillators and phase-shift networks for coupling and/or bypassing purposes. For microprocessors, capacitors are used for decoupling. The traditional way to combine these capacitors on a same chip is to fabricate them in different metal layers.
- Decoupling capacitors are used to decouple some parts of electrical networks from others. Noise caused by certain circuit elements is shunted through the decoupling capacitors, hence reducing the effect of the noise-generating circuit elements on adjacent circuits. In addition, Decoupling capacitors are also used in power supplies, so that the power supplies may accommodate the variations in current-draw, so that the variation in power supply voltage is minimized. When the current-draw in a device changes, the power supply itself cannot respond to the change instantaneously. The decoupling capacitors thus may act as power storages to maintain power supply voltages in response to the current-draw at frequencies ranging from hundreds of kilo-hertz to hundreds of mega-hertz.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 illustrates a cross-sectional view of a package in accordance with some embodiments, wherein a capacitor is formed in a top polymer layer in the package; -
FIG. 2 illustrates a cross-sectional view of a package in accordance with some embodiments, wherein a capacitor is formed in a polymer layer underlying the top polymer layer in the package; -
FIGS. 3 through 14 illustrate cross-sectional views and a top view of intermediate stages in the formation of package in accordance with some embodiments; and -
FIG. 15 illustrates a process flow for forming a capacitor in a polymer layer in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- A package and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the package are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
- Referring to
FIG. 1 ,wafer 2, which includessemiconductor substrate 10, is provided.Semiconductor substrate 10 may be a bulk silicon substrate or a silicon-on-insulator substrate. Alternatively, other semiconductor materials that include group III, group IV, and/or group V elements may also be used, which may include silicon germanium, silicon carbon, and/or III-V compound semiconductor materials. Integrated circuit devices such as transistors (schematically illustrated as 12) are formed at a surface ofsemiconductor substrate 10.Wafer 2 may further include Inter-Layer Dielectric (ILD) 14 andinterconnect structure 16 oversemiconductor substrate 10.Interconnect structure 16 includesmetal lines 20 andvias 22, which are formed indielectric layers 18. The metal lines at a same level are collectively referred to as a metal layer hereinafter. Accordingly,interconnect structure 16 may include a plurality of metal layers that are interconnected throughvias 22.Metal lines 20 andvias 22 may be formed of copper or copper alloys, although they can also be formed of other metals. In accordance with some embodiments of the present disclosure,dielectric layers 18 comprise low-k dielectric materials. The dielectric constants (k values) of the low-k dielectric materials may be lower than about 3.0, or lower than about 2.5, for example. -
Metal pads 30 are formed overinterconnect structure 16, and may be electrically couple to integratedcircuit devices 12 throughmetal lines 20 andvias 22.Metal pads 30 may be aluminum pads or aluminum-copper pads, and hence are alternatively referred to asaluminum pads 30 hereinafter, while other metallic materials may be used. For example,metal pads 30 may have an aluminum (atomic) percentage between about 99.5 percent and about 99.9 percent, and a copper percentage between about 0.1 percent and about 0.5 percent. In accordance with some embodiments of the present disclosure,metal pads 30 are in physical contact with the underlying metal lines (or pads) in the top metal layer ininterconnect structure 16. For example, as shown inFIG. 1 ,metal pads 30 have bottom surfaces in contact with the top surfaces ofmetal pads 29. - As also shown in
FIG. 1 ,passivation layer 32 is formed overinterconnect structure 16.Passivation layer 32 has a k value greater than 3.8, and is formed using a non-low-k dielectric material. In accordance with some embodiments of the present disclosure,passivation layer 32 is a composite layer comprising a silicon oxide layer (not shown), and a silicon nitride layer (not shown) over the silicon oxide layer.Passivation layer 32 may also be formed of other non-porous dielectric materials such as Un-doped Silicate Glass (USG), silicon oxynitride, and/or the like. -
Passivation layer 32 is patterned, so that some portions ofpassivation layer 32 cover the edge portions ofaluminum pads 30, and the central portions ofaluminum pads 30 are exposed through the openings inpassivation layer 32.Passivation layer 32 andmetal pads 30 have some portions level with each other in accordance with some embodiments of the present disclosure. -
Polymer layer 36 is formed overmetal pads 30 andpassivation layer 32.Polymer layer 36 is also patterned to form openings, with the central portions ofmetal pads 30 exposed through the openings inpolymer layer 36. In accordance with some embodiments of the present disclosure,polymer layer 36 is formed of polybenzoxazole (PBO). In alternative embodiments,polymer layer 36 is formed of other polymers such as polyimide, benzocyclobutene (BCB), or the like. The material ofpolymer layer 36 may be photo sensitive, although non-photo-sensitive materials may also be used. - Post-Passivation Interconnect (PPI) 38 is formed to have
line portions 38A (referred to as PPI lines) overpolymer layer 36, and viaportions 38B (referred to as PPI vias) extending intopolymer layer 36.PPI lines 38A are thus electrically connected tometal pads 30. -
Dielectric layers 40 andpolymer layer 42 are formed overpolymer layer 36 andPPI 38. In accordance with some embodiments of the present disclosure,dielectric layers 40 are formed of inorganic dielectric materials including silicon oxide, silicon carbide, silicon oxycarbide, silicon nitride, or the like. Furthermore,dielectric layers 40 may include two or more layers formed of different materials. For example,dielectric layers 40 may be formed of a silicon carbide layer and a silicon oxide layer over the silicon carbide layer. -
Polymer layer 42 is formed overdielectric layer 40, and is also patterned to form openings, withvias 44 formed in the openings. In accordance with some embodiments of the present disclosure,polymer layer 42 is formed of PBO. In alternative embodiments,polymer layer 42 is formed of other polymers such as polyimide, BCB, or the like. The material ofpolymer layer 36 may be photo sensitive, although non-photo-sensitive materials may also be used.Polymer layer 42 andpolymer layer 36 may be formed of a same type of polymer, or may be formed of different types of polymers. - In accordance with some embodiments of the present disclosure,
capacitor 46 andalignment mark 48 are embedded inpolymer layer 42. The bottom surfaces ofcapacitor 46 andalignment mark 48 may be in contact with the top surface of dielectric layers 40.Capacitor 46 andalignment mark 48 may have a same layered structure, with each of the layers incapacitor 46 having a corresponding layer inalignment mark 48, and vice versa.Alignment mark 48 may be electrically floating. In accordance with some embodiments of the present disclosure,capacitor 46 is a decoupling capacitor, with the top electrode and the bottom electrode ofcapacitor 46 being electrically coupled to power supply lines such as VDD and VSS, respectively. Accordingly,capacitor 46 is used to filter noise and also used as a power storage for reducing the voltage variation resulted from the current-drawn from the power source. In accordance with alternative embodiments of the present disclosure, the top electrode and the bottom electrode ofcapacitor 46 are connected to signal lines, andcapacitor 46 is used to filter noise. The top electrode and the bottom electrode ofcapacitor 46 are connected tovias 44, which extend to the top surface ofpolymer layer 42. -
PPI 50 is formed overpolymer layer 42, and is electrically connected tovias 44.PPI 50 includes a plurality of redistribution lines. In accordance with some embodiments of the present disclosure,PPI 50 andPPI 38 differ in structures. For example,PPI 38 includesPPI lines 38A and vias 38B, which are formed simultaneously using the same material(s). Accordingly,PPI lines 38A are continuously connected to therespective vias 38B, with no distinguishable interfaces betweenPPI lines 38A and therespective vias 38B.PPI lines 38A and vias 38B form conformal features, with thickness TP1 ofPPI lines 38A and thickness TP2 ofvias 38B substantially equal to each other, for example, with difference smaller than about 20 percent. On the other hand, the entireties (or substantially entireties) ofPPI 50 may be overpolymer layer 42.PPI 50 and vias 44 are formed in different processes, and may be formed of different materials. Accordingly, there may be distinguishable interfaces betweenPPI 50 and the respective connectingvias 44. In addition, the top surfaces of PPI vias 38B are not flat, and may include portions lower than the top surfaces ofPPI lines 38A, or even lower than the top surface ofpolymer layer 36. On the other hand, the top surfaces ofPPI 50 are substantially planar. - The difference in the structures of
PPI 38 andPPI 50 are resulted from their difference in formation processes. For example, the formation ofPPI 38 may include forming a blanket seed layer (not shown) overpolymer layer 36 and extending into the openings inpolymer layer 36, forming a mask (not shown) to cover some portions of the blanket seed layer, and performing a plating. After the plating, the mask layer is removed, and the portions of the seed layer covered by the mask layer are removed, leavingPPI 38. The top surface ofPPI 38 thus has a topology following the topology ofpolymer layer 36 and the openings inpolymer layer 36. On the other hand, vias 44 andPPI 50 are formed separately, as shown inFIGS. 13A and 14 , and hence vias 44 have top surfaces substantially level with the top surface ofpolymer layer 42. As a result,PPI 50 can have substantially planar top surfaces. - In accordance with some embodiments,
PPI 50 is inmolding compound 52, which encirclesPPI 50, and contacts the top surface ofpolymer layer 42. The top surfaces and sidewalls ofPPI 50 may also be in physical contact withmolding compound 52. - In accordance with some embodiments of the present disclosure,
electrical connectors 54 are formed to electrically connect toPPI 50.Electrical connectors 54 may include metal regions, which may include solder balls placed onPPI 50.Electrical connectors 54 may also include metal pillars. In the embodimentselectrical connectors 54 include solder, the solder may be placed or plated, and the plating of solder may be similar to the formation ofPPI 38.Electrical connectors 54 have upper portions over the top surface ofmolding compound 52, and lower portions embedded inmolding compound 52. - After the formation of
electrical connectors 54,wafer 2 may be sawed intoindividual packages 56, each including onecapacitor 46 andintegrated circuit device 12. -
FIG. 2 illustrates a cross-sectional view ofwafer 2 in accordance with alternative embodiments of the present disclosure. Unless specified otherwise, the materials and the formation methods of the components in these embodiments are essentially the same as the like components, which are denoted by like reference numerals in the embodiments shown inFIG. 1 . The details regarding the formation process and the materials of the components shown inFIG. 2 may thus be found in the discussion of the embodiments shown inFIG. 1 . - The
wafer 2 as shown inFIG. 2 differs from thewafer 2 inFIG. 1 in thatcapacitor 46 andalignment mark 48 are formed inpolymer layer 36, rather than inpolymer layer 42. Accordingly,dielectric layers 40 are formedunderlying polymer layer 36, rather than underlyingpolymer layer 42. The top surface ofpolymer layer 36 may be in contact with the bottom surface ofpolymer layer 42 in these embodiments. -
Capacitor 46 has a bottom surface in contact with the top surface of dielectric layers 40. Furthermore,capacitor 46 is encircled by, and is also covered by,polymer layer 36. Some ofvias 44 are formed inpolymer layer 36 to connect to the top electrode and the bottom electrode ofcapacitor 46.Additional vias 44 are formed to extend into bothdielectric layers 40 andpolymer layer 36 to electrically connect tometal pads 30. - In accordance with the embodiments shown in
FIG. 2 ,PPI 50 andPPI 38 also differ in structures. For example,PPI 50 includesPPI lines 50A and vias 50B, which are formed simultaneously using the same material(s). Accordingly,PPI lines 50A are continuously connected to therespective vias 50B, with no distinguishable interfaces betweenPPI lines 50A and therespective vias 50B. On the other hand, the entireties of PPI 38 (which includes a plurality of redistribution lines) may be overpolymer layer 36.PPI 38 and vias 44 are formed in different processes, and may be formed of different materials. Accordingly, there may be distinguishable interfaces betweenPPI 38 and the respective connectingvias 44. In addition, the top surfaces of PPI vias 50B are not planar, and may include portions lower than the top surfaces ofPPI lines 50A, or even lower than the top surface ofpolymer layer 42. On the other hand, the top surfaces ofvias 44 are substantially planar. -
FIGS. 3 through 14 illustrate the cross-sectional views and a top view of intermediate stages in the formation of some portions ofwafer 2 in accordance with some embodiments. The portions shown inFIGS. 3 through 14 include the portions ofcapacitor 46,alignment mark 48, and some overlying and underling portions. The steps shown inFIG. 3 through 14 are also illustrated schematically in the process flow shown inFIG. 15 . In the subsequent discussion, the process steps shown inFIGS. 3 through 14 are discussed referring to the process steps inFIG. 15 . - Referring to
FIG. 3 ,wafer 2 includescapacitor region 100 for forming a capacitor therein,logic region 200 for forming the electrical connections connected to logic (core) devices 12 (FIGS. 1 and 2 ), andalignment mark region 300 for forming an alignment mark therein. Conductive features 30/38 are provided. The portions ofwafer 2 underlying or coplanar withconductive features 30/38 are not illustrated. In the embodiments shown inFIG. 1 , conductive features 30/38 are portions ofPPI 38. In the embodiments inFIG. 2 , conductive features 30/38 are portions ofmetal pads 30. -
Dielectric layers 40 are formed overconductive features 30/38. The respective step is shown asstep 402 inprocess flow 400 illustrated inFIG. 15 . It is appreciated that althoughFIG. 3 illustrates thatdielectric layers 40 are planar layers,dielectric layers 40 may actually have the topology as shown inFIG. 1 or 2 .Dielectric layers 40 includedielectric layer 40A anddielectric layer 40B overdielectric layer 40A.Dielectric layers dielectric layer 40A may be formed of SiC. Thickness T1 ofdielectric layer 40A may be in the range between about 400 Å and about 700 Å.Dielectric layer 40B may be formed of silicon oxide. Thickness T2 ofdielectric layer 40B may be in the range between about 800 Å and about 1,200 Å.Dielectric layers - Referring to
FIG. 4 , a portion ofdielectric layer 40B is etched to formrecess 64. The respective step is shown asstep 404 inprocess flow 400 illustrated inFIG. 15 .Dielectric layer 40A is used as the etch stop layer, and hence a top surface ofdielectric layer 40A is exposed torecess 64. The top-view ofrecess 64 may have a shape that can be easily identified, wherein the available shapes include cross, triangle, hexagon, or the like. - Next, referring to
FIG. 5 , a plurality oflayers step 406 inprocess flow 400 illustrated inFIG. 15 . In accordance with some exemplary embodiments of the present disclosure,conductive layer 66 is formed of TiN, which has thickness T3 in the range between about 300 Å and about 500 Å.Dielectric layer 68 may be formed of stacked layers ZrO2/Al2O3/ZrO2 (ZAZ), which has thickness T4 in the range between about 80 Å and about 120 Å. ZAZ has the advantageous feature of having a low equivalent oxide thickness, and hence the capacitance value of the resulting capacitor is high. Conductive layer 70 may be formed of TiN, which has thickness T5 in the range between about 300 Å and about 500 Å. Layer 72, which is an anti-reflective coating, may be formed of SiON, which has thickness T6 in the range between about 250 Å and about 350 Å.Stacked layers FIG. 4 ), and hence stackedlayers form recess 74 inalignment mark region 300. - Layers 70 and 72 are patterned in a photolithography process to form a top electrode. The respective step is shown as
step 408 inprocess flow 400 illustrated inFIG. 15 . As shown inFIG. 6 , the patterned layers 70 and 72 have remainingportions capacitor region 100. The patterned layers 70 and 72 further have remainingportions alignment mark region 300. During the patterning, layer 72 may be used as an anti-reflective coating. Furthermore, during the photolithography process, recess 74 as shown inFIG. 5 is used as an alignment mark to align the position of the photolithography mask, and the position of thepatterned portions - Next, as shown in
FIG. 7 ,dielectric layers step 410 inprocess flow 400 illustrated inFIG. 15 . In accordance with some exemplary embodiments of the present disclosure,dielectric layer 76 is formed of silicon oxide, which has thickness T7 in the range between about 150 Å and about 250 Å.Dielectric layer 78 may be formed of SiN, which has thickness T8 in the range between about 400 Å and about 600 Å. -
FIG. 8 illustrates the further patterning oflayers step 412 inprocess flow 400 illustrated inFIG. 15 . The patterned layers incapacitor region 100 thusform capacitor 46. Incapacitor 46, layers 66, 68, and 70A are the bottom capacitor electrode, capacitor insulator, and the top capacitor electrode, respectively.Capacitor 46 is thus a Metal-Insulator-Metal (MIM) capacitor. - Furthermore, in the
alignment mark region 300,alignment mark 48 is formed. Sincealignment mark 48 is formed simultaneously ascapacitor 46,capacitor 46 andalignment mark 48 may have same number of layers, with each layer incapacitor 46 corresponding to one of the layers inalignment mark 48, and vice versa. Furthermore,alignment mark 48 may have a first bottom surface in contact with a top surface ofdielectric layer 40B, and a second bottom surface in contact with a top surface ofdielectric layer 40A, with a portion ofalignment mark 48 penetrating throughdielectric layer 40A. The resultingalignment mark 48 is formed as an isolated feature isolated from other conductive features. - Next, as shown in
FIG. 9 ,polymer layer 84 is formed.Polymer layer 84 may be the lower portion of thepolymer layer 42 in the embodiments shown inFIG. 1 , or the lower portion ofpolymer layer 36 in the embodiments shown inFIG. 2 .Alignment mark 48 is fully embedded in dielectric layers includingpolymer layer 84 anddielectric layers 40, and is electrically floating.Polymer layer 84 may have a thickness in the range between about 2 kÅ and about 5 kÅ. Overpolymer layer 84 is further formed ofhard mask layer 80 andanti-reflective coating 82. In accordance with some embodiments,hard mask layer 80 is formed of SiN, and has a thickness in the range between about 400 Å and about 600 Å.Anti-reflective coating 82 may be formed of SiON, and may have a thickness in the range between about 500 Å and about 700 Å. -
Hard mask layer 80 is then patterned, followed by the removal ofanti-reflective coating 82. The resulting structure is shown inFIG. 10 .Openings 81 are thus formed inhard mask layer 80, exposing theunderlying polymer layer 84. In a subsequent step, as shown inFIG. 11 ,polymer layer 86 is formed. The steps shown inFIGS. 9 through 11 are shown asstep 414 inprocess flow 400 illustrated inFIG. 15 .Polymer layer 86 may have a thickness in the range between about 25 kÅ and about 45 kÅ. Polymer layers 84 and 86 may be formed of the same polymer or different polymers.Anti-reflective coating 88 is formed overpolymer layer 86, and may be formed of SiON, with a thickness in the range between about 500 Å and about 700 Å. - Referring to
FIG. 12 , a photo lithography process is performed.Anti-reflective coating 88,polymer 86,hard mask layer 80, andpolymer layer 84 are patterned to formtrenches 90 inpolymer layer 86 and via openings 92 (including 92A, 92B, and 92C) inpolymer layer 84. The patterns of viaopenings 92 are defined by the patterns ofhard mask layer 80, and are defined by the sizes and the locations of openings 81 (FIG. 10 ). Accordingly,trenches 90 and viaopenings 92 may be formed in the same patterning process.Top electrode 70A andbottom electrode 66 are exposed to viaopenings conductive features 30/38 inlogic region 200 is exposed toopening 92C. -
FIG. 13A illustrates the formation of conductive vias 44A, 44B, and 44C, which are formed by fillingtrenches 90 and viaopenings 92 with a conductive material such as copper, aluminum, tungsten, cobalt, or alloys thereof. The respective step is shown asstep 402 inprocess flow 400 illustrated inFIG. 15 . The filling may be performed by a selective plating such as electro-less plating. In the resulting structure, the top surfaces of vias 44A, 44B, and 44C may be level with, slightly higher than, or slightly lower than, the top surface ofpolymer layer 86 or the top surface oflayer 88.Conductive vias top electrode 70A,bottom electrode 66, andconductive feature 30/38, respectively. - As shown in
FIG. 13A , via 44A includesupper portion 94A inpolymer layer 86 andlower portion 94B inpolymer layer 84, withlower portion 94B smaller thanupper portion 94A. Theupper portion 94A may further penetrate throughhard mask layer 80 and extend intopolymer layer 84 slightly. In alternative embodiments (not shown),lower portion 94B penetrates throughhard mask layer 80 andpolymer layer 84, whileupper portion 94A stops on the top surface ofhard mask layer 80.Vias dielectric layers conductive feature 30/38. -
FIG. 13B illustrates a top view of the structure shown inFIG. 13A , wherein the top view shapes of viaportions upper portions 94A of allvias 44 throughout theentire wafer 2 are used for interconnecting the respectivelower portions 94B to the overlying RDLs, and are not used for electrical routing laterally. - Polymer layers 84 and 86 are in combination referred to as a two-step polymer layer, which is either the
polymer layer 42 in the embodiments shown inFIG. 1 , or thepolymer layer 36 in the embodiments shown inFIG. 2 . - After the formation of the structure in
FIG. 14 , further process may be performed to formPPI 38/50, as shown inFIG. 14 . For example, when the embodiments shown inFIG. 1 are adopted,PPI 38/50 isPPI 50, while when the embodiments shown inFIG. 2 are adopted,PPI 38/50 isPPI 38.PPI 38/50 hs the function of lateral routing, unlikevias PPI 38/50 may be connected to power supplies such as VDD and VSS. - The embodiments of the present disclosure have some advantageous features. By forming capacitors such as decoupling capacitors in polymer layers, the formation of the capacitors may be integrated with the process of wafer level chip-scale package.
- In accordance with some embodiments of the present disclosure, a package includes an inorganic dielectric layer, and a capacitor. The capacitor includes a bottom electrode having a top surface in contact with a top surface of the inorganic dielectric layer, an insulator over the bottom electrode, and a top electrode over the insulator. The package further includes a polymer layer covering the capacitor, with a portion of the polymer layer being coplanar with the capacitor and encircling the capacitor. The polymer contacts the top surface of the inorganic dielectric layer.
- In accordance with alternative embodiments of the present disclosure, a package includes a capacitor, which includes a bottom electrode, an insulator over the bottom electrode, and a top electrode over the insulator. A polymer layer covers the capacitor, with a portion of the polymer layer being coplanar with the capacitor and encircling the capacitor. An alignment mark has an upper portion in the polymer layer, wherein the alignment mark has same layers formed of same materials as the capacitor. The alignment mark is electrically floating.
- In accordance with yet alternative embodiments of the present disclosure, a method includes forming a first conductive layer over a first dielectric layer, forming an insulator layer over the first conductive layer, and forming a second conductive layer over the insulator. The insulator layer and the second conductive layer are patterned, with each having a portion remaining. A dielectric layer is formed to cover the patterned insulator layer and the patterned second conductive layer. The first conductive layer is then patterned, with remaining portions of the second conductive layer, the insulator layer, and the first conductive layer forming a top electrode, a capacitor insulator, and a bottom electrode, respectively, of a capacitor. A polymer layer is disposed to cover the capacitor, with the first polymer layer including a portion level with the capacitor.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (23)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/659,000 US9461106B1 (en) | 2015-03-16 | 2015-03-16 | MIM capacitor and method forming the same |
CN201510453961.2A CN105990263B (en) | 2015-03-16 | 2015-07-29 | Mim capacitor and forming method thereof |
KR1020150141088A KR101881198B1 (en) | 2015-03-16 | 2015-10-07 | Mim capacitor and method forming the same |
TW104138920A TWI584424B (en) | 2015-03-16 | 2015-11-24 | Mim capacitor and method forming the same |
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Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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2015
- 2015-03-16 US US14/659,000 patent/US9461106B1/en active Active
- 2015-07-29 CN CN201510453961.2A patent/CN105990263B/en active Active
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- 2015-11-24 TW TW104138920A patent/TWI584424B/en active
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US11503711B2 (en) * | 2019-09-27 | 2022-11-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for inserting dummy capacitor structures |
Also Published As
Publication number | Publication date |
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US9461106B1 (en) | 2016-10-04 |
TW201635452A (en) | 2016-10-01 |
KR101881198B1 (en) | 2018-07-23 |
TWI584424B (en) | 2017-05-21 |
CN105990263B (en) | 2018-09-28 |
CN105990263A (en) | 2016-10-05 |
KR20160111311A (en) | 2016-09-26 |
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