US20150380276A1 - Method for manufacturing semiconductor package - Google Patents
Method for manufacturing semiconductor package Download PDFInfo
- Publication number
- US20150380276A1 US20150380276A1 US14/848,726 US201514848726A US2015380276A1 US 20150380276 A1 US20150380276 A1 US 20150380276A1 US 201514848726 A US201514848726 A US 201514848726A US 2015380276 A1 US2015380276 A1 US 2015380276A1
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- Prior art keywords
- frame
- forming
- package
- semiconductor package
- manufacturing
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- Abandoned
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title abstract description 72
- 238000000465 moulding Methods 0.000 claims abstract description 25
- 229920006336 epoxy molding compound Polymers 0.000 claims description 15
- 238000007747 plating Methods 0.000 claims description 5
- 239000003086 colorant Substances 0.000 claims description 2
- 239000002390 adhesive tape Substances 0.000 claims 2
- 229920005989 resin Polymers 0.000 abstract description 21
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- 238000005520 cutting process Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
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- 238000003754 machining Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
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- 239000004416 thermosoftening plastic Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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Images
Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
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- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/12—Passive devices, e.g. 2 terminal devices
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a method for manufacturing a semiconductor package.
- a semiconductor package is manufactured by first cutting a wafer along a scribe line to be separated into individual semiconductor chips and packaging the individual semiconductor chips.
- WLP wafer level package
- CSP semiconductor chip scale package
- a wafer level package (WLP) technology is a technology of implementing miniaturization, weight reduction, high performance, and the like.
- An embedded type of wafer level package enables a manufacturing of the wafer level package having a fan-out form in which an external connection terminal may be disposed in a package larger than a size of the semiconductor chip.
- Patent Document 1 International Patent Laid-Open Publication No. WO 2009-035858
- the present invention has been made in an effort to provide a method for improving pattern alignment and EMC molding flatness based on an epoxy molding compound (EMC) molding technology which enables a fan out wafer level package (fan out WLP) to have a substrate size to thereby mass-produce the fan out WLP.
- EMC epoxy molding compound
- the present invention has been made in an effort to provide a method for encapsulating a plurality of semiconductor devices already separated and then separating the semiconductor devices into individual chips in a final process.
- a method for manufacturing a semiconductor package including: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.
- the method for manufacturing a semiconductor package may further include: prior to the peeling of the tape, curing the molding part.
- the resin layer may be formed in a single layer or a multilayer.
- the frame may be an epoxy molding compound (EMC).
- EMC epoxy molding compound
- a cross section height of the frame may be larger than a thickness of the semiconductor chip.
- the molding part may be an epoxy molding compound (EMC).
- EMC epoxy molding compound
- the method for manufacturing a semiconductor package may further include: after the forming of the molding part, curing the molding part to fix the semiconductor chip.
- the frame and the molding part may have different colors.
- the forming of the wiring may include: forming a via hole in the resin layer; and forming the wiring by plating and filling the via hole.
- the method for manufacturing a semiconductor package may further include: after the forming of the wiring, singulating the semiconductor package as individual semiconductor packages by a sawing process, wherein in the singulating of the semiconductor package, a dummy part between the frame and the individual semiconductor package is removed.
- FIGS. 1 to 8 are process diagrams sequentially illustrating a method for manufacturing a semiconductor package according to a preferred embodiment of the present invention, in which
- FIG. 1 is a front view and FIGS. 2 to 8 are cross-sectional views.
- FIGS. 1 to 8 are process diagrams sequentially illustrating a method for manufacturing a semiconductor package 100 according to a preferred embodiment of the present invention, in which FIG. 1 is a front view and FIGS. 2 to 8 are cross-sectional views.
- FIG. 1 is a front view of a frame of the semiconductor package according to a preferred embodiment of the present invention.
- a quadrangular frame 10 having a plurality of quadrangular holes is prepared.
- the frame 10 may be manufactured at various sizes so as to easily mass-produced and may be used.
- the plurality of quadrangular holes may be manufactured at a proper size, and thus may be inserted with semiconductor chips 30 to be described below and a size of the quadrangular holes may also be changed depending on a size of the semiconductor chip 30 .
- the frame 10 may be represented by a color different from a molding part 40 to easily be differentiated from the molding part 40 to be described below.
- a material of the frame 10 may be an epoxy molding compound (EMC).
- EMC epoxy molding compound
- the material of the frame is not limited thereto, and therefore any material to facilitate cutting in a sawing process may be used.
- the cutting of the wafer level semiconductor package may be facilitated by using the above material when the semiconductor substrate is manufactured at a larger area like the general substrate, not at the existing wafer level size and then is finally singulated.
- the material of the frame 10 metal, ceramics, and a composite material thereof having high strength and excellent durability are used, characteristics of the frame 10 supporting the semiconductor chip 30 may be improved.
- the semiconductor package 100 may suffer from segmentation correction and manufacturing completeness thereof may be increased.
- the plurality of semiconductor chips 30 and the frame 20 are attached on one surface of a tape 20 .
- the frame 10 and the semiconductor chips 30 are bonded on the one surface of the tape 20 by preparing the film-shaped tape 20 having a predetermined level of adhesion.
- a cross section height of the frame 10 may be higher than that of the semiconductor chip 30 .
- a thickness of the cross section of the frame 10 may be controlled as the designer demand.
- the frame 10 formed with the mark is first bonded and then the semiconductor chip 30 is bonded, such that the frame 10 may be accurately bonded at positions at which the individual semiconductor chips 30 are bonded.
- connection pad of the semiconductor chip 30 is bonded with the tape 20 by a face-down type.
- the molding part 40 is formed on the tape 20 to cover the semiconductor chip 30 and the frame 10 .
- the molding part 40 is formed to be filled on the tape 20 , and the molding part 40 is formed and then cured such that the semiconductor chip 30 may be well fixed.
- thermal insulation of the semiconductor chip 30 is effectively performed by forming the molding part 40 .
- the material of the molding part 40 a silicon gel, an epoxy molding compound (EMC), and the like, may be used, but the preferred embodiment of the present invention is not limited thereto.
- EMC epoxy molding compound
- the tape 20 is peeled and then a portion from which the tape 20 is removed is provided with a resin layer 50 .
- the resin layer 50 may be formed in a single layer or a multilayer.
- a photosensitive insulating material or a resin insulating layer may be used as a material of the resin layer 50 .
- thermo-setting resin such as an epoxy resin, a thermo-plastic resin such as a polyimide resin, a resin having a reinforcement material such as a glass fiber or an inorganic filler impregnated in the thermo-setting resin and the thermo-plastic resin, for example, a prepreg
- a thermo-setting resin, a photo-curable resin, and the like may be used.
- the material of the resin insulating layer is not particularly limited thereto.
- the formed resin layer 50 is formed with a via hole 60 so as to expose the connection pad of the semiconductor chip 30 and then is provided with the wiring 61 to be connected to the outside.
- the wiring 61 is formed by forming the via hole 60 in the resin layer 50 and then plating and filling the via hole 60 .
- the method for forming a via hole 60 may be formed by being exposed and developed and may be formed by laser machining.
- the laser machining preferably uses a CO2 laser, but in the preferred embodiment of the present invention, a kind of laser is not particularly limited.
- the wiring 61 may be formed by plating and filling an inner wall of the via hole 60 with an insulating material by electroless plating and electroplating which are a general plating method.
- solder ball which is the external connection terminal part is formed on the wiring 61 .
- solder ball 70 Since the solder ball 70 is fixed by reflow but the contact reliability of solder tends to be reduced, some of the solder balls are buried in the insulating layer to strengthen a fixing force of the solder balls 70 and the rest thereof is exposed to the outside, thereby improving the reliability.
- the semiconductor package is singulated as the individual semiconductor package 100 by the sawing process.
- the semiconductor package 100 is formed by cutting the individual semiconductor chips 30 attached with the solder balls 70 by the connection with the wirings 61 based on the frame 10 .
- a dummy part between the frame 10 and the individual semiconductor package 100 is removed.
- the mark formed on the frame 10 and the material of the frame 10 are easy for the cutting.
- the frame 10 when the frame 10 is made of the epoxy molding compound (EMC), the frame 10 may be used without causing any problem in reliability even in the case in which the frame 10 is included in the unit semiconductor package 100 .
- EMC epoxy molding compound
- the individually formed semiconductor package 100 may also be made of a part of the frame 10 and the molding part 40 depending on the separation method and may be made of only the molding part 40 .
- the method for manufacturing a semiconductor package 100 it is possible to minimize the defect of products which may occur due to the handling problem at the time of performing the process by using the frame 10 serving as the supporter.
- the frame 10 is made of the material similar to that of the molding part 40 , the reliability of products is not affected even when the cut portion is not accurately removed at the time of performing the sawing process, such that the defects may be minimized and the manufacturing costs may be reduced.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Dicing (AREA)
Abstract
Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.
Description
- This application is a Continuation of U.S. patent application Ser. No. 14/527,733, filed Oct. 29, 2014, which claims the benefit of Korean Patent Application No. 10-2013-0143761, filed on Nov. 25, 2013, entitled “Method For Manufacturing Semiconductor Package”, which is hereby incorporated by reference in its entirety into this application.
- 1. Technical Field
- The present invention relates to a method for manufacturing a semiconductor package.
- 2. Description of the Related Art
- To cope with the increase in demand for light, small, high-speed, multi-functional, and high-performance electronic products, a technology of packaging a semiconductor chip has been developed.
- Generally, a semiconductor package is manufactured by first cutting a wafer along a scribe line to be separated into individual semiconductor chips and packaging the individual semiconductor chips.
- Recently, a method for manufacturing the package by performing a packaging process in the wafer state without first cutting the wafer and then finally cutting the wafer along the scribe line has been proposed.
- A wafer level package (WLP) or a semiconductor chip scale package (CSP) has been developed to provide another solution for a directly attached flip chip device.
- A wafer level package (WLP) technology is a technology of implementing miniaturization, weight reduction, high performance, and the like.
- An embedded type of wafer level package enables a manufacturing of the wafer level package having a fan-out form in which an external connection terminal may be disposed in a package larger than a size of the semiconductor chip.
- (Patent Document 1) International Patent Laid-Open Publication No. WO 2009-035858
- The present invention has been made in an effort to provide a method for improving pattern alignment and EMC molding flatness based on an epoxy molding compound (EMC) molding technology which enables a fan out wafer level package (fan out WLP) to have a substrate size to thereby mass-produce the fan out WLP.
- Further, the present invention has been made in an effort to provide a method for encapsulating a plurality of semiconductor devices already separated and then separating the semiconductor devices into individual chips in a final process.
- According to a preferred embodiment of the present invention, there is provided a method for manufacturing a semiconductor package, including: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.
- The method for manufacturing a semiconductor package may further include: prior to the peeling of the tape, curing the molding part.
- The resin layer may be formed in a single layer or a multilayer.
- The frame may be an epoxy molding compound (EMC).
- In the attaching of the plurality of semiconductor chips and the frame on one surface of a tape, the semiconductor chips may be spaced from each other and thus may be attached within the quadrangular holes of the frame in a face-down type.
- A cross section height of the frame may be larger than a thickness of the semiconductor chip.
- The molding part may be an epoxy molding compound (EMC).
- The method for manufacturing a semiconductor package may further include: after the forming of the molding part, curing the molding part to fix the semiconductor chip.
- The frame and the molding part may have different colors.
- The forming of the wiring may include: forming a via hole in the resin layer; and forming the wiring by plating and filling the via hole.
- The method for manufacturing a semiconductor package may further include: after the forming of the wiring, forming a solder ball, which is an external connection terminal part, on the wiring.
- The method for manufacturing a semiconductor package may further include: after the forming of the wiring, singulating the semiconductor package as individual semiconductor packages by a sawing process, wherein in the singulating of the semiconductor package, a dummy part between the frame and the individual semiconductor package is removed.
- The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
-
FIGS. 1 to 8 are process diagrams sequentially illustrating a method for manufacturing a semiconductor package according to a preferred embodiment of the present invention, in which -
FIG. 1 is a front view andFIGS. 2 to 8 are cross-sectional views. - The objects, features and advantages of the present invention will be more clearly understood from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant descriptions thereof are omitted. Further, in the following description, the terms “first”, “second”, “one side”, “the other side” and the like are used to differentiate a certain component from other components, but the configuration of such components should not be construed to be limited by the terms. Further, in the description of the present invention, when it is determined that the detailed description of the related art would obscure the gist of the present invention, the description thereof will be omitted.
- Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.
- Method For Manufacturing Semiconductor Package
-
FIGS. 1 to 8 are process diagrams sequentially illustrating a method for manufacturing asemiconductor package 100 according to a preferred embodiment of the present invention, in whichFIG. 1 is a front view andFIGS. 2 to 8 are cross-sectional views. - Referring first to
FIG. 1 ,FIG. 1 is a front view of a frame of the semiconductor package according to a preferred embodiment of the present invention. - A
quadrangular frame 10 having a plurality of quadrangular holes is prepared. - In this case, the
frame 10 may be manufactured at various sizes so as to easily mass-produced and may be used. - Further, the plurality of quadrangular holes may be manufactured at a proper size, and thus may be inserted with
semiconductor chips 30 to be described below and a size of the quadrangular holes may also be changed depending on a size of thesemiconductor chip 30. - In addition, the
frame 10 according to the preferred embodiment of the present invention may be represented by a color different from amolding part 40 to easily be differentiated from themolding part 40 to be described below. - Herein, a material of the
frame 10 may be an epoxy molding compound (EMC). However, according to the preferred embodiment of the present invention, the material of the frame is not limited thereto, and therefore any material to facilitate cutting in a sawing process may be used. - As described above, according to the method for manufacturing a wafer level semiconductor package, the cutting of the wafer level semiconductor package may be facilitated by using the above material when the semiconductor substrate is manufactured at a larger area like the general substrate, not at the existing wafer level size and then is finally singulated.
- Further, when as the material of the
frame 10, metal, ceramics, and a composite material thereof having high strength and excellent durability are used, characteristics of theframe 10 supporting thesemiconductor chip 30 may be improved. - In addition, when a mark is formed in the
frame 10 to improve the alignment of thesemiconductor package 100, thesemiconductor package 100 may suffer from segmentation correction and manufacturing completeness thereof may be increased. - Next, referring to
FIGS. 2 and 3 , the plurality ofsemiconductor chips 30 and theframe 20 are attached on one surface of atape 20. - The
frame 10 and thesemiconductor chips 30 are bonded on the one surface of thetape 20 by preparing the film-shaped tape 20 having a predetermined level of adhesion. - In this case, a cross section height of the
frame 10 may be higher than that of thesemiconductor chip 30. - Further, a thickness of the cross section of the
frame 10 may be controlled as the designer demand. - In this case, the
frame 10 formed with the mark is first bonded and then thesemiconductor chip 30 is bonded, such that theframe 10 may be accurately bonded at positions at which theindividual semiconductor chips 30 are bonded. - Herein, a connection pad of the
semiconductor chip 30 is bonded with thetape 20 by a face-down type. - This is a manufacturing method to facilitate the manufacturing of the wafer level semiconductor package in a fan-out form, in which the connection pad of the
semiconductor chip 30 bonded with thetape 20 is connected to asolder ball 70, which is an external connection terminal part, by awiring 61 to be described below. - The above drawings do not illustrate in detail components of the
semiconductor chip 30 and therefore schematically illustrate the components, but a person having ordinary skill in the art to which the present invention pertains may sufficiently recognize that thesemiconductor chip 30 having all the known structures may be applied to the present invention without being particularly limited. - Next, referring to
FIG. 4 , themolding part 40 is formed on thetape 20 to cover thesemiconductor chip 30 and theframe 10. - The
molding part 40 is formed to be filled on thetape 20, and themolding part 40 is formed and then cured such that thesemiconductor chip 30 may be well fixed. - Further, thermal insulation of the
semiconductor chip 30 is effectively performed by forming themolding part 40. - In this case, as the material of the
molding part 40, a silicon gel, an epoxy molding compound (EMC), and the like, may be used, but the preferred embodiment of the present invention is not limited thereto. - Next, retelling to
FIGS. 5 and 7 , thetape 20 is peeled and then a portion from which thetape 20 is removed is provided with aresin layer 50. - In this case, the
resin layer 50 may be formed in a single layer or a multilayer. - Herein, as a material of the
resin layer 50, a photosensitive insulating material or a resin insulating layer may be used. - As a material of the resin insulating layer, a thermo-setting resin such as an epoxy resin, a thermo-plastic resin such as a polyimide resin, a resin having a reinforcement material such as a glass fiber or an inorganic filler impregnated in the thermo-setting resin and the thermo-plastic resin, for example, a prepreg may be used. In addition, a thermo-setting resin, a photo-curable resin, and the like, may be used. However, the material of the resin insulating layer is not particularly limited thereto.
- Further, the formed
resin layer 50 is formed with a viahole 60 so as to expose the connection pad of thesemiconductor chip 30 and then is provided with thewiring 61 to be connected to the outside. - In this case, the
wiring 61 is formed by forming the viahole 60 in theresin layer 50 and then plating and filling the viahole 60. - Herein, the method for forming a via
hole 60 may be formed by being exposed and developed and may be formed by laser machining. - In this case, the laser machining preferably uses a CO2 laser, but in the preferred embodiment of the present invention, a kind of laser is not particularly limited.
- Herein, the
wiring 61 may be formed by plating and filling an inner wall of the viahole 60 with an insulating material by electroless plating and electroplating which are a general plating method. - Next, the solder ball which is the external connection terminal part is formed on the
wiring 61. - Since the
solder ball 70 is fixed by reflow but the contact reliability of solder tends to be reduced, some of the solder balls are buried in the insulating layer to strengthen a fixing force of thesolder balls 70 and the rest thereof is exposed to the outside, thereby improving the reliability. - Finally, referring to
FIG. 8 , the semiconductor package is singulated as theindividual semiconductor package 100 by the sawing process. - The
semiconductor package 100 is formed by cutting theindividual semiconductor chips 30 attached with thesolder balls 70 by the connection with thewirings 61 based on theframe 10. - Herein, a dummy part between the
frame 10 and theindividual semiconductor package 100 is removed. In this case, the mark formed on theframe 10 and the material of theframe 10 are easy for the cutting. - Further, when the
frame 10 is made of the epoxy molding compound (EMC), theframe 10 may be used without causing any problem in reliability even in the case in which theframe 10 is included in theunit semiconductor package 100. - Therefore, the individually formed
semiconductor package 100 may also be made of a part of theframe 10 and themolding part 40 depending on the separation method and may be made of only themolding part 40. - According to the method for manufacturing a
semiconductor package 100 according to the preferred embodiments of the present invention, it is possible to minimize the defect of products which may occur due to the handling problem at the time of performing the process by using theframe 10 serving as the supporter. - Further, according to the preferred embodiments of the present invention, it is possible to make the alignment between the semiconductor chips 30 excellent at the time of manufacturing the semiconductor package using the
frame 10 formed with the mark used in the method for manufacturing asemiconductor package 100. - In addition, it is possible to efficiently mass-produce the semiconductor package by molding a large number of
semiconductor chips 30 to have a larger area than that of the existing wafer level semiconductor package. - Moreover, since the
frame 10 is made of the material similar to that of themolding part 40, the reliability of products is not affected even when the cut portion is not accurately removed at the time of performing the sawing process, such that the defects may be minimized and the manufacturing costs may be reduced. - Although the embodiments of the present invention have been disclosed for illustrative purposes, it will be appreciated that the present invention is not limited thereto, and those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention.
- Accordingly, any and all modifications, variations or equivalent arrangements should be considered to be within the scope of the invention, and the detailed scope of the invention will be disclosed by the accompanying claims.
Claims (14)
1. A method for manufacturing a package, comprising:
preparing a frame having holes;
disposing an element in a hole of the frame;
forming a molding part to cover the element;
forming a redistribution layer (RDL) on one side of the frame and the element.
2-5. (canceled)
6. The method of claim 1 , wherein a thickness of the frame is greater than a thickness of the element.
7. The method of claim 1 , wherein the molding part is an epoxy molding compound (EMC).
8. (canceled)
9. The method of claim 1 , wherein the frame and the molding part have different colors.
10. The method claim 1 , wherein the forming of the RDL comprises:
forming an insulating layer;
forming a via hole in the insulating layer; and
forming the wiring by plating and filling the via hole.
11. The method of claim 10 , further comprising:
after the forming of the wiring, forming a connecting terminal, which is an external connection terminal part, on the wiring.
12. (canceled)
13. The method of claim 1 , wherein the disposing the element in the hole of the frame comprises:
attaching a portion of adhesive tape to one surface of the frame; and
attaching the element to a portion of the adhesive tape exposed by the hole of the frame.
14. The method of claim 13 , further comprising:
after the forming of the molding part, peeling the tape.
15. A method for manufacturing a package, comprising:
preparing a frame having a plurality of holes;
disposing a plurality of elements in the holes of the frame, respectively;
forming a molding part to cover the elements;
forming a redistribution layer (RDL) on one side of the frame and the elements; and
singulating the package as a plurality of individual unit packages.
16. The method of claim 15 , wherein after the singulating of the package, at least a portion of the frame remains on side surfaces of the individual unit packages.
17. The method of claim 15 , wherein after the singulating of the package, the frame is removed in the individual unit packages.
Priority Applications (1)
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US14/848,726 US20150380276A1 (en) | 2013-11-25 | 2015-09-09 | Method for manufacturing semiconductor package |
Applications Claiming Priority (4)
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KR1020130143761A KR101681360B1 (en) | 2013-11-25 | 2013-11-25 | Method for Manufacturing Electronic Component Package |
KR10-2013-0143761 | 2013-11-25 | ||
US14/527,733 US9171780B2 (en) | 2013-11-25 | 2014-10-29 | Method for manufacturing semiconductor package |
US14/848,726 US20150380276A1 (en) | 2013-11-25 | 2015-09-09 | Method for manufacturing semiconductor package |
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US14/527,733 Continuation US9171780B2 (en) | 2013-11-25 | 2014-10-29 | Method for manufacturing semiconductor package |
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US14/848,726 Abandoned US20150380276A1 (en) | 2013-11-25 | 2015-09-09 | Method for manufacturing semiconductor package |
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Cited By (3)
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CN108831863A (en) * | 2018-05-31 | 2018-11-16 | 华进半导体封装先导技术研发中心有限公司 | Chip packaging method |
US10153222B2 (en) | 2016-11-14 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US11527454B2 (en) | 2016-11-14 | 2022-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
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KR101973427B1 (en) | 2015-11-18 | 2019-04-29 | 삼성전기주식회사 | Electronic component package and electronic device comprising the same |
KR102513427B1 (en) * | 2016-04-26 | 2023-03-24 | 삼성전자주식회사 | fan-out panel level package and fabrication method of the same |
US11081371B2 (en) * | 2016-08-29 | 2021-08-03 | Via Alliance Semiconductor Co., Ltd. | Chip package process |
US11227848B2 (en) * | 2016-08-29 | 2022-01-18 | Via Alliance Semiconductor Co., Ltd. | Chip package array, and chip package |
KR102200744B1 (en) * | 2017-06-14 | 2021-01-11 | 주식회사 케이씨텍 | Substrate treating apparatus and substrate carrier using the same |
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Also Published As
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US9171780B2 (en) | 2015-10-27 |
KR101681360B1 (en) | 2016-11-30 |
KR20150059963A (en) | 2015-06-03 |
US20150147849A1 (en) | 2015-05-28 |
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