US20150348913A1 - Planar metrology pad adjacent a set of fins in a fin field effect transistor device - Google Patents

Planar metrology pad adjacent a set of fins in a fin field effect transistor device Download PDF

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US20150348913A1
US20150348913A1 US14/818,039 US201514818039A US2015348913A1 US 20150348913 A1 US20150348913 A1 US 20150348913A1 US 201514818039 A US201514818039 A US 201514818039A US 2015348913 A1 US2015348913 A1 US 2015348913A1
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fins
substrate
pad
mandrel
hardmask
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US14/818,039
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Xiang Hu
Lokesh Subramany
Alok Vaid
Sipeng Gu
Akshey Sehgal
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GlobalFoundries Inc
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GlobalFoundries Inc
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Priority to US14/818,039 priority Critical patent/US20150348913A1/en
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SUBRAMANY, LOKESH, VAID, ALOK, GU, SIPENG, HU, XIANG, SEHGAL, AKSHEY
Publication of US20150348913A1 publication Critical patent/US20150348913A1/en
Assigned to GLOBALFOUNDRIES U.S. INC. reassignment GLOBALFOUNDRIES U.S. INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates generally to the field of semiconductors, and more particularly, to providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device.
  • FinFET fin field effect transistor
  • a typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin field effect transistors (FinFETs)) and connect the devices into circuits.
  • FinFETs fin field effect transistors
  • CMOS complementary insulated gate FinFET process
  • layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer.
  • SOI silicon on insulator
  • a simple FinFET includes a gate layer rectangle on a silicon island formed from the silicon surface layer.
  • Each of these layers of shapes may be created or printed optically through well-known photolithographic masking, developing and level definition (e.g., etching, implanting, deposition, etc.).
  • fins of the FinFET are created by a process that is similar to self-aligned double patterning. The process involves patterning of a spacer and deposition of liners on top of one or more hardmasks. The spacer is then etched away, followed by the hardmask, leaving behind fins. However, it currently is not possible to obtain a FIN-free region due to the nature of the hardmask etch process.
  • Optical metrology is commonly employed in process control applications in the semiconductor manufacturing industry due to optical metrology's non-contact and non-destructive nature.
  • FinFETs raise new metrology complexities, as the entire 3D structure becomes critical for process control, including fin and gate dimensions, profiles and roughness, and metal gate undercuts. Due to the finification process of FinFET devices, metrology models must now take into account the fins underlying the planar metrology pad, which provides additional challenges, and may lead to insufficient results.
  • a previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist.
  • a pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon.
  • This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
  • One aspect of the present invention includes a method for forming a device, the method comprising: removing an amorphous carbon layer from over a mandrel formed on a subset of a substrate; forming a pad hardmask over the mandrel on the subset of the substrate, wherein the forming results in the pad hardmask covering the mandrel on the subset of the substrate and the amorphous carbon layer covering the mandrel on a remainder of the substrate; removing the amorphous carbon layer from over the mandrel on the remainder of the substrate; and forming a set of fins in the remainder of the substrate, wherein the amorphous carbon layer keeps the set of fins from being formed in the subset of the substrate.
  • Another aspect of the present invention includes a method for forming a planar metrology pad on a substrate of a fin field effect transistor (FinFET) device, the method comprising: removing an amorphous carbon layer from over a mandrel formed on a subset of a substrate; forming a pad hardmask over the mandrel on the subset of the substrate, wherein the forming results in the pad hardmask covering the mandrel on the subset of the substrate and the amorphous carbon layer covering the mandrel on a remainder of the substrate; removing the amorphous carbon layer from over the mandrel on the remainder of the substrate; and forming a set of fins in the remainder of the substrate, wherein the amorphous carbon layer keeps the set of fins from being formed in the subset of the substrate.
  • FinFET fin field effect transistor
  • Yet another aspect of the present invention includes a fin field effect transistor (FinFET) device, comprising: a set of fins patterned in a substrate of the FinFET device; and a planar metrology pad formed adjacent to the set of fins in a metrology measurement area of the FinFET device, wherein the planar metrology pad is substantially flat and oriented substantially perpendicular to the set of fins.
  • FinFET fin field effect transistor
  • FIG. 1 shows a cross-sectional view of the formation of a hardmask over a substrate of a FinFET device according to illustrative embodiments
  • FIG. 2 shows a cross-sectional view of the formation of a mandrel layer over the device according to illustrative embodiments
  • FIG. 3 shows a cross-sectional view of the patterning of a set of openings in the mandrel layer according to illustrative embodiments
  • FIG. 4 shows a cross-sectional view of the formation of a set of spacers according to illustrative embodiments
  • FIG. 5 shows a cross-sectional view of the formation of an amorphous carbon layer over the device according to illustrative embodiments
  • FIG. 6 shows a cross-sectional view of the formation of a photoresist layer over a portion of the device according to illustrative embodiments
  • FIG. 7 shows a cross-sectional view of the partial removal of the amorphous carbon layer according to illustrative embodiments
  • FIG. 8 shows a cross-sectional view of the removal of the photoresist layer according to illustrative embodiments
  • FIG. 9 shows a cross-sectional view of the formation of a pad hardmask according to illustrative embodiments.
  • FIG. 10 shows a cross-sectional view of the partial removal of the pad hardmask according to illustrative embodiments
  • FIG. 11 shows a cross-sectional view of the removal of the remainder of the amorphous carbon layer according to illustrative embodiments
  • FIG. 12 shows a cross-sectional view of the device following partial removal of the mandrel layer from between the set of spacers according to illustrative embodiments
  • FIG. 13 shows a cross-sectional view of a set of fins patterned in the substrate according to illustrative embodiments.
  • FIG. 14 shows a cross-sectional view of the device following deposition of an oxide and planarization according to illustrative embodiments.
  • This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
  • first element such as a first structure, e.g., a first layer
  • second element such as a second structure, e.g. a second layer
  • intervening elements such as an interface structure, e.g. interface layer
  • depositing may include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-improved CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation, etc.
  • CVD chemical vapor deposition
  • LPCVD low-pressure CVD
  • PECVD plasma-improved CVD
  • SACVD semi-
  • FIG. 1 shows a cross-sectional view of a device 100 according to an embodiment of the invention.
  • Device 100 e.g., a FinFET device
  • Device 100 comprises a substrate 102 and a hardmask 104 formed over substrate 102 .
  • substrate as used herein is intended to include a semiconductor substrate, a semiconductor epitaxial layer deposited or otherwise formed on a semiconductor substrate and/or any other type of semiconductor body, and all such structures are contemplated as falling within the scope of the present invention.
  • the semiconductor substrate may comprise a semiconductor wafer (e.g., silicon, SiGe, or an SOI wafer) or one or more die on a wafer, and any epitaxial layers or other type semiconductor layers formed thereover or associated therewith.
  • a portion or entire semiconductor substrate may be amorphous, polycrystalline, or single-crystalline.
  • the semiconductor substrate employed in the present invention may also comprise a hybrid oriented (HOT) semiconductor substrate in which the HOT substrate has surface regions of different crystallographic orientation.
  • the semiconductor substrate may be doped, undoped, or contain doped regions and undoped regions therein.
  • the semiconductor substrate may contain regions with strain and regions without strain therein, or contain regions of tensile strain and compressive strain.
  • hardmask 104 may comprise either silicon nitride (SiN) or silicon dioxide (SiO2), or any other material(s) suitable as a hardmask, including silicon oxynitride (SiON), siliocon oxycarbide (SiOC), and the like.
  • Hardmask 104 can be prepared by PVD, CVD, spin coating, etc., depending on the material. It will be appreciated that hardmask 104 may include an alignment mark (not shown) due to its high optical contrast (e.g., 14%-35%).
  • mandrel layer 114 is formed over device 100 .
  • mandrel layer 114 may comprise an inorganic and/or dielectric material such as amorphous silicon, polycrystalline silicon, or silicon oxide (SiO x ) where x is a number greater than zero, silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or the like.
  • Mandrel layer 114 may be deposited using physical vapor deposition (PVD), CVD, plasma-improved chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HD CVD), atomic layer CVD (ALCVD), and/or other suitable processes.
  • PVD physical vapor deposition
  • CVD plasma-improved chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • LPCVD low-pressure CVD
  • HD CVD high density plasma CVD
  • ACVD atomic layer CVD
  • mandrel layer 114 is patterned to form a set of openings 116 therein, e.g., using a photo-lithography process or other lithographic process (e.g., electron beam lithography, imprint lithography, EUV lithography, etc.), and removed by a suitable etching process including a wet etch, dry etch, plasma etch, and the like.
  • a photo-lithography process or other lithographic process e.g., electron beam lithography, imprint lithography, EUV lithography, etc.
  • a suitable etching process including a wet etch, dry etch, plasma etch, and the like.
  • a set of spacers 120 is then formed within each opening 116 along sidewalls of the patterned mandrel layer 114 .
  • spacers 120 provide a protective dielectric layer on the sidewalls of mandrel layer 114 .
  • the material of each spacer 120 is selected to provide a material that will not be substantially etched by the etchant that subsequently removes mandrel layer 114 .
  • set of spacers 120 comprises an oxide, and is formed using a sidewall image transfer (SIT) atomic layer deposition (ALD), and etch processes.
  • SIT sidewall image transfer
  • ALD atomic layer deposition
  • amorphous carbon layer 118 is formed over device 100 .
  • amorphous carbon layer 118 may comprise a dielectric material such as silicon carbonate, or the like.
  • Amorphous carbon layer 118 may be deposited using physical vapor deposition (PVD), CVD, plasma-improved chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HD CVD), atomic layer CVD (ALCVD), and/or other suitable processes.
  • PVD physical vapor deposition
  • PECVD plasma-improved chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • LPCVD low-pressure CVD
  • HD CVD high density plasma CVD
  • ACVD atomic layer CVD
  • a photoresist (PR) 122 is applied to a portion of the surface of amorphous carbon layer 118 of device 100 .
  • a region (subset) of device 100 can be designated as a metrology measurement area 108 .
  • the metrology measurement area 108 can be any subset of the substrate 102 that has been designated as not having a finned structure of a remainder region 106 .
  • metrology measurement area 108 can be formed anywhere on device 100 , including an edge region or an interior region.
  • PR 122 can be patterned in such a manner as to create a plurality of contiguous and/or non-contiguous metrology measurement areas 108 on the same device.
  • PR 122 can be applied to a subset of the surface of amorphous carbon layer 118 in remainder area 108 of device 100 , exposed to a pattern of radiation, and then the pattern can be developed into PR 122 utilizing a resist developer. Once the patterning of PR 122 is completed, the sections covered by the photoresist are protected.
  • the exposed regions of amorphous carbon layer 118 are removed using a selective etching process that removes the unprotected regions, leaving exposed the subset of the mandrel region 114 and set of spacers 120 in the metrology measurement area 108 .
  • the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied.
  • PR 122 may be removed using an O 2 ash process, or it may be stripped using a wet chemical process, as illustrated in FIG. 8 .
  • pad hardmask 124 is formed over device 100 .
  • pad hardmask 124 can include a nitride, an oxide, SiON, SiOC (C-doped silicon oxide), and/or any other material which has an etch resistance that is similar to that of set of spacers 120 .
  • the remaining amorphous carbon layer 118 in the remainder area 106 e.g., the subset of device 100 not in metrology area 108 ) has caused a difference in relative height between metrology measurement area 108 and remainder area 106 .
  • This difference in relative height allows the pad hardmask 124 to flow from the remainder area 106 into metrology measurement area 108 and fill the openings 116 in the mandrel layer 114 and set of spacers 120 .
  • a depth 126 a of the pad hardmask 124 in the remainder area 106 is less than a depth 126 b of the pad hardmask 124 in the metrology measurement area 108 .
  • pad hardmask 124 may be deposited using physical vapor deposition (PVD), CVD, plasma-improved chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HD CVD), atomic layer CVD (ALCVD), and/or other suitable processes.
  • PVD physical vapor deposition
  • CVD plasma-improved chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • LPCVD low-pressure CVD
  • HD CVD high density plasma CVD
  • ACVD atomic layer CVD
  • pad hardmask 124 can be removed from over amorphous carbon layer 118 in remainder area 106 of device 100 . This process can be performed using a blanket etch and/or any other suitable process. Because the depth 126 a ( FIG. 9 ) of the pad hardmask 124 is less in the remainder area 106 than the depth 126 b ( FIG. 9 ) in the metrology measurement area 108 , the pad hardmask 124 can be removed from the remainder area 106 while leaving a remainder of the pad hardmask 124 in the metrology measurement area 108 .
  • the metrology measurement area 108 and the remainder area 106 each have a different substance covering the mandrel layer 116 and set of spacers 120 , with the pad hardmask covering the mandrel layer 116 and set of spacers 120 in the metrology measurement area 108 and the amorphous carbon layer 118 covering the mandrel layer 116 and set of spacers 120 in the remainder area 106 .
  • amorphous carbon layer 118 is removed from over the mandrel layer 114 and set of spacers 120 in the remainder area 106 of device 100 .
  • This removal can be performed using a strip that is selective to the pad hardmask 124 , removing the amorphous carbon layer 118 in the remainder area 106 while leaving the pad hardmask 124 intact in the metrology measurement area 108 while leaving the mandrel layer 114 and set of spacers 120 exposed in the remainder area 106 of device 100 .
  • mandrel layer 114 is removed from between the set of spacers 120 in pad area 104 the selective to hardmask 104 .
  • a fin etch process is performed and openings 116 are extended into substrate 102 to form set of fins 128 .
  • the fin etch process does not impact the silicon of substrate 102 in the metrology measurement area 108 due to the presence of pad hardmask 124 .
  • Substrate 102 is preserved, thus allowing for the subsequent formation of a planar metrology pad 132 ( FIG. 14 ).
  • oxide 130 is deposited over device 100 , filling openings 116 .
  • Oxide 130 may be formed using a high aspect ratio process such as PVD, CVD, PECVD, APCVD, LPCVD, HD CVD, ALCVD, and/or other suitable processes.
  • oxide 130 is deposited atop all of device 100 , and then removed (e.g., via chemical mechanical planarization (CMP)).
  • CMP chemical mechanical planarization
  • the planarization process also removes mandrel layer 114 , set of spacers 120 , pad hardmask 124 , and hardmask 104 ( FIG. 13 ) from metrology measurement area 108 to form planar metrology pad 132 , which is suitable for metrology measurements and data extraction.
  • planar metrology pad 132 comprises a flat, horizontal surface which can be oriented substantially perpendicular to set of fins 128 .
  • planar metrology pad 132 provides a fin-free region to ensure that metrology techniques (e.g., ellipsometry, X-ray diffraction, X-ray reflectance, X-ray fluorescence, etc.) that rely on the existence of a uniform planar metrology pad can still be used, as there are no underlying fins 128 to be considered.
  • metrology techniques e.g., ellipsometry, X-ray diffraction, X-ray reflectance, X-ray fluorescence, etc.
  • gate electrode and gate dielectric layers are then patterned to form gate stacks over fins 128 .
  • the fin portions not under the gate stacks are then optionally doped to form doped drain and source regions.
  • the dopant used depends on the conductivity type of the transistor.
  • the doped regions may be doped by ion-implanting or by plasma doping where dopants are deposited onto the fin and annealed.
  • Source and drain regions are formed across the gate stack. Source and drain regions may be formed by ion-implanting a source/drain region or by removing a portion of the fin and epitaxially re-growing the removed portion under doping conditions to form a source/drain region.
  • design tools can be provided and configured to create the datasets used to pattern the semiconductor layers as described herein.
  • design tools can be used for: forming a first hardmask over a substrate; forming a photoresist over a portion of the first hardmask in a metrology measurement area of the device; removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist; forming a second hardmask over the device; forming a mandrel layer over the second hardmask; forming a set of openings in the mandrel layer; forming a set of spacers within the set of openings; removing the mandrel layer selective to the second hardmask; removing the second hardmask; patterning a set of openings in the substrate to form a set of fins in the device in the area adjacent the metrology measurement area; depositing an oxide over the device; and planarizing the device to form a planar metrology pad in the metrology measurement area.
  • a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof.
  • a tool can be a computing device or other appliance on which software runs or in which hardware is implemented.
  • a module might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, logical components, software routines or other mechanisms might be implemented to make up a module.
  • the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules.
  • the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Even though various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality can be shared among one or more common software and hardware elements, and such description shall not require or imply that separate hardware or software components are used to implement such features or functionality.

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Abstract

Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.

Description

    BACKGROUND
  • 1. Technical Field
  • This invention relates generally to the field of semiconductors, and more particularly, to providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device.
  • 2. Related Art
  • A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin field effect transistors (FinFETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FinFET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FinFET includes a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well-known photolithographic masking, developing and level definition (e.g., etching, implanting, deposition, etc.). In some approaches, fins of the FinFET are created by a process that is similar to self-aligned double patterning. The process involves patterning of a spacer and deposition of liners on top of one or more hardmasks. The spacer is then etched away, followed by the hardmask, leaving behind fins. However, it currently is not possible to obtain a FIN-free region due to the nature of the hardmask etch process.
  • Optical metrology is commonly employed in process control applications in the semiconductor manufacturing industry due to optical metrology's non-contact and non-destructive nature. FinFETs raise new metrology complexities, as the entire 3D structure becomes critical for process control, including fin and gate dimensions, profiles and roughness, and metal gate undercuts. Due to the finification process of FinFET devices, metrology models must now take into account the fins underlying the planar metrology pad, which provides additional challenges, and may lead to insufficient results.
    • SUMMARY
  • In general, approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
  • One aspect of the present invention includes a method for forming a device, the method comprising: removing an amorphous carbon layer from over a mandrel formed on a subset of a substrate; forming a pad hardmask over the mandrel on the subset of the substrate, wherein the forming results in the pad hardmask covering the mandrel on the subset of the substrate and the amorphous carbon layer covering the mandrel on a remainder of the substrate; removing the amorphous carbon layer from over the mandrel on the remainder of the substrate; and forming a set of fins in the remainder of the substrate, wherein the amorphous carbon layer keeps the set of fins from being formed in the subset of the substrate.
  • Another aspect of the present invention includes a method for forming a planar metrology pad on a substrate of a fin field effect transistor (FinFET) device, the method comprising: removing an amorphous carbon layer from over a mandrel formed on a subset of a substrate; forming a pad hardmask over the mandrel on the subset of the substrate, wherein the forming results in the pad hardmask covering the mandrel on the subset of the substrate and the amorphous carbon layer covering the mandrel on a remainder of the substrate; removing the amorphous carbon layer from over the mandrel on the remainder of the substrate; and forming a set of fins in the remainder of the substrate, wherein the amorphous carbon layer keeps the set of fins from being formed in the subset of the substrate.
  • Yet another aspect of the present invention includes a fin field effect transistor (FinFET) device, comprising: a set of fins patterned in a substrate of the FinFET device; and a planar metrology pad formed adjacent to the set of fins in a metrology measurement area of the FinFET device, wherein the planar metrology pad is substantially flat and oriented substantially perpendicular to the set of fins.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:
  • FIG. 1 shows a cross-sectional view of the formation of a hardmask over a substrate of a FinFET device according to illustrative embodiments;
  • FIG. 2 shows a cross-sectional view of the formation of a mandrel layer over the device according to illustrative embodiments;
  • FIG. 3 shows a cross-sectional view of the patterning of a set of openings in the mandrel layer according to illustrative embodiments;
  • FIG. 4 shows a cross-sectional view of the formation of a set of spacers according to illustrative embodiments;
  • FIG. 5 shows a cross-sectional view of the formation of an amorphous carbon layer over the device according to illustrative embodiments;
  • FIG. 6 shows a cross-sectional view of the formation of a photoresist layer over a portion of the device according to illustrative embodiments;
  • FIG. 7 shows a cross-sectional view of the partial removal of the amorphous carbon layer according to illustrative embodiments;
  • FIG. 8 shows a cross-sectional view of the removal of the photoresist layer according to illustrative embodiments;
  • FIG. 9 shows a cross-sectional view of the formation of a pad hardmask according to illustrative embodiments;
  • FIG. 10 shows a cross-sectional view of the partial removal of the pad hardmask according to illustrative embodiments;
  • FIG. 11 shows a cross-sectional view of the removal of the remainder of the amorphous carbon layer according to illustrative embodiments;
  • FIG. 12 shows a cross-sectional view of the device following partial removal of the mandrel layer from between the set of spacers according to illustrative embodiments;
  • FIG. 13 shows a cross-sectional view of a set of fins patterned in the substrate according to illustrative embodiments; and
  • FIG. 14 shows a cross-sectional view of the device following deposition of an oxide and planarization according to illustrative embodiments.
  • The drawings are not necessarily to scale. The drawings are merely representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting in scope. In the drawings, like numbering represents like elements.
    •  DETAILED DESCRIPTION
  • Exemplary embodiments will now be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. It will be appreciated that this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art.
  • Described herein are approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
  • The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. For example, as used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
  • Reference throughout this specification to “one embodiment,” “an embodiment,” “embodiments,” “exemplary embodiments,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” “in embodiments” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
  • The terms “overlying” or “atop”, “positioned on” or “positioned atop”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure, e.g., a first layer, is present on a second element, such as a second structure, e.g. a second layer, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element.
  • As used herein, “depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-improved CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation, etc.
  • Referring now to the figures, FIG. 1 shows a cross-sectional view of a device 100 according to an embodiment of the invention. Device 100 (e.g., a FinFET device) comprises a substrate 102 and a hardmask 104 formed over substrate 102. The term “substrate” as used herein is intended to include a semiconductor substrate, a semiconductor epitaxial layer deposited or otherwise formed on a semiconductor substrate and/or any other type of semiconductor body, and all such structures are contemplated as falling within the scope of the present invention. For example, the semiconductor substrate may comprise a semiconductor wafer (e.g., silicon, SiGe, or an SOI wafer) or one or more die on a wafer, and any epitaxial layers or other type semiconductor layers formed thereover or associated therewith. A portion or entire semiconductor substrate may be amorphous, polycrystalline, or single-crystalline. In addition to the aforementioned types of semiconductor substrates, the semiconductor substrate employed in the present invention may also comprise a hybrid oriented (HOT) semiconductor substrate in which the HOT substrate has surface regions of different crystallographic orientation. The semiconductor substrate may be doped, undoped, or contain doped regions and undoped regions therein. The semiconductor substrate may contain regions with strain and regions without strain therein, or contain regions of tensile strain and compressive strain.
  • In one embodiment, hardmask 104 may comprise either silicon nitride (SiN) or silicon dioxide (SiO2), or any other material(s) suitable as a hardmask, including silicon oxynitride (SiON), siliocon oxycarbide (SiOC), and the like. Hardmask 104 can be prepared by PVD, CVD, spin coating, etc., depending on the material. It will be appreciated that hardmask 104 may include an alignment mark (not shown) due to its high optical contrast (e.g., 14%-35%).
  • Next, as shown in FIG. 2, a mandrel layer 114 is formed over device 100. In various embodiments, mandrel layer 114 may comprise an inorganic and/or dielectric material such as amorphous silicon, polycrystalline silicon, or silicon oxide (SiOx) where x is a number greater than zero, silicon nitride (Si3N4), silicon oxynitride (SiON), or the like. Mandrel layer 114 may be deposited using physical vapor deposition (PVD), CVD, plasma-improved chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HD CVD), atomic layer CVD (ALCVD), and/or other suitable processes.
  • Next, as shown in FIG. 3, mandrel layer 114 is patterned to form a set of openings 116 therein, e.g., using a photo-lithography process or other lithographic process (e.g., electron beam lithography, imprint lithography, EUV lithography, etc.), and removed by a suitable etching process including a wet etch, dry etch, plasma etch, and the like.
  • As shown in FIG. 4, a set of spacers 120 is then formed within each opening 116 along sidewalls of the patterned mandrel layer 114. As is known, spacers 120 provide a protective dielectric layer on the sidewalls of mandrel layer 114. In one embodiment, the material of each spacer 120 is selected to provide a material that will not be substantially etched by the etchant that subsequently removes mandrel layer 114. In one embodiment, set of spacers 120 comprises an oxide, and is formed using a sidewall image transfer (SIT) atomic layer deposition (ALD), and etch processes.
  • In current solutions, the formation of the set of spacers is often followed straightway by removal of the mandrel layer 114 from between each set of spacers 120 and subsequent etching to form a set of fins. However, the inventors of the current invention have discovered certain drawbacks to the current solutions. For example, these solutions often result in a finification of the entirety of the substrate. This completely finned substrate can prove to be inadequate if the use of metrology techniques is desired. Such metrology techniques require the presence of a uniform pad surface (e.g., of a Si based substrate). This uniform pad surface can be difficult to create in conjunction with the current completely finned solutions.
  • Referring now to FIG. 5, an amorphous carbon layer 118 is formed over device 100. In various embodiments, amorphous carbon layer 118 may comprise a dielectric material such as silicon carbonate, or the like. Amorphous carbon layer 118 may be deposited using physical vapor deposition (PVD), CVD, plasma-improved chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HD CVD), atomic layer CVD (ALCVD), and/or other suitable processes.
  • Referring now to FIG. 6, a photoresist (PR) 122 is applied to a portion of the surface of amorphous carbon layer 118 of device 100. For example, a region (subset) of device 100 can be designated as a metrology measurement area 108. The metrology measurement area 108 can be any subset of the substrate 102 that has been designated as not having a finned structure of a remainder region 106. To this extent, metrology measurement area 108 can be formed anywhere on device 100, including an edge region or an interior region. Furthermore, PR 122 can be patterned in such a manner as to create a plurality of contiguous and/or non-contiguous metrology measurement areas 108 on the same device. In any case, PR 122 can be applied to a subset of the surface of amorphous carbon layer 118 in remainder area 108 of device 100, exposed to a pattern of radiation, and then the pattern can be developed into PR 122 utilizing a resist developer. Once the patterning of PR 122 is completed, the sections covered by the photoresist are protected.
  • Referring now to FIG. 7, the exposed regions of amorphous carbon layer 118 (e.g., within metrology measurement area 108) are removed using a selective etching process that removes the unprotected regions, leaving exposed the subset of the mandrel region 114 and set of spacers 120 in the metrology measurement area 108. The term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. PR 122 may be removed using an O2 ash process, or it may be stripped using a wet chemical process, as illustrated in FIG. 8.
  • Referring now to FIG. 9, a pad hardmask 124 is formed over device 100. In various embodiments, pad hardmask 124 can include a nitride, an oxide, SiON, SiOC (C-doped silicon oxide), and/or any other material which has an etch resistance that is similar to that of set of spacers 120. As shown, the remaining amorphous carbon layer 118 in the remainder area 106 (e.g., the subset of device 100 not in metrology area 108) has caused a difference in relative height between metrology measurement area 108 and remainder area 106. This difference in relative height allows the pad hardmask 124 to flow from the remainder area 106 into metrology measurement area 108 and fill the openings 116 in the mandrel layer 114 and set of spacers 120. As a result, a depth 126 a of the pad hardmask 124 in the remainder area 106 is less than a depth 126 b of the pad hardmask 124 in the metrology measurement area 108. To this extent, pad hardmask 124 may be deposited using physical vapor deposition (PVD), CVD, plasma-improved chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HD CVD), atomic layer CVD (ALCVD), and/or other suitable processes.
  • Referring now to FIG. 10, pad hardmask 124 can be removed from over amorphous carbon layer 118 in remainder area 106 of device 100. This process can be performed using a blanket etch and/or any other suitable process. Because the depth 126 a (FIG. 9) of the pad hardmask 124 is less in the remainder area 106 than the depth 126 b (FIG. 9) in the metrology measurement area 108, the pad hardmask 124 can be removed from the remainder area 106 while leaving a remainder of the pad hardmask 124 in the metrology measurement area 108. As a result of this process, the metrology measurement area 108 and the remainder area 106 each have a different substance covering the mandrel layer 116 and set of spacers 120, with the pad hardmask covering the mandrel layer 116 and set of spacers 120 in the metrology measurement area 108 and the amorphous carbon layer 118 covering the mandrel layer 116 and set of spacers 120 in the remainder area 106.
  • Referring now to FIG. 11, amorphous carbon layer 118 is removed from over the mandrel layer 114 and set of spacers 120 in the remainder area 106 of device 100. This removal can be performed using a strip that is selective to the pad hardmask 124, removing the amorphous carbon layer 118 in the remainder area 106 while leaving the pad hardmask 124 intact in the metrology measurement area 108 while leaving the mandrel layer 114 and set of spacers 120 exposed in the remainder area 106 of device 100.
  • Next, as shown in FIG. 12, mandrel layer 114 is removed from between the set of spacers 120 in pad area 104 the selective to hardmask 104. Then, as shown in FIG. 13, a fin etch process is performed and openings 116 are extended into substrate 102 to form set of fins 128. Here, the fin etch process does not impact the silicon of substrate 102 in the metrology measurement area 108 due to the presence of pad hardmask 124. Substrate 102 is preserved, thus allowing for the subsequent formation of a planar metrology pad 132 (FIG. 14).
  • Next, as shown in FIG. 14, an oxide 130 is deposited over device 100, filling openings 116. Oxide 130 may be formed using a high aspect ratio process such as PVD, CVD, PECVD, APCVD, LPCVD, HD CVD, ALCVD, and/or other suitable processes. In this embodiment, oxide 130 is deposited atop all of device 100, and then removed (e.g., via chemical mechanical planarization (CMP)). The planarization process also removes mandrel layer 114, set of spacers 120, pad hardmask 124, and hardmask 104 (FIG. 13) from metrology measurement area 108 to form planar metrology pad 132, which is suitable for metrology measurements and data extraction. As shown, planar metrology pad 132 comprises a flat, horizontal surface which can be oriented substantially perpendicular to set of fins 128. With this structure, planar metrology pad 132 provides a fin-free region to ensure that metrology techniques (e.g., ellipsometry, X-ray diffraction, X-ray reflectance, X-ray fluorescence, etc.) that rely on the existence of a uniform planar metrology pad can still be used, as there are no underlying fins 128 to be considered.
  • Although not shown for the sake of brevity, it is appreciated that gate electrode and gate dielectric layers are then patterned to form gate stacks over fins 128. The fin portions not under the gate stacks are then optionally doped to form doped drain and source regions. The dopant used depends on the conductivity type of the transistor. The doped regions may be doped by ion-implanting or by plasma doping where dopants are deposited onto the fin and annealed. Source and drain regions are formed across the gate stack. Source and drain regions may be formed by ion-implanting a source/drain region or by removing a portion of the fin and epitaxially re-growing the removed portion under doping conditions to form a source/drain region.
  • In various embodiments, design tools can be provided and configured to create the datasets used to pattern the semiconductor layers as described herein. For example, design tools can be used for: forming a first hardmask over a substrate; forming a photoresist over a portion of the first hardmask in a metrology measurement area of the device; removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist; forming a second hardmask over the device; forming a mandrel layer over the second hardmask; forming a set of openings in the mandrel layer; forming a set of spacers within the set of openings; removing the mandrel layer selective to the second hardmask; removing the second hardmask; patterning a set of openings in the substrate to form a set of fins in the device in the area adjacent the metrology measurement area; depositing an oxide over the device; and planarizing the device to form a planar metrology pad in the metrology measurement area.
  • To accomplish this, data sets can be created to generate photomasks used during lithography operations to pattern the layers for structures as described herein. Such design tools can include a collection of one or more modules and can also be comprised of hardware, software, or a combination thereof. Thus, for example, a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof. As another example, a tool can be a computing device or other appliance on which software runs or in which hardware is implemented. As used herein, a module might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, logical components, software routines or other mechanisms might be implemented to make up a module. In implementation, the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules. In other words, as would be apparent to one of ordinary skill in the art after reading this description, the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Even though various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality can be shared among one or more common software and hardware elements, and such description shall not require or imply that separate hardware or software components are used to implement such features or functionality. It is apparent that approaches have been described for providing a planar metrology pad adjacent a set of fins of a FinFET device. While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.

Claims (12)

What is claimed is:
1-15. (canceled)
16. A fin field effect transistor (FinFET) device, comprising:
a set of fins patterned in a substrate of the FinFET device; and
a planar metrology pad formed on the substrate adjacent to the set of fins in a metrology measurement area of the FinFET device, wherein the planar metrology pad is substantially flat and oriented substantially perpendicular to the set of fins.
17. The FinFET device of claim 16, further comprising an oxide formed between each of the set of fins.
18. The FinFET device of claim 16, wherein the set of fins comprises silicon.
19. The FinFET device of claim 16, wherein the planar metrology pad is contiguous with the set of fins and has an identical substance as the set of fins.
20. The FinFET device of claim 16, wherein the set of fins comprises a hardmask and a spacer material.
21. The FinFET device of claim 16, wherein planar metrology pad comprises a first hardmask, a spacer material, and a pad hardmask.
22. The FinFET device of claim 16, wherein a top surface of each of the set of fins is at substantially the same height as a top surface of the planar metrology pad.
23. A fin field effect transistor (FinFET) device, comprising:
a set of fins patterned in a substrate of the FinFET device;
a planar metrology pad formed on the substrate adjacent to the set of fins in a metrology measurement area of the FinFET device, wherein the planar metrology pad is substantially flat and oriented substantially perpendicular to the set of fins; and
an oxide formed between each of the set of fins.
24. The FinFET device of claim 23, wherein the set of fins comprises silicon.
25. The FinFET device of claim 23, wherein the planar metrology pad is contiguous with the set of fins and has an identical substance as the set of fins.
26. The FinFET device of claim 23, wherein a top surface of each of the set of fins is at substantially the same height as a top surface of the planar metrology pad.
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