US20150207499A1 - Frequency shift-keying reader circuit - Google Patents
Frequency shift-keying reader circuit Download PDFInfo
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- US20150207499A1 US20150207499A1 US14/273,725 US201414273725A US2015207499A1 US 20150207499 A1 US20150207499 A1 US 20150207499A1 US 201414273725 A US201414273725 A US 201414273725A US 2015207499 A1 US2015207499 A1 US 2015207499A1
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- 238000002347 injection Methods 0.000 claims abstract description 27
- 239000007924 injection Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000001914 filtration Methods 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims description 38
- 230000008878 coupling Effects 0.000 claims description 15
- 238000010168 coupling process Methods 0.000 claims description 15
- 238000005859 coupling reaction Methods 0.000 claims description 15
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 6
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 6
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1475—Subharmonic mixer arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
- H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/32—Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/411—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45394—Indexing scheme relating to differential amplifiers the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45544—Indexing scheme relating to differential amplifiers the IC comprising one or more capacitors, e.g. coupling capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45594—Indexing scheme relating to differential amplifiers the IC comprising one or more resistors, which are not biasing resistor
Definitions
- the present invention is generally relating to a frequency shift-keying reader circuit, more particularly to the frequency shift-keying reader circuit with characteristic of injection lock.
- a conventional frequency shift-keying reader circuit comprises a band-pass filter, an injection-locked oscillator and a multiplier.
- the low-pass filter receives an input signal and performs a filtering procedure to the input signal.
- the injection locked oscillator receives the filtered input signal.
- the injection-locked oscillator is locked by the filtered input signal and outputs an oscillation signal.
- the input signal and the oscillation signal are received by the multiplier so as to perform a mixing procedure. Thereafter, an output signal is outputted from a low-pass filter after a filtering procedure of the low-pass filter.
- the operational frequency of modern wireless radio frequency achieves Giga Hertz level, the higher the operational frequency, the larger the power consumption for the frequency shift-keying reader circuit.
- the conventional frequency shift-keying reader circuit acquires stable demodulating quality under the condition of high DC power consumption.
- the conventional frequency shift-keying reader circuit does not meet the Spec demand of short distance wireless communication characterized in low power consumption.
- the output signal outputted from the multiplier further includes a self-mixing component of local oscillation signal.
- the self-mixing component is a DC displacement therefore increasing the bit error rate of the demodulating signal.
- a primary object of the present invention is to make a lock frequency of a divide-by-2 frequency divider become half the operational frequency of a radio frequency signal to lower the power consumption of the frequency shift-keying reader circuit.
- the frequency shift-keying reader circuit possesses high signal isolation to effectively decrease the DC displacement output of the frequency shift-keying reader circuit therefore improving the sensitivity of the frequency shift-keying reader circuit.
- the frequency shift-keying reader circuit possesses the function of low power consumption.
- a frequency shift-keying reader circuit includes a band-pass filter, a low noise amplifier, a first balun, an injection-lock divide-by-2 frequency divider, a sub-harmonic mixer and a low-pass filter.
- the band-pass filter receives a radio frequency signal and performs a filtering procedure, wherein the radio frequency signal comprises an operational frequency.
- the low noise amplifier connects to the band-pass filter and receives the filtered radio frequency signal, wherein the low noise amplifier is used for amplifying the radio frequency signal to provide an injection signal.
- the first balun connects to the low noise amplifier and receives the injection signal, the first balun generates a first differential signal and a second differential signal, wherein the first differential signal and the second differential signal are mutually inverted.
- the injection-lock divide-by-2 frequency divider connects to the low noise amplifier and receives the injection signal, the injection-lock divide-by-2 frequency divider is locked at a lock frequency by the injection signal, the lock frequency is half the operational frequency, the injection-lock divide-by-2 frequency divider provides a first oscillation signal and a second oscillation signal, wherein the first oscillation signal and the second oscillation signal are mutually inverted.
- the sub-harmonic mixer connects to the first balun and the injection-lock divide-by-2 frequency divider, the sub-harmonic mixer receives the first differential signal, the second differential signal, the first oscillation signal and the second oscillation signal for performing a mixing procedure and thereafter generates an output signal.
- the low-pass filter connects to the sub-harmonic mixer and performs a filtering procedure to the output signal.
- the lock frequency of the injection-lock divide-by-2 frequency divider is half the operational frequency of the injection signal, thus, the power consumption for injection lock is well reduced. Besides, due to excellent isolation of the sub-harmonic mixer, the DC displacement output of the frequency shift-keying reader circuit may be lowered effectively therefore making the sensitivity of the frequency shift-keying reader circuit improved substantially.
- the frequency shift-keying reader circuit in the present invention meets the Spec demand of short distance wireless communication owing to the characteristics of low power consumption and high sensitivity.
- FIG. 1 is the diagram illustrating a frequency shift-keying reader circuit in accordance with an embodiment of the present invention.
- FIG. 2 is the circuit diagram illustrating a low noise amplifier and a first balun in accordance with the embodiment of the present invention.
- FIG. 3 is the circuit diagram illustrating an injection-lock divide-by-2 frequency divider in accordance with the embodiment of the present invention.
- FIG. 4 is the circuit diagram illustrating a sub-harmonic mixer in accordance with the embodiment of the present invention.
- a frequency shift-keying reader circuit 100 in accordance with an embodiment of the present invention includes an antenna A, a band-pass filter 110 , a low noise amplifier 120 , a first balun 130 , an injection-lock divide-by-2 frequency divider 140 , a sub-harmonic mixer 150 and a low-pass filter 160 .
- the antenna A is used for receiving a radio frequency signal v in (t) and transmitting the radio frequency signal v in (t) to the band-pass filter 110 ,
- the radio frequency signal v in (t) comprises an operational frequency ⁇ i (t), wherein the band-pass filter 110 connects to the antenna A, the band-pass filter 110 receives the radio frequency signal v in (t) and performs a filtering procedure, and the low noise amplifier 120 connects to the band-pass filter 110 and receives the filtered radio frequency signal v in (t).
- the low noise amplifier 120 is a cascade amplifier, and the low noise amplifier 120 comprises an inductor 121 , a first capacitor 122 , a first N-type transistor 123 , a second N-type transistor 124 , a first bias resistor 125 and a first resistor 126 .
- One end of the inductor 121 of the low noise amplifier 120 receives the filtered radio frequency signal v in (t)
- the other end of the inductor 121 connects to one end of the first capacitor 122
- the other end of the first capacitor 122 connects to a gate terminal 123 a of the first N-type transistor 123 to make the first N-type transistor 123 receive the filtered radio frequency signal v in (t).
- the gate terminal 123 a of the first N-type transistor 123 receives a first bias voltage V B1 via the first bias resistor 125 , a source terminal 123 b of the first N-type transistor 123 is grounded, a source terminal 124 b of the second N-type transistor 124 connects to a drain terminal 123 c of the first N-type transistor 123 , wherein a gate terminal 124 a of the second N-type transistor 124 connects to a first power terminal VDD 1 , and a drain terminal 124 c of the second N-type transistor 124 connects to the first power terminal VDD 1 via the first resistor 126 .
- the low noise amplifier 120 is used for amplifying the radio frequency signal v in (t) to provide an injection signal v inj , wherein the injection signal v inj is outputted from the drain terminal 124 c of the second N-type transistor 124 .
- the first balun 130 connects to the low noise amplifier 120 and receives the injection signal v inj to generate a first differential signal v rf , and a second differential signal v rf+ .
- the first balun 130 is an active balun and comprises a second capacitor 131 , a third N-type transistor 132 , a fourth N-type transistor 133 , a second bias resistor 134 , a second resistor 135 and a third resistor 136 , wherein one end of the second capacitor 131 connects to the drain terminal 124 c of the second N-type transistor 124 for receiving the injection signal v inj , the other end of the second capacitor 131 connects to a gate terminal 132 a of the third N-type transistor 132 to make the third N-type transistor 132 receive the injection signal v inj , the gate terminal 132 a of the third N-type transistor 132 receives a second bias voltage V B2 via the second bias resistor 134 , a drain terminal 132 c of the third N-type transistor 132 connects to the first power terminal VDD 1 via the second resistor 135 , a source terminal 132 b of the third N-type transistor 132 is
- the injection-lock divide-by-2 frequency divider 140 connects to the low noise amplifier 120 and receives the injection signal v inj .
- the injection-lock divide-by-2 frequency divider 140 comprises a ring oscillator 170 and a second balun 180 connected to the ring oscillator 170 , and the ring oscillator 170 connects to the low noise amplifier 120 for receiving the injection signal v inj .
- the ring oscillator 170 is a three-stage oscillator and comprises a first oscillation device 171 , two second oscillation devices 172 , a current source 173 , an input transistor 174 , a third capacitor 175 , a first input resistor 176 , two second input resistors 177 , a third bias resistor 178 and a fourth bias resistor 179 .
- the first oscillation device 171 comprises a first P-type oscillating transistor 171 a and a first N-type oscillating transistor 171 b
- each of the second oscillation devices 172 comprises a second P-type oscillating transistor 172 a and a second N-type oscillating transistor 172 b
- a gate terminal 171 c of the first P-type oscillating transistor 171 a receives a third bias voltage V B3 via the third bias resistor 178
- a source terminal 171 d of the first P-type oscillating transistor 171 a connects to a second power terminal VDD 2
- a body terminal 171 f of the first P-type oscillating transistor 171 a receives an adjusting voltage V Time via the first input resistor 176
- a drain terminal 171 i of the first N-type oscillating transistor 171 b connects to a drain terminal 171 e of the first P-type oscillating transistor 171 a
- a gate terminal 171
- a gate terminal 172 c of each of the second P-type oscillating transistors 172 a receives the third bias voltage V B3 via the third bias resistor 178
- a body terminal 172 f of each of the second P-type oscillating transistors 172 a receives the adjusting voltage V Time via each of the second input resistors 177
- a source terminal 172 d of each of the second P-type oscillating transistors 172 a connects to the second power terminal VDD 2
- the drain terminal 172 i of each of the second N-type oscillating transistors 172 b connects to a drain terminal 172 e of the second P-type oscillating transistor 172 a
- a gate terminal 172 g of one of the second N-type oscillating transistors 172 b connects to the drain terminal 172 i of another second N-type oscillating transistor 172 b
- the gate terminal 172 g of one of the second N-type oscillating transistors 172 b connects
- a gate terminal 174 a of the input transistor 174 receives a fourth bias voltage V B4 via the fourth bias resistor 179 .
- the gate terminal 174 a of the input transistor 174 also connects to the drain terminal 124 c of the first N-type oscillating transistor 124 via the third capacitor 175 for receiving the injection signal v inj
- a drain terminal 174 c of the input transistor 174 connects to the gate terminal 171 g of the first N-type oscillating transistor 171 b so as to inject the injection signal v inj and to lock the ring oscillator 170 at a lock frequency ⁇ o (t), wherein the lock frequency ⁇ o (t) is half the operational frequency ⁇ i (t) of the radio frequency signal v in (t) therefore decreasing the power consumption that the injection lock requires.
- the second balun 180 is an active balun
- the second balun 180 comprises a fourth capacitor 181 , a fifth N-type transistor 182 , a sixth N-type transistor 183 , a fifth bias resistor 184 , a fourth resistor 185 and a fifth resistor 186
- one end of the fourth capacitor 181 connects to the drain terminal 171 i of the first N-type oscillating transistor 171 b
- the other end of the fourth capacitor 181 connects to a gate terminal 182 a of the fifth N-type transistor 182
- the gate terminal 182 a of the fifth N-type transistor 182 receives a fifth bias voltage V B5 via the fifth bias resistor 184
- a drain terminal 182 c of the fifth N-type transistor 182 connects to the first power terminal VDD 1 via the fourth resistor 185
- a source terminal 182 b of the fifth N-type transistor 182 is grounded via the fifth resistor 186
- the sub-harmonic mixer 150 connects to the first balun 130 and the injection-lock divide-by-2 frequency divider 140 for receiving the first differential signal v rf ⁇ and the second differential signal v rf+ both outputted from the first balun 130 and receiving the first oscillation signal v osc ⁇ and the second oscillation signal v osc+ both outputted from the injection-lock divide-by-2 frequency divider 140 .
- the sub-harmonic mixer 150 is stacked by two differential pairs and comprises a transconductance stage 151 , a switch stage 152 , a first coupling capacitor C 1 , a second coupling capacitor C 2 , a third coupling capacitor C 3 , a fourth capacitor C 4 , a sixth bias resistor 153 , a sixth resistor 154 , a seventh bias resistor 155 , a seventh resistor 156 , an eighth bias resistor 157 and a ninth bias resistor 158 , wherein the transconductance stage 151 comprises a first differential transistor 151 a and a second differential transistor 151 b , a gate terminal 151 c of the first differential transistor 151 a receives the first differential signal v rf ⁇ via the first coupling capacitor C 1 .
- the gate terminal 151 c of the first differential transistor 151 a receives the sixth bias voltage V B6 via the sixth bias resistor 153 , and a drain terminal 151 e of the first differential transistor 151 a connects to the first power terminal VDD 1 via the sixth resistor 154 .
- a gate terminal 151 f of the second differential transistor 151 b receives the second differential signal v rf+ via the second coupling capacitor C 2 .
- the gate terminal 151 f of the second differential transistor 151 b receives the seventh bias voltage V B7 via the seventh bias resistor 155 , and a drain terminal 151 h of the second differential transistor 151 b connects to the first power terminal VDD 1 via the seventh resistor 156 .
- the switch stage 152 connects to the transconductance stage 151 and comprises a third differential transistor 152 a and a fourth differential transistor 152 b .
- a gate terminal 152 c of the third differential transistor 152 a receives the first oscillation signal v osc ⁇ via the third coupling capacitor C 3 .
- the gate terminal 152 c of the third differential transistor 152 a receives the eighth bias voltage V B8 via the eighth bias resistor 157 .
- a gate terminal 152 f of the fourth differential resistor 152 b receives the second oscillation signal v osc+ via the fourth coupling capacitor C 4 .
- the gate terminal 152 f of the fourth differential transistor 152 b receives the ninth bias voltage V B9 via the ninth bias resistor 158 .
- a source terminal 152 d of the third differential transistor 152 a and a source terminal 152 g of the fourth differential transistor 152 b are grounded, wherein a drain terminal 152 e of the third differential transistor 152 a and a drain terminal 152 h of the fourth differential transistor 152 b connect to the source terminal 151 d of the first differential transistor 151 a and the source terminal 151 g of the second differential transistor 151 b .
- the first oscillation signal v osc ⁇ and the second oscillation signal v osc+ received by the switch stage 152 are mutually inverted differential signals, thus, the frequency of the current formed at a node n of the switch stage 152 is two times the first oscillation signal v osc ⁇ and the second oscillation signal v osc+ .
- the sub-harmonic mixer 150 possesses excellent isolation to prevent the transconductance stage from DC displacement caused by the first oscillation signal v osc ⁇ and the second oscillation signal v osc+ therefore improving the sensitivity of the frequency shift-keying reader circuit 100 .
- the voltage difference between the drain terminal 151 e of the first differential transistor 151 a and the drain terminal 151 h of the second differential transistor 151 b is the output signal v out (t).
- the low-pass filter 160 connects to the sub-harmonic mixer 150 for receiving the output signal v out (t) and filtering the output signal v out (t) therefore achieving the demodulation of radio frequency signal.
- the lock frequency ⁇ o (t) of the injection-lock divide-by-2 frequency divider 140 is half the operational frequency ⁇ i (t) of the radio frequency signal v in (t), thus, the power consumption for injection lock is well reduced.
- the DC displacement output of the frequency shift-keying reader circuit 100 may be lowered effectively therefore making the sensitivity of the frequency shift-keying reader circuit 100 improved substantially.
- the frequency shift-keying reader circuit 100 in the present invention meets the Spec demand of short distance wireless communication owing to the characteristics of low power consumption and high sensitivity.
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Abstract
Description
- The present invention is generally relating to a frequency shift-keying reader circuit, more particularly to the frequency shift-keying reader circuit with characteristic of injection lock.
- A conventional frequency shift-keying reader circuit comprises a band-pass filter, an injection-locked oscillator and a multiplier. The low-pass filter receives an input signal and performs a filtering procedure to the input signal. The injection locked oscillator receives the filtered input signal. Besides, the injection-locked oscillator is locked by the filtered input signal and outputs an oscillation signal. The input signal and the oscillation signal are received by the multiplier so as to perform a mixing procedure. Thereafter, an output signal is outputted from a low-pass filter after a filtering procedure of the low-pass filter. The operational frequency of modern wireless radio frequency achieves Giga Hertz level, the higher the operational frequency, the larger the power consumption for the frequency shift-keying reader circuit. Therefore, the conventional frequency shift-keying reader circuit acquires stable demodulating quality under the condition of high DC power consumption. The conventional frequency shift-keying reader circuit does not meet the Spec demand of short distance wireless communication characterized in low power consumption. Besides, owing to low isolation from the local oscillation port of the conventional frequency shift-keying reader circuit to the radio frequency signal, the output signal outputted from the multiplier further includes a self-mixing component of local oscillation signal. The self-mixing component is a DC displacement therefore increasing the bit error rate of the demodulating signal.
- A primary object of the present invention is to make a lock frequency of a divide-by-2 frequency divider become half the operational frequency of a radio frequency signal to lower the power consumption of the frequency shift-keying reader circuit. Besides, by a mixing procedure of a sub-harmonic mixer, the frequency shift-keying reader circuit possesses high signal isolation to effectively decrease the DC displacement output of the frequency shift-keying reader circuit therefore improving the sensitivity of the frequency shift-keying reader circuit. Furthermore, the frequency shift-keying reader circuit possesses the function of low power consumption.
- A frequency shift-keying reader circuit includes a band-pass filter, a low noise amplifier, a first balun, an injection-lock divide-by-2 frequency divider, a sub-harmonic mixer and a low-pass filter. The band-pass filter receives a radio frequency signal and performs a filtering procedure, wherein the radio frequency signal comprises an operational frequency. The low noise amplifier connects to the band-pass filter and receives the filtered radio frequency signal, wherein the low noise amplifier is used for amplifying the radio frequency signal to provide an injection signal. The first balun connects to the low noise amplifier and receives the injection signal, the first balun generates a first differential signal and a second differential signal, wherein the first differential signal and the second differential signal are mutually inverted. The injection-lock divide-by-2 frequency divider connects to the low noise amplifier and receives the injection signal, the injection-lock divide-by-2 frequency divider is locked at a lock frequency by the injection signal, the lock frequency is half the operational frequency, the injection-lock divide-by-2 frequency divider provides a first oscillation signal and a second oscillation signal, wherein the first oscillation signal and the second oscillation signal are mutually inverted. The sub-harmonic mixer connects to the first balun and the injection-lock divide-by-2 frequency divider, the sub-harmonic mixer receives the first differential signal, the second differential signal, the first oscillation signal and the second oscillation signal for performing a mixing procedure and thereafter generates an output signal. The low-pass filter connects to the sub-harmonic mixer and performs a filtering procedure to the output signal.
- In the present invention, the lock frequency of the injection-lock divide-by-2 frequency divider is half the operational frequency of the injection signal, thus, the power consumption for injection lock is well reduced. Besides, due to excellent isolation of the sub-harmonic mixer, the DC displacement output of the frequency shift-keying reader circuit may be lowered effectively therefore making the sensitivity of the frequency shift-keying reader circuit improved substantially. The frequency shift-keying reader circuit in the present invention meets the Spec demand of short distance wireless communication owing to the characteristics of low power consumption and high sensitivity.
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FIG. 1 is the diagram illustrating a frequency shift-keying reader circuit in accordance with an embodiment of the present invention. -
FIG. 2 is the circuit diagram illustrating a low noise amplifier and a first balun in accordance with the embodiment of the present invention. -
FIG. 3 is the circuit diagram illustrating an injection-lock divide-by-2 frequency divider in accordance with the embodiment of the present invention. -
FIG. 4 is the circuit diagram illustrating a sub-harmonic mixer in accordance with the embodiment of the present invention. - Please refer to
FIG. 1 , a frequency shift-keying reader circuit 100 in accordance with an embodiment of the present invention includes an antenna A, a band-pass filter 110, alow noise amplifier 120, afirst balun 130, an injection-lock divide-by-2frequency divider 140, asub-harmonic mixer 150 and a low-pass filter 160. - Please refer to
FIGS. 1 and 2 , the antenna A is used for receiving a radio frequency signal vin(t) and transmitting the radio frequency signal vin(t) to the band-pass filter 110, the radio frequency signal vin(t) comprises an operational frequency ωi(t), wherein the band-pass filter 110 connects to the antenna A, the band-pass filter 110 receives the radio frequency signal vin(t) and performs a filtering procedure, and thelow noise amplifier 120 connects to the band-pass filter 110 and receives the filtered radio frequency signal vin(t). - With reference to
FIG. 2 , in this embodiment, thelow noise amplifier 120 is a cascade amplifier, and thelow noise amplifier 120 comprises aninductor 121, afirst capacitor 122, a first N-type transistor 123, a second N-type transistor 124, afirst bias resistor 125 and afirst resistor 126. One end of theinductor 121 of thelow noise amplifier 120 receives the filtered radio frequency signal vin(t), the other end of theinductor 121 connects to one end of thefirst capacitor 122, the other end of thefirst capacitor 122 connects to agate terminal 123 a of the first N-type transistor 123 to make the first N-type transistor 123 receive the filtered radio frequency signal vin(t). Thegate terminal 123 a of the first N-type transistor 123 receives a first bias voltage VB1 via thefirst bias resistor 125, asource terminal 123 b of the first N-type transistor 123 is grounded, asource terminal 124 b of the second N-type transistor 124 connects to adrain terminal 123 c of the first N-type transistor 123, wherein agate terminal 124 a of the second N-type transistor 124 connects to a first power terminal VDD1, and adrain terminal 124 c of the second N-type transistor 124 connects to the first power terminal VDD1 via thefirst resistor 126. Thelow noise amplifier 120 is used for amplifying the radio frequency signal vin(t) to provide an injection signal vinj, wherein the injection signal vinj is outputted from thedrain terminal 124 c of the second N-type transistor 124. - With reference to
FIGS. 1 and 2 , thefirst balun 130 connects to thelow noise amplifier 120 and receives the injection signal vinj to generate a first differential signal vrf, and a second differential signal vrf+. Referring toFIG. 2 , in this embodiment, thefirst balun 130 is an active balun and comprises asecond capacitor 131, a third N-type transistor 132, a fourth N-type transistor 133, asecond bias resistor 134, asecond resistor 135 and athird resistor 136, wherein one end of thesecond capacitor 131 connects to thedrain terminal 124 c of the second N-type transistor 124 for receiving the injection signal vinj, the other end of thesecond capacitor 131 connects to agate terminal 132 a of the third N-type transistor 132 to make the third N-type transistor 132 receive the injection signal vinj, thegate terminal 132 a of the third N-type transistor 132 receives a second bias voltage VB2 via thesecond bias resistor 134, adrain terminal 132 c of the third N-type transistor 132 connects to the first power terminal VDD1 via thesecond resistor 135, asource terminal 132 b of the third N-type transistor 132 is grounded via thethird resistor 136, adrain terminal 133 c of the fourth N-type transistor 133 connects to thesource terminal 132 b of the third N-type transistor 132, wherein agate terminal 133 a of the fourth N-type transistor 133 and asource terminal 133 b of the fourth N-type transistor 133 are grounded, wherein thedrain terminal 132 c and thesource terminal 132 b of the third N-type transistor 132 provide the first differential signal vrf− and the second differential signal vrf+ respectively, wherein the first differential signal vrf and the second differential signal vrf+ are mutually inverted to provide thesub-harmonic mixer 150 of the rear end with a differential signal. - Referring to
FIGS. 1 , 2 and 3, the injection-lock divide-by-2frequency divider 140 connects to thelow noise amplifier 120 and receives the injection signal vinj. With reference toFIG. 3 , the injection-lock divide-by-2frequency divider 140 comprises aring oscillator 170 and asecond balun 180 connected to thering oscillator 170, and thering oscillator 170 connects to thelow noise amplifier 120 for receiving the injection signal vinj. In this embodiment, thering oscillator 170 is a three-stage oscillator and comprises afirst oscillation device 171, twosecond oscillation devices 172, acurrent source 173, aninput transistor 174, athird capacitor 175, afirst input resistor 176, twosecond input resistors 177, athird bias resistor 178 and afourth bias resistor 179. Thefirst oscillation device 171 comprises a first P-type oscillating transistor 171 a and a first N-type oscillating transistor 171 b, each of thesecond oscillation devices 172 comprises a second P-type oscillating transistor 172 a and a second N-type oscillating transistor 172 b, wherein agate terminal 171 c of the first P-type oscillating transistor 171 a receives a third bias voltage VB3 via thethird bias resistor 178, asource terminal 171 d of the first P-type oscillating transistor 171 a connects to a second power terminal VDD2, abody terminal 171 f of the first P-type oscillating transistor 171 a receives an adjusting voltage VTime via thefirst input resistor 176, adrain terminal 171 i of the first N-type oscillating transistor 171 b connects to adrain terminal 171 e of the first P-type oscillating transistor 171 a, agate terminal 171 g of the first N-type oscillating transistor 171 b connects to adrain terminal 172 i of one of the second N-type oscillating transistors 172 b, wherein asource terminal 171 h of the first N-type oscillating transistor 171 b connects to thecurrent source 173. Agate terminal 172 c of each of the second P-type oscillating transistors 172 a receives the third bias voltage VB3 via thethird bias resistor 178, abody terminal 172 f of each of the second P-type oscillating transistors 172 a receives the adjusting voltage VTime via each of thesecond input resistors 177, asource terminal 172 d of each of the second P-type oscillating transistors 172 a connects to the second power terminal VDD2, thedrain terminal 172 i of each of the second N-type oscillating transistors 172 b connects to adrain terminal 172 e of the second P-type oscillating transistor 172 a, agate terminal 172 g of one of the second N-type oscillating transistors 172 b connects to thedrain terminal 172 i of another second N-type oscillating transistor 172 b, thegate terminal 172 g of one of the second N-type oscillating transistors 172 b connects to thedrain terminal 171 i of the first N-type oscillating transistor 171 b, asource terminal 172 h of each of the second N-type oscillating transistors 172 b connects to thecurrent source 173. - Referring to
FIG. 3 , agate terminal 174 a of theinput transistor 174 receives a fourth bias voltage VB4 via thefourth bias resistor 179. Thegate terminal 174 a of theinput transistor 174 also connects to thedrain terminal 124 c of the first N-type oscillating transistor 124 via thethird capacitor 175 for receiving the injection signal vinj, and adrain terminal 174 c of theinput transistor 174 connects to thegate terminal 171 g of the first N-type oscillating transistor 171 b so as to inject the injection signal vinj and to lock thering oscillator 170 at a lock frequency ωo(t), wherein the lock frequency ωo(t) is half the operational frequency ωi(t) of the radio frequency signal vin(t) therefore decreasing the power consumption that the injection lock requires. - With reference to
FIG. 3 , thesecond balun 180 is an active balun, thesecond balun 180 comprises afourth capacitor 181, a fifth N-type transistor 182, a sixth N-type transistor 183, afifth bias resistor 184, afourth resistor 185 and afifth resistor 186, one end of thefourth capacitor 181 connects to thedrain terminal 171 i of the first N-type oscillating transistor 171 b, the other end of thefourth capacitor 181 connects to agate terminal 182 a of the fifth N-type transistor 182, thegate terminal 182 a of the fifth N-type transistor 182 receives a fifth bias voltage VB5 via thefifth bias resistor 184, adrain terminal 182 c of the fifth N-type transistor 182 connects to the first power terminal VDD1 via thefourth resistor 185, asource terminal 182 b of the fifth N-type transistor 182 is grounded via thefifth resistor 186, adrain terminal 183 c of the sixth N-type transistor 183 connects to thesource terminal 182 b of the fifth N-type transistor 182, wherein agate terminal 183 a of the sixth N-type transistor 183 and asource terminal 183 b of the sixth N-type transistor 183 are grounded, wherein thedrain terminal 182 c of the fifth N-type transistor 182 provide the first oscillation signal and thesource terminal 182 b of the fifth N-type transistor 182 provide the second oscillation signal vosc+. Besides, the first oscillation signal vosc− and the second oscillation signal vosc+ are mutually inverted to provide thesub-harmonic mixer 150 of the rear end with a differential oscillation signal. - With reference to
FIGS. 1 , 2, 3 and 4, thesub-harmonic mixer 150 connects to thefirst balun 130 and the injection-lock divide-by-2frequency divider 140 for receiving the first differential signal vrf−− and the second differential signal vrf+ both outputted from thefirst balun 130 and receiving the first oscillation signal vosc− and the second oscillation signal vosc+ both outputted from the injection-lock divide-by-2frequency divider 140. - Referring to
FIG. 4 , thesub-harmonic mixer 150 is stacked by two differential pairs and comprises atransconductance stage 151, aswitch stage 152, a first coupling capacitor C1, a second coupling capacitor C2, a third coupling capacitor C3, a fourth capacitor C4, asixth bias resistor 153, asixth resistor 154, aseventh bias resistor 155, aseventh resistor 156, aneighth bias resistor 157 and aninth bias resistor 158, wherein thetransconductance stage 151 comprises a firstdifferential transistor 151 a and a seconddifferential transistor 151 b, agate terminal 151 c of the firstdifferential transistor 151 a receives the first differential signal vrf− via the first coupling capacitor C1. Thegate terminal 151 c of the firstdifferential transistor 151 a receives the sixth bias voltage VB6 via thesixth bias resistor 153, and adrain terminal 151 e of the firstdifferential transistor 151 a connects to the first power terminal VDD1 via thesixth resistor 154. Agate terminal 151 f of the seconddifferential transistor 151 b receives the second differential signal vrf+ via the second coupling capacitor C2. Thegate terminal 151 f of the seconddifferential transistor 151 b receives the seventh bias voltage VB7 via theseventh bias resistor 155, and adrain terminal 151 h of the seconddifferential transistor 151 b connects to the first power terminal VDD1 via theseventh resistor 156. - With reference to
FIG. 4 , theswitch stage 152 connects to thetransconductance stage 151 and comprises a thirddifferential transistor 152 a and a fourthdifferential transistor 152 b. Agate terminal 152 c of the thirddifferential transistor 152 a receives the first oscillation signal vosc− via the third coupling capacitor C3. Thegate terminal 152 c of the thirddifferential transistor 152 a receives the eighth bias voltage VB8 via theeighth bias resistor 157. Agate terminal 152 f of the fourthdifferential resistor 152 b receives the second oscillation signal vosc+ via the fourth coupling capacitor C4. Thegate terminal 152 f of the fourthdifferential transistor 152 b receives the ninth bias voltage VB9 via theninth bias resistor 158. Asource terminal 152 d of the thirddifferential transistor 152 a and asource terminal 152 g of the fourthdifferential transistor 152 b are grounded, wherein adrain terminal 152 e of the thirddifferential transistor 152 a and adrain terminal 152 h of the fourthdifferential transistor 152 b connect to thesource terminal 151 d of the firstdifferential transistor 151 a and thesource terminal 151 g of the seconddifferential transistor 151 b. The first oscillation signal vosc− and the second oscillation signal vosc+ received by theswitch stage 152 are mutually inverted differential signals, thus, the frequency of the current formed at a node n of theswitch stage 152 is two times the first oscillation signal vosc− and the second oscillation signal vosc+. Besides, owing to the circuit characteristics of the node n, thesub-harmonic mixer 150 possesses excellent isolation to prevent the transconductance stage from DC displacement caused by the first oscillation signal vosc− and the second oscillation signal vosc+ therefore improving the sensitivity of the frequency shift-keyingreader circuit 100. - Referring to
FIGS. 1 and 4 , the voltage difference between thedrain terminal 151 e of the firstdifferential transistor 151 a and thedrain terminal 151 h of the seconddifferential transistor 151 b is the output signal vout(t). The low-pass filter 160 connects to thesub-harmonic mixer 150 for receiving the output signal vout(t) and filtering the output signal vout(t) therefore achieving the demodulation of radio frequency signal. - In the present invention, the lock frequency ωo(t) of the injection-lock divide-by-2
frequency divider 140 is half the operational frequency ωi(t) of the radio frequency signal vin(t), thus, the power consumption for injection lock is well reduced. Besides, due to excellent isolation of thesub-harmonic mixer 150, the DC displacement output of the frequency shift-keying reader circuit 100 may be lowered effectively therefore making the sensitivity of the frequency shift-keying reader circuit 100 improved substantially. The frequency shift-keying reader circuit 100 in the present invention meets the Spec demand of short distance wireless communication owing to the characteristics of low power consumption and high sensitivity. - While this invention has been particularly illustrated and described in detail with respect to the preferred embodiments thereof, it will be clearly understood by those skilled in the art that is not limited to the specific features shown and described and various modified and changed in form and details may be made without departing from the spirit and scope of this invention.
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TW103101890A TWI533647B (en) | 2014-01-17 | 2014-01-17 | Frequency-shift key receiver |
TW103101890A | 2014-01-17 |
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US9673829B1 (en) * | 2015-12-02 | 2017-06-06 | Innophase, Inc. | Wideband polar receiver architecture and signal processing methods |
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TWI645678B (en) * | 2018-05-02 | 2018-12-21 | 國立暨南國際大學 | Divide by three injection locked frequency divider |
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TW201531066A (en) | 2015-08-01 |
TWI533647B (en) | 2016-05-11 |
US9088272B1 (en) | 2015-07-21 |
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