US20150149733A1 - Supporting speculative modification in a data cache - Google Patents

Supporting speculative modification in a data cache Download PDF

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US20150149733A1
US20150149733A1 US13/007,015 US201113007015A US2015149733A1 US 20150149733 A1 US20150149733 A1 US 20150149733A1 US 201113007015 A US201113007015 A US 201113007015A US 2015149733 A1 US2015149733 A1 US 2015149733A1
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cache
state
speculative
cache line
buffer
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US13/007,015
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Guillermo Rozas
Alexander Klaiber
David Dunn
Paul Serris
Lacky Shah
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Intellectual Ventures Holding 81 LLC
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Guillermo Rozas
Alexander Klaiber
David Dunn
Paul Serris
Lacky Shah
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Assigned to INTELLECTUAL VENTURES HOLDING 81 LLC reassignment INTELLECTUAL VENTURES HOLDING 81 LLC CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 036711 FRAME: 0160. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Assignors: INTELLECTUAL VENTURES FUNDING LLC
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/603—Details of cache memory of operating mode, e.g. cache mode or local memory mode

Definitions

  • Embodiments generally relate to data caches. More particularly, embodiments relate to the field of supporting speculative modification in a data cache.
  • a data cache interacts with a processor to increase system performance. However, if the processor is speculatively executing instructions, a traditional data cache is unable to properly deal with speculative modifications.
  • FIG. 1 illustrates a system in accordance with a first embodiment.
  • FIG. 2 illustrates a state diagram of a data cache in accordance with a first embodiment.
  • FIG. 3 illustrates a system in accordance with a second embodiment.
  • FIG. 4 illustrates a first state diagram of a speculative cache buffer in accordance with a second embodiment.
  • FIG. 5 illustrates a second state diagram of a speculative cache buffer in accordance with a second embodiment.
  • FIG. 1 illustrates a system 100 in accordance with a first embodiment. As illustrated in FIG. 1 , the system 100 includes a processor 10 and a data cache 20 .
  • the processor 10 is able to speculatively execute instructions. If the processor 10 speculatively executes instructions to a particular instruction boundary without generating errors, the speculative store operations to the data cache 20 can be made permanent with a commit operation. However, if errors occur before reaching the particular instruction boundary, the speculative store operations to the data cache 20 have to be undone with a rollback operation.
  • the data cache 20 includes a plurality of cache lines 25 .
  • Each cache line includes a state indicator 27 for indicating any one of a plurality of states.
  • the plurality of states include an invalid state, a valid state, a dirty state, and a speculative state.
  • the invalid state indicates that the respective cache line is not being used.
  • the valid state indicates that the respective cache line has clean data.
  • the dirty state indicates that the respective cache line has dirty data (or the most recent data compared to other memory components such as L2 data cache, main memory, etc.).
  • the speculative state enables keeping track of speculative modification to data in said respective cache line.
  • the speculative state enables a speculative modification to the data in the respective cache line to be made permanent in response to a commit operation.
  • the speculative state enables the speculative modification to the data in the respective cache line to be undone in response to a rollback operation.
  • Cache lines having the speculative state cannot be drained to other memory components such as L2 data cache, main memory, etc.
  • FIG. 2 illustrates a state diagram of a data cache in accordance with a first embodiment.
  • a cache line can have an invalid state I, a valid state V, a dirty state D, or a speculative state S.
  • V, D, and S states For clarity, state transitions from V, D, and S states to the I state, corresponding to the traditional operation of the data cache evicting a cache line, have been omitted in the figure.
  • the cache line moves to the dirty state D. If data is loaded from memory components such as L2 data cache, main memory, etc., the cache line moves to the valid state V, where the data is clean (has same version as the memory components such as L2 data cache, main memory, etc.). If a speculative store is performed by the processor 10 ( FIG. 1 ), the cache line moves to the speculative state S.
  • the cache line moves to the dirty state D. If a speculative store is performed by the processor 10 ( FIG. 1 ), the cache line moves to the speculative state S.
  • a speculative store is performed by the processor 10 ( FIG. 1 ) to this cache line, the cache line is first written back to a memory component such as L2 data cache, main memory, etc., thus preserving the cache line data as of before the speculative modification. Then, the speculative store is performed, moving the cache line to the speculative state S.
  • FIG. 3 illustrates a system 300 in accordance with a second embodiment.
  • the system 300 includes a processor 10 , a data cache 20 , and a speculative cache buffer 50 .
  • the discussion with respect to the processor 10 and the data cache 20 is equally applicable to FIG. 3 .
  • the speculative cache buffer 50 receives cache lines which have the speculative state S and are evicted or drained from the data cache 20 . Hence, the data cache 20 can send cache lines having the speculative state to the speculative cache buffer 50 and retrieve them when necessary.
  • the speculative cache buffer 50 has a plurality of cache lines 55 .
  • Each cache line 55 includes a state indicator 57 for indicating any one of a plurality of states.
  • the plurality of states includes an invalid state, a dirty state, and a speculative state.
  • the speculative cache buffer 50 is fully associative.
  • the data cache 20 can drain cache lines that are in the dirty state D or the speculative state S to the speculative cache buffer 50 .
  • the speculative cache buffer 50 can drain cache lines that are in the dirty state D to a memory component such as L2 data cache, main memory, etc.
  • FIG. 4 illustrates a first state diagram of a speculative cache buffer in accordance with a second embodiment.
  • a cache line can have an invalid state I, a dirty state D, or a speculative state S.
  • the cache line moves to the dirty state D. If the data cache 20 evicts a cache line having the speculative state S, the cache line moves to the speculative state S.
  • the speculative cache buffer 50 drains the cache line having the dirty state D to a memory component such as L2 data cache, main memory, etc., the cache line moves to the invalid state I. In case the data cache requests the cache line back, it moves to the invalid state I in the speculative cache buffer.
  • the data cache 20 may drain the cache line having the dirty state to the speculative cache buffer 50 because a speculative store has to be performed to the cache line in the data cache 20 . If the cache line having the speculative state is later drained to the speculative cache buffer 50 and if a commit operation is performed, then the speculative cache buffer 50 would have two cache lines with different versions of the data, whereas only one version of the data needs to be drained to a memory component such as L2 data cache, main memory, etc.
  • the plurality of states also includes a commit-kill state, in addition to the invalid state, the dirty state, and the speculative state.
  • the commit-kill state indicates that the data cache 20 has evicted the respective cache line having the dirty state in response to a speculative modification operation (or speculative store) to the respective cache line in the data cache 20 .
  • the commit-kill state reduces the number of copies of a cache line in the dirty state and saves bandwidth in case of the commit operation, as detailed below.
  • FIG. 5 illustrates a second state diagram of a speculative cache buffer in accordance with a second embodiment.
  • a cache line can have an invalid state I, a dirty state D, a commit-kill state K, or a speculative state S.
  • the cache line Assuming the cache line is in the invalid state I, there are several possibilities for this cache line. If the data cache 20 evicts a cache line having the dirty state D but not due to a speculative store operation, the cache line moves to the dirty state D. If the data cache 20 evicts a cache line having the speculative state S, the cache line moves to the speculative state S. If the data cache 20 evicts a cache line having the dirty state D in response to a speculative store operation to that cache line, the cache line moves to the commit-kill state K.
  • the speculative cache buffer 50 drains the cache line having the dirty state D to a memory component such as L2 data cache, main memory, etc., the cache line moves to the invalid state I. In case the data cache requests the cache line back, it moves to the invalid state I in the speculative cache buffer.
  • the cache line moves to the invalid state I. If a commit operation is performed, the cache line moves to the invalid state I. If a rollback operation is performed, the cache line moves to the dirty state D. If the speculative cache buffer 50 drains the cache line having the commit-kill state K to a memory component such as L2 data cache, main memory, etc., the cache line moves to the invalid state I.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Method and system for supporting speculative modification in a data cache are provided and described. In one embodiment, a speculative cache buffer includes a plurality of cache lines and a plurality of state indicators. At least one of the cache lines is operable to receive an evicted cache line from a cache. The at least one of the cache lines is operable to return the evicted cache line to the cache if the cache requests the evicted cache line. Further, the plurality of state indicators is operable to indicate a state of a corresponding cache line of the cache lines.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a Continuation of and claims priority to U.S. patent application Ser. No. 11/807,629, filed on May 29, 2007, which is a Continuation of and claims priority to U.S. patent application Ser. No. 10/662,028, filed on Jul. 16, 2003, which are hereby incorporated by reference in their entirety.
    • FIELD
  • Embodiments generally relate to data caches. More particularly, embodiments relate to the field of supporting speculative modification in a data cache.
    • BACKGROUND
  • A data cache interacts with a processor to increase system performance. However, if the processor is speculatively executing instructions, a traditional data cache is unable to properly deal with speculative modifications.
    • SUMMARY
  • Method and system for supporting speculative modification in a data cache are provided and described.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments, together with the description, serve to explain the principles of the disclosure.
  • FIG. 1 illustrates a system in accordance with a first embodiment.
  • FIG. 2 illustrates a state diagram of a data cache in accordance with a first embodiment.
  • FIG. 3 illustrates a system in accordance with a second embodiment.
  • FIG. 4 illustrates a first state diagram of a speculative cache buffer in accordance with a second embodiment.
  • FIG. 5 illustrates a second state diagram of a speculative cache buffer in accordance with a second embodiment.
    •  DETAILED DESCRIPTION
  • Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the disclosure to these embodiments. On the contrary, the disclosure is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the disclosure as defined by the appended claims. Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a thorough understanding. However, it will be recognized by one of ordinary skill in the art that embodiments may be practiced without these specific details.
  • FIG. 1 illustrates a system 100 in accordance with a first embodiment. As illustrated in FIG. 1, the system 100 includes a processor 10 and a data cache 20.
  • The processor 10 is able to speculatively execute instructions. If the processor 10 speculatively executes instructions to a particular instruction boundary without generating errors, the speculative store operations to the data cache 20 can be made permanent with a commit operation. However, if errors occur before reaching the particular instruction boundary, the speculative store operations to the data cache 20 have to be undone with a rollback operation.
  • The data cache 20 includes a plurality of cache lines 25. Each cache line includes a state indicator 27 for indicating any one of a plurality of states. The plurality of states include an invalid state, a valid state, a dirty state, and a speculative state. The invalid state indicates that the respective cache line is not being used. The valid state indicates that the respective cache line has clean data. The dirty state indicates that the respective cache line has dirty data (or the most recent data compared to other memory components such as L2 data cache, main memory, etc.). The speculative state enables keeping track of speculative modification to data in said respective cache line. The speculative state enables a speculative modification to the data in the respective cache line to be made permanent in response to a commit operation. Moreover, the speculative state enables the speculative modification to the data in the respective cache line to be undone in response to a rollback operation. Cache lines having the speculative state cannot be drained to other memory components such as L2 data cache, main memory, etc.
  • FIG. 2 illustrates a state diagram of a data cache in accordance with a first embodiment. As described above, a cache line can have an invalid state I, a valid state V, a dirty state D, or a speculative state S. (For clarity, state transitions from V, D, and S states to the I state, corresponding to the traditional operation of the data cache evicting a cache line, have been omitted in the figure.)
  • Invalid State I
  • Assuming the cache line is in the invalid state I, there are several possibilities for this cache line. If a non-speculative store is performed by the processor 10 (FIG. 1), the cache line moves to the dirty state D. If data is loaded from memory components such as L2 data cache, main memory, etc., the cache line moves to the valid state V, where the data is clean (has same version as the memory components such as L2 data cache, main memory, etc.). If a speculative store is performed by the processor 10 (FIG. 1), the cache line moves to the speculative state S.
  • Valid State V
  • Assuming the cache line is in the valid state V, there are several possibilities for this cache line. If a non-speculative store is performed by the processor 10 (FIG. 1), the cache line moves to the dirty state D. If a speculative store is performed by the processor 10 (FIG. 1), the cache line moves to the speculative state S.
  • Dirty State D
  • Assuming the cache line is in the dirty state D, there are several possibilities for this cache line. If a speculative store is performed by the processor 10 (FIG. 1) to this cache line, the cache line is first written back to a memory component such as L2 data cache, main memory, etc., thus preserving the cache line data as of before the speculative modification. Then, the speculative store is performed, moving the cache line to the speculative state S.
  • Speculative State S
  • Assuming the cache line is in the speculative state S, there are several possibilities for this cache line. If a commit operation is performed, the cache line moves to the dirty state D. If a rollback operation is performed, the cache line moves to the invalid state I.
  • FIG. 3 illustrates a system 300 in accordance with a second embodiment. The system 300 includes a processor 10, a data cache 20, and a speculative cache buffer 50. The discussion with respect to the processor 10 and the data cache 20 is equally applicable to FIG. 3.
  • The speculative cache buffer 50 receives cache lines which have the speculative state S and are evicted or drained from the data cache 20. Hence, the data cache 20 can send cache lines having the speculative state to the speculative cache buffer 50 and retrieve them when necessary.
  • Moreover, the speculative cache buffer 50 has a plurality of cache lines 55. Each cache line 55 includes a state indicator 57 for indicating any one of a plurality of states. The plurality of states includes an invalid state, a dirty state, and a speculative state. In one embodiment, the speculative cache buffer 50 is fully associative.
  • The data cache 20 can drain cache lines that are in the dirty state D or the speculative state S to the speculative cache buffer 50. Moreover, the speculative cache buffer 50 can drain cache lines that are in the dirty state D to a memory component such as L2 data cache, main memory, etc.
  • FIG. 4 illustrates a first state diagram of a speculative cache buffer in accordance with a second embodiment. As described above, a cache line can have an invalid state I, a dirty state D, or a speculative state S.
  • Invalid State I
  • Assuming the cache line is in the invalid state I, there are several possibilities for this cache line. If the data cache 20 evicts a cache line having the dirty state D, the cache line moves to the dirty state D. If the data cache 20 evicts a cache line having the speculative state S, the cache line moves to the speculative state S.
  • Dirty State D
  • Assuming the cache line is in the dirty state D, there are several possibilities for this cache line. If the speculative cache buffer 50 drains the cache line having the dirty state D to a memory component such as L2 data cache, main memory, etc., the cache line moves to the invalid state I. In case the data cache requests the cache line back, it moves to the invalid state I in the speculative cache buffer.
  • Speculative State S
  • Assuming the cache line is in the speculative state S, there are several possibilities for this cache line. If a commit operation is performed, the cache line moves to the dirty state D. If a rollback operation is performed, the cache line moves to the invalid state I. In case the data cache requests the cache line back, it moves to the invalid state I in the speculative cache buffer.
  • It is possible that multiple versions of a cache line in the dirty state may exist in the speculative cache buffer 50. For instance, the data cache 20 may drain the cache line having the dirty state to the speculative cache buffer 50 because a speculative store has to be performed to the cache line in the data cache 20. If the cache line having the speculative state is later drained to the speculative cache buffer 50 and if a commit operation is performed, then the speculative cache buffer 50 would have two cache lines with different versions of the data, whereas only one version of the data needs to be drained to a memory component such as L2 data cache, main memory, etc.
  • In an alternate embodiment of the speculative cache buffer 50, the plurality of states also includes a commit-kill state, in addition to the invalid state, the dirty state, and the speculative state. The commit-kill state indicates that the data cache 20 has evicted the respective cache line having the dirty state in response to a speculative modification operation (or speculative store) to the respective cache line in the data cache 20. The commit-kill state reduces the number of copies of a cache line in the dirty state and saves bandwidth in case of the commit operation, as detailed below.
  • FIG. 5 illustrates a second state diagram of a speculative cache buffer in accordance with a second embodiment. As described above, a cache line can have an invalid state I, a dirty state D, a commit-kill state K, or a speculative state S.
  • Invalid State I
  • Assuming the cache line is in the invalid state I, there are several possibilities for this cache line. If the data cache 20 evicts a cache line having the dirty state D but not due to a speculative store operation, the cache line moves to the dirty state D. If the data cache 20 evicts a cache line having the speculative state S, the cache line moves to the speculative state S. If the data cache 20 evicts a cache line having the dirty state D in response to a speculative store operation to that cache line, the cache line moves to the commit-kill state K.
  • Dirty State D
  • Assuming the cache line is in the dirty state D, there are several possibilities for this cache line. If the speculative cache buffer 50 drains the cache line having the dirty state D to a memory component such as L2 data cache, main memory, etc., the cache line moves to the invalid state I. In case the data cache requests the cache line back, it moves to the invalid state I in the speculative cache buffer.
  • Speculative State S
  • Assuming the cache line is in the speculative state S, there are several possibilities for this cache line. If a commit operation is performed, the cache line moves to the dirty state D. If a rollback operation is performed, the cache line moves to the invalid state I. In case the data cache requests the cache line back, it moves to the invalid state I in the speculative cache buffer.
  • Commit-Kill State K
  • Assuming the cache line is in the commit-kill state K, there are several possibilities for this cache line. If a commit operation is performed, the cache line moves to the invalid state I. If a rollback operation is performed, the cache line moves to the dirty state D. If the speculative cache buffer 50 drains the cache line having the commit-kill state K to a memory component such as L2 data cache, main memory, etc., the cache line moves to the invalid state I.
  • The foregoing descriptions of specific embodiments have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed, and many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the disclosure be defined by the Claims appended hereto and their equivalents.

Claims (20)

1. A speculative cache buffer comprising:
a plurality of cache lines, wherein at least one of the cache lines is operable to receive an evicted cache line from a cache, wherein the at least one of the cache lines is operable to return the evicted cache line to the cache if the cache requests the evicted cache line, and wherein if data is stored in the cache lines, the data has been received from the cache; and
a plurality of state indicators operable to indicate a state of a corresponding cache line of the cache lines.
2. The speculative cache buffer of claim 1, wherein the evicted cache line includes speculatively modified data.
3. The speculative cache buffer of claim 1, wherein the evicted cache line includes dirty data.
4. The speculative cache buffer of claim 1, wherein the plurality of state indicators include an invalid state, a dirty state, and a speculative state.
5. The speculative cache buffer of claim 4, wherein the plurality of state indicators include a commit-kill state.
6. The speculative cache buffer of claim 5, wherein if the state indicator of a cache line is the commit-kill state, the state indicator is changed to the invalid state in response to a commit operation.
7. The speculative cache buffer of claim 5, wherein if the state indicator of a cache line is the commit-kill state, the state indicator is changed to the dirty state in response to a rollback operation.
8. The speculative cache buffer of claim 1, wherein if the state indicator of a cache line is a dirty state, the cache line is drained to a memory.
9. The speculative cache buffer of claim 8, wherein the state indicator is changed to an invalid state.
10. A method comprising:
speculatively modifying a cache line of a cache;
evicting the cache line from the cache to a speculative cache buffer, wherein if data is stored in cache lines of the speculative cache buffer, the data has been received from the cache; and
retrieving the cache line from the speculative cache buffer to the cache.
11. The method of claim 10, wherein said evicting comprises:
setting a state indicator of the cache line in the speculative cache buffer to a speculative state.
12. The method of claim 11, wherein in response to a rollback operation, setting the state indicator of the cache line in the speculative cache buffer to an invalid state.
13. The method of claim 11, wherein in response to a commit operation, setting the state indicator of the cache line in the speculative cache buffer to a dirty state.
14. The method of claim 10, wherein said retrieving comprises:
setting a state indicator of the cache line in the speculative cache buffer to an invalid state.
15. The method of claim 10, further comprising:
modifying a second cache line of the cache;
evicting the second cache line from the cache to the speculative cache buffer;
setting a state indicator of the second cache line in the speculative cache buffer to a commit-kill state;
in response to a rollback operation, setting the state indicator of the second cache line in the speculative cache buffer to a dirty state; and
in response to a commit operation, setting the state indicator of the second cache line in the speculative cache buffer to an invalid state.
16. A method comprising:
evicting a cache line from a cache to a speculative cache buffer, wherein the cache line includes dirty data;
if said evicting is initiated by a speculative store operation to the cache line, setting a state indicator of the cache line in the speculative cache buffer to a first state; and
if said evicting is initiated by a non-speculative store operation to the cache line, setting the state indicator of the cache line in the speculative cache buffer to a second state.
17. The method of claim 16, wherein the first state is a commit-kill state.
18. The method of claim 17, wherein in response to a rollback operation, setting the state indicator of the cache line in the speculative cache buffer to a dirty state.
19. The method of claim 17, wherein in response to a commit operation, setting the state indicator of the cache line in the speculative cache buffer to an invalid state.
20. The method of claim 16, wherein the second state is a dirty state.
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