US20150101856A1 - Eliminating poor reveal of through silicon vias - Google Patents
Eliminating poor reveal of through silicon vias Download PDFInfo
- Publication number
- US20150101856A1 US20150101856A1 US14/052,366 US201314052366A US2015101856A1 US 20150101856 A1 US20150101856 A1 US 20150101856A1 US 201314052366 A US201314052366 A US 201314052366A US 2015101856 A1 US2015101856 A1 US 2015101856A1
- Authority
- US
- United States
- Prior art keywords
- back side
- wafer
- silicon vias
- opening
- front side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F17/00—Multi-step processes for surface treatment of metallic material involving at least one process provided for in class C23 and at least one process covered by subclass C21D or C22F or class C25
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- Embodiments of the present invention relate generally to integrated circuit chips, and more specifically, to eliminating poor reveal of through silicon vias (TSVs).
- TSVs through silicon vias
- TSVs are generally vertical connections etched through a silicon wafer and filled with metal. With TSVs, two or more vertically stacked chips (or dies) can be joined by vertical interconnects running through the stack and functioning as components of an integrated circuit. Stacking chips in comparison to wire bonding, reduces inductive loses which increases speed of data exchange. Since TSVs have shorter interconnects between the dies, there will be reduced power consumption caused by long horizontal wiring. As a result, TSVs allow much higher input/output density than wire bonding, which consumes much more space.
- TSVs allow multiple integrated circuit chips to be stacked together, allowing greater amounts of information to be passed between the chips.
- integrated circuit chips and memory devices which typically reside side-by-side on a silicon wafer, can be stacked on top of another with the advent of the TSVs. Stacking the integrated circuit chips with the memory devices will dramatically reduce the size of the overall chip package and boost speeds at which data flows among the functions on the chip.
- a back side grind operation is typically performed on the back side of the wafer to reveal the TSVs.
- Poor reveal of the TSVs can arise due to the vias not being etched deep enough during their formation. That is, if the trenches of the TSVs are not etched deep enough during formation, then when the back side grind operation is performed on the wafer, the TSVs will not be revealed. Poor reveal of TSVs that are not etched enough are problematic because a vertical electrical connection will not be attained.
- the impact of poor reveal of the TSVs will depend on how much of the wafer has the poor reveal. Typically, poor reveal of TSVs will appear on the edge of the wafer and progress towards the center of the wafer. If the poor reveal is within a wafer pickable area, then the wafer may need to be scrapped.
- a method comprises: obtaining a wafer having a front side, a back side and a plurality of partially etched and metalized through silicon vias each extending from a portion of the front side through a portion of the back side, terminating before reaching an end surface of the back side; patterning and etching a region of the back side of the wafer to expose and reveal a portion of each of the plurality of through silicon vias; and depositing a metal layer on the back side of the wafer to form a back side metallization, the metal layer covering all of the back side including the etched region of the back side and the exposed portions of each of the plurality of through silicon vias.
- a method comprises: obtaining a wafer having a front side, a back side and a plurality of partially etched and metalized through silicon vias each extending from a portion of the front side through a portion of the back side, terminating before reaching an end surface of the back side; thinning the back side of the wafer to prevent exposure of the metalized through silicon vias at the wafer front side and exposure of a bottom surface of the metalized through silicon vias at the wafer front side; patterning and etching an opening in the back side of the wafer to expose and reveal a trench portion of each of the plurality of through silicon vias; and depositing a metal layer on the back side of the wafer to form a back side metallization, the metal layer extending along a surface of the back side including along the opening and the exposed trench portions of each of the plurality of through silicon vias.
- a structure in a third embodiment, comprises: a wafer having a front side, a back side and a plurality of partially etched and metalized through silicon vias each extending through the front side to the back side, the back side having an opening formed therein that reveals a portion of a trench associated with each of the plurality of through silicon vias; and a metal layer deposited on the back side of the wafer to form a back side metallization, the metal layer covering all of the back side including along the opening and the exposed portions of each trench associated with the plurality of through silicon vias.
- FIGS. 1-3 show a method of forming partial front side through silicon vias (TSVs) according to a first embodiment of the present invention
- FIGS. 4-6 show a method of forming partial front side through silicon vias (TSVs) according to a second embodiment of the present invention.
- FIGS. 1-3 show a method of forming partial front side through silicon vias (TSVs) according to a first embodiment of the present invention.
- the method of forming partial front side TSVs according to this embodiment begins at FIG. 1 by obtaining a wafer 100 optionally coupled to a wafer carrier 105 .
- Wafer 100 includes a wafer front side 110 , a wafer back side 115 and a plurality of partially etched and metalized TSVs 120 each extending from a portion of the front side through a portion of back side, terminating before reaching an end surface of the back side.
- wafer 100 with the partially etched and metalized TSVs 120 can be formed by photolithography, etching (e.g., reactive ion etch (RIE), inductive coupling of RF power etch (ICP)), metal or dielectric and metal deposition, and chemical-mechanical planarization (CMP).
- etching e.g., reactive ion etch (RIE), inductive coupling of RF power etch (ICP)
- ICP inductive coupling of RF power etch
- CMP chemical-mechanical planarization
- a region 125 of wafer back side 115 is lithographically patterned and etched 130 to expose a trench portion 127 of each of the plurality of TSVs 120 .
- the etching 130 of region 125 of back side 115 comprises etching an area of the back side that encompasses each of the plurality of TSVs 120 .
- Etching 130 region 125 of back side 115 can include applying a plasma etch, a RIE, an anisotropic wet etch, an ICP etch, or an electron cyclotron resonance (ECR) etch as known in the art.
- the patterned wafer back side 115 can be etched using xenon difluoride (XeF 2 ) gas.
- the wafer backside can be thinned using standard methods such as backside grind, etch, and/or chemical mechanical polish to a desired thickness which does not reach the bottom of the TSV's 120 before exposing the wafer back side to the patterning and etch step.
- the thinning of back side of the wafer can prevent exposure of the metalized through silicon vias at the wafer front side and exposure of a bottom surface of the metalized through silicon vias at the wafer front side.
- the starting wafer thickness can be approximately 725 microns; the wafer front side TSV's can be etched 80+/ ⁇ 2 microns into the wafer, the wafer back side can be thinned using a back side grind operation and CMP to a thickness of 90+/ ⁇ 4 microns; and the wafer back side post patterning etch depth can be 18+/ ⁇ 1 microns.
- the wafer backside lithographic patterning process used with etching 130 can be precisely aligned to features the wafer frontside TSV's and/or other structures, with a tight registration tolerance, such as +/ ⁇ 5 microns or less.
- the lithographic patterning of back side 115 of wafer 100 can include applying a mask such as a waffle mask pattern to the back side to obtain an opening 135 with no alignment of the waffle mask to features on the wafer front side such as the TSVs.
- the waffle mask would only be aligned to the wafer back side features, such as the wafer edge, notch, and/or flat. Since this embodiment does not require alignment to the wafer front side features, it is simpler to implement than the option requiring alignment.
- the waffle mask openings would be designed such that they open up all area inside the active chip that has wafer front side metalized TSV's and only the dicing channel regions would not be opened.
- the waffle mask would have a registration tolerance to wafer front side features on the order of +/ ⁇ 25 to +/ ⁇ 100 microns, and thusly the waffle mask openings would need to be about 25 to about 100 microns wider than the portions of the active chips which have wafer front side metalized TSV's.
- an almost full chip RIE or anisotropic etch can be used to obtain opening 135 . It is understood that for an RIE etch of a large opening, there will be no RIE lag which results in a faster etch rate.
- a benefit of using an anisotropic etch to form opening 135 is that it allows for wide, imprecise sidewall edges.
- the use of the mask and the etching results in revealed TSV s and the formation of rim structures 140 on back side 115 , which provides mechanical strength.
- a metal layer 145 is deposited on back side 115 of wafer 100 .
- Metal layer 145 can cover all of back side 115 including the etched region of the back side and the exposed trench portions 127 ( FIG. 2 ) of each of TSVs 120 .
- depositing metal layer 145 on back side 115 of wafer 100 can include depositing a deposit of titanium nitride (TiN) layer and a copper (Cu) seed followed by Cu electro plating.
- TiN titanium nitride
- Cu copper
- the front side of the TSVs can have dielectrics and multilevel metallization.
- a multilevel front side metallization can include aluminum (Al), Cu, etc.
- the multilevel front side metallization can include a hybrid multilevel metallization of Cu and Al wires.
- FIGS. 4-6 show a method of forming partial front side through silicon vias (TSVs) according to a second embodiment of the present invention.
- the method of forming partial front side TSVs according to this embodiment begins at FIG. 4 by obtaining a wafer 200 coupled to a wafer carrier 205 .
- Wafer 200 includes a wafer front side 210 , a wafer back side 215 and a plurality of partially etched TSVs 220 , each extending from a portion of the front side through a portion of back side, terminating before reaching an end surface of the back side.
- wafer 200 with the partially etched TSVs 220 can be formed in the same manner mentioned above for FIGS. 1-3 .
- regions 225 of back side 215 of wafer 200 are etched 230 to create openings 235 in the back side.
- Each opening 235 coincides with one of the plurality of TSVs 220 , wherein each opening extends beyond a width of the coinciding TSV, and each opening is separated from an adjacent opening by an unetched portion of back side 215 .
- a trench portion 227 of each of the plurality of TSVs 220 is exposed in a respective opening 235 .
- etching 230 of regions 225 of back side 215 can include applying a plasma etch, a RIE, an anisotropic wet etch, an ICP etch, or an ECR etch.
- etching 230 of regions 225 of back side 215 can include a localized backside RIE with regions 225 .
- each of openings 235 formed during the etching align with one of the TSVs 220 , encompassing each TSV by a predetermined amount.
- the use of the etching in this manner results in the formation of rim structures 240 on back side 215 of each of the chips on wafer 200 that encompasses the TSVs 220 .
- a metal layer 245 is deposited on back side 215 of wafer 200 .
- Metal layer 245 can cover all of back side 215 including the etched regions of the back side including openings 235 and the exposed trench portions of each of TSVs 220 .
- Deposition techniques described above with respect to FIGS. 1-3 can be used in this embodiment to deposit metal layer 245 on back side 215 of wafer 200 .
- the front side of the TSVs can have dielectrics and multilevel metallization.
- a multilevel front side metallization can include aluminum (Al), Cu, etc.
- the multilevel front side metallization can include a hybrid multilevel metallization of Cu and Al wires.
- Advantages of the partial front side TSVs that are formed according to FIGS. 1-6 include eliminating poor reveal TSVs since etching occurs at the both the front side and back side of the wafer, ensuring that the TSVs are completely etched through the wafer and revealed.
- the partial front side TSVs formed according to FIGS. 1-6 cause an increase in mechanical strength to the wafers in comparison to wafers that have TSVs formed according to conventional approaches because of the remaining rim.
- resolving poor reveal of TSVs will result in a wafer that is less susceptible to cracking
- Another improvement includes a thermal benefit to the wafer since there is better heat dissipation due to increased surface area.
- a further benefit includes a grounding advantage since the partial front side TSVs formed according to FIGS.
- FIGS. 1-6 enable the devices in the integrated circuit chips to be closer to ground, thereby having lower inductance. Still other benefits are that the partially-etched front side TSVs formed according to FIGS. 1-6 are shallower, allowing for wider vias that can be etched faster, easier and with more control.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
Abstract
Description
- Embodiments of the present invention relate generally to integrated circuit chips, and more specifically, to eliminating poor reveal of through silicon vias (TSVs).
- TSVs are generally vertical connections etched through a silicon wafer and filled with metal. With TSVs, two or more vertically stacked chips (or dies) can be joined by vertical interconnects running through the stack and functioning as components of an integrated circuit. Stacking chips in comparison to wire bonding, reduces inductive loses which increases speed of data exchange. Since TSVs have shorter interconnects between the dies, there will be reduced power consumption caused by long horizontal wiring. As a result, TSVs allow much higher input/output density than wire bonding, which consumes much more space.
- In this manner, TSVs allow multiple integrated circuit chips to be stacked together, allowing greater amounts of information to be passed between the chips. For example, integrated circuit chips and memory devices which typically reside side-by-side on a silicon wafer, can be stacked on top of another with the advent of the TSVs. Stacking the integrated circuit chips with the memory devices will dramatically reduce the size of the overall chip package and boost speeds at which data flows among the functions on the chip.
- After formation of TSVs in a silicon wafer, a back side grind operation is typically performed on the back side of the wafer to reveal the TSVs. Poor reveal of the TSVs can arise due to the vias not being etched deep enough during their formation. That is, if the trenches of the TSVs are not etched deep enough during formation, then when the back side grind operation is performed on the wafer, the TSVs will not be revealed. Poor reveal of TSVs that are not etched enough are problematic because a vertical electrical connection will not be attained. The impact of poor reveal of the TSVs will depend on how much of the wafer has the poor reveal. Typically, poor reveal of TSVs will appear on the edge of the wafer and progress towards the center of the wafer. If the poor reveal is within a wafer pickable area, then the wafer may need to be scrapped.
- In one embodiment, a method is provided. In this embodiment, the method comprises: obtaining a wafer having a front side, a back side and a plurality of partially etched and metalized through silicon vias each extending from a portion of the front side through a portion of the back side, terminating before reaching an end surface of the back side; patterning and etching a region of the back side of the wafer to expose and reveal a portion of each of the plurality of through silicon vias; and depositing a metal layer on the back side of the wafer to form a back side metallization, the metal layer covering all of the back side including the etched region of the back side and the exposed portions of each of the plurality of through silicon vias.
- In a second embodiment, a method is provided. In this embodiment, the method comprises: obtaining a wafer having a front side, a back side and a plurality of partially etched and metalized through silicon vias each extending from a portion of the front side through a portion of the back side, terminating before reaching an end surface of the back side; thinning the back side of the wafer to prevent exposure of the metalized through silicon vias at the wafer front side and exposure of a bottom surface of the metalized through silicon vias at the wafer front side; patterning and etching an opening in the back side of the wafer to expose and reveal a trench portion of each of the plurality of through silicon vias; and depositing a metal layer on the back side of the wafer to form a back side metallization, the metal layer extending along a surface of the back side including along the opening and the exposed trench portions of each of the plurality of through silicon vias.
- In a third embodiment, a structure is provided. In this embodiment, the structure comprises: a wafer having a front side, a back side and a plurality of partially etched and metalized through silicon vias each extending through the front side to the back side, the back side having an opening formed therein that reveals a portion of a trench associated with each of the plurality of through silicon vias; and a metal layer deposited on the back side of the wafer to form a back side metallization, the metal layer covering all of the back side including along the opening and the exposed portions of each trench associated with the plurality of through silicon vias.
-
FIGS. 1-3 show a method of forming partial front side through silicon vias (TSVs) according to a first embodiment of the present invention; and -
FIGS. 4-6 show a method of forming partial front side through silicon vias (TSVs) according to a second embodiment of the present invention. - Referring now to the figures,
FIGS. 1-3 show a method of forming partial front side through silicon vias (TSVs) according to a first embodiment of the present invention. The method of forming partial front side TSVs according to this embodiment begins atFIG. 1 by obtaining awafer 100 optionally coupled to awafer carrier 105.Wafer 100 includes awafer front side 110, awafer back side 115 and a plurality of partially etched and metalizedTSVs 120 each extending from a portion of the front side through a portion of back side, terminating before reaching an end surface of the back side. In one embodiment, wafer 100 with the partially etched and metalizedTSVs 120 can be formed by photolithography, etching (e.g., reactive ion etch (RIE), inductive coupling of RF power etch (ICP)), metal or dielectric and metal deposition, and chemical-mechanical planarization (CMP). - In
FIG. 2 , aregion 125 ofwafer back side 115 is lithographically patterned and etched 130 to expose atrench portion 127 of each of the plurality ofTSVs 120. In this embodiment, theetching 130 ofregion 125 ofback side 115 comprises etching an area of the back side that encompasses each of the plurality ofTSVs 120. Etching 130region 125 ofback side 115 can include applying a plasma etch, a RIE, an anisotropic wet etch, an ICP etch, or an electron cyclotron resonance (ECR) etch as known in the art. In one embodiment, the patterned wafer backside 115 can be etched using xenon difluoride (XeF2) gas. Optionally, the wafer backside can be thinned using standard methods such as backside grind, etch, and/or chemical mechanical polish to a desired thickness which does not reach the bottom of the TSV's 120 before exposing the wafer back side to the patterning and etch step. In this manner, the thinning of back side of the wafer can prevent exposure of the metalized through silicon vias at the wafer front side and exposure of a bottom surface of the metalized through silicon vias at the wafer front side. - In one embodiment, the starting wafer thickness can be approximately 725 microns; the wafer front side TSV's can be etched 80+/−2 microns into the wafer, the wafer back side can be thinned using a back side grind operation and CMP to a thickness of 90+/−4 microns; and the wafer back side post patterning etch depth can be 18+/−1 microns.
- In one embodiment, the wafer backside lithographic patterning process used with
etching 130 can be precisely aligned to features the wafer frontside TSV's and/or other structures, with a tight registration tolerance, such as +/−5 microns or less. - In one embodiment, the lithographic patterning of
back side 115 ofwafer 100 can include applying a mask such as a waffle mask pattern to the back side to obtain anopening 135 with no alignment of the waffle mask to features on the wafer front side such as the TSVs. For this embodiment, the waffle mask would only be aligned to the wafer back side features, such as the wafer edge, notch, and/or flat. Since this embodiment does not require alignment to the wafer front side features, it is simpler to implement than the option requiring alignment. For this embodiment, the waffle mask openings would be designed such that they open up all area inside the active chip that has wafer front side metalized TSV's and only the dicing channel regions would not be opened. The waffle mask would have a registration tolerance to wafer front side features on the order of +/−25 to +/−100 microns, and thusly the waffle mask openings would need to be about 25 to about 100 microns wider than the portions of the active chips which have wafer front side metalized TSV's. In one embodiment, an almost full chip RIE or anisotropic etch can be used to obtain opening 135. It is understood that for an RIE etch of a large opening, there will be no RIE lag which results in a faster etch rate. A benefit of using an anisotropic etch to formopening 135 is that it allows for wide, imprecise sidewall edges. The use of the mask and the etching results in revealed TSV s and the formation ofrim structures 140 onback side 115, which provides mechanical strength. - In
FIG. 3 , ametal layer 145 is deposited onback side 115 ofwafer 100.Metal layer 145 can cover all ofback side 115 including the etched region of the back side and the exposed trench portions 127 (FIG. 2 ) of each ofTSVs 120. In one embodiment, depositingmetal layer 145 onback side 115 ofwafer 100 can include depositing a deposit of titanium nitride (TiN) layer and a copper (Cu) seed followed by Cu electro plating. It is understood that the front side of the TSVs can have dielectrics and multilevel metallization. In one embodiment, a multilevel front side metallization can include aluminum (Al), Cu, etc. In another embodiment, the multilevel front side metallization can include a hybrid multilevel metallization of Cu and Al wires. -
FIGS. 4-6 show a method of forming partial front side through silicon vias (TSVs) according to a second embodiment of the present invention. The method of forming partial front side TSVs according to this embodiment begins atFIG. 4 by obtaining awafer 200 coupled to awafer carrier 205.Wafer 200 includes a waferfront side 210, a wafer backside 215 and a plurality of partially etchedTSVs 220, each extending from a portion of the front side through a portion of back side, terminating before reaching an end surface of the back side. In one embodiment, wafer 200 with the partially etchedTSVs 220 can be formed in the same manner mentioned above forFIGS. 1-3 . - In
FIG. 5 ,regions 225 ofback side 215 ofwafer 200 are etched 230 to createopenings 235 in the back side. Eachopening 235 coincides with one of the plurality ofTSVs 220, wherein each opening extends beyond a width of the coinciding TSV, and each opening is separated from an adjacent opening by an unetched portion ofback side 215. In this manner, atrench portion 227 of each of the plurality ofTSVs 220 is exposed in arespective opening 235. In this embodiment, like the one described with respect toFIGS. 1-3 , etching 230 ofregions 225 ofback side 215 can include applying a plasma etch, a RIE, an anisotropic wet etch, an ICP etch, or an ECR etch. - In one embodiment, etching 230 of
regions 225 ofback side 215 can include a localized backside RIE withregions 225. In this manner, each ofopenings 235 formed during the etching align with one of theTSVs 220, encompassing each TSV by a predetermined amount. The use of the etching in this manner results in the formation ofrim structures 240 onback side 215 of each of the chips onwafer 200 that encompasses theTSVs 220. - In
FIG. 6 , ametal layer 245 is deposited onback side 215 ofwafer 200.Metal layer 245 can cover all ofback side 215 including the etched regions of the backside including openings 235 and the exposed trench portions of each ofTSVs 220. Deposition techniques described above with respect toFIGS. 1-3 can be used in this embodiment to depositmetal layer 245 onback side 215 ofwafer 200. Note that the front side of the TSVs can have dielectrics and multilevel metallization. In one embodiment, a multilevel front side metallization can include aluminum (Al), Cu, etc. In another embodiment, the multilevel front side metallization can include a hybrid multilevel metallization of Cu and Al wires. - Advantages of the partial front side TSVs that are formed according to
FIGS. 1-6 include eliminating poor reveal TSVs since etching occurs at the both the front side and back side of the wafer, ensuring that the TSVs are completely etched through the wafer and revealed. In addition, the partial front side TSVs formed according toFIGS. 1-6 cause an increase in mechanical strength to the wafers in comparison to wafers that have TSVs formed according to conventional approaches because of the remaining rim. Thus, resolving poor reveal of TSVs will result in a wafer that is less susceptible to cracking Another improvement includes a thermal benefit to the wafer since there is better heat dissipation due to increased surface area. A further benefit includes a grounding advantage since the partial front side TSVs formed according toFIGS. 1-6 enable the devices in the integrated circuit chips to be closer to ground, thereby having lower inductance. Still other benefits are that the partially-etched front side TSVs formed according toFIGS. 1-6 are shallower, allowing for wider vias that can be etched faster, easier and with more control. - While the disclosure has been particularly shown and described in conjunction with a preferred embodiment thereof, it will be appreciated that variations and modifications will occur to those skilled in the art. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the disclosure.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/052,366 US9443764B2 (en) | 2013-10-11 | 2013-10-11 | Method of eliminating poor reveal of through silicon vias |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/052,366 US9443764B2 (en) | 2013-10-11 | 2013-10-11 | Method of eliminating poor reveal of through silicon vias |
Publications (2)
Publication Number | Publication Date |
---|---|
US20150101856A1 true US20150101856A1 (en) | 2015-04-16 |
US9443764B2 US9443764B2 (en) | 2016-09-13 |
Family
ID=52808695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/052,366 Expired - Fee Related US9443764B2 (en) | 2013-10-11 | 2013-10-11 | Method of eliminating poor reveal of through silicon vias |
Country Status (1)
Country | Link |
---|---|
US (1) | US9443764B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170202083A1 (en) * | 2016-01-08 | 2017-07-13 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board |
CN117253872A (en) * | 2023-11-15 | 2023-12-19 | 深圳市新凯来技术有限公司 | Interconnect structure and method for manufacturing interconnect structure |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100252934A1 (en) * | 2009-04-07 | 2010-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-Dimensional Semiconductor Architecture |
US8212331B1 (en) * | 2006-10-02 | 2012-07-03 | Newport Fab, Llc | Method for fabricating a backside through-wafer via in a processed wafer and related structure |
US20130168803A1 (en) * | 2011-09-16 | 2013-07-04 | Sionyx, Inc. | Semiconductor-On-Insulator Devices and Associated Methods |
US20130299969A1 (en) * | 2012-05-11 | 2013-11-14 | Samsung Electronics Co., Ltd. | Semiconductor package and method of manufacturing the semiconductor package |
US20140035109A1 (en) * | 2012-07-31 | 2014-02-06 | International Business Machines Corporation | Method and structure of forming backside through silicon via connections |
US20140275911A1 (en) * | 2013-03-13 | 2014-09-18 | Advanced Semiconductor Engineering, Inc. | Neural sensing device and method for making the same |
US20140327105A1 (en) * | 2013-05-06 | 2014-11-06 | Qualcomm Incorporated | Electrostatic discharge diode |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6800930B2 (en) * | 2002-07-31 | 2004-10-05 | Micron Technology, Inc. | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies |
US6897125B2 (en) | 2003-09-17 | 2005-05-24 | Intel Corporation | Methods of forming backside connections on a wafer stack |
US7199449B2 (en) | 2004-08-24 | 2007-04-03 | Micron Technology, Inc. | Wafer backside removal to complete through-holes and provide wafer singulation during the formation of a semiconductor device |
US7425499B2 (en) | 2004-08-24 | 2008-09-16 | Micron Technology, Inc. | Methods for forming interconnects in vias and microelectronic workpieces including such interconnects |
US8035198B2 (en) | 2008-08-08 | 2011-10-11 | International Business Machines Corporation | Through wafer via and method of making same |
US8384224B2 (en) | 2008-08-08 | 2013-02-26 | International Business Machines Corporation | Through wafer vias and method of making same |
US7935571B2 (en) | 2008-11-25 | 2011-05-03 | Freescale Semiconductor, Inc. | Through substrate vias for back-side interconnections on very thin semiconductor wafers |
US8263497B2 (en) | 2009-01-13 | 2012-09-11 | International Business Machines Corporation | High-yield method of exposing and contacting through-silicon vias |
US8062975B2 (en) | 2009-04-16 | 2011-11-22 | Freescale Semiconductor, Inc. | Through substrate vias |
US8349734B2 (en) * | 2010-04-07 | 2013-01-08 | GlobalFoundries, Inc. | Integrated circuits having backside test structures and methods for the fabrication thereof |
US8361828B1 (en) | 2011-08-31 | 2013-01-29 | Alta Devices, Inc. | Aligned frontside backside laser dicing of semiconductor films |
US20150048496A1 (en) * | 2013-08-13 | 2015-02-19 | Macrotech Technology Inc. | Fabrication process and structure to form bumps aligned on tsv on chip backside |
-
2013
- 2013-10-11 US US14/052,366 patent/US9443764B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8212331B1 (en) * | 2006-10-02 | 2012-07-03 | Newport Fab, Llc | Method for fabricating a backside through-wafer via in a processed wafer and related structure |
US20100252934A1 (en) * | 2009-04-07 | 2010-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-Dimensional Semiconductor Architecture |
US20130168803A1 (en) * | 2011-09-16 | 2013-07-04 | Sionyx, Inc. | Semiconductor-On-Insulator Devices and Associated Methods |
US20130299969A1 (en) * | 2012-05-11 | 2013-11-14 | Samsung Electronics Co., Ltd. | Semiconductor package and method of manufacturing the semiconductor package |
US20140035109A1 (en) * | 2012-07-31 | 2014-02-06 | International Business Machines Corporation | Method and structure of forming backside through silicon via connections |
US20140275911A1 (en) * | 2013-03-13 | 2014-09-18 | Advanced Semiconductor Engineering, Inc. | Neural sensing device and method for making the same |
US20140327105A1 (en) * | 2013-05-06 | 2014-11-06 | Qualcomm Incorporated | Electrostatic discharge diode |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170202083A1 (en) * | 2016-01-08 | 2017-07-13 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board |
US10477683B2 (en) * | 2016-01-08 | 2019-11-12 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board including sub-circuit board |
US10701806B2 (en) | 2016-01-08 | 2020-06-30 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board including sub-circuit board |
CN117253872A (en) * | 2023-11-15 | 2023-12-19 | 深圳市新凯来技术有限公司 | Interconnect structure and method for manufacturing interconnect structure |
Also Published As
Publication number | Publication date |
---|---|
US9443764B2 (en) | 2016-09-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6867073B1 (en) | Single mask via method and device | |
US8952506B2 (en) | Through silicon via structure | |
KR101137624B1 (en) | via structure and via etching process of forming the same | |
US8034713B2 (en) | Method for stacking and interconnecting integrated circuits | |
US20100065949A1 (en) | Stacked Semiconductor Chips with Through Substrate Vias | |
US10515892B2 (en) | TSV interconnect structure and manufacturing method thereof | |
US20080113505A1 (en) | Method of forming a through-substrate via | |
US20100072579A1 (en) | Through Substrate Conductors | |
SE1250228A1 (en) | Method of making close-packed via structures having in-planerouting | |
CN109712959B (en) | Monolithic integration of MEMS and IC devices | |
US9666507B2 (en) | Through-substrate structure and method for fabricating the same | |
CN214672598U (en) | Three-dimensional semiconductor device structure and three-dimensional semiconductor device | |
US7723821B2 (en) | Microelectronic assembly | |
US9443764B2 (en) | Method of eliminating poor reveal of through silicon vias | |
US8853073B2 (en) | Method for producing vias | |
CN103247569B (en) | Wear the preparation method and structure of silicon conducting body | |
US8753982B2 (en) | Method for producing a connection region on a side wall of a semiconductor body | |
TWI741270B (en) | Method of manufacturing semiconductor device | |
US20140291856A1 (en) | Tsv layout structure and tsv interconnect structure, and fabrication methods thereof | |
TW202404893A (en) | Mems device and method forming the same | |
AU2004286545B2 (en) | Single mask via method and device | |
TWI531027B (en) | Fabrication method and structure of through silicon via | |
CN117410256A (en) | TSV structure and forming method thereof | |
TW201332056A (en) | Through silicon via structure and method of fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MALING, JEFFREY C.;STAMPER, ANTHONY K.;TOPIC-BEGANOVIC, ZELJKA;AND OTHERS;SIGNING DATES FROM 20131007 TO 20131008;REEL/FRAME:031404/0758 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: ALSEPHINA INNOVATIONS INC., CANADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049669/0749 Effective date: 20181126 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20200913 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |