US20150091077A1 - Method of fabricating a non-volatile memory - Google Patents

Method of fabricating a non-volatile memory Download PDF

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US20150091077A1
US20150091077A1 US14/318,703 US201414318703A US2015091077A1 US 20150091077 A1 US20150091077 A1 US 20150091077A1 US 201414318703 A US201414318703 A US 201414318703A US 2015091077 A1 US2015091077 A1 US 2015091077A1
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layer
substrate
well
forming
gate
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Wein-Town Sun
Cheng-Yen Shen
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eMemory Technology Inc
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eMemory Technology Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
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    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
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    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
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    • G11C16/02—Erasable programmable read-only memories electrically programmable
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    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
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    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
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    • G11C2216/10—Floating gate memory cells with a single polysilicon layer

Definitions

  • the present invention relates to a non-volatile memory cell, and more specifically, to a non-volatile memory cell having a metal gate and a method of fabricating the non-volatile memory cell.
  • Non-volatile memory can store data in the absence of a power supply, therefore it is preferred to be used by various portable electronic products such as personal digital assistants (PDAs), mobile phones, and memory cards.
  • PDAs personal digital assistants
  • non-volatile memory technology must have compatibility with CMOS processing, low power consumption, high writing efficiency, low cost, and high density.
  • the gate oxide layer becomes accordingly thinner making stored data dissipate easily and causes a problem in the data storing ability. And as the gate length becomes smaller, the greater a problem the gate leakage power becomes.
  • a stacked gate memory cell may be used.
  • An embodiment of the present invention discloses a method of forming a memory cell.
  • the method comprises providing a substrate, forming a plurality of isolations on the substrate, forming a well on the substrate, forming a stacked layer comprising a tunneling layer and a charge trapping layer on the substrate, forming a high-k gate dielectric layer on the stacked layer, forming a poly silicon gate on the high-k gate dielectric layer, forming at least two source/drain doped regions on the well, removing the poly silicon gate, and depositing a metal to a removed area of the poly silicon gate to form a metal gate.
  • Another embodiment of the present invention discloses a method of forming a memory cell.
  • the method comprises providing a substrate, forming a plurality of isolations on the substrate, forming a well on the substrate, forming a high-k gate dielectric layer on the well, forming a poly silicon gate on the high-k gate dielectric layer, forming at least two source/drain doped regions on the well, removing the poly silicon gate, forming a stacked layer comprising a tunneling layer and a charge trapping layer and a charge stop layer on a removed area of the poly silicon gate, and depositing a metal to the removed area of the poly silicon gate to form a metal gate.
  • An additional embodiment of the present invention discloses a memory cell.
  • the memory cell comprises isolations formed on a substrate, a well formed directly on the substrate wherein the isolations define a region of the well, at least two source/drain doped regions formed on the well, a stacked layer comprising a tunneling layer and a charge trapping layer formed between the at least two source/drain doped regions on the well, a high-k gate dielectric layer formed on the stacked layer, and a metal gate formed on the high-k gate dielectric layer.
  • FIG. 1 illustrates a memory cell according to an embodiment of the present invention.
  • FIG. 2 illustrates a flowchart of a first method of fabricating the memory cell in FIG. 1 .
  • FIG. 3 illustrates a flowchart of a second method of fabricating the memory cell in FIG. 1 .
  • FIG. 4 illustrates the memory cell after performing Steps 202 to 205 in FIG. 2 .
  • FIG. 5 illustrates the memory cell after performing Steps 302 to 305 in FIG. 3 .
  • FIG. 6 illustrates the memory cell after performing Step 206 in FIG. 2 or Step 306 in FIG. 3 .
  • FIG. 7 illustrates the memory cell after performing Step 207 in FIG. 2 or Step 307 in FIG. 3 .
  • FIG. 8 illustrates the memory cell having spacers formed on the substrate in FIG. 4 .
  • FIG. 9 illustrates the memory cell after depositing the interlayer dielectric on the substrate in FIG. 4 .
  • FIG. 10 illustrates the memory cell after the interlayer dielectric in FIG. 9 is polished.
  • FIG. 11 illustrates the memory cell after performing Step 209 in FIG. 2 or Step 309 in FIG. 3 .
  • FIG. 12 illustrates a flowchart of a third method of fabricating the memory cell in FIG. 1 .
  • FIG. 13 illustrates a flowchart of a fourth method of fabricating the memory cell in FIG. 1 .
  • FIG. 14 illustrates a flowchart of a fifth method of fabricating the memory cell in FIG. 1 .
  • FIG. 15 illustrates a flowchart of a sixth method of fabricating the memory cell in FIG. 1 .
  • FIG. 1 illustrates a memory cell 100 according to an embodiment of the present invention.
  • the memory cell 100 comprises a substrate 110 , a well 120 , two source/drain doped regions 131 and 132 , a stacked layer 140 , and a metal gate 150 .
  • the memory cell 100 may be formed directly on the substrate 110 and the substrate 110 may be a p-type substrate.
  • the well 120 may be formed directly on the substrate 110 by implanting impurities on the substrate 110 .
  • the well may be an N-well.
  • the two source/drain doped regions 131 and 132 may be formed on the well 120 by implanting ions on the substrate 110 .
  • the two source/drain doped regions 131 and 132 may be p+ doped regions.
  • the stacked layer 140 may comprise a tunneling layer 141 , a charge trapping layer 142 and an optional charge stop layer 143 .
  • the tunneling layer 141 may be formed on the well 120 and placed between a first source/drain doped region 131 and a second source/drain doped region 132 .
  • the tunneling layer 141 may be a high-k dielectric layer.
  • the charge trapping layer 142 may be formed on the tunneling layer 141 .
  • the charge trapping layer 142 may be composed of silicon nitride or silicon oxynitride which is a charge trapping compound.
  • the optional charge stop layer 143 may be formed on the charge trapping layer 142 by depositing a high-k dielectric layer.
  • a high-k gate dielectric layer 40 may be formed on the stacked layer 140 .
  • the high-k gate dielectric layer may comprises Hafnium based dielectrics, Nitride Hafnium silicates, Zirconium based dielectrics, Titanium based dielectrics, and etc.
  • the metal gate 150 may be formed on the high-k gate dielectric layer 40 .
  • the metal gate 150 may comprise of tungsten, aluminum, titanium nitride, tantalum nitride, tantalum and/or copper.
  • the metal gate 150 may be formed by removing poly silicon gate and replacing the poly silicon gate with the metal gate 150 .
  • the memory cell 100 may further comprise two lightly doped regions 161 and 162 .
  • the two lightly doped regions 161 and 162 may be P-doped regions.
  • the first lightly doped region 161 may be formed on the well 120 in contact with the first source/drain doped region 131 and between the tunneling layer 141 and the first source/drain doped region 131 .
  • the second lightly doped region 162 may be formed on the well 120 in contact with the second source/drain doped region 132 and between the tunneling layer 141 and the second source/drain doped region 132 .
  • At least two spacers 171 and 172 may be formed on two sides of the stacked layer 140 and the metal gate 150 to protect the two lightly doped regions 161 and 162 when the two source/drain doped regions 131 and 132 are being formed.
  • At least two isolations 191 and 192 may be formed on the substrate 110 .
  • a region of the well 120 may be defined by the two isolations 191 and 192 .
  • FIG. 2 illustrates a flowchart of a method of fabricating the memory cell 100 in FIG. 1 .
  • the first method of fabrication may include but is not limited to the following steps:
  • Step 202 Form at least two isolations 191 and 192 on the substrate 110 ;
  • Step 203 Form the well 120 on the substrate 110 ;
  • Step 204 Form the stacked layer 140 comprising the tunneling layer 141 and the charge trapping layer 142 on the substrate 110 ;
  • Step 205 Form a high-k gate dielectric layer 40 as shown in FIG. 4 on the stacked layer 140 ;
  • Step 206 Form a poly silicon gate 51 as shown in FIG. 6 on the high-k gate dielectric layer 40 ;
  • Step 207 Form a plurality of lightly doped regions 161 and 162 on the well 120 ;
  • Step 208 Format least two source/drain doped regions 131 and 132 on the well 120 ;
  • Step 209 Remove the poly silicon gate 51 ;
  • Step 210 Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150 .
  • a layer of bottom dielectric compound and a layer of charge trapping compound may be deposited on the substrate 110 . Selected areas of the layer of bottom dielectric compound, and the layer of charge trapping compound may be etched to form the stacked layer 140 on the well 120 .
  • a layer of high-k gate dielectric compound may be deposited on the substrate 110 . Selected areas of the layer of high-k gate dielectric compound may be etched to form the high-k gate dielectric layer 40 on the stacked layer 140 .
  • a layer of poly silicon compound may be deposited on the substrate 110 .
  • Selected areas of the layer of poly silicon compound may be etched to form the poly silicon gate 51 on the high-k dielectric layer 40 , thereafter the stacked layer 140 and the high-k dielectric layer 40 out of the poly silicon gate 51 are etched as shown in FIG. 6 .
  • ions may be implanted on the well 120 to format least two lightly doped regions 161 and 162 on the well 120 .
  • At least two spacers 171 and 172 may be formed on at least two sides of the poly silicon gate 51 .
  • ions may be implanted on the well 120 to form at least two source/drain doped regions 131 and 132 on the well 120 .
  • Interlayer dielectric 80 may be deposited on the substrate 110 .
  • the interlayer dielectric 80 may be polished to a level same as the top of the poly silicon gate 51 .
  • the poly silicon gate 51 is then removed in step 209 , and a metal in place of the removed poly silicon gate 51 is deposited to form the metal gate 150 in step 210 .
  • FIG. 3 illustrates a flowchart of a second method of fabricating the memory cell 100 in FIG. 1 .
  • the first method of fabrication may include but is not limited to the following steps:
  • Step 302 Form at least two isolations 191 and 192 on the substrate 110 ;
  • Step 303 Form the well 120 on the substrate 110 ;
  • Step 304 Form the stacked layer 140 comprising the tunneling layer 141 , the charge trapping layer 142 , and the charge stop layer 143 on the substrate 110 ;
  • Step 305 Form a high-k gate dielectric layer 40 as shown in FIG. 5 on the stacked layer 140 ;
  • Step 306 Form the poly silicon gate 51 as shown in FIG. 6 on the high-k gate dielectric layer 40 ;
  • Step 307 Form a plurality of lightly doped regions 161 and 162 on the well 120 ;
  • Step 308 Form at least two source/drain doped regions 131 and 132 on the well 120 ;
  • Step 309 Remove the poly silicon gate 51 ;
  • Step 310 Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150 .
  • the layer of bottom dielectric compound, the layer of charge trapping compound, and a layer of top dielectric compound may be deposited on the substrate 110 . Selected areas of the layer of bottom dielectric compound, the layer of charge trapping compound and the top dielectric layer may be etched to form the stacked layer 140 on the well 120 .
  • a layer of high-k gate dielectric compound may be deposited on the substrate 110 . Selected areas of the layer of high-k gate dielectric compound may be etched to form the high-k gate dielectric layer 40 on the stacked layer 140 .
  • the layer of poly silicon compound may be deposited on the substrate 110 .
  • Selected areas of the layer of poly silicon compound may be etched to form the poly silicon gate 51 on the high-k dielectric layer 40 , thereafter the stacked layer 140 and the high-k dielectric layer 40 out of the poly silicon gate 51 are etched as shown in FIG. 6 .
  • ions may be implanted on the well 120 to form at least two lightly doped regions 161 and 162 on the well 120 .
  • At least two spacers 171 and 172 may be formed on at least two sides of the poly silicon gate 51 .
  • ions may be implanted on the well 120 to form at least two source/drain doped regions 131 and 132 on the well 120 .
  • Interlayer dielectric 80 may be deposited on the substrate 110 .
  • the interlayer dielectric 80 may be polished to a level same as the top of the poly silicon gate 51 .
  • the poly silicon gate 51 is then removed in step 309 , and a metal in place of the removed poly silicon gate 51 is deposited to form the metal gate 150 in step 310 .
  • FIG. 4 illustrates the memory cell 100 after performing Steps 202 to 205 in FIG. 2 .
  • the isolations 191 and 192 may be formed on the substrate 110 by depositing field oxide on selected areas of the substrate 110 where the isolations 191 and 192 are to be formed. Impurities may then be implanted to form the well 120 .
  • the well 120 may be isolated from other components being fabricated on the substrate 110 by using of the isolations 191 and 192 .
  • the step is followed by depositing a layer of bottom dielectric compound and a layer of charge trapping compound on the substrate 110 .
  • the layer of charge trapping compound is formed on the layer of bottom dielectric compound.
  • Selected areas of the layer of bottom dielectric compound and the layer of charge trapping compound may be etched from areas of the substrate 110 where the stacked layer 140 is not needed to be formed.
  • the layer of bottom dielectric compound that remained on the substrate 110 after etching may be the tunneling layer 141 .
  • the layer of charge trapping compound that remained on the substrate 110 after etching may be the charge trapping layer 142 .
  • the tunneling layer 141 may be formed on the substrate 110 .
  • the charge trapping layer 142 may be formed on the tunneling layer 141 .
  • the high-k gate dielectric layer 40 may be formed on the stacked layer 140 and etched to align with the stacked layer 140 and functioned as a charge stop layer.
  • FIG. 5 illustrates the memory cell 100 after performing Steps 302 to 305 in FIG. 3 .
  • the isolations 191 and 192 may be formed on the substrate 110 by depositing field oxide on selected areas of the substrate 110 where the isolations 191 and 192 are to be formed. Impurities may then be implanted to form the well 120 .
  • the well 120 may be isolated from other components being fabricated on the substrate 110 by using of the isolations 191 and 192 .
  • the step is followed by depositing a layer of bottom dielectric compound, a layer of charge trapping compound and a layer of top dielectric compound on the substrate 110 .
  • the layer of charge trapping compound is formed on the layer of bottom dielectric compound.
  • the layer of top dielectric compound may be formed on the layer of charge trapping compound.
  • Selected areas of the layer of bottom dielectric compound, the layer of charge trapping compound, and the layer of top dielectric compound may be etched from areas of the substrate 110 where the stacked layer 140 is not needed to be formed.
  • the layer of bottom dielectric compound that remained on the substrate 110 after etching may be the tunneling layer 141 .
  • the layer of charge trapping compound that remained on the substrate 110 after etching may be the charge trapping layer 142 .
  • the layer of top dielectric compound that remained on the substrate 110 after etching may be the charge stop layer 143 .
  • the tunneling layer 141 may be formed on the substrate 110 .
  • the charge trapping layer 142 may be formed on the tunneling layer 141 .
  • the charge stop layer 143 may be formed on the charge trapping layer 142 .
  • the high-k gate dielectric layer 40 may be formed on the stacked layer 140 and etched to merge with the charge stop layer 143 already formed.
  • FIG. 6 illustrates the memory cell 100 after performing Step 206 in FIG. 2 or Step 306 in FIG. 3 .
  • FIG. 7 illustrates the memory cell 100 after performing Step 207 in FIG. 2 or Step 307 in FIG. 3 .
  • the lightly doped regions 161 and 162 are formed on the substrate 110 .
  • the lightly doped regions 161 and 162 may be formed before forming the source/drain doped regions 131 and 132 .
  • the lightly doped regions 161 and 162 may be used to reduce the short channel effect of the memory cell 100 .
  • FIG. 8 illustrates the memory cell 100 having spacers 171 and 172 formed on the substrate 110 .
  • Spacer oxide is deposited on the surface of the substrate 110 and is in contact with sides of the poly silicon gate 51 and the stacked layer 140 . Selected areas of the spacer oxide is etched to form at least two spacers 171 and 172 on at least two sides of the poly silicon gate 51 and at least two sides of the stacked layer 140 .
  • the at least two sides of the poly silicon gate 51 and at least two sides of the stacked layer 140 may be the sides of the poly silicon gate 51 and the stacked layer 140 where the at least two source/drain doped regions 131 and 132 are to be formed.
  • Ions are implanted on the well 120 to form the at least two source/drain doped regions 131 and 132 on the well 120 .
  • the area of the well 120 where the at least two source/drain doped regions 131 and 132 are formed may be an area that is defined by the at least two spacers 171 and 172 and the isolations 191 and 192 .
  • the at least two spacers 171 and 172 may serve the purpose of protecting the lightly doped regions 161 and 162 that may be covered over when the source/drain doped regions 131 and 132 are being formed.
  • FIG. 9 illustrates the memory cell 100 after depositing the interlayer dielectric 80 on the substrate 110 .
  • FIG. 10 illustrates the memory cell 100 after the interlayer dielectric 80 is polished.
  • the interlayer dielectric 80 may be deposited on the substrate 110 covering the entire memory cell 100 .
  • the interlayer dielectric 80 may be polished until the top of the poly silicon gate 51 is reached making the interlayer dielectric 80 and the poly silicon gate 51 to be leveled and exposing the poly silicon gate 51 in preparation for the next step in the fabrication process.
  • FIG. 11 illustrates the memory cell 100 after performing Step 209 in FIG. 2 or Step 309 in FIG. 3 .
  • the poly silicon gate 51 may be removed from the substrate 110 but leaving the stacked layer 140 intact. Removal of the poly silicon gate 51 shall allow the deposition of the metal gate 150 in place of the poly silicon gate 51 .
  • the memory cell 100 having the metal gate 150 is illustrated in FIG. 1 .
  • a layer of photoresist may be deposited on the substrate 110 after the interlayer dielectric 80 is polished in FIG. 10 . Areas of the layer of photoresist where memory cells 100 formed with the metal gate 150 are etched while areas of the layer of photoresist where memory cells formed with the poly silicon gate 51 are left behind to protect the poly silicon gate 51 of memory cells that need not be removed.
  • FIGS. 12 to 15 illustrate other embodiments of the method of fabrication of the memory cell 100 .
  • the difference in sequence of the steps in fabricating will vary the characteristics of the memory cell 100 of which may include the conductivity or reliability of the components of the memory cell 100 .
  • FIG. 12 illustrates a flowchart of a third method of fabricating the memory cell 100 in FIG. 1 .
  • the third method of fabrication may include but is not limited to the following steps:
  • Step 1202 Form at least two isolations 191 and 192 on the substrate 110 ;
  • Step 1203 Form the stacked layer 140 comprising the tunneling layer 141 and the charge trapping layer 142 on the substrate 110 ;
  • Step 1204 Form the well 120 on the substrate 110 ;
  • Step 1205 Form the high-k gate dielectric layer 40 as shown in FIG. 4 on the stacked layer 140 ;
  • Step 1206 Form the poly silicon gate 51 on the high-k gate dielectric layer 40 ;
  • Step 1207 Form a plurality of lightly doped regions 161 and 162 on the well 120 ;
  • Step 1208 Format least two source/drain doped regions 131 and 132 on the well 120 ;
  • Step 1209 Remove the poly silicon gate 51 ;
  • Step 1210 Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150 .
  • FIG. 13 illustrates a flowchart of a fourth method of fabricating the memory cell 100 in FIG. 1 .
  • the fourth method of fabrication may include but is not limited to the following steps:
  • Step 1302 Form at least two isolations 191 and 192 on the substrate 110 ;
  • Step 1303 Form the stacked layer 140 comprising the tunneling layer 141 , the charge trapping layer 142 , and the charge stop layer 143 on the substrate 110 ;
  • Step 1304 Form the well 120 on the substrate 110 ;
  • Step 1305 Form the high-k gate dielectric layer 40 as shown in FIG. 5 on the stacked layer 140 ;
  • Step 1306 Form the poly silicon gate 51 on the high-k gate dielectric layer 40 ;
  • Step 1307 Form a plurality of lightly doped regions 161 and 162 on the well 120 ;
  • Step 1308 Form at least two source/drain doped regions 131 and 132 on the well 120 ;
  • Step 1309 Remove the poly silicon gate 51 ;
  • Step 1310 Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150 .
  • FIG. 14 illustrates a flowchart of a fifth method of fabricating the memory cell 100 in FIG. 1 .
  • the fifth method of fabrication may include but is not limited to the following steps:
  • Step 1402 Form the stacked layer 140 comprising the tunneling layer 141 , the charge trapping layer 142 , and the charge stop layer 143 on the substrate 110 ;
  • Step 1403 Form at least two isolations 191 and 192 on the substrate 110 ;
  • Step 1404 Form the well 120 on the substrate 110 ;
  • Step 1405 Form the high-k gate dielectric layer 40 as shown in FIG. 5 on the stacked layer 140 ;
  • Step 1406 Form the poly silicon gate 51 on the high-k gate dielectric layer 40 ;
  • Step 1407 Form a plurality of lightly doped regions 161 and 162 on the well 120 ;
  • Step 1408 Form at least two source/drain doped regions 131 and 132 on the well 120 ;
  • Step 1409 Remove the poly silicon gate 51 ;
  • Step 1410 Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150 .
  • the stacked layer 140 is formed before forming the well 120 . Changing the sequence of when to form the well 120 will affect the final characteristic of the well 120 . Since the well 120 is formed after the stacked layer 140 , the final characteristics of the well 120 will be closer to the intended characteristics as the forming of the stacked layer 140 shall not affect the well 120 .
  • FIG. 15 illustrates a flowchart of a sixth method of fabricating the memory cell 100 in FIG. 1 .
  • the sixth method of fabrication may include but is not limited to the following steps:
  • Step 1502 Form the at least two isolations 191 and 192 on the substrate 110 ;
  • Step 1503 Form the well 120 on the substrate 110 ;
  • Step 1504 Form the high-k gate dielectric layer 40 on the substrate 110 ;
  • Step 1505 Form the poly silicon gate 51 on the high-k gate dielectric layer 40 ;
  • Step 1506 Form a plurality of lightly doped regions 161 and 162 on the well 120 ;
  • Step 1507 Format least two source/drain doped regions 131 and 132 on the well 120 ;
  • Step 1508 Remove the poly silicon gate 51 ;
  • Step 1509 Form the stacked layer 140 comprising the tunneling layer 141 , the charge trapping layer 142 , and the charge stop layer 143 on the substrate 110 ;
  • Step 1510 Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150 .
  • the stacked layer 140 and the metal gate 150 may be formed after the poly silicon gate 51 has been removed. After the poly silicon gate 51 has been removed, a hole between the spacers 171 and 172 may be left behind.
  • a bottom dielectric compound may be first deposited to the hole to form the tunneling layer 141 .
  • a charge trapping compound may then be deposited to the hole to form the charge trapping layer 142 on the tunneling layer 141 .
  • a top dielectric compound may be deposited to the hole to form the charge stop layer 143 on the charge trapping layer 142 .
  • Metal is then deposited on top of the charge trapping layer 142 to form the metal gate 150 .
  • the high-k gate dielectric layer 40 formed under the poly silicon gate 51 may be etched together with the poly silicon gate 51 or left behind to merge with the deposited bottom dielectric compound to form the tunneling layer 141 . Since the stacked layer 140 is formed in the latter part of the fabrication, other components of the memory cell 100 formed before the forming of the stacked layer 140 will not affect to the characteristic variation of the stacked layer 140 .
  • the bottom dielectric compound may not be deposited. Instead, the charge trapping compound may be deposited to the hole to form the charge trapping layer 142 on the high-k gate dielectric layer 40 .
  • a top dielectric compound may be deposited to the hole to form the charge stop layer 143 on the charge trapping layer 142 .
  • Metal is then deposited on top of the charge trapping layer 142 to form the metal gate 150 .
  • the sequence of each of the flowcharts is just some embodiments of the method of the present invention. It is used to illustrate aspects of the present invention and is not intended to limit the scope of the invention. For example, the sequence of forming lightly doped regions and source/drain doped regions may be interchanged such that the source/drain doped regions are formed before forming the lightly doped regions.
  • the present invention discloses a memory cell with a metal gate and methods of fabricating the memory cell using a replacement metal gate fabrication technology.
  • the memory cell is directly formed on a substrate.
  • the substrate may be a silicon wafer.
  • the use of lightly doped regions reduces the short channel effect on the non-volatile memory cell.
  • the methods of fabricating the memory cell may differ in the sequence each step is performed.
  • the latter components of the memory cell formed may present a closer characteristic to the targeted characteristic of the component since the latter components formed shall not be affected by forming of components formed before the latter components are formed.
  • the use of metal gate shall reduce the problems such as random parasitic resistance or capacitance or missing device gates from random voids or missing metal that is usually found in conventional memory cells using poly silicon gates.
  • standby power is reduced due to the reduction of gate leakage.

Abstract

A structure of a memory cell includes a substrate, a well, two source/drain doped regions, a stacked layer and a metal gate. The stacked layer includes a tunneling layer, and a charge trapping layer. A method of fabricating the memory cell may vary with the change in sequence of performing steps. The difference in sequence of fabrication may yield different characteristic variations for the formed components of the memory cell.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This non-provisional application claims priority of US provisional application U.S. 61/883,205 filed on Sep. 27, 2013.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a non-volatile memory cell, and more specifically, to a non-volatile memory cell having a metal gate and a method of fabricating the non-volatile memory cell.
  • 2. Description of the Prior Art
  • Non-volatile memory can store data in the absence of a power supply, therefore it is preferred to be used by various portable electronic products such as personal digital assistants (PDAs), mobile phones, and memory cards. In order to respond to the requirements of the market, non-volatile memory technology must have compatibility with CMOS processing, low power consumption, high writing efficiency, low cost, and high density. However, as non-volatile memory becomes smaller in size, the gate oxide layer becomes accordingly thinner making stored data dissipate easily and causes a problem in the data storing ability. And as the gate length becomes smaller, the greater a problem the gate leakage power becomes. A stacked gate memory cell may be used.
  • In fabricating a stacked gate memory cell using an advance replacement metal gate process, problems may be encountered with regard to fitting the fabrication process of the stacked gate memory cell into the advance replacement metal gate process. Therefore, there is a need for a change in the replacement metal gate process to fit the fabrication process of the stacked gate memory cell.
    • SUMMARY OF THE INVENTION
  • An embodiment of the present invention discloses a method of forming a memory cell. The method comprises providing a substrate, forming a plurality of isolations on the substrate, forming a well on the substrate, forming a stacked layer comprising a tunneling layer and a charge trapping layer on the substrate, forming a high-k gate dielectric layer on the stacked layer, forming a poly silicon gate on the high-k gate dielectric layer, forming at least two source/drain doped regions on the well, removing the poly silicon gate, and depositing a metal to a removed area of the poly silicon gate to form a metal gate.
  • Another embodiment of the present invention discloses a method of forming a memory cell. The method comprises providing a substrate, forming a plurality of isolations on the substrate, forming a well on the substrate, forming a high-k gate dielectric layer on the well, forming a poly silicon gate on the high-k gate dielectric layer, forming at least two source/drain doped regions on the well, removing the poly silicon gate, forming a stacked layer comprising a tunneling layer and a charge trapping layer and a charge stop layer on a removed area of the poly silicon gate, and depositing a metal to the removed area of the poly silicon gate to form a metal gate.
  • An additional embodiment of the present invention discloses a memory cell. The memory cell comprises isolations formed on a substrate, a well formed directly on the substrate wherein the isolations define a region of the well, at least two source/drain doped regions formed on the well, a stacked layer comprising a tunneling layer and a charge trapping layer formed between the at least two source/drain doped regions on the well, a high-k gate dielectric layer formed on the stacked layer, and a metal gate formed on the high-k gate dielectric layer.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates a memory cell according to an embodiment of the present invention.
  • FIG. 2 illustrates a flowchart of a first method of fabricating the memory cell in FIG. 1.
  • FIG. 3 illustrates a flowchart of a second method of fabricating the memory cell in FIG. 1.
  • FIG. 4 illustrates the memory cell after performing Steps 202 to 205 in FIG. 2.
  • FIG. 5 illustrates the memory cell after performing Steps 302 to 305 in FIG. 3.
  • FIG. 6 illustrates the memory cell after performing Step 206 in FIG. 2 or Step 306 in FIG. 3.
  • FIG. 7 illustrates the memory cell after performing Step 207 in FIG. 2 or Step 307 in FIG. 3.
  • FIG. 8 illustrates the memory cell having spacers formed on the substrate in FIG. 4.
  • FIG. 9 illustrates the memory cell after depositing the interlayer dielectric on the substrate in FIG. 4.
  • FIG. 10 illustrates the memory cell after the interlayer dielectric in FIG. 9 is polished.
  • FIG. 11 illustrates the memory cell after performing Step 209 in FIG. 2 or Step 309 in FIG. 3.
  • FIG. 12 illustrates a flowchart of a third method of fabricating the memory cell in FIG. 1.
  • FIG. 13 illustrates a flowchart of a fourth method of fabricating the memory cell in FIG. 1.
  • FIG. 14 illustrates a flowchart of a fifth method of fabricating the memory cell in FIG. 1.
  • FIG. 15 illustrates a flowchart of a sixth method of fabricating the memory cell in FIG. 1.
    •  DETAILED DESCRIPTION
  • FIG. 1 illustrates a memory cell 100 according to an embodiment of the present invention. The memory cell 100 comprises a substrate 110, a well 120, two source/drain doped regions 131 and 132, a stacked layer 140, and a metal gate 150. The memory cell 100 may be formed directly on the substrate 110 and the substrate 110 may be a p-type substrate. The well 120 may be formed directly on the substrate 110 by implanting impurities on the substrate 110. The well may be an N-well. The two source/drain doped regions 131 and 132 may be formed on the well 120 by implanting ions on the substrate 110. The two source/drain doped regions 131 and 132 may be p+ doped regions. The stacked layer 140 may comprise a tunneling layer 141, a charge trapping layer 142 and an optional charge stop layer 143. The tunneling layer 141 may be formed on the well 120 and placed between a first source/drain doped region 131 and a second source/drain doped region 132. The tunneling layer 141 may be a high-k dielectric layer. The charge trapping layer 142 may be formed on the tunneling layer 141. The charge trapping layer 142 may be composed of silicon nitride or silicon oxynitride which is a charge trapping compound. The optional charge stop layer 143 may be formed on the charge trapping layer 142 by depositing a high-k dielectric layer. A high-k gate dielectric layer 40 may be formed on the stacked layer 140. The high-k gate dielectric layer may comprises Hafnium based dielectrics, Nitride Hafnium silicates, Zirconium based dielectrics, Titanium based dielectrics, and etc. The metal gate 150 may be formed on the high-k gate dielectric layer 40. The metal gate 150 may comprise of tungsten, aluminum, titanium nitride, tantalum nitride, tantalum and/or copper. The metal gate 150 may be formed by removing poly silicon gate and replacing the poly silicon gate with the metal gate 150.
  • In addition, the memory cell 100 may further comprise two lightly doped regions 161 and 162. The two lightly doped regions 161 and 162 may be P-doped regions. The first lightly doped region 161 may be formed on the well 120 in contact with the first source/drain doped region 131 and between the tunneling layer 141 and the first source/drain doped region 131. The second lightly doped region 162 may be formed on the well 120 in contact with the second source/drain doped region 132 and between the tunneling layer 141 and the second source/drain doped region 132. At least two spacers 171 and 172 may be formed on two sides of the stacked layer 140 and the metal gate 150 to protect the two lightly doped regions 161 and 162 when the two source/drain doped regions 131 and 132 are being formed.
  • To separate the memory cell 100 from other components built on the substrate 110 at least two isolations 191 and 192 may be formed on the substrate 110. A region of the well 120 may be defined by the two isolations 191 and 192.
  • FIG. 2 illustrates a flowchart of a method of fabricating the memory cell 100 in FIG. 1. The first method of fabrication may include but is not limited to the following steps:
  • Step 202: Form at least two isolations 191 and 192 on the substrate 110;
  • Step 203: Form the well 120 on the substrate 110;
  • Step 204: Form the stacked layer 140 comprising the tunneling layer 141 and the charge trapping layer 142 on the substrate 110;
  • Step 205: Form a high-k gate dielectric layer 40 as shown in FIG. 4 on the stacked layer 140;
  • Step 206: Form a poly silicon gate 51 as shown in FIG. 6 on the high-k gate dielectric layer 40;
  • Step 207: Form a plurality of lightly doped regions 161 and 162 on the well 120;
  • Step 208: Format least two source/drain doped regions 131 and 132 on the well 120;
  • Step 209: Remove the poly silicon gate 51;
  • Step 210: Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150.
  • In step 204, a layer of bottom dielectric compound and a layer of charge trapping compound may be deposited on the substrate 110. Selected areas of the layer of bottom dielectric compound, and the layer of charge trapping compound may be etched to form the stacked layer 140 on the well 120. In step 205, a layer of high-k gate dielectric compound may be deposited on the substrate 110. Selected areas of the layer of high-k gate dielectric compound may be etched to form the high-k gate dielectric layer 40 on the stacked layer 140. In step 206, a layer of poly silicon compound may be deposited on the substrate 110. Selected areas of the layer of poly silicon compound may be etched to form the poly silicon gate 51 on the high-k dielectric layer 40, thereafter the stacked layer 140 and the high-k dielectric layer 40 out of the poly silicon gate 51 are etched as shown in FIG. 6. In step 207, ions may be implanted on the well 120 to format least two lightly doped regions 161 and 162 on the well 120. At least two spacers 171 and 172 may be formed on at least two sides of the poly silicon gate 51. In step 208, ions may be implanted on the well 120 to form at least two source/drain doped regions 131 and 132 on the well 120. Interlayer dielectric 80 may be deposited on the substrate 110. The interlayer dielectric 80 may be polished to a level same as the top of the poly silicon gate 51. The poly silicon gate 51 is then removed in step 209, and a metal in place of the removed poly silicon gate 51 is deposited to form the metal gate 150 in step 210.
  • FIG. 3 illustrates a flowchart of a second method of fabricating the memory cell 100 in FIG. 1. The first method of fabrication may include but is not limited to the following steps:
  • Step 302: Form at least two isolations 191 and 192 on the substrate 110;
  • Step 303: Form the well 120 on the substrate 110;
  • Step 304: Form the stacked layer 140 comprising the tunneling layer 141, the charge trapping layer 142, and the charge stop layer 143 on the substrate 110;
  • Step 305: Form a high-k gate dielectric layer 40 as shown in FIG. 5 on the stacked layer 140;
  • Step 306: Form the poly silicon gate 51 as shown in FIG. 6 on the high-k gate dielectric layer 40;
  • Step 307: Form a plurality of lightly doped regions 161 and 162 on the well 120;
  • Step 308: Form at least two source/drain doped regions 131 and 132 on the well 120;
  • Step 309: Remove the poly silicon gate 51;
  • Step 310: Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150.
  • In step 304, the layer of bottom dielectric compound, the layer of charge trapping compound, and a layer of top dielectric compound may be deposited on the substrate 110. Selected areas of the layer of bottom dielectric compound, the layer of charge trapping compound and the top dielectric layer may be etched to form the stacked layer 140 on the well 120. In step 305, a layer of high-k gate dielectric compound may be deposited on the substrate 110. Selected areas of the layer of high-k gate dielectric compound may be etched to form the high-k gate dielectric layer 40 on the stacked layer 140. In step 306, the layer of poly silicon compound may be deposited on the substrate 110. Selected areas of the layer of poly silicon compound may be etched to form the poly silicon gate 51 on the high-k dielectric layer 40, thereafter the stacked layer 140 and the high-k dielectric layer 40 out of the poly silicon gate 51 are etched as shown in FIG. 6. In step 307, ions may be implanted on the well 120 to form at least two lightly doped regions 161 and 162 on the well 120. At least two spacers 171 and 172 may be formed on at least two sides of the poly silicon gate 51. In step 308, ions may be implanted on the well 120 to form at least two source/drain doped regions 131 and 132 on the well 120. Interlayer dielectric 80 may be deposited on the substrate 110. The interlayer dielectric 80 may be polished to a level same as the top of the poly silicon gate 51. The poly silicon gate 51 is then removed in step 309, and a metal in place of the removed poly silicon gate 51 is deposited to form the metal gate 150 in step 310.
  • FIG. 4 illustrates the memory cell 100 after performing Steps 202 to 205 in FIG. 2. The isolations 191 and 192 may be formed on the substrate 110 by depositing field oxide on selected areas of the substrate 110 where the isolations 191 and 192 are to be formed. Impurities may then be implanted to form the well 120. The well 120 may be isolated from other components being fabricated on the substrate 110 by using of the isolations 191 and 192. The step is followed by depositing a layer of bottom dielectric compound and a layer of charge trapping compound on the substrate 110. The layer of charge trapping compound is formed on the layer of bottom dielectric compound.
  • Selected areas of the layer of bottom dielectric compound and the layer of charge trapping compound may be etched from areas of the substrate 110 where the stacked layer 140 is not needed to be formed. The layer of bottom dielectric compound that remained on the substrate 110 after etching may be the tunneling layer 141. The layer of charge trapping compound that remained on the substrate 110 after etching may be the charge trapping layer 142. The tunneling layer 141 may be formed on the substrate 110. The charge trapping layer 142 may be formed on the tunneling layer 141. The high-k gate dielectric layer 40 may be formed on the stacked layer 140 and etched to align with the stacked layer 140 and functioned as a charge stop layer.
  • FIG. 5 illustrates the memory cell 100 after performing Steps 302 to 305 in FIG. 3. The isolations 191 and 192 may be formed on the substrate 110 by depositing field oxide on selected areas of the substrate 110 where the isolations 191 and 192 are to be formed. Impurities may then be implanted to form the well 120. The well 120 may be isolated from other components being fabricated on the substrate 110 by using of the isolations 191 and 192. The step is followed by depositing a layer of bottom dielectric compound, a layer of charge trapping compound and a layer of top dielectric compound on the substrate 110. The layer of charge trapping compound is formed on the layer of bottom dielectric compound. The layer of top dielectric compound may be formed on the layer of charge trapping compound.
  • Selected areas of the layer of bottom dielectric compound, the layer of charge trapping compound, and the layer of top dielectric compound may be etched from areas of the substrate 110 where the stacked layer 140 is not needed to be formed.
  • The layer of bottom dielectric compound that remained on the substrate 110 after etching may be the tunneling layer 141. The layer of charge trapping compound that remained on the substrate 110 after etching may be the charge trapping layer 142. The layer of top dielectric compound that remained on the substrate 110 after etching may be the charge stop layer 143. The tunneling layer 141 may be formed on the substrate 110. The charge trapping layer 142 may be formed on the tunneling layer 141. And the charge stop layer 143 may be formed on the charge trapping layer 142. The high-k gate dielectric layer 40 may be formed on the stacked layer 140 and etched to merge with the charge stop layer 143 already formed.
  • FIG. 6 illustrates the memory cell 100 after performing Step 206 in FIG. 2 or Step 306 in FIG. 3. FIG. 7 illustrates the memory cell 100 after performing Step 207 in FIG. 2 or Step 307 in FIG. 3. The lightly doped regions 161 and 162 are formed on the substrate 110. The lightly doped regions 161 and 162 may be formed before forming the source/drain doped regions 131 and 132. The lightly doped regions 161 and 162 may be used to reduce the short channel effect of the memory cell 100.
  • FIG. 8 illustrates the memory cell 100 having spacers 171 and 172 formed on the substrate 110. Spacer oxide is deposited on the surface of the substrate 110 and is in contact with sides of the poly silicon gate 51 and the stacked layer 140. Selected areas of the spacer oxide is etched to form at least two spacers 171 and 172 on at least two sides of the poly silicon gate 51 and at least two sides of the stacked layer 140. The at least two sides of the poly silicon gate 51 and at least two sides of the stacked layer 140 may be the sides of the poly silicon gate 51 and the stacked layer 140 where the at least two source/drain doped regions 131 and 132 are to be formed. Ions are implanted on the well 120 to form the at least two source/drain doped regions 131 and 132 on the well 120. The area of the well 120 where the at least two source/drain doped regions 131 and 132 are formed may be an area that is defined by the at least two spacers 171 and 172 and the isolations 191 and 192. The at least two spacers 171 and 172 may serve the purpose of protecting the lightly doped regions 161 and 162 that may be covered over when the source/drain doped regions 131 and 132 are being formed.
  • FIG. 9 illustrates the memory cell 100 after depositing the interlayer dielectric 80 on the substrate 110. FIG. 10 illustrates the memory cell 100 after the interlayer dielectric 80 is polished. The interlayer dielectric 80 may be deposited on the substrate 110 covering the entire memory cell 100. The interlayer dielectric 80 may be polished until the top of the poly silicon gate 51 is reached making the interlayer dielectric 80 and the poly silicon gate 51 to be leveled and exposing the poly silicon gate 51 in preparation for the next step in the fabrication process.
  • FIG. 11 illustrates the memory cell 100 after performing Step 209 in FIG. 2 or Step 309 in FIG. 3. The poly silicon gate 51 may be removed from the substrate 110 but leaving the stacked layer 140 intact. Removal of the poly silicon gate 51 shall allow the deposition of the metal gate 150 in place of the poly silicon gate 51. The memory cell 100 having the metal gate 150 is illustrated in FIG. 1.
  • In another embodiment, a layer of photoresist may be deposited on the substrate 110 after the interlayer dielectric 80 is polished in FIG. 10. Areas of the layer of photoresist where memory cells 100 formed with the metal gate 150 are etched while areas of the layer of photoresist where memory cells formed with the poly silicon gate 51 are left behind to protect the poly silicon gate 51 of memory cells that need not be removed.
  • FIGS. 12 to 15 illustrate other embodiments of the method of fabrication of the memory cell 100. The difference in sequence of the steps in fabricating will vary the characteristics of the memory cell 100 of which may include the conductivity or reliability of the components of the memory cell 100.
  • FIG. 12 illustrates a flowchart of a third method of fabricating the memory cell 100 in FIG. 1. The third method of fabrication may include but is not limited to the following steps:
  • Step 1202: Form at least two isolations 191 and 192 on the substrate 110;
  • Step 1203: Form the stacked layer 140 comprising the tunneling layer 141 and the charge trapping layer 142 on the substrate 110;
  • Step 1204: Form the well 120 on the substrate 110;
  • Step 1205: Form the high-k gate dielectric layer 40 as shown in FIG. 4 on the stacked layer 140;
  • Step 1206: Form the poly silicon gate 51 on the high-k gate dielectric layer 40;
  • Step 1207: Form a plurality of lightly doped regions 161 and 162 on the well 120;
  • Step 1208: Format least two source/drain doped regions 131 and 132 on the well 120;
  • Step 1209: Remove the poly silicon gate 51;
  • Step 1210: Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150.
  • FIG. 13 illustrates a flowchart of a fourth method of fabricating the memory cell 100 in FIG. 1. The fourth method of fabrication may include but is not limited to the following steps:
  • Step 1302: Form at least two isolations 191 and 192 on the substrate 110;
  • Step 1303: Form the stacked layer 140 comprising the tunneling layer 141, the charge trapping layer 142, and the charge stop layer 143 on the substrate 110;
  • Step 1304: Form the well 120 on the substrate 110;
  • Step 1305: Form the high-k gate dielectric layer 40 as shown in FIG. 5 on the stacked layer 140;
  • Step 1306: Form the poly silicon gate 51 on the high-k gate dielectric layer 40;
  • Step 1307: Form a plurality of lightly doped regions 161 and 162 on the well 120;
  • Step 1308: Form at least two source/drain doped regions 131 and 132 on the well 120;
  • Step 1309: Remove the poly silicon gate 51;
  • Step 1310: Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150.
  • FIG. 14 illustrates a flowchart of a fifth method of fabricating the memory cell 100 in FIG. 1. The fifth method of fabrication may include but is not limited to the following steps:
  • Step 1402: Form the stacked layer 140 comprising the tunneling layer 141, the charge trapping layer 142, and the charge stop layer 143 on the substrate 110;
  • Step 1403: Form at least two isolations 191 and 192 on the substrate 110;
  • Step 1404: Form the well 120 on the substrate 110;
  • Step 1405: Form the high-k gate dielectric layer 40 as shown in FIG. 5 on the stacked layer 140;
  • Step 1406: Form the poly silicon gate 51 on the high-k gate dielectric layer 40;
  • Step 1407: Form a plurality of lightly doped regions 161 and 162 on the well 120;
  • Step 1408: Form at least two source/drain doped regions 131 and 132 on the well 120;
  • Step 1409: Remove the poly silicon gate 51;
  • Step 1410: Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150.
  • For the methods in FIGS. 12 and 14, the stacked layer 140 is formed before forming the well 120. Changing the sequence of when to form the well 120 will affect the final characteristic of the well 120. Since the well 120 is formed after the stacked layer 140, the final characteristics of the well 120 will be closer to the intended characteristics as the forming of the stacked layer 140 shall not affect the well 120.
  • FIG. 15 illustrates a flowchart of a sixth method of fabricating the memory cell 100 in FIG. 1. The sixth method of fabrication may include but is not limited to the following steps:
  • Step 1502: Form the at least two isolations 191 and 192 on the substrate 110;
  • Step 1503: Form the well 120 on the substrate 110;
  • Step 1504: Form the high-k gate dielectric layer 40 on the substrate 110;
  • Step 1505: Form the poly silicon gate 51 on the high-k gate dielectric layer 40;
  • Step 1506: Form a plurality of lightly doped regions 161 and 162 on the well 120;
  • Step 1507: Format least two source/drain doped regions 131 and 132 on the well 120;
  • Step 1508: Remove the poly silicon gate 51;
  • Step 1509: Form the stacked layer 140 comprising the tunneling layer 141, the charge trapping layer 142, and the charge stop layer 143 on the substrate 110;
  • Step 1510: Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150.
  • For the method of fabrication shown in FIG. 15, the stacked layer 140 and the metal gate 150 may be formed after the poly silicon gate 51 has been removed. After the poly silicon gate 51 has been removed, a hole between the spacers 171 and 172 may be left behind. A bottom dielectric compound may be first deposited to the hole to form the tunneling layer 141. A charge trapping compound may then be deposited to the hole to form the charge trapping layer 142 on the tunneling layer 141. A top dielectric compound may be deposited to the hole to form the charge stop layer 143 on the charge trapping layer 142. Metal is then deposited on top of the charge trapping layer 142 to form the metal gate 150. The high-k gate dielectric layer 40 formed under the poly silicon gate 51 may be etched together with the poly silicon gate 51 or left behind to merge with the deposited bottom dielectric compound to form the tunneling layer 141. Since the stacked layer 140 is formed in the latter part of the fabrication, other components of the memory cell 100 formed before the forming of the stacked layer 140 will not affect to the characteristic variation of the stacked layer 140.
  • If the high-k gate dielectric layer 40 is not etched, the bottom dielectric compound may not be deposited. Instead, the charge trapping compound may be deposited to the hole to form the charge trapping layer 142 on the high-k gate dielectric layer 40. A top dielectric compound may be deposited to the hole to form the charge stop layer 143 on the charge trapping layer 142. Metal is then deposited on top of the charge trapping layer 142 to form the metal gate 150.
  • In FIGS. 2 and 12-15, the sequence of each of the flowcharts is just some embodiments of the method of the present invention. It is used to illustrate aspects of the present invention and is not intended to limit the scope of the invention. For example, the sequence of forming lightly doped regions and source/drain doped regions may be interchanged such that the source/drain doped regions are formed before forming the lightly doped regions.
  • The present invention discloses a memory cell with a metal gate and methods of fabricating the memory cell using a replacement metal gate fabrication technology. The memory cell is directly formed on a substrate. The substrate may be a silicon wafer. The use of lightly doped regions reduces the short channel effect on the non-volatile memory cell. The methods of fabricating the memory cell may differ in the sequence each step is performed. The latter components of the memory cell formed may present a closer characteristic to the targeted characteristic of the component since the latter components formed shall not be affected by forming of components formed before the latter components are formed. Also, the use of metal gate shall reduce the problems such as random parasitic resistance or capacitance or missing device gates from random voids or missing metal that is usually found in conventional memory cells using poly silicon gates. Also, standby power is reduced due to the reduction of gate leakage.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (18)

What is claimed is:
1. A method of forming a memory cell, comprising:
providing a substrate;
forming a plurality of isolations on the substrate;
forming a well on the substrate;
forming a stacked layer comprising a tunneling layer and a charge trapping layer on the substrate;
forming a high-k gate dielectric layer on the stacked layer;
forming a poly silicon gate on the high-k gate dielectric layer;
forming at least two source/drain doped regions on the well;
removing the poly silicon gate; and
depositing a metal to a removed area of the poly silicon gate to form a metal gate.
2. The method of claim 1, further comprising:
forming a plurality of lightly doped regions on the well;
wherein each of the lightly doped regions is between one of the source/drain doped regions and the stacked layer.
3. The method of claim 1, wherein the stacked layer further comprises a charge stop layer formed on the charge trapping layer.
4. The method of claim 3, wherein the step of forming the well on the substrate is proceeded after the step of forming the stacked layer.
5. The method of claim 3, wherein the step of forming the plurality of isolations is proceeded after the step of forming the stacked layer.
6. The method of claim 1, wherein the step of forming the well on the substrate is proceeded after the step of forming the stacked layer.
7. The method of claim 1, wherein the step of forming the plurality of isolations is proceeded after the step of forming the stacked layer.
8. A method of forming a memory cell, comprising:
providing a substrate;
forming a plurality of isolations on the substrate;
forming a well on the substrate;
forming a high-k gate dielectric layer on the well;
forming a poly silicon gate on the high-k gate dielectric layer;
forming at least two source/drain doped regions on the well;
removing the poly silicon gate;
forming a stacked layer comprising a tunneling layer, a charge trapping layer and a charge stop layer on a removed area of the poly silicon gate; and
depositing a metal to the removed area of the poly silicon gate to form a metal gate.
9. The method of claim 8, further comprising:
forming a plurality of lightly doped regions on the well;
wherein each of the lightly doped regions is between one of the source/drain doped regions and the stacked layer.
10. A memory cell, comprising:
isolations formed on a substrate;
a well formed directly on the substrate wherein the isolations define a region of the well;
at least two source/drain doped regions formed on the well;
a stacked layer comprising a tunneling layer and a charge trapping layer formed between the at least two source/drain doped regions on the well;
a high-k gate dielectric layer formed on the stacked layer; and
a metal gate formed on the high-k gate dielectric layer.
11. The memory cell of claim 10, wherein the stacked layer further comprises:
a charge stop layer formed on the charge trapping layer.
12. The memory cell of claim 11, wherein the charge stop layer is a high-k dielectric layer.
13. The memory cell of claim 10, further comprising:
a spacer formed on each of at least two sides of the metal gate.
14. The memory cell of claim 13, further comprising interlayer dielectric formed on the substrate encompassing the spacer.
15. The memory cell of claim 10, further comprising:
lightly doped regions formed on the well;
wherein each of the lightly doped regions is between one of the source/drain doped regions and the stacked layer.
16. The memory cell of claim 10, wherein the tunneling layer is a high-k dielectric layer.
17. The memory cell of claim 10, wherein the metal gate is formed of tungsten, aluminum, titanium nitride, tantalum nitride, tantalum or copper.
18. The memory cell of claim 10, wherein the substrate is a P-substrate, the well is an N-well, and the source/drain doped regions are P-type source/drain doped regions.
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