US20150076438A1 - Non-volatile resistive memory cells - Google Patents
Non-volatile resistive memory cells Download PDFInfo
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- US20150076438A1 US20150076438A1 US14/396,406 US201214396406A US2015076438A1 US 20150076438 A1 US20150076438 A1 US 20150076438A1 US 201214396406 A US201214396406 A US 201214396406A US 2015076438 A1 US2015076438 A1 US 2015076438A1
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- resistive memory
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- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
Definitions
- FIG. 1 illustrates an example of a schematic perspective view of a crossbar array of non-volatile resistive memory cells in accordance with the present disclosure.
- FIG. 2 illustrates an example of a schematic perspective view of a non-volatile resistive memory cell and associated components according to the present disclosure.
- FIG. 3 is an example of a schematic cross-sectional view of a non-volatile resistive memory cell with a switching element formed on a sidewall of a first portion thereof according to the present disclosure.
- FIG. 4 is an example of a schematic cross-sectional view of a non-volatile resistive memory cell with a spacer formed on a sidewall thereof according to the present disclosure.
- FIG. 5 is a block diagram of a non-volatile resistive memory cell formed according to the present disclosure.
- FIG. 6 is an example of a schematic cross-sectional view of a non-volatile resistive memory cell with a switching element formed on a sidewall of a top electrode according to the present disclosure.
- FIG. 7 is another example of a schematic cross-sectional view of a non-volatile resistive memory cell with a switching element formed on a sidewall of a top electrode according to the present disclosure.
- Nanoscale devices using switching materials show resistive switching behavior.
- the switching behavior of such devices has been identified as a memristor circuit element.
- the discovery of the memristive behavior, applied to nanoscale switches, has generated interest and on-going research efforts to implement the memristive behavior in various applications.
- One of many potential applications is to use such switching materials in memory cells to store digital data.
- An array of such memory cells formed with switching materials e.g., elements
- a switching element and/or components associated therewith can contribute to reducing probabilities of such issues. For example, if a switching oxide, as described herein, is formed (e.g., deposited) early in a fabrication process, damage and/or contamination may potentially result from subsequent etching in the vicinity of the switching oxide.
- the switching element later in the fabrication process can reduce damage to and/or contamination of (e.g., passivate) the switching oxide.
- the non-volatile resistive memory cells and/or arrays thereof thus fabricated may have a better switching ON/OFF ratio, a reduction of OFF state and/or total currents, a lower initial resistance, a longer endurance, and/or a longer data retention, among other benefits.
- Examples of the present disclosure include non-volatile resistive memory cells and methods of forming the same.
- An example of a non-volatile resistive memory cell includes a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure on a first electrode, where the first portion includes at least one memristive material across a width of the vertically-extending structure.
- the non-volatile resistive memory cell also includes a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion.
- Memristive materials can be defined as having a controllable state variable that determines an electrical property (e.g., resistivity) of the material.
- Memristive materials can be oxides, sulfides, selenides, nitrides, carbides, phosphides, arsenides, chlorides, and/or bromides of transition and/or rare earth metals, among other materials presented herein or otherwise.
- FIG. 1 illustrates an example of a schematic perspective view of a crossbar array of non-volatile resistive memory cells in accordance with the present disclosure.
- FIG. 1 shows an example of a two-dimensional array 100 of such non-volatile resistive memory cells (e.g., memristors).
- the array 100 has a first group 101 of generally parallel conductor lines 102 (e.g., bit lines) in a top layer, and a second group 103 of generally parallel conductor lines 104 (e.g., word lines) in a bottom layer.
- the conductor lines 102 in the first group 101 run in a first direction
- the conductor lines 104 in the second group 103 run in a second direction at an angle (e.g., orthogonally) from the first direction.
- the two layers of conductor lines 102 , 104 form a two-dimensional crossbar structure, with each conductor line 102 in the top layer crossing over a plurality of the conductor lines 104 of the bottom layer.
- a non-volatile resistive memory cell 105 may be formed at each location where the conductor lines intersect in the array 100 .
- the non-volatile resistive memory cell 105 can be interfaced with the conductor line 102 in the first group 101 to serve as a top electrode or the non-volatile resistive memory cell 105 can be interfaced with an intervening conductive material (not shown) to serve as the top electrode.
- the non-volatile resistive memory cell 105 can be interfaced with the conductor line 104 in the second group 103 to serve as a bottom electrode or the non-volatile resistive memory cell 105 can be interfaced with an intervening conductive material (not shown) to serve as the bottom electrode.
- a region containing a switching element 107 is between the top and bottom conductor lines 102 , 104 and a protective spacer material 109 can, in various examples as described herein, be formed on at least one sidewall of at least a portion of the non-volatile resistive memory cell 105 (e.g., to passivate that portion of the non-volatile resistive memory cell against damage, contamination, etc., during subsequent processing of array 100 ).
- Other spaces between the top and bottom conductor lines 102 , 104 and/or outside the spacer material 109 of the array 100 may be filled with a dielectric material to form an interlayer dielectric (ILD), which for clarity of illustration is not explicitly shown in FIG. 1 .
- ILD interlayer dielectric
- the spacer material 109 is different from the dielectric material of the ILD in that the spacer material 109 can be selected to be unreactive with the switching element of the non-volatile resistive memory cell or, in various examples, can serve as the switching element.
- FIG. 2 illustrates an example of a schematic perspective view of a non-volatile resistive memory cell and associated components according to the present disclosure.
- the example of the memory cell and associated components 210 shown in FIG. 2 includes a bottom contact structure that can have a conductive line 212 (e.g., a word line) and a bottom electrode 214 , and a top contact structure that includes a top electrode 220 and a conductive line 222 (e.g., a bit line).
- a conductive line 212 e.g., a word line
- a top contact structure that includes a top electrode 220 and a conductive line 222 (e.g., a bit line).
- a region that contains at least a portion of the material (e.g., including memristive material) for the non-volatile resistive memory cell 224 which in some examples can include a switching element.
- a switching element is formed from a memristive material that has electrical characteristics that depend on a state variable (e.g., resistivity) that can be controllably modified to allow a device (e.g., a memristor) to be switched to an ON state with a low-resistance value and an OFF state with a high-resistance value, or intermediate states between the ON and OFF states.
- a state variable e.g., resistivity
- Each of the bottom and top electrodes 214 , 220 may have a width on the nanoscale.
- the term “nanoscale” indicates that an object has one or more dimensions less than one micrometer.
- nanoscale can indicate that an object has one or more dimensions less than 100 nanometers (nm).
- the bottom and top electrodes 214 , 220 may have a width in a range of from 5 nm to 500 nm.
- the region that contains at least a portion of the material for the memory cell 224 may have a height that is from a few nanometers to tens of nanometers.
- the conductive line 212 e.g., the word line
- the bottom electrode 214 may provide sufficient conductivity and/or low resistance and the word line 212 and bit line 222 may not be necessary or the word line 212 and bit line 222 may provide sufficient conductivity and/or low resistance and the bottom and top electrodes 214 , 220 may not be necessary, among other modifications that achieve the same or similar functions.
- the word line 212 , bit line 222 , and the bottom and top electrodes 214 , 220 are electrically conductive but may be formed of different materials.
- the word line 212 and bit line 222 may provide high conductivity and/or low resistance and, as such, may be formed by processes appropriate for forming on the nanoscale, for example, tungsten (W), copper (Cu), and/or aluminum (Al) conductor lines, among other suitably conductive materials.
- the bottom and top electrodes 214 , 220 may be formed of a conductive material selected, for example, to prevent the material thereof from interacting with the switching element material.
- the conductive material may be a metal such as, for example, platinum (Pt), gold (Au), copper (Cu), tantalum (Ta), tungsten (W), etc., metallic compounds such as, for example, titanium nitride (TiN), tungsten nitride (WN), etc., and/or doped or undoped semiconductor materials, among other suitably conductive materials.
- a metal such as, for example, platinum (Pt), gold (Au), copper (Cu), tantalum (Ta), tungsten (W), etc.
- metallic compounds such as, for example, titanium nitride (TiN), tungsten nitride (WN), etc., and/or doped or undoped semiconductor materials, among other suitably conductive materials.
- the top electrode 220 extends at an angle to the bottom electrode 214 .
- the angle may be, for example, around 90 degrees, but may intersect at other angles depending on design choices.
- structural support can, in various examples, be provided. Accordingly, spaces around and/or between the bottom and top electrodes 214 , 220 and outside the region that contains the material (e.g., including the memristive material) for the portion of the memory cell 224 and associated components can be filled with a dielectric material, in various examples, to form an ILD 226 .
- the ILD 226 can provide structural support and/or electrically insulate the bottom and top electrodes 214 , 220 .
- the ILD 226 also can shield (e.g., isolate) the material for the portion of the memory cell 224 and associated components from material of adjacent memory cells (e.g., switching elements) and associated components.
- the memory cell and associated components 210 can, in various examples, have a spacer material 228 .
- the spacer material 228 can be different from the material of the ILD 226 in that the spacer material 228 can be selected to be unreactive with a switching element of the memory cell, to protect the switching element from damage, contamination, etc., during subsequent processing (e.g., formation of the ILD), to direct flow of oxygen vacancies, and/or, in various examples, to serve as the switching element.
- the spacer material 228 can be formed on at least one (e.g., one or more) sidewall of the material for the portion of the memory cell 224 . In some examples (e.g., as shown in FIG.
- the spacer material 228 can be formed to surround the sidewalls (e.g., to extend in height between at least the bottom and top electrodes 214 , 220 ). As such, the spacer material can shield (e.g., isolate) the material for the portion of the memory cell 224 from, for example, the ILD 226 and/or other components (e.g., during and after processing and/or formation of the same).
- the portions of the memory cell 224 between the bottom and top electrodes 214 , 220 can, in various examples, contain memristive material for a switching element.
- the switching element is capable of carrying a species of mobile ionic dopants such that the dopants can be controllably transported through the switching element and redistributed to change electrical properties of either the switching element or an interface of the switching element and an electrode. This ability to change the electrical properties as a function of dopant distribution allows the switching element to be placed in different switching states by applying a switching voltage from a voltage source (not shown) to the bottom and/or top electrodes 214 , 220 .
- the portion of the memory cell 224 between the bottom and top electrodes 214 , 220 can include an active region that has two sub-regions: a primary active region and a dopant source region.
- the primary active region can contain material for the memristive switching element.
- memristive material for the switching element may be electronically resistive (e.g., semiconducting or nominally insulating with a weak ionic conducting capacity).
- Suitable switching materials include elemental semiconductors such as Si and Ge, including binary, ternary, and quaternary compounds thereof, and compound semiconductors such as III-V and II-VI compound semiconductors.
- the III-V semiconductors include, for instance, BN, BP, BSb, AlP, AlSb, GaAs, GaP, GaN, InN, InP, InAs, and InSb, and ternary and quaternary compounds.
- the II-VI compound semiconductors include, for instance, CdSe, CdS, CdTe, ZnSe, ZnS, ZnO, and ternary compounds.
- the suitable materials include GeO, SiGe, GeSb, SiGeSb, GeSbTe, and GaInZnO, among other compounds.
- the II-VI compound materials may also include phase change materials.
- PCRAM and STT-RAM technologies can be included as memristive materials.
- the materials may also include filament structures such as a-Si:Ag that has Ag filaments in an a-Si matrix.
- Dopant species from the dopant source region can be used to alter the electrical properties of the material of the switching element.
- the dopant species also are considered memristive materials. Which one or more of the dopant species are combined with the material of the switching element depends on the particular type of switching material utilized.
- the dopant species may be cations, anions, vacancies, and/or impurities acting, for example, as electron donors or acceptors.
- the dopant species acting as the state variable may be charged oxygen vacancies (V O 2+ ) or ions.
- the dopant species acting as the state variable may be charged nitride vacancies and/or sulfide ions.
- the dopants acting as the state variable may be n-type or p-type impurities.
- the dopant source region can contain a dopant source material that functions as a source/sink of dopants that can be driven into or out of the switching material in the primary active region to alter the overall resistance of the switching element.
- the dopant source material may be generally the same as the switching material but with a higher dopant concentration.
- the switching material is TiO 2
- the dopant source material may be TiO 2-x where x is a number significantly smaller than 1, such as from 0.01 to 0.1.
- the TiO 2-x material can act as a source/sink of charged oxygen vacancies (V O 2+ ) or ions that can drift into and through the TiO 2 switching material in the primary active region.
- the non-volatile resistive memory cell 210 illustrated in FIG. 2 can be switched between ON and OFF states by controlling the concentration and distribution of dopants in the primary active region.
- Switching materials that use dopants may have a DC switching voltage from a voltage source applied to top and bottom electrodes to create an electric field across the switching element.
- the electric field if of sufficient strength and proper polarity, may drive the oxygen vacancies to drift through the switching element toward an electrode, thereby turning the device into an ON state. If the polarity of the electric field is reversed, the oxygen vacancies may drift in an opposite direction across the switching element and away from the electrode, thereby turning the device into an OFF state. In this way, the switching is reversible and may be repeated. Due to a relatively large electric field to cause dopant drifting, after the switching voltage is removed the locations of the oxygen vacancies may remain stable in the switching element. As such, the switching may be non-volatile and the switching element can be utilized for a non-volatile resistive memory cell.
- a switching oxide e.g., a TMO such as TiO 2
- a sub-oxide e.g., Ti 4 O 7
- the switching can occur when the charged oxygen vacancies or ions in the sub-oxide migrate into the switching oxide under the influence of an applied electrical field (e.g., to create a conducting channel through the switching oxide).
- the path of least electrical resistance between the top and bottom electrodes traverses through the switching element located immediately between them and not through a path traversing a sidewall spacer and/or the ILD.
- materials for the sidewall spacer are intentionally selected to be lower in electrical resistance (e.g., less resistive) than materials constituting components that would otherwise be located in a position of the switching element.
- the sidewall spacer is the actual switching element, while a stack of materials located immediately between the electrodes contains materials that act as a higher-resistance blocking element (e.g., insulator) that can shunt the electrical path through the sidewall spacer functioning as the switching element.
- a bottom electrode and a top electrode can sandwich the switching oxide and/or the sub-oxide to form a non-volatile resistive memory cell.
- the top and bottom electrodes can, for example, be patterned (e.g., by suitable etching techniques) into lines, the set of top electrodes generally aligned perpendicularly to the set of bottom electrodes, as shown in FIG. 1 .
- the oxide switching element between the bottom electrode and the top electrode may be deposited as a layer that is substantially parallel to an underlying substrate and to layers that constitute precursors for the bottom and top electrodes.
- both the switching oxide and the sub-oxide layers may be deposited onto the substrate and processed together, for instance, patterned (e.g., by suitable etching techniques) into a vertically standing “resistor column” to bridge the two electrodes. This process may introduce damage and/or contamination to the switching oxide, especially at sidewalls of the patterned resistor.
- etch-induced damage such as dangling chemical bonds and/or metallic reaction products or etch residue, etc.
- etch-induced damage could induce creation of electrical paths between the electrodes that are not dependent on intended signals for switching of the oxide (e.g., a TMO). Therefore, it is advantageous to reduce such damage to, and/or contamination, of the switching oxide and/or associated components.
- damage and/or contamination can be reduced (e.g., passivated) by forming (e.g., depositing) at least a portion of the switching element (e.g., a TMO) and/or associated components after a number of particular portions of the processing has been performed (e.g., depositing and/or etching of other components).
- FIG. 3 is an example of a schematic cross-sectional view of a non-volatile resistive memory cell with a switching element formed on a sidewall of a first portion thereof according to the present disclosure.
- the non-volatile resistive memory cell (e.g., a memristor) and associated components 330 illustrated in FIG. 3 show a schematic cross-sectional view of a conductive line 332 (e.g., a word line) and a bottom electrode 334 formed thereon or, in some examples, precursors thereof (e.g., layers of conductive line and bottom electrode materials).
- the conductive line 332 and the bottom electrode 334 extend left to right substantially in the plane of FIG. 3 .
- the conductive line 332 and the precursor thereof can be formed from a material that includes tungsten (W), although other materials can be used (e.g., aluminum (Al) and/or copper (Cu), among others), and the bottom electrode 334 and the precursor thereof can be formed from a material that includes titanium nitride (TiN), although other materials can be used (e.g., tantalum nitride (TaN) and/or platinum (Pt), among others).
- W tungsten
- Al aluminum
- Cu copper
- the bottom electrode 334 and the precursor thereof can be formed from a material that includes titanium nitride (TiN), although other materials can be used (e.g., tantalum nitride (TaN) and/or platinum (Pt), among others).
- a sub-oxide layer as described herein, can be formed (e.g., deposited) on an exposed surface of the precursor layer of the bottom electrode.
- an insulating layer can be formed (e.g., deposited) on an exposed surface of the sub-oxide layer and a precursor layer for a second electrode can be formed (e.g., deposited) on an exposed surface of the insulating layer.
- the precursor layer for the second electrode can, in some examples, be formed to serve as a hard mask for subsequent etching processes.
- suitable patterning and etching techniques can be utilized to form a vertically-extending first portion of the non-volatile resistive memory cell 335 on the bottom electrode 334 , where the first portion 335 has a sub-oxide 337 , an insulator 339 , and/or at least part of a second electrode 341 extending across a width of the first portion 335 .
- at least part of the second electrode precursor serving as the hard mask 343 can be removed by the etching technique that forms the vertically-extending first portion of the non-volatile resistive memory cell 335 .
- a switching material 344 (e.g., a switching element) can be formed (e.g., deposited) as a second portion of the non-volatile resistive memory cell on at least one sidewall of the vertically-extending first portion of the non-volatile resistive memory cell 335 .
- Deposition of the switching material 344 can be implemented by spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or plasma enhanced atomic layer deposition (PEALD), among other techniques.
- the switching material 344 can be deposited (e.g., to substantially a uniform thickness via ALD) to a nanoscale thickness (e.g., up to 5 nm thick) to form a vertically-extending structure as the switching element.
- the switching material 344 can be formed to surround the sidewalls of the vertically-extending first portion of the non-volatile resistive memory cell 335 (e.g., as shown in FIG. 2 ).
- the nanoscale thickness of the switching element 344 can define a size of a current path 345 between the sub-oxide 337 and the part of a second electrode 341 .
- the effective junction area can be reduced to the cross-sectional area of the thickness of the junction, thereby reducing an OFF state current and an overall current level.
- the vertically-extending switching element 344 may be protected (e.g., passivated) from further processing by an insulating layer (not shown) that covers the vertically-extending switching element 344 .
- the vertically-extending switching element 344 and/or the insulating layer can be formed into a sidewall spacer structure along the sidewalls of the first portion of the non-volatile resistive memory cell 335 (e.g., via anisotropic vertical reactive ion etching).
- An ILD 347 material can, in various examples, be formed (e.g., deposited) on the portions of the non-volatile resistive memory cell (e.g., 335 and 344 ) just described.
- a trench 346 can be formed in the ILD 347 (e.g., via suitable patterning and/or etching techniques, such as photolithography and/or wet or dry etching techniques, among others) with a long axis substantially orthogonal to the conductive line 332 and/or the bottom electrode 334 and to a depth that exposes at least a portion of a surface of the portion of the second electrode 341 .
- Another portion of the second electrode 348 can, in various examples, be formed (e.g., deposited) in the trench 346 to connect with the previously formed portion of the second electrode 341 .
- the two portions of the second electrode 341 , 348 can be formed from the same or different materials.
- the material for the second electrode 348 can be deposited (e.g., to a substantially uniform thickness via ALD) to form a cavity 349 in the trench 346 .
- the cavity 349 can be filled with suitable material (e.g., via suitable deposition techniques) to form a conductive line (e.g., a bit line).
- suitable material e.g., via suitable deposition techniques
- the non-volatile resistive memory cells (e.g., memristors) and associated components 330 can be formed from various materials, as described herein by way of example and not by way of limitation.
- a sub-oxide e.g., as shown in FIGS. 3-4 and 6 - 7
- the switching element e.g., as shown in FIGS. 3-4 and 6 - 7
- the switching material can be TiO 2 , TaO x , among others
- the sub-oxide material can be TiO 2-x (e.g., Ti 2 O 3 ), TaO x-y , among others.
- An insulator (e.g., as shown in FIG. 3 ) can, for example, be formed from SiO 2 and/or Si 3 N 4 , among other suitable insulating materials.
- the ILD can, for example, be formed from a silicon oxide (e.g., SiO 2 ), a silicon nitride, and/or a silicon carbon nitride, among others.
- the top conductive line (e.g., bit line) (e.g., as shown in FIGS.
- the bottom conductive line e.g., word line
- tungsten (W) tungsten
- Cu copper
- Al aluminum
- the portions of the second electrode can, in some examples, be formed from the same material as the first electrode (e.g., TiN) or a different material (e.g., tantalum nitride (TaN) and/or platinum (Pt), among other suitably conductive materials).
- FIG. 4 is an example of a schematic cross-sectional view of a non-volatile resistive memory cell with a spacer formed on a sidewall thereof according to the present disclosure.
- the non-volatile resistive memory cell (e.g., a memristor) and associated components 450 illustrated in FIG. 4 show a schematic cross-sectional view of a conductive line 432 (e.g., a word line) and a bottom electrode 434 formed thereon or, in some examples, precursors thereof (e.g., layers of conductive line and bottom electrode materials), substantially as described with regard to FIG. 3 .
- a sub-oxide layer as described herein, can be formed (e.g., deposited) on an exposed surface of the precursor layer of the bottom electrode.
- a switching material layer can be formed (e.g., deposited) on an exposed surface of the sub-oxide layer and a precursor layer for a second electrode can be formed (e.g., deposited) on an exposed surface of the switching material layer.
- the precursor layer for the second electrode can, in some examples, be formed to serve as a hard mask for subsequent etching processes.
- suitable patterning and etching techniques can be utilized to form a vertically-extending first portion of the non-volatile resistive memory cell 435 on the bottom electrode 434 , where the first portion 435 has a sub-oxide 437 , a switching element 451 , and/or at least part of a second electrode 441 extending across a width of the first portion 435 .
- at least part of the second electrode precursor serving as the hard mask 443 can be removed by the etching technique that forms the vertically-extending first portion of the non-volatile resistive memory cell 435 .
- the vertically-extending first portion of the non-volatile resistive memory cell 435 may be protected (e.g., passivated) from further processing by a spacer layer 453 that covers the vertically-extending first portion of the non-volatile resistive memory cell 435 , including the switching element 451 .
- the spacer layer 453 can be formed into a sidewall spacer structure along the sidewalls of the first portion of the non-volatile resistive memory cell 435 (e.g., via anisotropic vertical reactive ion etching).
- the spacer layer 453 can be formed to surround the sidewalls of the vertically-extending first portion of the non-volatile resistive memory cell 435 (e.g., as shown in FIG. 2 ).
- the non-volatile resistive memory cells e.g., memristors
- associated components 450 can be formed from various materials, as described herein by way of example and not by way of limitation.
- a sub-oxide e.g., as shown in FIGS. 3-4 and 6 - 7
- the switching element e.g., as shown in FIGS. 3-4 and 6 - 7
- the sub-oxide material can have more charged oxygen vacancies or ions than the switching element material.
- the switching material can be TiO 2 , TaO x , among others, and the sub-oxide material can be TiO 2-x (e.g., Ti 2 O 3 ), TaO x-y , among others.
- the spacer layer 453 shown in FIG. 4 can be formed from a material that is no more resistive (e.g., no less oxygen-deficient) than the switching element material.
- the spacer layer 453 and the switching element 451 both can be formed from TiO 2 , or the spacer layer 453 can be formed from Ta 2 O 5 when the switching element 451 is formed from TiO 2 , among other such combinations.
- FIG. 4 shows that (e.g., similar to FIG. 3 ) an ILD 447 material can, in various examples, be formed (e.g., deposited) on the portions of the non-volatile resistive memory cell (e.g., 435 and 453 ) just described.
- a trench 446 can be formed in the ILD 447 (e.g., via suitable patterning and/or etching techniques) with a long axis substantially orthogonal to the conductive line 432 and/or the bottom electrode 434 and to a depth that exposes at least a portion of a surface of the portion of the second electrode 441 .
- Another portion of the second electrode 448 can, in various examples, be formed (e.g., deposited) in the trench 446 to connect with the previously formed portion of the second electrode 441 .
- the material for the second electrode 448 can be deposited (e.g., to a substantially uniform thickness via ALD) to form a cavity 449 in the trench 446 .
- the cavity 449 can be filled with suitable material (e.g., via suitable deposition techniques) to form a conductive line (e.g., a bit line).
- suitable material e.g., via suitable deposition techniques
- FIG. 5 is a block diagram of a non-volatile resistive memory cell formed according to the present disclosure.
- a non-volatile resistive memory cell can include a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure (e.g., 335 , 435 ) on a first electrode (e.g., 334 , 434 ), where the first portion comprises at least one memristive material (e.g., 337 or 437 and 451 ) across a width of the vertically-extending structure.
- the non-volatile resistive memory cell also can include a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion (e.g., 344 , 453 ).
- the memristive material can be formed from at least one TMO (e.g., various oxides of Ti and/or Ta, among others).
- the second portion can, for example, surround sidewalls of the first portion to passivate the first portion (e.g., from subsequent processing).
- the first portion e.g., 335
- the second portion e.g., 344
- the first portion (e.g., 335 ) can, in various examples, include an insulator (e.g., 339 ) between the first memristive material (e.g., 337 ) and a second electrode (e.g., 341 ).
- an insulator e.g., 339
- the first memristive material e.g., 337
- a second electrode e.g., 341
- the first portion can, in various examples, include a first memristive material (e.g., 437 ) and a second memristive material (e.g., 451 ), where the second memristive material is a switching element and is more resistive than the first memristive material, and the second portion (e.g., 453 ) can, in various examples, include a third memristive material that is no less resistive than the second memristive material.
- FIG. 6 is an example of a schematic cross-sectional view of a non-volatile resistive memory cell with a switching element formed on a sidewall of a top electrode according to the present disclosure.
- the non-volatile resistive memory cell (e.g., a memristor) and associated components 660 illustrated in FIG. 6 shows a schematic cross-sectional view of a conductive line 632 (e.g., a word line) and a bottom electrode 634 formed thereon or, in some examples, precursors thereof (e.g., layers of conductive line and bottom electrode materials), as described herein.
- a conductive line 632 e.g., a word line
- bottom electrode 634 formed thereon or, in some examples, precursors thereof (e.g., layers of conductive line and bottom electrode materials), as described herein.
- a sub-oxide layer as described herein, can be formed (e.g., deposited) on an exposed surface of the precursor layer of the bottom electrode.
- a hard mask for subsequent etching processes can be formed (e.g., deposited) on an exposed surface of the sub-oxide layer.
- suitable patterning and/or etching techniques can be utilized to form a vertically-extending first portion of the non-volatile resistive memory cell 635 on the bottom electrode 634 , where the first portion 635 has a sub-oxide 637 extending across a width of the first portion 635 .
- the hard mask 643 can be removed by the etching technique that forms the vertically-extending first portion of the non-volatile resistive memory cell 635 to expose at least a portion of a surface of the sub-oxide 637 .
- the vertically-extending first portion of the non-volatile resistive memory cell 635 may be protected (e.g., passivated) from further processing by a spacer layer 661 that covers the vertically-extending first portion of the non-volatile resistive memory cell 635 .
- the spacer layer 661 can be formed into a sidewall spacer structure along the sidewalls of the first portion of the non-volatile resistive memory cell 635 (e.g., via anisotropic vertical reactive ion etching).
- the spacer layer 661 can be formed to surround the sidewalls of the vertically-extending first portion of the non-volatile resistive memory cell 635 (e.g., as shown in FIG. 2 ).
- the spacer layer 661 can, for example, be formed from a material that is substantially non-reactive with the sub-oxide 637 and/or an ILD 647 material (e.g., various nitrides, such as a silicon nitride and/or a silicon carbon nitride, among others).
- An ILD 647 material can, in various examples, be formed (e.g., deposited) on the first portion of the non-volatile resistive memory cell (e.g., 635 ) just described.
- a trench can be formed in the ILD 647 (e.g., via suitable patterning and/or etching techniques) with a long axis substantially orthogonal to the conductive line 632 and/or the bottom electrode 634 and to a depth that exposes at least a portion of a surface of the sub-oxide 637 .
- the trench can be formed to have two parts.
- the trench can have a lower part 662 that exposes at least the portion of the surface of the sub-oxide 637 .
- the lower part of the trench 662 can be formed with a frustoconical cross-section having a truncated end exposing at least the portion of the surface of the sub-oxide 637 and a wider distal end connecting with an upper part 665 of the trench at a particular height above the truncated end.
- sidewalls of the lower part 662 can be formed at angles to connect with the upper part 665 that is wider than the truncated end of the lower part 662 of the trench and, in some examples, the wider distal end of the lower part 662 of the trench.
- the upper part 665 can, in some examples, have sidewalls formed substantially perpendicular to the conductive line 632 and/or the bottom electrode 634 .
- a second portion of the of the non-volatile resistive memory cell can be formed (e.g., deposited to a substantially uniform thickness via ALD) as a switching material 663 (e.g., a switching element) on at least one sidewall of the lower portion 662 of the trench as a vertically-extending structure (e.g., in contact with at least a portion of the exposed surface of the sub-oxide 637 and extending to the particular height above the truncated end) to connect with, for example, the upper part 665 of the trench.
- a switching material 663 e.g., a switching element
- the switching material 663 (e.g., the switching element) can be formed to cover both sidewalls of the lower part 662 of the trench to the particular height, along with substantially the entire exposed upper surface of the sub-oxide 637 .
- a first cavity 664 can, in various examples, be formed within the switching element 663 in the lower part 662 of the trench.
- Forming the switching element 663 subsequent to, for example, suitable patterning and/or etching techniques utilized to form the vertically-extending first portion of the non-volatile resistive memory cell 635 , forming the ILD 647 , and/or suitable patterning and/or etching techniques utilized to form the upper 665 and/or lower 662 portions of the trench can reduce damage and/or contamination (e.g., passivate) resulting from such processing (e.g., to the switching element 663 ).
- damage and/or contamination e.g., passivate
- a second electrode material e.g., as described herein
- the second electrode material can, in some examples, form the via within the first cavity 664 to substantially the particular height above the truncated end to connect with, for example, the upper part 665 of the trench.
- the switching element 663 is formed on the sidewalls of the via (e.g., the second, or top, electrode) within the first cavity 664 .
- a second electrode material 667 can be formed (e.g., deposited to a substantially uniform thickness via ALD) in the upper part 665 of the trench.
- the second electrode material 667 (as described herein) can be the same as or different from the second electrode material utilized to form the via within the first cavity 664 .
- the second electrode material 667 can cover the sidewalls and the bottom of upper part 665 of the trench to connect with the second electrode material utilized to form the via within the first cavity 664 .
- the second electrode material 667 can be formed (e.g., deposited) within the upper part 665 of the trench to form a second cavity 668 .
- a conductive material (e.g., as described herein) can, in various examples, be formed (e.g., deposited) within the second cavity 668 (e.g., to form a top conductive material or bit line).
- the conductive material can, in various examples, be formed (e.g., deposited) directly within the upper part 665 of the trench (e.g., without the second electrode material 667 ) to connect with the second electrode material utilized to form the via within the first cavity 664 .
- FIG. 7 is another example of a schematic cross-sectional view of a non-volatile resistive memory cell with a switching element formed on a sidewall of a top electrode according to the present disclosure.
- the non-volatile resistive memory cell (e.g., a memristor) and associated components 770 illustrated in FIG. 7 show a schematic cross-sectional view of a conductive line 732 (e.g., a word line) and a bottom electrode 734 formed thereon or, in some examples, precursors thereof (e.g., layers of conductive line and bottom electrode materials), as described herein.
- Suitable patterning and/or etching techniques can be utilized to form a vertically-extending first portion of a non-volatile resistive memory cell 735 on the bottom electrode 734 substantially as described herein with regard to FIG. 6 .
- An ILD 747 material can, in various examples, be formed (e.g., deposited) on the first portion of the non-volatile resistive memory cell (e.g., 735 ) substantially as described herein.
- a trench 762 can be formed in the ILD 747 (e.g., via suitable patterning and/or etching techniques) with a long axis substantially orthogonal to the conductive line 732 and/or the bottom electrode 734 and to a depth that exposes at least a portion of a surface of the sub-oxide 737 .
- the trench can be formed to have a lower part that exposes at least the portion of the surface of the sub-oxide 737 .
- the lower part of the trench can be formed with a frustoconical cross-section having a truncated end exposing at least the portion of the surface of the sub-oxide 737 and a wider distal part transitioning to an upper part of the trench (e.g., at a particular height above the truncated end).
- sidewalls of the lower part of the trench 762 can be formed at angles to connect with the upper part of the trench 762 that is wider than the truncated end of the lower part of the trench.
- the upper part of the trench 762 can, in some examples, have sidewalls formed substantially perpendicular to the conductive line 732 and/or the bottom electrode 734 .
- a second portion of the of the non-volatile resistive memory cell can be formed (e.g., deposited to a substantially uniform thickness via ALD) as a switching material 771 (e.g., a switching element) on at least one sidewall of the lower portion of the trench 762 as a vertically-extending structure (e.g., in contact with at least a portion of the exposed surface of the sub-oxide 737 ).
- the switching material 771 can, in various examples, extend to whatever height is selected for a particular application (e.g., to a top of the trench 762 and/or the ILD 747 ).
- the switching material 771 e.g., the switching element
- the switching material 771 can be formed to cover both sidewalls of the trench 762 to the selected height, along with substantially the entire exposed upper surface of the sub-oxide 737 .
- a first cavity (not shown) can, in various examples, be formed within the switching element 771 in the trench 762 .
- Forming the switching element 771 subsequent to, for example, suitable patterning and/or etching techniques utilized to form the vertically-extending first portion of the non-volatile resistive memory cell 735 , forming the ILD 747 , and/or suitable patterning and/or etching techniques utilized to form the portions of the trench 762 can reduce damage and/or contamination (e.g., passivate) resulting from such processing (e.g., to the switching element 771 ).
- damage and/or contamination e.g., passivate
- a second electrode material e.g., as described herein
- ALD substantially uniform thickness via ALD
- the second electrode 773 can, in some examples, be formed within the first cavity to substantially the selected height of the switching element 771 in the trench 762 .
- the switching element 771 is formed on the sidewalls of the second, or top, electrode within the first cavity.
- the second electrode material 773 can cover the sidewalls and the bottom of the trench 762 to form a second cavity 775 .
- a conductive material e.g., as described herein
- a non-volatile resistive memory cell can include a first portion of the non-volatile resistive memory cell formed as a first vertically-extending memristive material structure (e.g., 635 , 735 ) on a first electrode (e.g., 634 , 734 ).
- the non-volatile resistive memory cell also can include a second portion of the non-volatile resistive memory cell (e.g., 663 , 771 ) formed on at least one sidewall of a trench (e.g., 662 , 762 ) as a second vertically-extending memristive material structure to contact an exposed upper surface of the first vertically-extending memristive material structure (e.g., 637 , 737 ), where the second memristive material is a switching element.
- a second portion of the non-volatile resistive memory cell e.g., 663 , 771
- a trench e.g., 662 , 762
- a second vertically-extending memristive material structure to contact an exposed upper surface of the first vertically-extending memristive material structure (e.g., 637 , 737 ), where the second memristive material is a switching element.
- the first vertically-extending memristive material structure (e.g., 635 , 735 ) is formed substantially from a sub-oxide, as described herein.
- the second portion of the non-volatile resistive memory cell (e.g., 663 , 771 ) can cover the exposed upper surface of the first vertically-extending memristive material structure (e.g., 637 , 737 ) and sidewalls of the trench (e.g., 662 , 762 ) to form a first cavity (e.g., 564 ).
- At least a portion of the second electrode can, in various examples, be formed as a via within the first cavity 564 .
- At least a portion of the second electrode can, in various examples, cover a surface of the first cavity to form a second cavity (e.g., 568 , 675 ).
- a method of forming a non-volatile resistive memory cell can include forming a precursor of a first portion of the non-volatile resistive memory cell as a vertically-extending structure (e.g., 335 , 435 , 635 , 735 ) on a first electrode (e.g., 334 , 434 , 634 , 734 ), where the first portion comprises at least one memristive material across a width of the vertically-extending structure (e.g., 337 , 437 , 451 , 637 , 737 ) and a hard mask material (e.g., 343 , 443 , 643 , 743 ) above the at least one memristive material, where etching the precursor of the first portion of the non-volatile resistive memory cell can be utilized to form a patterned first portion of the non-volatile resistive memory cell (e.g., 335 , 435 )
- the patterned first portion of the non-volatile resistive memory cell (e.g., 335 , 435 , 635 , 735 ) can be passivated by forming a spacer material around sidewalls (e.g., 344 , 453 , 661 , 761 ) of the patterned first portion.
- sidewalls e.g., 344 , 453 , 661 , 761
- the method examples described herein are not constrained to a particular order or sequence. Additionally, some of the described method examples, or elements thereof, can occur or be performed at the same, or substantially the same, point in time.
- forming the spacer material around the sidewalls includes forming a memristive material that vertically-extends (e.g., 344 , 453 ) from the first electrode (e.g., 334 , 434 , 634 , 734 ) to a height of an upper one of the at least one memristive material (e.g., 337 , 451 , 637 , 737 ) or a remaining portion of the hard mask material (e.g., 341 , 441 , 643 , 743 ) of the patterned first portion (e.g., 335 , 435 , 635 , 735 ).
- the spacer material around the sidewalls can extend from the first electrode to a top of an upper memristive material (e.g., a sub-oxide or a switching element) or to a top of the remaining portion of the hard mask material.
- an upper memristive material e.g., a sub-oxide or a switching element
- forming the memristive material that vertically-extends includes forming a memristive material that is no less resistive than the least resistive of the at least one memristive material (e.g., 337 , 437 , 451 , 637 , 737 ) of the patterned first portion (e.g., 335 , 435 , 635 , 735 ).
- a trench (e.g., 346 , 446 , 662 , 665 , 762 ) can be formed in an ILD material (e.g., 347 , 447 , 647 , 737 ) to expose at least part of a surface of the upper one of the at least one memristive material (e.g., 637 , 737 ) or the remaining portion of the hard mask material (e.g., 341 , 441 ) and, in various examples, a second portion of the non-volatile resistive memory cell can be formed as a switching element (e.g., 663 , 771 ) to cover the exposed surface and sidewalls of the trench to form a first cavity (e.g., 564 ).
- ILD material e.g., 347 , 447 , 647 , 737
- a second portion of the non-volatile resistive memory cell can be formed as a switching element (e.g., 663 , 771 )
- At least a portion of a second electrode can, in various examples, be formed as a via within the first cavity (e.g., 564 ). At least a portion of a second electrode (e.g., 773 ) can, in various examples, be formed to cover a surface of the first cavity to form a second cavity (e.g., 568 ).
- Examples of the present disclosure can include non-volatile resistive memory cells (e.g., memristors) apparatuses, systems, and methods, including executable instructions and/or logic to facilitate fabricating and/or operating the non-volatile resistive memory cells (e.g., memristors), apparatuses, and systems.
- Processing resources can include one or more processors able to access data stored in memory to execute the formations, actions, functions, etc., as described herein.
- logic is an alternative or additional processing resource to execute the formations, actions, functions, etc., described herein, which includes hardware (e.g., various forms of transistor logic, application specific integrated circuits (ASICs), etc.), as opposed to computer executable instructions (e.g., software, firmware, etc.) stored in memory and executable by a processor.
- hardware e.g., various forms of transistor logic, application specific integrated circuits (ASICs), etc.
- computer executable instructions e.g., software, firmware, etc.
- non-volatile resistive memory cell e.g., memristor
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Abstract
Description
- Research and development efforts are directed toward designing and manufacturing non-volatile resistive memory cells, such as for use in crossbar memory arrays. Such electronics may enable significant advances, including markedly reduced component sizes. However, the design and manufacture of such electronic devices may present a number of challenges.
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FIG. 1 illustrates an example of a schematic perspective view of a crossbar array of non-volatile resistive memory cells in accordance with the present disclosure. -
FIG. 2 illustrates an example of a schematic perspective view of a non-volatile resistive memory cell and associated components according to the present disclosure. -
FIG. 3 is an example of a schematic cross-sectional view of a non-volatile resistive memory cell with a switching element formed on a sidewall of a first portion thereof according to the present disclosure. -
FIG. 4 is an example of a schematic cross-sectional view of a non-volatile resistive memory cell with a spacer formed on a sidewall thereof according to the present disclosure. -
FIG. 5 is a block diagram of a non-volatile resistive memory cell formed according to the present disclosure. -
FIG. 6 is an example of a schematic cross-sectional view of a non-volatile resistive memory cell with a switching element formed on a sidewall of a top electrode according to the present disclosure. -
FIG. 7 is another example of a schematic cross-sectional view of a non-volatile resistive memory cell with a switching element formed on a sidewall of a top electrode according to the present disclosure. - Nanoscale devices using switching materials, such as titanium oxide and others presented herein, show resistive switching behavior. The switching behavior of such devices has been identified as a memristor circuit element. The discovery of the memristive behavior, applied to nanoscale switches, has generated interest and on-going research efforts to implement the memristive behavior in various applications. One of many potential applications is to use such switching materials in memory cells to store digital data. An array of such memory cells formed with switching materials (e.g., elements) can be constructed in a crossbar configuration to provide a high device density. There are, however, technical issues to be addressed in order to improve fabrication and/or reliability issues pertaining to memory cells and/or arrays having switching elements.
- Among such issues is maintaining switching characteristics of the switching elements over multiple ON/OFF cycles to provide an acceptable operation life (e.g., via reduction of OFF state and/or total currents, as described herein). Protection of a switching element and/or components associated therewith from adverse effects (e.g., damage and/or contamination resulting from processes associated with fabrication of the non-volatile resistive memory cells and/or arrays thereof) can contribute to reducing probabilities of such issues. For example, if a switching oxide, as described herein, is formed (e.g., deposited) early in a fabrication process, damage and/or contamination may potentially result from subsequent etching in the vicinity of the switching oxide. Thus, formation (e.g., deposition) of the switching element later in the fabrication process can reduce damage to and/or contamination of (e.g., passivate) the switching oxide. The non-volatile resistive memory cells and/or arrays thereof thus fabricated may have a better switching ON/OFF ratio, a reduction of OFF state and/or total currents, a lower initial resistance, a longer endurance, and/or a longer data retention, among other benefits.
- Examples of the present disclosure include non-volatile resistive memory cells and methods of forming the same. An example of a non-volatile resistive memory cell includes a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure on a first electrode, where the first portion includes at least one memristive material across a width of the vertically-extending structure. The non-volatile resistive memory cell also includes a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion. Memristive materials can be defined as having a controllable state variable that determines an electrical property (e.g., resistivity) of the material. Memristive materials can be oxides, sulfides, selenides, nitrides, carbides, phosphides, arsenides, chlorides, and/or bromides of transition and/or rare earth metals, among other materials presented herein or otherwise.
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FIG. 1 illustrates an example of a schematic perspective view of a crossbar array of non-volatile resistive memory cells in accordance with the present disclosure.FIG. 1 shows an example of a two-dimensional array 100 of such non-volatile resistive memory cells (e.g., memristors). Thearray 100 has afirst group 101 of generally parallel conductor lines 102 (e.g., bit lines) in a top layer, and asecond group 103 of generally parallel conductor lines 104 (e.g., word lines) in a bottom layer. Theconductor lines 102 in thefirst group 101 run in a first direction, and theconductor lines 104 in thesecond group 103 run in a second direction at an angle (e.g., orthogonally) from the first direction. The two layers ofconductor lines conductor line 102 in the top layer crossing over a plurality of theconductor lines 104 of the bottom layer. - In the detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof and in which is shown by way of illustration how examples of the disclosure may be practiced. These examples are described in sufficient detail to enable those of ordinary skill in the art to practice the examples of this disclosure and it is to be understood that other examples may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. Further, where appropriate, as used herein, “for example’ and “by way of example” should be understood as abbreviations for “by way of example and not by way of limitation”.
- The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 111 may reference element “11” in
FIG. 1 , and a similar element may be referenced as 211 inFIG. 2 . Elements shown in the various figures herein may be added, exchanged, and/or eliminated so as to provide a number of additional examples of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the examples of the present disclosure and should not be taken in a limiting sense. - A non-volatile
resistive memory cell 105, as illustrated inFIG. 1 , may be formed at each location where the conductor lines intersect in thearray 100. The non-volatileresistive memory cell 105 can be interfaced with theconductor line 102 in thefirst group 101 to serve as a top electrode or the non-volatileresistive memory cell 105 can be interfaced with an intervening conductive material (not shown) to serve as the top electrode. Similarly, the non-volatileresistive memory cell 105 can be interfaced with theconductor line 104 in thesecond group 103 to serve as a bottom electrode or the non-volatileresistive memory cell 105 can be interfaced with an intervening conductive material (not shown) to serve as the bottom electrode. - A region containing a
switching element 107 is between the top andbottom conductor lines protective spacer material 109 can, in various examples as described herein, be formed on at least one sidewall of at least a portion of the non-volatile resistive memory cell 105 (e.g., to passivate that portion of the non-volatile resistive memory cell against damage, contamination, etc., during subsequent processing of array 100). Other spaces between the top andbottom conductor lines spacer material 109 of thearray 100 may be filled with a dielectric material to form an interlayer dielectric (ILD), which for clarity of illustration is not explicitly shown inFIG. 1 . As described herein, thespacer material 109 is different from the dielectric material of the ILD in that thespacer material 109 can be selected to be unreactive with the switching element of the non-volatile resistive memory cell or, in various examples, can serve as the switching element. -
FIG. 2 illustrates an example of a schematic perspective view of a non-volatile resistive memory cell and associated components according to the present disclosure. The example of the memory cell and associatedcomponents 210 shown inFIG. 2 includes a bottom contact structure that can have a conductive line 212 (e.g., a word line) and a bottom electrode 214, and a top contact structure that includes atop electrode 220 and a conductive line 222 (e.g., a bit line). Between the bottom andtop electrodes 214, 220 is a region that contains at least a portion of the material (e.g., including memristive material) for the non-volatile resistive memory cell 224 (e.g., a memristor), which in some examples can include a switching element. As described further herein, a switching element is formed from a memristive material that has electrical characteristics that depend on a state variable (e.g., resistivity) that can be controllably modified to allow a device (e.g., a memristor) to be switched to an ON state with a low-resistance value and an OFF state with a high-resistance value, or intermediate states between the ON and OFF states. - Each of the bottom and
top electrodes 214, 220 may have a width on the nanoscale. As used hereinafter, the term “nanoscale” indicates that an object has one or more dimensions less than one micrometer. In some examples, nanoscale can indicate that an object has one or more dimensions less than 100 nanometers (nm). For example, the bottom andtop electrodes 214, 220 may have a width in a range of from 5 nm to 500 nm. Likewise, the region that contains at least a portion of the material for thememory cell 224 may have a height that is from a few nanometers to tens of nanometers. - The structure, function, and/or arrangement of the conductive line 212 (e.g., the word line), the bottom electrode 214, the
top electrode 220, and/or the conductive line 222 (e.g., the bit line) are presented below by way of example and not by way of limitation. That is, in some examples, the bottom andtop electrodes 214, 220 may provide sufficient conductivity and/or low resistance and theword line 212 andbit line 222 may not be necessary or theword line 212 andbit line 222 may provide sufficient conductivity and/or low resistance and the bottom andtop electrodes 214, 220 may not be necessary, among other modifications that achieve the same or similar functions. - As such, in the example shown in
FIG. 2 , theword line 212,bit line 222, and the bottom andtop electrodes 214, 220 are electrically conductive but may be formed of different materials. In some examples, theword line 212 andbit line 222 may provide high conductivity and/or low resistance and, as such, may be formed by processes appropriate for forming on the nanoscale, for example, tungsten (W), copper (Cu), and/or aluminum (Al) conductor lines, among other suitably conductive materials. The bottom andtop electrodes 214, 220 may be formed of a conductive material selected, for example, to prevent the material thereof from interacting with the switching element material. As such, the conductive material may be a metal such as, for example, platinum (Pt), gold (Au), copper (Cu), tantalum (Ta), tungsten (W), etc., metallic compounds such as, for example, titanium nitride (TiN), tungsten nitride (WN), etc., and/or doped or undoped semiconductor materials, among other suitably conductive materials. - In the example shown in
FIG. 2 , thetop electrode 220 extends at an angle to the bottom electrode 214. The angle may be, for example, around 90 degrees, but may intersect at other angles depending on design choices. Because the bottom andtop electrodes 214, 220 are on different planes, and the region that contains the material for the portion of thememory cell 224 may be positioned at an area of overlap between the electrodes, structural support can, in various examples, be provided. Accordingly, spaces around and/or between the bottom andtop electrodes 214, 220 and outside the region that contains the material (e.g., including the memristive material) for the portion of thememory cell 224 and associated components can be filled with a dielectric material, in various examples, to form anILD 226. TheILD 226 can provide structural support and/or electrically insulate the bottom andtop electrodes 214, 220. TheILD 226 also can shield (e.g., isolate) the material for the portion of thememory cell 224 and associated components from material of adjacent memory cells (e.g., switching elements) and associated components. - As described in further detail herein, the memory cell and associated
components 210 can, in various examples, have aspacer material 228. Thespacer material 228 can be different from the material of theILD 226 in that thespacer material 228 can be selected to be unreactive with a switching element of the memory cell, to protect the switching element from damage, contamination, etc., during subsequent processing (e.g., formation of the ILD), to direct flow of oxygen vacancies, and/or, in various examples, to serve as the switching element. In various examples, thespacer material 228 can be formed on at least one (e.g., one or more) sidewall of the material for the portion of thememory cell 224. In some examples (e.g., as shown inFIG. 2 ), thespacer material 228 can be formed to surround the sidewalls (e.g., to extend in height between at least the bottom and top electrodes 214, 220). As such, the spacer material can shield (e.g., isolate) the material for the portion of thememory cell 224 from, for example, theILD 226 and/or other components (e.g., during and after processing and/or formation of the same). - To facilitate understanding of issues addressed by the present disclosure, the components and operational principles of the non-volatile resistive memory cell and associated components 210 (e.g., a memristor) are described with reference to
FIG. 2 . As shown inFIG. 2 , the portion of thememory cell 224 between the bottom andtop electrodes 214, 220 can, in various examples, contain memristive material for a switching element. The switching element is capable of carrying a species of mobile ionic dopants such that the dopants can be controllably transported through the switching element and redistributed to change electrical properties of either the switching element or an interface of the switching element and an electrode. This ability to change the electrical properties as a function of dopant distribution allows the switching element to be placed in different switching states by applying a switching voltage from a voltage source (not shown) to the bottom and/ortop electrodes 214, 220. - In various examples, the portion of the
memory cell 224 between the bottom andtop electrodes 214, 220 can include an active region that has two sub-regions: a primary active region and a dopant source region. The primary active region can contain material for the memristive switching element. In various instances, memristive material for the switching element may be electronically resistive (e.g., semiconducting or nominally insulating with a weak ionic conducting capacity). - Many different materials can be used as memristive materials for switching elements. Materials that exhibit suitable properties for switching include oxides, sulfides, selenides, nitrides, carbides, phosphides, arsenides, chlorides, and bromides of transition and rare earth metals. Suitable switching materials also include elemental semiconductors such as Si and Ge, including binary, ternary, and quaternary compounds thereof, and compound semiconductors such as III-V and II-VI compound semiconductors. The III-V semiconductors include, for instance, BN, BP, BSb, AlP, AlSb, GaAs, GaP, GaN, InN, InP, InAs, and InSb, and ternary and quaternary compounds. The II-VI compound semiconductors include, for instance, CdSe, CdS, CdTe, ZnSe, ZnS, ZnO, and ternary compounds. The suitable materials include GeO, SiGe, GeSb, SiGeSb, GeSbTe, and GaInZnO, among other compounds. The II-VI compound materials may also include phase change materials. In addition, PCRAM and STT-RAM technologies can be included as memristive materials. The materials may also include filament structures such as a-Si:Ag that has Ag filaments in an a-Si matrix. These listings of possible switching materials are presented by way of example and do not restrict the scope of the present disclosure.
- Dopant species from the dopant source region can be used to alter the electrical properties of the material of the switching element. As utilized in the present disclosure, the dopant species also are considered memristive materials. Which one or more of the dopant species are combined with the material of the switching element depends on the particular type of switching material utilized. As such, the dopant species may be cations, anions, vacancies, and/or impurities acting, for example, as electron donors or acceptors. For instance, in the case of transition metal oxides (TMOs) (e.g., TiO2, TaOx, among others), the dopant species acting as the state variable may be charged oxygen vacancies (VO 2+) or ions. For nitrides (e.g., BN, GaN, InN, among others), the dopant species acting as the state variable may be charged nitride vacancies and/or sulfide ions. For compound semiconductors, the dopants acting as the state variable may be n-type or p-type impurities.
- The dopant source region can contain a dopant source material that functions as a source/sink of dopants that can be driven into or out of the switching material in the primary active region to alter the overall resistance of the switching element. The dopant source material may be generally the same as the switching material but with a higher dopant concentration. For example, if the switching material is TiO2, the dopant source material may be TiO2-x where x is a number significantly smaller than 1, such as from 0.01 to 0.1. In this case, the TiO2-x material can act as a source/sink of charged oxygen vacancies (VO 2+) or ions that can drift into and through the TiO2 switching material in the primary active region. Accordingly, the non-volatile
resistive memory cell 210 illustrated inFIG. 2 can be switched between ON and OFF states by controlling the concentration and distribution of dopants in the primary active region. - Switching materials that use dopants (e.g., charged oxygen vacancies or ions) may have a DC switching voltage from a voltage source applied to top and bottom electrodes to create an electric field across the switching element. The electric field, if of sufficient strength and proper polarity, may drive the oxygen vacancies to drift through the switching element toward an electrode, thereby turning the device into an ON state. If the polarity of the electric field is reversed, the oxygen vacancies may drift in an opposite direction across the switching element and away from the electrode, thereby turning the device into an OFF state. In this way, the switching is reversible and may be repeated. Due to a relatively large electric field to cause dopant drifting, after the switching voltage is removed the locations of the oxygen vacancies may remain stable in the switching element. As such, the switching may be non-volatile and the switching element can be utilized for a non-volatile resistive memory cell.
- As an example of utilizing memristive materials as described herein, and not by way of limitation, in non-volatile resistive memory cells (e.g., a memristor), a switching oxide (e.g., a TMO such as TiO2) can be substantially lacking oxygen vacancies and can be formed in contact with a sub-oxide (e.g., Ti4O7) that is rich in oxygen vacancies due, for instance, to insufficient pairing of unpaired Ti electrons with unpaired O electrons. The switching can occur when the charged oxygen vacancies or ions in the sub-oxide migrate into the switching oxide under the influence of an applied electrical field (e.g., to create a conducting channel through the switching oxide).
- It is understood in all following examples that the path of least electrical resistance between the top and bottom electrodes traverses through the switching element located immediately between them and not through a path traversing a sidewall spacer and/or the ILD. A notable exception to this is where materials for the sidewall spacer are intentionally selected to be lower in electrical resistance (e.g., less resistive) than materials constituting components that would otherwise be located in a position of the switching element. In that case, the sidewall spacer is the actual switching element, while a stack of materials located immediately between the electrodes contains materials that act as a higher-resistance blocking element (e.g., insulator) that can shunt the electrical path through the sidewall spacer functioning as the switching element.
- In some examples, a bottom electrode and a top electrode can sandwich the switching oxide and/or the sub-oxide to form a non-volatile resistive memory cell. In order to form an addressable array of non-volatile resistive memory cells, the top and bottom electrodes can, for example, be patterned (e.g., by suitable etching techniques) into lines, the set of top electrodes generally aligned perpendicularly to the set of bottom electrodes, as shown in
FIG. 1 . - During formation of such memory cells and/or arrays, the oxide switching element between the bottom electrode and the top electrode may be deposited as a layer that is substantially parallel to an underlying substrate and to layers that constitute precursors for the bottom and top electrodes. When patterned, both the switching oxide and the sub-oxide layers may be deposited onto the substrate and processed together, for instance, patterned (e.g., by suitable etching techniques) into a vertically standing “resistor column” to bridge the two electrodes. This process may introduce damage and/or contamination to the switching oxide, especially at sidewalls of the patterned resistor. For instance, etch-induced damage, such as dangling chemical bonds and/or metallic reaction products or etch residue, etc., could induce creation of electrical paths between the electrodes that are not dependent on intended signals for switching of the oxide (e.g., a TMO). Therefore, it is advantageous to reduce such damage to, and/or contamination, of the switching oxide and/or associated components. In various examples presented herein, such damage and/or contamination can be reduced (e.g., passivated) by forming (e.g., depositing) at least a portion of the switching element (e.g., a TMO) and/or associated components after a number of particular portions of the processing has been performed (e.g., depositing and/or etching of other components).
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FIG. 3 is an example of a schematic cross-sectional view of a non-volatile resistive memory cell with a switching element formed on a sidewall of a first portion thereof according to the present disclosure. The non-volatile resistive memory cell (e.g., a memristor) and associatedcomponents 330 illustrated inFIG. 3 show a schematic cross-sectional view of a conductive line 332 (e.g., a word line) and abottom electrode 334 formed thereon or, in some examples, precursors thereof (e.g., layers of conductive line and bottom electrode materials). As illustrated, theconductive line 332 and thebottom electrode 334 extend left to right substantially in the plane ofFIG. 3 . In some examples, theconductive line 332 and the precursor thereof can be formed from a material that includes tungsten (W), although other materials can be used (e.g., aluminum (Al) and/or copper (Cu), among others), and thebottom electrode 334 and the precursor thereof can be formed from a material that includes titanium nitride (TiN), although other materials can be used (e.g., tantalum nitride (TaN) and/or platinum (Pt), among others). - As an example of utilizing memristive materials as described herein, and not by way of limitation, a sub-oxide layer, as described herein, can be formed (e.g., deposited) on an exposed surface of the precursor layer of the bottom electrode. In various examples, an insulating layer can be formed (e.g., deposited) on an exposed surface of the sub-oxide layer and a precursor layer for a second electrode can be formed (e.g., deposited) on an exposed surface of the insulating layer. The precursor layer for the second electrode can, in some examples, be formed to serve as a hard mask for subsequent etching processes. For example, suitable patterning and etching techniques can be utilized to form a vertically-extending first portion of the non-volatile
resistive memory cell 335 on thebottom electrode 334, where thefirst portion 335 has a sub-oxide 337, aninsulator 339, and/or at least part of asecond electrode 341 extending across a width of thefirst portion 335. In some examples, at least part of the second electrode precursor serving as thehard mask 343 can be removed by the etching technique that forms the vertically-extending first portion of the non-volatileresistive memory cell 335. - A switching material 344 (e.g., a switching element) can be formed (e.g., deposited) as a second portion of the non-volatile resistive memory cell on at least one sidewall of the vertically-extending first portion of the non-volatile
resistive memory cell 335. Deposition of the switchingmaterial 344 can be implemented by spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or plasma enhanced atomic layer deposition (PEALD), among other techniques. For example, the switchingmaterial 344 can be deposited (e.g., to substantially a uniform thickness via ALD) to a nanoscale thickness (e.g., up to 5 nm thick) to form a vertically-extending structure as the switching element. In some examples, the switchingmaterial 344 can be formed to surround the sidewalls of the vertically-extending first portion of the non-volatile resistive memory cell 335 (e.g., as shown inFIG. 2 ). - The nanoscale thickness of the
switching element 344 can define a size of acurrent path 345 between the sub-oxide 337 and the part of asecond electrode 341. When thecurrent path 345 between thefirst electrode 334 and thesecond electrode 341 is directed (e.g., by the insulator 339) through the vertically-extendingswitching element 344, the effective junction area can be reduced to the cross-sectional area of the thickness of the junction, thereby reducing an OFF state current and an overall current level. In some examples, the vertically-extendingswitching element 344 may be protected (e.g., passivated) from further processing by an insulating layer (not shown) that covers the vertically-extendingswitching element 344. In some examples, the vertically-extendingswitching element 344 and/or the insulating layer can be formed into a sidewall spacer structure along the sidewalls of the first portion of the non-volatile resistive memory cell 335 (e.g., via anisotropic vertical reactive ion etching). - An
ILD 347 material can, in various examples, be formed (e.g., deposited) on the portions of the non-volatile resistive memory cell (e.g., 335 and 344) just described. Atrench 346 can be formed in the ILD 347 (e.g., via suitable patterning and/or etching techniques, such as photolithography and/or wet or dry etching techniques, among others) with a long axis substantially orthogonal to theconductive line 332 and/or thebottom electrode 334 and to a depth that exposes at least a portion of a surface of the portion of thesecond electrode 341. - Another portion of the
second electrode 348 can, in various examples, be formed (e.g., deposited) in thetrench 346 to connect with the previously formed portion of thesecond electrode 341. The two portions of thesecond electrode second electrode 348 can be deposited (e.g., to a substantially uniform thickness via ALD) to form acavity 349 in thetrench 346. Thecavity 349 can be filled with suitable material (e.g., via suitable deposition techniques) to form a conductive line (e.g., a bit line). There may be multiple non-volatile resistive memory cells (e.g., memristors) and associatedcomponents 330 formed as just described into an array, as presented with regard toFIGS. 1 and 2 . - The non-volatile resistive memory cells (e.g., memristors) and associated
components 330 can be formed from various materials, as described herein by way of example and not by way of limitation. For example, when present, a sub-oxide (e.g., as shown inFIGS. 3-4 and 6-7) can be formed from at least one TMO. The switching element (e.g., as shown inFIGS. 3-4 and 6-7) can be formed from at least one TMO that is more resistive (e.g., less oxygen-deficient) than the sub-oxide. That is, the sub-oxide material can have more charged oxygen vacancies or ions than the switching element material. For example, the switching material can be TiO2, TaOx, among others, and the sub-oxide material can be TiO2-x (e.g., Ti2O3), TaOx-y, among others. - An insulator (e.g., as shown in
FIG. 3 ) can, for example, be formed from SiO2 and/or Si3N4, among other suitable insulating materials. The ILD can, for example, be formed from a silicon oxide (e.g., SiO2), a silicon nitride, and/or a silicon carbon nitride, among others. The top conductive line (e.g., bit line) (e.g., as shown inFIGS. 3-4 and 6-7) can, in some examples, be formed from the same material as the bottom conductive line (e.g., word line) (e.g., tungsten (W)) or a different material (e.g., copper (Cu), and/or aluminum (Al), among other suitably conductive materials). The portions of the second electrode (e.g., as shown inFIGS. 3-4 and 6-7) can, in some examples, be formed from the same material as the first electrode (e.g., TiN) or a different material (e.g., tantalum nitride (TaN) and/or platinum (Pt), among other suitably conductive materials). -
FIG. 4 is an example of a schematic cross-sectional view of a non-volatile resistive memory cell with a spacer formed on a sidewall thereof according to the present disclosure. The non-volatile resistive memory cell (e.g., a memristor) and associatedcomponents 450 illustrated inFIG. 4 show a schematic cross-sectional view of a conductive line 432 (e.g., a word line) and abottom electrode 434 formed thereon or, in some examples, precursors thereof (e.g., layers of conductive line and bottom electrode materials), substantially as described with regard toFIG. 3 . - As an example of utilizing memristive materials as described herein, and not by way of limitation, a sub-oxide layer, as described herein, can be formed (e.g., deposited) on an exposed surface of the precursor layer of the bottom electrode. In various examples, a switching material layer can be formed (e.g., deposited) on an exposed surface of the sub-oxide layer and a precursor layer for a second electrode can be formed (e.g., deposited) on an exposed surface of the switching material layer. The precursor layer for the second electrode can, in some examples, be formed to serve as a hard mask for subsequent etching processes. For example, suitable patterning and etching techniques can be utilized to form a vertically-extending first portion of the non-volatile
resistive memory cell 435 on thebottom electrode 434, where thefirst portion 435 has a sub-oxide 437, aswitching element 451, and/or at least part of asecond electrode 441 extending across a width of thefirst portion 435. In some examples, at least part of the second electrode precursor serving as thehard mask 443 can be removed by the etching technique that forms the vertically-extending first portion of the non-volatileresistive memory cell 435. - In some examples, the vertically-extending first portion of the non-volatile
resistive memory cell 435 may be protected (e.g., passivated) from further processing by aspacer layer 453 that covers the vertically-extending first portion of the non-volatileresistive memory cell 435, including theswitching element 451. In some examples, thespacer layer 453 can be formed into a sidewall spacer structure along the sidewalls of the first portion of the non-volatile resistive memory cell 435 (e.g., via anisotropic vertical reactive ion etching). In some examples, thespacer layer 453 can be formed to surround the sidewalls of the vertically-extending first portion of the non-volatile resistive memory cell 435 (e.g., as shown inFIG. 2 ). - As described herein, the non-volatile resistive memory cells (e.g., memristors) and associated
components 450 can be formed from various materials, as described herein by way of example and not by way of limitation. For example, when present, a sub-oxide (e.g., as shown inFIGS. 3-4 and 6-7) can be formed from at least one TMO. The switching element (e.g., as shown inFIGS. 3-4 and 6-7) can be formed from at least one TMO that is more resistive (e.g., less oxygen-deficient) than the sub-oxide. That is, the sub-oxide material can have more charged oxygen vacancies or ions than the switching element material. For example, the switching material can be TiO2, TaOx, among others, and the sub-oxide material can be TiO2-x (e.g., Ti2O3), TaOx-y, among others. Thespacer layer 453 shown inFIG. 4 can be formed from a material that is no more resistive (e.g., no less oxygen-deficient) than the switching element material. For example, thespacer layer 453 and theswitching element 451 both can be formed from TiO2, or thespacer layer 453 can be formed from Ta2O5 when the switchingelement 451 is formed from TiO2, among other such combinations. -
FIG. 4 shows that (e.g., similar toFIG. 3 ) anILD 447 material can, in various examples, be formed (e.g., deposited) on the portions of the non-volatile resistive memory cell (e.g., 435 and 453) just described. Atrench 446 can be formed in the ILD 447 (e.g., via suitable patterning and/or etching techniques) with a long axis substantially orthogonal to theconductive line 432 and/or thebottom electrode 434 and to a depth that exposes at least a portion of a surface of the portion of thesecond electrode 441. - Another portion of the
second electrode 448 can, in various examples, be formed (e.g., deposited) in thetrench 446 to connect with the previously formed portion of thesecond electrode 441. In various examples, the material for thesecond electrode 448 can be deposited (e.g., to a substantially uniform thickness via ALD) to form acavity 449 in thetrench 446. Thecavity 449 can be filled with suitable material (e.g., via suitable deposition techniques) to form a conductive line (e.g., a bit line). There may be multiple non-volatile resistive memory cells (e.g., memristors) and associatedcomponents 450 formed as just described into an array, as presented with regard toFIGS. 1 and 2 . -
FIG. 5 is a block diagram of a non-volatile resistive memory cell formed according to the present disclosure. As shown inblock 555 and consistent with the examples illustrated inFIGS. 3 and 4 , a non-volatile resistive memory cell can include a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure (e.g., 335, 435) on a first electrode (e.g., 334, 434), where the first portion comprises at least one memristive material (e.g., 337 or 437 and 451) across a width of the vertically-extending structure. As shown inblock 557, the non-volatile resistive memory cell also can include a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion (e.g., 344, 453). - As described herein, among other possibilities, the memristive material can be formed from at least one TMO (e.g., various oxides of Ti and/or Ta, among others). As further described herein, the second portion can, for example, surround sidewalls of the first portion to passivate the first portion (e.g., from subsequent processing). The first portion (e.g., 335) can, in various examples, include a first memristive material (e.g., 337) and the second portion (e.g., 344) can include a second memristive material as a switching element, where the second memristive material is more resistive than the first memristive material. The first portion (e.g., 335) can, in various examples, include an insulator (e.g., 339) between the first memristive material (e.g., 337) and a second electrode (e.g., 341). Alternatively, the first portion (e.g., 435) can, in various examples, include a first memristive material (e.g., 437) and a second memristive material (e.g., 451), where the second memristive material is a switching element and is more resistive than the first memristive material, and the second portion (e.g., 453) can, in various examples, include a third memristive material that is no less resistive than the second memristive material.
-
FIG. 6 is an example of a schematic cross-sectional view of a non-volatile resistive memory cell with a switching element formed on a sidewall of a top electrode according to the present disclosure. The non-volatile resistive memory cell (e.g., a memristor) and associatedcomponents 660 illustrated inFIG. 6 shows a schematic cross-sectional view of a conductive line 632 (e.g., a word line) and abottom electrode 634 formed thereon or, in some examples, precursors thereof (e.g., layers of conductive line and bottom electrode materials), as described herein. - As an example of utilizing memristive materials as described herein, and not by way of limitation, a sub-oxide layer, as described herein, can be formed (e.g., deposited) on an exposed surface of the precursor layer of the bottom electrode. In various examples, a hard mask for subsequent etching processes can be formed (e.g., deposited) on an exposed surface of the sub-oxide layer. For example, suitable patterning and/or etching techniques can be utilized to form a vertically-extending first portion of the non-volatile
resistive memory cell 635 on thebottom electrode 634, where thefirst portion 635 has a sub-oxide 637 extending across a width of thefirst portion 635. In some examples, thehard mask 643 can be removed by the etching technique that forms the vertically-extending first portion of the non-volatileresistive memory cell 635 to expose at least a portion of a surface of the sub-oxide 637. - In some examples, the vertically-extending first portion of the non-volatile
resistive memory cell 635 may be protected (e.g., passivated) from further processing by aspacer layer 661 that covers the vertically-extending first portion of the non-volatileresistive memory cell 635. In some examples, thespacer layer 661 can be formed into a sidewall spacer structure along the sidewalls of the first portion of the non-volatile resistive memory cell 635 (e.g., via anisotropic vertical reactive ion etching). In some examples, thespacer layer 661 can be formed to surround the sidewalls of the vertically-extending first portion of the non-volatile resistive memory cell 635 (e.g., as shown inFIG. 2 ). Thespacer layer 661 can, for example, be formed from a material that is substantially non-reactive with the sub-oxide 637 and/or anILD 647 material (e.g., various nitrides, such as a silicon nitride and/or a silicon carbon nitride, among others). AnILD 647 material can, in various examples, be formed (e.g., deposited) on the first portion of the non-volatile resistive memory cell (e.g., 635) just described. - A trench can be formed in the ILD 647 (e.g., via suitable patterning and/or etching techniques) with a long axis substantially orthogonal to the
conductive line 632 and/or thebottom electrode 634 and to a depth that exposes at least a portion of a surface of the sub-oxide 637. In various examples, the trench can be formed to have two parts. For example, the trench can have alower part 662 that exposes at least the portion of the surface of the sub-oxide 637. In some examples, the lower part of thetrench 662 can be formed with a frustoconical cross-section having a truncated end exposing at least the portion of the surface of the sub-oxide 637 and a wider distal end connecting with anupper part 665 of the trench at a particular height above the truncated end. As such, sidewalls of thelower part 662 can be formed at angles to connect with theupper part 665 that is wider than the truncated end of thelower part 662 of the trench and, in some examples, the wider distal end of thelower part 662 of the trench. Theupper part 665 can, in some examples, have sidewalls formed substantially perpendicular to theconductive line 632 and/or thebottom electrode 634. - A second portion of the of the non-volatile resistive memory cell can be formed (e.g., deposited to a substantially uniform thickness via ALD) as a switching material 663 (e.g., a switching element) on at least one sidewall of the
lower portion 662 of the trench as a vertically-extending structure (e.g., in contact with at least a portion of the exposed surface of the sub-oxide 637 and extending to the particular height above the truncated end) to connect with, for example, theupper part 665 of the trench. In some examples, the switching material 663 (e.g., the switching element) can be formed to cover both sidewalls of thelower part 662 of the trench to the particular height, along with substantially the entire exposed upper surface of the sub-oxide 637. As such, afirst cavity 664 can, in various examples, be formed within the switchingelement 663 in thelower part 662 of the trench. - Forming the
switching element 663 subsequent to, for example, suitable patterning and/or etching techniques utilized to form the vertically-extending first portion of the non-volatileresistive memory cell 635, forming theILD 647, and/or suitable patterning and/or etching techniques utilized to form the upper 665 and/or lower 662 portions of the trench can reduce damage and/or contamination (e.g., passivate) resulting from such processing (e.g., to the switching element 663). - In some examples, at least a portion of a second electrode material (e.g., as described herein) can be formed (e.g., deposited) within the
first cavity 664 to form a via within thefirst cavity 664. The second electrode material can, in some examples, form the via within thefirst cavity 664 to substantially the particular height above the truncated end to connect with, for example, theupper part 665 of the trench. Hence, the switchingelement 663 is formed on the sidewalls of the via (e.g., the second, or top, electrode) within thefirst cavity 664. - In some examples, at least a portion of a
second electrode material 667 can be formed (e.g., deposited to a substantially uniform thickness via ALD) in theupper part 665 of the trench. The second electrode material 667 (as described herein) can be the same as or different from the second electrode material utilized to form the via within thefirst cavity 664. When utilized, thesecond electrode material 667 can cover the sidewalls and the bottom ofupper part 665 of the trench to connect with the second electrode material utilized to form the via within thefirst cavity 664. Thesecond electrode material 667 can be formed (e.g., deposited) within theupper part 665 of the trench to form asecond cavity 668. - A conductive material (e.g., as described herein) can, in various examples, be formed (e.g., deposited) within the second cavity 668 (e.g., to form a top conductive material or bit line). In some examples, the conductive material can, in various examples, be formed (e.g., deposited) directly within the
upper part 665 of the trench (e.g., without the second electrode material 667) to connect with the second electrode material utilized to form the via within thefirst cavity 664. There may be multiple non-volatile resistive memory cells (e.g., memristors) and associatedcomponents 660 formed as just described into an array, as presented with regard toFIGS. 1 and 2 . -
FIG. 7 is another example of a schematic cross-sectional view of a non-volatile resistive memory cell with a switching element formed on a sidewall of a top electrode according to the present disclosure. The non-volatile resistive memory cell (e.g., a memristor) and associatedcomponents 770 illustrated inFIG. 7 show a schematic cross-sectional view of a conductive line 732 (e.g., a word line) and abottom electrode 734 formed thereon or, in some examples, precursors thereof (e.g., layers of conductive line and bottom electrode materials), as described herein. - Suitable patterning and/or etching techniques can be utilized to form a vertically-extending first portion of a non-volatile
resistive memory cell 735 on thebottom electrode 734 substantially as described herein with regard toFIG. 6 . AnILD 747 material can, in various examples, be formed (e.g., deposited) on the first portion of the non-volatile resistive memory cell (e.g., 735) substantially as described herein. - A
trench 762 can be formed in the ILD 747 (e.g., via suitable patterning and/or etching techniques) with a long axis substantially orthogonal to theconductive line 732 and/or thebottom electrode 734 and to a depth that exposes at least a portion of a surface of the sub-oxide 737. In various examples, the trench can be formed to have a lower part that exposes at least the portion of the surface of the sub-oxide 737. In some examples, the lower part of the trench can be formed with a frustoconical cross-section having a truncated end exposing at least the portion of the surface of the sub-oxide 737 and a wider distal part transitioning to an upper part of the trench (e.g., at a particular height above the truncated end). As such, sidewalls of the lower part of thetrench 762 can be formed at angles to connect with the upper part of thetrench 762 that is wider than the truncated end of the lower part of the trench. The upper part of thetrench 762 can, in some examples, have sidewalls formed substantially perpendicular to theconductive line 732 and/or thebottom electrode 734. - A second portion of the of the non-volatile resistive memory cell can be formed (e.g., deposited to a substantially uniform thickness via ALD) as a switching material 771 (e.g., a switching element) on at least one sidewall of the lower portion of the
trench 762 as a vertically-extending structure (e.g., in contact with at least a portion of the exposed surface of the sub-oxide 737). The switchingmaterial 771 can, in various examples, extend to whatever height is selected for a particular application (e.g., to a top of thetrench 762 and/or the ILD 747). In some examples, the switching material 771 (e.g., the switching element) can be formed to cover both sidewalls of thetrench 762 to the selected height, along with substantially the entire exposed upper surface of the sub-oxide 737. As such, a first cavity (not shown) can, in various examples, be formed within the switchingelement 771 in thetrench 762. - Forming the
switching element 771 subsequent to, for example, suitable patterning and/or etching techniques utilized to form the vertically-extending first portion of the non-volatileresistive memory cell 735, forming theILD 747, and/or suitable patterning and/or etching techniques utilized to form the portions of thetrench 762 can reduce damage and/or contamination (e.g., passivate) resulting from such processing (e.g., to the switching element 771). - In some examples, a second electrode material (e.g., as described herein) can be formed (e.g., deposited to a substantially uniform thickness via ALD) within the first cavity to form a
second electrode 773 within the first cavity. Thesecond electrode 773 can, in some examples, be formed within the first cavity to substantially the selected height of theswitching element 771 in thetrench 762. Hence, the switchingelement 771 is formed on the sidewalls of the second, or top, electrode within the first cavity. - The
second electrode material 773 can cover the sidewalls and the bottom of thetrench 762 to form asecond cavity 775. A conductive material (e.g., as described herein) can, in various examples, be formed (e.g., deposited) within the second cavity 775 (e.g., to form a top conductive material or bit line). There may be multiple non-volatile resistive memory cells (e.g., memristors) and associatedcomponents 770 formed as just described into an array, as presented with regard toFIGS. 1 and 2 . - Accordingly, consistent with the examples illustrated in
FIGS. 6 and 7 , a non-volatile resistive memory cell can include a first portion of the non-volatile resistive memory cell formed as a first vertically-extending memristive material structure (e.g., 635, 735) on a first electrode (e.g., 634, 734). The non-volatile resistive memory cell also can include a second portion of the non-volatile resistive memory cell (e.g., 663, 771) formed on at least one sidewall of a trench (e.g., 662, 762) as a second vertically-extending memristive material structure to contact an exposed upper surface of the first vertically-extending memristive material structure (e.g., 637, 737), where the second memristive material is a switching element. - In some examples, the first vertically-extending memristive material structure (e.g., 635, 735) is formed substantially from a sub-oxide, as described herein. In various examples, the second portion of the non-volatile resistive memory cell (e.g., 663, 771) can cover the exposed upper surface of the first vertically-extending memristive material structure (e.g., 637, 737) and sidewalls of the trench (e.g., 662, 762) to form a first cavity (e.g., 564). At least a portion of the second electrode can, in various examples, be formed as a via within the first cavity 564. At least a portion of the second electrode can, in various examples, cover a surface of the first cavity to form a second cavity (e.g., 568, 675).
- As such, a method of forming a non-volatile resistive memory cell, consistent with
FIGS. 3-7 , can include forming a precursor of a first portion of the non-volatile resistive memory cell as a vertically-extending structure (e.g., 335, 435, 635, 735) on a first electrode (e.g., 334, 434, 634, 734), where the first portion comprises at least one memristive material across a width of the vertically-extending structure (e.g., 337, 437, 451, 637, 737) and a hard mask material (e.g., 343, 443, 643, 743) above the at least one memristive material, where etching the precursor of the first portion of the non-volatile resistive memory cell can be utilized to form a patterned first portion of the non-volatile resistive memory cell (e.g., 335, 435, 635, 735). The patterned first portion of the non-volatile resistive memory cell (e.g., 335, 435, 635, 735) can be passivated by forming a spacer material around sidewalls (e.g., 344, 453, 661, 761) of the patterned first portion. Unless explicitly stated, the method examples described herein are not constrained to a particular order or sequence. Additionally, some of the described method examples, or elements thereof, can occur or be performed at the same, or substantially the same, point in time. - In various examples, forming the spacer material around the sidewalls (e.g., 344, 453, 661, 761) includes forming a memristive material that vertically-extends (e.g., 344, 453) from the first electrode (e.g., 334, 434, 634, 734) to a height of an upper one of the at least one memristive material (e.g., 337, 451, 637, 737) or a remaining portion of the hard mask material (e.g., 341, 441, 643, 743) of the patterned first portion (e.g., 335, 435, 635, 735). That is, as selected for a particular application, the spacer material around the sidewalls (e.g., 344, 453, 661, 761) can extend from the first electrode to a top of an upper memristive material (e.g., a sub-oxide or a switching element) or to a top of the remaining portion of the hard mask material. In various examples, forming the memristive material that vertically-extends (e.g., 344, 453) includes forming a memristive material that is no less resistive than the least resistive of the at least one memristive material (e.g., 337, 437, 451, 637, 737) of the patterned first portion (e.g., 335, 435, 635, 735).
- In various examples, a trench (e.g., 346, 446, 662, 665, 762) can be formed in an ILD material (e.g., 347, 447, 647, 737) to expose at least part of a surface of the upper one of the at least one memristive material (e.g., 637, 737) or the remaining portion of the hard mask material (e.g., 341, 441) and, in various examples, a second portion of the non-volatile resistive memory cell can be formed as a switching element (e.g., 663, 771) to cover the exposed surface and sidewalls of the trench to form a first cavity (e.g., 564). At least a portion of a second electrode can, in various examples, be formed as a via within the first cavity (e.g., 564). At least a portion of a second electrode (e.g., 773) can, in various examples, be formed to cover a surface of the first cavity to form a second cavity (e.g., 568).
- Examples of the present disclosure can include non-volatile resistive memory cells (e.g., memristors) apparatuses, systems, and methods, including executable instructions and/or logic to facilitate fabricating and/or operating the non-volatile resistive memory cells (e.g., memristors), apparatuses, and systems. Processing resources can include one or more processors able to access data stored in memory to execute the formations, actions, functions, etc., as described herein. As used herein, “logic” is an alternative or additional processing resource to execute the formations, actions, functions, etc., described herein, which includes hardware (e.g., various forms of transistor logic, application specific integrated circuits (ASICs), etc.), as opposed to computer executable instructions (e.g., software, firmware, etc.) stored in memory and executable by a processor.
- It is to be understood that the descriptions presented herein have been made in an illustrative manner and not a restrictive manner. Although specific examples for non-volatile resistive memory cell (e.g., memristor) apparatuses, systems, methods, computing devices, and instructions have been illustrated and described herein, other equivalent component arrangements, instructions, and/or device logic can be substituted for the specific examples presented herein without departing from the spirit and scope of the present disclosure.
Claims (15)
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170243645A1 (en) * | 2014-11-25 | 2017-08-24 | Hewlett-Packard Development Company, L.P. | Bi-polar memristor |
US20220077057A1 (en) * | 2020-09-06 | 2022-03-10 | Nanya Technology Corporation | Electrical fuse matrix |
US11557723B2 (en) * | 2019-02-18 | 2023-01-17 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115117236A (en) * | 2021-03-17 | 2022-09-27 | 华邦电子股份有限公司 | Resistive random access memory and manufacturing method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7675052B2 (en) * | 2006-09-22 | 2010-03-09 | Hynix Semiconductor Inc. | Nonvolatile memory device and fabrication method thereof |
US8921155B2 (en) * | 2011-04-12 | 2014-12-30 | Freescale Semiconductor, Inc. | Resistive random access memory (RAM) cell and method for forming |
US9111609B2 (en) * | 2008-08-26 | 2015-08-18 | International Business Machines Corporation | Concentric phase change memory element |
US9123888B2 (en) * | 2011-10-17 | 2015-09-01 | Micron Technology, Inc. | Memory cells and memory cell arrays |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6864503B2 (en) * | 2002-08-09 | 2005-03-08 | Macronix International Co., Ltd. | Spacer chalcogenide memory method and device |
US7812404B2 (en) | 2005-05-09 | 2010-10-12 | Sandisk 3D Llc | Nonvolatile memory cell comprising a diode and a resistance-switching material |
US7390691B2 (en) * | 2005-10-28 | 2008-06-24 | Intel Corporation | Increasing phase change memory column landing margin |
US7560337B2 (en) | 2006-01-09 | 2009-07-14 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
KR100855855B1 (en) * | 2006-10-04 | 2008-09-01 | 주식회사 하이닉스반도체 | Nonvolatile memory device and manufacturing method of the same |
US7616472B2 (en) | 2006-10-23 | 2009-11-10 | Macronix International Co., Ltd. | Method and apparatus for non-volatile multi-bit memory |
KR100801084B1 (en) | 2007-01-08 | 2008-02-05 | 삼성전자주식회사 | Nonvolatile memory device using variable resistive element and fabricating method thereof |
US7786461B2 (en) * | 2007-04-03 | 2010-08-31 | Macronix International Co., Ltd. | Memory structure with reduced-size memory element between memory material portions |
JP2008257789A (en) | 2007-04-04 | 2008-10-23 | Sharp Corp | Cross-point rram memory array having reduced bit line crosstalk |
KR100852206B1 (en) | 2007-04-04 | 2008-08-13 | 삼성전자주식회사 | Resist random access memory device and method for manufacturing the same |
US8034655B2 (en) | 2008-04-08 | 2011-10-11 | Micron Technology, Inc. | Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays |
US8105884B2 (en) | 2008-10-06 | 2012-01-31 | Samsung Electronics Co., Ltd. | Cross point memory arrays, methods of manufacturing the same, masters for imprint processes, and methods of manufacturing masters |
KR20110086089A (en) | 2008-10-20 | 2011-07-27 | 더 리젠츠 오브 더 유니버시티 오브 미시건 | A silicon based nanoscale crossbar memory |
US8623697B2 (en) | 2008-12-31 | 2014-01-07 | Micron Technology, Inc. | Avoiding degradation of chalcogenide material during definition of multilayer stack structure |
JP2010212541A (en) | 2009-03-12 | 2010-09-24 | Panasonic Corp | Nonvolatile memory device and method of manufacturing the same |
CN101840994B (en) | 2009-03-16 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory devices and manufacture method |
US8441839B2 (en) | 2010-06-03 | 2013-05-14 | Panasonic Corporation | Cross point variable resistance nonvolatile memory device |
KR20120012049A (en) | 2010-07-30 | 2012-02-09 | 서울대학교산학협력단 | Rram device with minimized contact of top electrode and fabrication method thereof |
US20120080725A1 (en) * | 2010-09-30 | 2012-04-05 | Seagate Technology Llc | Vertical transistor memory array |
JP5442876B2 (en) * | 2010-12-03 | 2014-03-12 | パナソニック株式会社 | Nonvolatile memory element, nonvolatile memory device and manufacturing method thereof |
-
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- 2012-07-31 EP EP12882243.4A patent/EP2880689A4/en not_active Withdrawn
- 2012-07-31 CN CN201280072903.XA patent/CN104303300B/en active Active
- 2012-07-31 KR KR20147030671A patent/KR20150041609A/en not_active Application Discontinuation
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7675052B2 (en) * | 2006-09-22 | 2010-03-09 | Hynix Semiconductor Inc. | Nonvolatile memory device and fabrication method thereof |
US9111609B2 (en) * | 2008-08-26 | 2015-08-18 | International Business Machines Corporation | Concentric phase change memory element |
US8921155B2 (en) * | 2011-04-12 | 2014-12-30 | Freescale Semiconductor, Inc. | Resistive random access memory (RAM) cell and method for forming |
US9123888B2 (en) * | 2011-10-17 | 2015-09-01 | Micron Technology, Inc. | Memory cells and memory cell arrays |
Non-Patent Citations (1)
Title |
---|
Partial translation of JP 2010-212541, June 2016 * |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US20170243645A1 (en) * | 2014-11-25 | 2017-08-24 | Hewlett-Packard Development Company, L.P. | Bi-polar memristor |
US10026476B2 (en) * | 2014-11-25 | 2018-07-17 | Hewlett-Packard Development Company, L.P. | Bi-polar memristor |
US11557723B2 (en) * | 2019-02-18 | 2023-01-17 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20230083978A1 (en) * | 2019-02-18 | 2023-03-16 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20220077057A1 (en) * | 2020-09-06 | 2022-03-10 | Nanya Technology Corporation | Electrical fuse matrix |
US20220102272A1 (en) * | 2020-09-06 | 2022-03-31 | Nanya Technology Corporation | Method of forming electrical fuse matrix |
US11621225B2 (en) * | 2020-09-06 | 2023-04-04 | Nanya Technology Corporation | Electrical fuse matrix |
US11955427B2 (en) * | 2020-09-06 | 2024-04-09 | Nanya Technology Corporation | Method of forming electrical fuse matrix |
Also Published As
Publication number | Publication date |
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WO2014021833A1 (en) | 2014-02-06 |
EP2880689A4 (en) | 2016-04-06 |
CN104303300B (en) | 2017-08-15 |
KR20150041609A (en) | 2015-04-16 |
CN104303300A (en) | 2015-01-21 |
EP2880689A1 (en) | 2015-06-10 |
US10008666B2 (en) | 2018-06-26 |
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