US20150027532A1 - Solar cell, solar cell module and method of manufacturing solar cell - Google Patents

Solar cell, solar cell module and method of manufacturing solar cell Download PDF

Info

Publication number
US20150027532A1
US20150027532A1 US14/453,769 US201414453769A US2015027532A1 US 20150027532 A1 US20150027532 A1 US 20150027532A1 US 201414453769 A US201414453769 A US 201414453769A US 2015027532 A1 US2015027532 A1 US 2015027532A1
Authority
US
United States
Prior art keywords
solar cell
side electrode
type surface
insulating layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/453,769
Inventor
Tsutomu Yamaguchi
Masayoshi Ono
Naoteru Matsubara
Tsuyoshi Takahama
Mitsuaki Morigami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Intellectual Property Management Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Assigned to SANYO ELECTRIC CO., LTD. reassignment SANYO ELECTRIC CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MORIGAMI, MITSUAKI, MATSUBARA, NAOTERU, TAKAHAMA, TSUYOSHI, ONO, MASAYOSHI, YAMAGUCHI, TSUTOMU
Publication of US20150027532A1 publication Critical patent/US20150027532A1/en
Assigned to PANASONIC CORPORATION reassignment PANASONIC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SANYO ELECTRIC CO., LTD.
Assigned to PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. reassignment PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PANASONIC CORPORATION
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0236Special surface textures
    • H01L31/02366Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0203Containers; Encapsulations, e.g. encapsulation of photodiodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441Electrode arrangements specially adapted for back-contact solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/03529Shape of the potential jump barrier or surface barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0376Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors
    • H01L31/03762Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors including only elements of Group IV of the Periodic System
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/547Monocrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/548Amorphous silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This disclosure relates to a solar cell, a solar cell module and a method of manufacturing a solar cell.
  • a back contact solar cell has been known as a solar cell achieving improved photoelectric conversion efficiency (for example, see Patent Document 1).
  • Patent Document 1 Japanese Patent Application Publication No. 2005-101151
  • An embodiment of the invention has an objective to provide a solar cell with improved photoelectric conversion efficiency.
  • a first aspect of the invention is a solar cell including a photoelectric conversion body, a p-side electrode, an n-side electrode, and an insulating layer.
  • the photoelectric conversion body includes a p-type surface and an n-type surface in one principal surface.
  • the p-side electrode is disposed on the p-type surface.
  • the n-side electrode is disposed on the n-type surface.
  • the insulating layer is disposed between the p-side electrode and the n-side electrode. A surface of the insulating layer has a convex shape.
  • a second aspect of the invention is a solar cell module.
  • the solar cell module includes the solar cell of the first aspect and a resin encapsulant.
  • the resin encapsulant seals the solar cell.
  • the insulating layer contains a resin.
  • a third aspect of the invention is a method of manufacturing a solar cell.
  • the method of manufacturing a solar cell includes: preparing a photoelectric conversion body including one principal surface provided with a p-type surface and an n-type surface; forming an insulating layer on a border portion between the p-type surface and the n-type surface in the one principal surface of the photoelectric conversion body in such a way that an exposed portion of the p-type surface and an exposed portion of the n-type surface are defined by the insulating layer; and after forming the insulating layer, forming a p-side electrode on the p-type surface and an n-side electrode on the n-type surface concurrently by plating.
  • a solar cell with improved photoelectric conversion efficiency can be provided.
  • FIG. 1 is a schematic cross sectional diagram of a solar cell according to a first embodiment.
  • FIG. 2 is a schematic cross sectional diagram of a solar cell module according to the first embodiment.
  • FIG. 3 is a schematic cross sectional diagram of a solar cell according to a second embodiment.
  • FIG. 4 is a schematic cross sectional diagram of a solar cell according to a third embodiment.
  • FIG. 5 is an exemplary cross sectional diagram of multiple solar cells stacked in the third embodiment.
  • FIG. 6 is a schematic cross sectional diagram of a solar cell according to a fourth embodiment.
  • solar cell 1 a includes photoelectric conversion body 10 having light-receiving surface 10 a and back surface 10 b.
  • Photoelectric conversion body 10 includes substrate 11 .
  • Substrate 11 is made of a semiconductor material.
  • Substrate 11 may be made of a crystalline semiconductor such as crystalline silicon, for example, or the like.
  • Substrate 11 has one conductivity type. Specifically, in the present embodiment, description is provided for an example where the conductivity type of substrate 11 is n-type.
  • Semiconductor layer 12 n made of an n-type semiconductor which is of the same conductivity type as substrate 11 is disposed on first principal surface 11 a located on a light-receiving surface 10 a side of substrate 11 .
  • First principal surface 11 a is substantially entirely covered with semiconductor layer 12 n.
  • Semiconductor layer 12 n may be made of n-type amorphous silicon or the like.
  • the thickness of semiconductor layer 12 n may be about 1 nm to 10 nm, for example.
  • a semiconductor layer made of a substantially-intrinsic i-type semiconductor may be provided between semiconductor layer 12 n and first principal surface 11 a.
  • the semiconductor layer has a thickness of about several ⁇ to 250 ⁇ , for example, with which the semiconductor layer cannot substantially contribute to power generation.
  • Anti-reflective layer 13 is disposed on a surface of semiconductor layer 12 n on the opposite side from substrate 11 .
  • Anti-reflective layer 13 has both a function to inhibit reflection and a function as a protective film.
  • Anti-reflective layer 13 constitutes light-receiving surface 10 a of photoelectric conversion body 10 .
  • Anti-reflective layer 13 may be made of, for example, silicon nitride or the like.
  • the thickness of anti-reflective layer 13 can be set as needed depending on a factor such as the wavelength of light whose reflection is to be inhibited.
  • the thickness of anti-reflective layer 13 may be, for example, about 50 nm to 200 nm.
  • Semiconductor layer 14 p made of a p-type semiconductor which is of a conductivity type different from substrate 11 is disposed on a portion of second principal surface 11 b of substrate 11 .
  • Semiconductor layer 15 n made of an n-type semiconductor which is of the same conductivity type as substrate 11 is disposed on at least part of the other portion of second principal surface 11 b of substrate 11 where no semiconductor layer 14 p is disposed.
  • second principal surface 11 b is substantially entirely covered with semiconductor layer 14 p and semiconductor layer 15 n.
  • Semiconductor layer 14 p and semiconductor layer 15 n maybe made of materials such as p-type amorphous silicon and n-type amorphous silicon, respectively.
  • Semiconductor layer 14 p and semiconductor layer 15 n constitute back surface 10 b of photoelectric conversion body 10 .
  • Semiconductor layer 14 p constitutes p-type surface 10 bp
  • semiconductor layer 15 n constitutes n-type surface 10 bn.
  • the thickness of semiconductor layer 14 p may be about 2 nm to 20 nm, for example.
  • the thickness of semiconductor layer 15 n may be about 5 nm to 50 nm, for example.
  • a semiconductor layer made of a substantially-intrinsic i-type semiconductor may be provided between semiconductor layer 14 p and second principal surface 11 b. This semiconductor layer has a thickness of about several ⁇ to 250 ⁇ , for example, with which the semiconductor layer cannot substantially contribute to power generation.
  • a semiconductor layer made of a substantially-intrinsic i-type semiconductor may be provided between semiconductor layer 15 n and second principal surface 11 b. This semiconductor layer has a thickness of about several ⁇ to 250 ⁇ , for example, with which the semiconductor layer cannot substantially contribute to power generation.
  • Such semiconductor layers made of substantially-intrinsic i-type semiconductors may be made of amorphous silicon or the like.
  • Insulating layer 16 is disposed between the end portions of semiconductor layer 14 p and semiconductor layer 15 n.
  • Insulating layer 16 maybe made of, for example, silicon nitride, silicon oxide or the like.
  • First seed layer 17 is disposed on semiconductor layer 14 p.
  • First seed layer 17 is a layer having a function as a seed to form p-side electrode 21 p by plating as described later.
  • second seed layer 18 is disposed on semiconductor layer 15 n.
  • Second seed layer 18 is a layer having a function as a seed to form n-side electrode 22 n by plating as described later.
  • First and second seed layers 17 , 18 may be each made of transparent conductive oxide such as indium tin oxide (ITO) or at least one kind of metal such as Cu or Ag.
  • Each of first and second seed layers 17 , 18 may be formed of a multilayer including a transparent conductive oxide layer and a metal layer disposed on the transparent conductive oxide layer, for example.
  • the thickness of each of first and second seed layers 17 , 18 may be about 0.1 ⁇ m to 1.0 ⁇ m.
  • P-side electrode 21 p to collect positive holes is disposed on first seed layer 17 disposed on p-type surface 10 bp.
  • P-side electrode 21 p is electrically connected to p-type surface 10 bp via first seed layer 17 .
  • n-side electrode 22 n to collect electrons is disposed on second seed layer 18 disposed on n-type surface 10 bn.
  • N-side electrode 22 n is electrically connected to n-type surface 10 bn via second seed layer 18 .
  • p-side electrode 21 p may be disposed directly on p-type surface 10 bp
  • n-side electrode 22 n may be disposed directly on n-type surface 10 bn.
  • Each of p-side electrode 21 p and n-side electrode 22 n may preferably include a plating film, or may be more preferably formed of a plating film.
  • each of p-side electrode 21 p and n-side electrode 22 n may be formed of a laminate of two or more plating films.
  • each of p-side electrode 21 p and n-side electrode 22 n may be formed of a multilayer of a first plating film made of Cu and a second plating film made of Sn, for example.
  • each of p-side electrode 21 p and n-side electrode 22 n may be about 20 ⁇ m to 30 ⁇ m.
  • Insulating layer 23 is disposed between p-side electrode 21 p and n-side electrode 22 n in a planar direction of back surface 10 b of photoelectric conversion body 10 .
  • Surface 23 a of insulating layer 23 has a convex shape. In other words, the cross-sectional shape of insulating layer 23 is a dome shape.
  • Insulating layer 23 is provided between and on top of end portions of first seed layer 17 and second seed layer 18 which are neighboring in the x-axis direction. Insulating layer 23 is embedded between first seed layer 17 and p-side electrode 21 p and between second seed layer 18 and n-side electrode 22 n.
  • Insulating layer 23 may be made of an inorganic insulating material such as silicon oxide or silicon nitride, for example, but maybe preferably made of an organic insulating material such as an epoxy resin, an acrylic resin or a urethane resin, for example, and more preferably made of a plating resist made of a resist material containing an epoxy resin.
  • an inorganic insulating material such as silicon oxide or silicon nitride
  • an organic insulating material such as an epoxy resin, an acrylic resin or a urethane resin, for example, and more preferably made of a plating resist made of a resist material containing an epoxy resin.
  • first seed layer 17 is formed on p-type surface 10 bp and second seed layer 18 is formed on n-type surface 10 bn.
  • First and second seed layers 17 , 18 may be formed by, for example, sputtering, a CVD (Chemical Vapor Deposition) technique, or the like.
  • insulating layer 23 is formed. Specifically, insulating layer 23 having convex-shaped surface 23 a is formed on each boundary portion between p-type surface 10 bp and n-type surface 10 bn of back surface 10 b of photoelectric conversion body 10 in such a manner that an exposed portion of p-type surface 10 bp and an exposed portion of n-type surface 10 bn are defined by insulating layer 23 .
  • a method of forming insulating layer 23 is not particularly limited. For example, in the case where insulating layer 23 is made of an organic insulating material, insulating layer 23 may be formed by, for example, a screen printing method, an inkjet method, a photolithography method, or the like.
  • p-side electrode 21 p is formed on p-type surface 10 bp and n-side electrode 22 n is formed on n-type surface 10 bn, concurrently.
  • insulating layer 23 it is preferable to form insulating layer 23 by using a plating resist.
  • insulating layer 23 disposed between p-side electrode 21 p and n-side electrode 22 n has convex-shaped surface 23 a. This makes it possible to secure a long distance on back surface 10 b between p-side electrode 21 p and n-side electrode 22 n. Thus, even if the distance in the x-axis direction between p-side electrode 21 p and n-side electrode 22 n is set short, high insulating resistance between p-side electrode 21 p and n-side electrode 22 n can be achieved. This enables achievement of improved photoelectric conversion efficiency.
  • the electrodes is formed over an area wider than the seed layers, and the p-side and n-side electrodes may come into contact with each other in some cases. To prevent contact between the p-side electrode and the n-side electrode, a large distance needs to be secured between the first seed layer and the second seed layer.
  • the present embodiment since the present embodiment has insulating layer 23 provided, the distance between first seed layer 17 and second seed layer 18 can be made short because p-side electrode 21 p and n-side electrode 22 n are kept from contacting each other.
  • the convex shape of surface 23 a of insulating layer 23 more effectively keeps p-side electrode 21 p and n-side electrode 22 n from contacting each other, and enables a much shorter distance between first seed layer 17 and second seed layer 18 . Accordingly, more improved photoelectric conversion efficiency can be achieved.
  • insulating layer 23 by using a plating resist more effectively keeps p-side electrode 21 p and n-side electrode 22 n from contacting each other, and enables a much shorter distance between first seed layer 17 and second seed layer 18 . Accordingly, more improved photoelectric conversion efficiency can be achieved.
  • Insulating layer 23 is provided between and on first seed layer 17 and second seed layer 18 .
  • a width of insulating layer 23 on the surface plane of first seed layer 17 and second seed layer 18 is longer than a width insulating layer 23 on the surface plane of semiconductor layer 14 p and semiconductor layer 15 n. For this reason, insulating layer 23 can inhibit first and second seed layers 17 , 18 from peeling off from photoelectric conversion body 10 .
  • FIG. 2 is a schematic cross-sectional diagram of a solar cell module in the first embodiment.
  • solar cell module 2 includes solar cell 1 a.
  • Solar cell la is sealed by resin encapsulant 30 .
  • Light-receiving surface member 31 is provided on a light-receiving surface 10 a side of resin encapsulant 30 .
  • back surface member 32 is provided on a back surface 10 b side of resin encapsulant 30 .
  • resin encapsulant 30 can more suitably seal solar cell 1 a, and can inhibit moisture or the like from reaching solar cell 1 a.
  • the adhesive strength between insulating layer 23 and resin encapsulant 30 is 75 N, and the adhesive strength between semiconductor layer 14 p and insulating layer 23 is 75 N or higher.
  • solar cell module 2 is configured such that semiconductor layer 14 p and resin encapsulant 30 adhere to each other. In this case, the adhesive strength between semiconductor layer 14 p and resin encapsulant 30 is 42 N.
  • insulating layer 23 leads to an increase in the adhesive strength between semiconductor layer 14 p and resin encapsulant 30 , and therefore makes it possible to inhibit entry of moisture or the like.
  • the adhesive strengths presented above were each measured by a test of tensile strength between the two kinds of layers.
  • resin encapsulant 30 may be made of a resin such for example as ethylene-vinyl acetate copolymer (EVA), polyvinyl butyral (PVB), polyethylene (PE), or polyurethane (PU).
  • EVA ethylene-vinyl acetate copolymer
  • PVB polyvinyl butyral
  • PE polyethylene
  • PU polyurethane
  • Light-receiving surface member 31 may be formed of, for example, a translucent or transparent glass plate, plastic plate or the like.
  • Back surface member 32 may be formed of, for example, a resin film such as a polyethylene terephthalate (PET) film, a multilayer film in which a metal foil such as an Al foil is inserted between stacked resin films, a steel sheet, or the like.
  • PET polyethylene terephthalate
  • FIG. 3 is a schematic cross sectional diagram of solar cell 1 b in a second embodiment. As illustrated in FIG. 3 , solar cell 1 b in the second embodiment is different from solar cell 1 a in the first embodiment in term of the configuration of photoelectric conversion body 10 . The configuration of photoelectric conversion body 10 in the present embodiment is described below.
  • Semiconductor layer 14 i made of a substantially-intrinsic i-type semiconductor is provided between substrate 11 and semiconductor layer 14 p.
  • Semiconductor layer 14 i has a thickness of about several ⁇ to 250 ⁇ , for example, with which semiconductor layer 14 i cannot substantially contribute to power generation.
  • Semiconductor layer 15 i made of a substantially-intrinsic i-type semiconductor is provided between substrate 11 and semiconductor layer 15 n.
  • Semiconductor layer 15 i has a thickness of about several ⁇ to 250 ⁇ , for example, with which semiconductor layer 15 i cannot substantially contribute to power generation.
  • Semiconductor layer 14 i and semiconductor layer 14 p are provided so as to substantially entirely cover second principal surface 11 b including a portion above semiconductor layer 15 n. Thus, Semiconductor layer 14 i and semiconductor layer 14 p are also provided above semiconductor layer 15 n. Recombination layer 19 is provided between semiconductor layer 15 n and semiconductor layer 14 p. In this way, another semiconductor layer maybe further provided on n-type surface 10 bn constituted by semiconductor layer 15 n.
  • Electric charges collected on p-type surface 10 bp are extracted from p-side electrode 21 p in direct contact with semiconductor layer 14 p as in the case of the first embodiment.
  • electrons collected on n-type surface 10 bn are extracted from n-side electrode 22 n via recombination layer 19 , semiconductor layer 14 i, and semiconductor layer 14 p
  • Recombination layer 19 may be made of a material such as a semiconductor material in which many midgap levels exist in energy bands, or a metallic material capable of coming in ohmic contact with a p-type semiconductor layer. The selection of such a material makes it possible to reduce a loss of electrons extracted from n-side electrode 22 n. More specifically, recombination layer 19 may be made of, for example, p-type or n-type amorphous silicon, p-type or n-type microcrystalline silicon, or the like.
  • P-type surface 10 bp and n-type surface 10 bn are connected with semiconductor layer 14 i and semiconductor layer 14 p interposed in between.
  • semiconductor layer 14 i and semiconductor layer 14 p have such small film thicknesses as to have high resistance that allows only a small current to flow.
  • This configuration enables generated electric current to be efficiently extracted from p-side electrode 21 p and n-side electrode 22 n without needing the processes of forming semiconductor layer 14 i and semiconductor layer 14 p.
  • solar cell 1 b can produce the same effects as solar cell 1 a.
  • solar cell 1 b does not need a patterning process of semiconductor layer 14 p and the like. Accordingly, the manufacturing cost can be reduced.
  • FIG. 4 is a schematic cross sectional diagram of solar cell 1 c according to a third embodiment.
  • solar cell 1 c includes insulating layer 23 protruding from p-side electrode 21 p and n-side electrode 22 n.
  • Insulating layer 23 is made of an elastic body such as a resin. For this reason, if multiple solar cells 1 c are stacked as illustrated in FIG. 5 , only insulating layers 23 made of the elastic bodies contact neighboring solar cells 1 c. The parts of solar cells 1 c other than insulating layers 23 are kept from contacting neighboring solar cells 1 c. This inhibits solar cells 1 c from being damaged even if solar cells 1 c are stacked without resin sheets or the like inserted therebetween. As a result, solar cells 1 c are easy to store, which enables reduction in the manufacturing costs for solar cell module 2 as well.
  • all insulating layers 23 do not necessarily have to protrude from p-side electrode 21 p and n-side electrode 22 n, but only some of insulating layers 23 may protrude from p-side electrode 21 p and n-side electrode 22 n.
  • FIG. 6 is a schematic cross sectional diagram of solar cell 1 d according to a fourth embodiment.
  • insulating layer 23 is formed before the formation of p-side electrode 21 p and n-side electrode 22 n.
  • insulating layer 23 is formed after the formation of p-side electrode 21 p and n-side electrode 22 n. Even in this case, the same effects as those described in the third embodiment can be obtained.

Abstract

A solar cell includes a photoelectric conversion body including one principal surface provided with a p-type surface and an n-type surface, a p-side electrode disposed on the p-type surface, an n-side electrode disposed on the n-type surface, and an insulating layer disposed between the p-side electrode and the n-side electrode and including a convex shaped surface.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation application of International Application No. PCT/JP2012/081086, filed on Nov. 30, 2012, entitled “SOLAR CELL, SOLAR CELL MODULE AND METHOD OF MANUFACTURING SOLAR CELL”, which claims priority from prior Japanese Patent Applications No. 2011-0264659 filed on Dec. 02, 2011 and No. 2012-031464 filed on Feb. 16, 2012, the entire contents of which are incorporated herein by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This disclosure relates to a solar cell, a solar cell module and a method of manufacturing a solar cell.
  • 2. Description of Related Art
  • Heretofore, a back contact solar cell has been known as a solar cell achieving improved photoelectric conversion efficiency (for example, see Patent Document 1).
  • Patent Document 1: Japanese Patent Application Publication No. 2005-101151
  • SUMMARY OF THE INVENTION
  • In recent years, there has been a demand for further improvement in photoelectric conversion efficiency of back contact solar cells.
  • An embodiment of the invention has an objective to provide a solar cell with improved photoelectric conversion efficiency.
  • A first aspect of the invention is a solar cell including a photoelectric conversion body, a p-side electrode, an n-side electrode, and an insulating layer. The photoelectric conversion body includes a p-type surface and an n-type surface in one principal surface. The p-side electrode is disposed on the p-type surface. The n-side electrode is disposed on the n-type surface. The insulating layer is disposed between the p-side electrode and the n-side electrode. A surface of the insulating layer has a convex shape.
  • A second aspect of the invention is a solar cell module. The solar cell module includes the solar cell of the first aspect and a resin encapsulant. The resin encapsulant seals the solar cell. The insulating layer contains a resin.
  • A third aspect of the invention is a method of manufacturing a solar cell. The method of manufacturing a solar cell includes: preparing a photoelectric conversion body including one principal surface provided with a p-type surface and an n-type surface; forming an insulating layer on a border portion between the p-type surface and the n-type surface in the one principal surface of the photoelectric conversion body in such a way that an exposed portion of the p-type surface and an exposed portion of the n-type surface are defined by the insulating layer; and after forming the insulating layer, forming a p-side electrode on the p-type surface and an n-side electrode on the n-type surface concurrently by plating.
  • According to the first aspect of the invention, a solar cell with improved photoelectric conversion efficiency can be provided.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic cross sectional diagram of a solar cell according to a first embodiment.
  • FIG. 2 is a schematic cross sectional diagram of a solar cell module according to the first embodiment.
  • FIG. 3 is a schematic cross sectional diagram of a solar cell according to a second embodiment.
  • FIG. 4 is a schematic cross sectional diagram of a solar cell according to a third embodiment.
  • FIG. 5 is an exemplary cross sectional diagram of multiple solar cells stacked in the third embodiment.
  • FIG. 6 is a schematic cross sectional diagram of a solar cell according to a fourth embodiment.
  • DESCRIPTION OF EMBODIMENTS
  • Hereinafter, examples of preferred embodiments carrying out the invention are described. It should be noted that the following embodiments are provided just for illustrative purposes. The invention should not be limited at all to the following embodiments.
  • In the drawings referred to in the embodiments and other parts, components having substantially the same function are referred to with the same reference numeral. In addition, the drawings referred to in the embodiments and other parts are illustrated just schematically, and the dimensional ratio and the like of objects depicted in the drawings are different from those of the actual ones in some cases. The dimensional ratio and the like of objects are also different among the drawings in some cases. The specific dimensional ratio and the like of objects should be determined with the following description taken into consideration.
  • First Embodiment
  • (Configuration of Solar Cell 1 a)
  • As illustrated in FIG. 1, solar cell 1 a includes photoelectric conversion body 10 having light-receiving surface 10 a and back surface 10 b. Photoelectric conversion body 10 includes substrate 11. Substrate 11 is made of a semiconductor material. Substrate 11 may be made of a crystalline semiconductor such as crystalline silicon, for example, or the like. Substrate 11 has one conductivity type. Specifically, in the present embodiment, description is provided for an example where the conductivity type of substrate 11 is n-type.
  • Semiconductor layer 12 n made of an n-type semiconductor which is of the same conductivity type as substrate 11 is disposed on first principal surface 11 a located on a light-receiving surface 10 a side of substrate 11. First principal surface 11 a is substantially entirely covered with semiconductor layer 12 n. Semiconductor layer 12 n may be made of n-type amorphous silicon or the like. The thickness of semiconductor layer 12 n may be about 1 nm to 10 nm, for example.
  • Here, a semiconductor layer made of a substantially-intrinsic i-type semiconductor may be provided between semiconductor layer 12 n and first principal surface 11 a. The semiconductor layer has a thickness of about several Å to 250 Å, for example, with which the semiconductor layer cannot substantially contribute to power generation.
  • Anti-reflective layer 13 is disposed on a surface of semiconductor layer 12 n on the opposite side from substrate 11. Anti-reflective layer 13 has both a function to inhibit reflection and a function as a protective film. Anti-reflective layer 13 constitutes light-receiving surface 10 a of photoelectric conversion body 10. Anti-reflective layer 13 may be made of, for example, silicon nitride or the like. Here, the thickness of anti-reflective layer 13 can be set as needed depending on a factor such as the wavelength of light whose reflection is to be inhibited. The thickness of anti-reflective layer 13 may be, for example, about 50 nm to 200 nm.
  • Semiconductor layer 14 p made of a p-type semiconductor which is of a conductivity type different from substrate 11 is disposed on a portion of second principal surface 11 b of substrate 11. Semiconductor layer 15 n made of an n-type semiconductor which is of the same conductivity type as substrate 11 is disposed on at least part of the other portion of second principal surface 11 b of substrate 11 where no semiconductor layer 14 p is disposed. In this embodiment, second principal surface 11 b is substantially entirely covered with semiconductor layer 14 p and semiconductor layer 15 n. Semiconductor layer 14 p and semiconductor layer 15 n maybe made of materials such as p-type amorphous silicon and n-type amorphous silicon, respectively.
  • Semiconductor layer 14 p and semiconductor layer 15 n constitute back surface 10 b of photoelectric conversion body 10. Semiconductor layer 14 p constitutes p-type surface 10 bp, whereas semiconductor layer 15 n constitutes n-type surface 10 bn.
  • The thickness of semiconductor layer 14 p may be about 2 nm to 20 nm, for example. The thickness of semiconductor layer 15 n may be about 5 nm to 50 nm, for example. Here, a semiconductor layer made of a substantially-intrinsic i-type semiconductor may be provided between semiconductor layer 14 p and second principal surface 11 b. This semiconductor layer has a thickness of about several Å to 250 Å, for example, with which the semiconductor layer cannot substantially contribute to power generation. Similarly, a semiconductor layer made of a substantially-intrinsic i-type semiconductor may be provided between semiconductor layer 15 n and second principal surface 11 b. This semiconductor layer has a thickness of about several Å to 250 Å, for example, with which the semiconductor layer cannot substantially contribute to power generation. Such semiconductor layers made of substantially-intrinsic i-type semiconductors may be made of amorphous silicon or the like.
  • End portions of semiconductor layer 14 p in an x axial direction overlap semiconductor layer 15 n in a thickness direction z. Insulating layer 16 is disposed between the end portions of semiconductor layer 14 p and semiconductor layer 15 n. Insulating layer 16 maybe made of, for example, silicon nitride, silicon oxide or the like.
  • First seed layer 17 is disposed on semiconductor layer 14 p. First seed layer 17 is a layer having a function as a seed to form p-side electrode 21 p by plating as described later. On the other hand, second seed layer 18 is disposed on semiconductor layer 15 n. Second seed layer 18 is a layer having a function as a seed to form n-side electrode 22 n by plating as described later. First and second seed layers 17, 18 may be each made of transparent conductive oxide such as indium tin oxide (ITO) or at least one kind of metal such as Cu or Ag. Each of first and second seed layers 17, 18 may be formed of a multilayer including a transparent conductive oxide layer and a metal layer disposed on the transparent conductive oxide layer, for example. The thickness of each of first and second seed layers 17, 18 may be about 0.1 μm to 1.0 μm.
  • P-side electrode 21 p to collect positive holes is disposed on first seed layer 17 disposed on p-type surface 10 bp. P-side electrode 21 p is electrically connected to p-type surface 10 bp via first seed layer 17. On the other hand, n-side electrode 22 n to collect electrons is disposed on second seed layer 18 disposed on n-type surface 10 bn. N-side electrode 22 n is electrically connected to n-type surface 10 bn via second seed layer 18. Here, p-side electrode 21 p may be disposed directly on p-type surface 10 bp, while n-side electrode 22 n may be disposed directly on n-type surface 10 bn.
  • Each of p-side electrode 21 p and n-side electrode 22 n may preferably include a plating film, or may be more preferably formed of a plating film. For example, each of p-side electrode 21 p and n-side electrode 22 n may be formed of a laminate of two or more plating films. Specifically, each of p-side electrode 21 p and n-side electrode 22 n may be formed of a multilayer of a first plating film made of Cu and a second plating film made of Sn, for example.
  • The thickness of each of p-side electrode 21 p and n-side electrode 22 n may be about 20 μm to 30 μm.
  • Insulating layer 23 is disposed between p-side electrode 21 p and n-side electrode 22 n in a planar direction of back surface 10 b of photoelectric conversion body 10. Surface 23 a of insulating layer 23 has a convex shape. In other words, the cross-sectional shape of insulating layer 23 is a dome shape. Insulating layer 23 is provided between and on top of end portions of first seed layer 17 and second seed layer 18 which are neighboring in the x-axis direction. Insulating layer 23 is embedded between first seed layer 17 and p-side electrode 21 p and between second seed layer 18 and n-side electrode 22 n.
  • Insulating layer 23 may be made of an inorganic insulating material such as silicon oxide or silicon nitride, for example, but maybe preferably made of an organic insulating material such as an epoxy resin, an acrylic resin or a urethane resin, for example, and more preferably made of a plating resist made of a resist material containing an epoxy resin.
  • (Method of Manufacturing Solar Cell 1 a)
  • Next, an example of a method of manufacturing a solar cell 1 a is described.
  • Firstly, photoelectric conversion body 10 is prepared. Then, first seed layer 17 is formed on p-type surface 10 bp and second seed layer 18 is formed on n-type surface 10 bn. First and second seed layers 17, 18 may be formed by, for example, sputtering, a CVD (Chemical Vapor Deposition) technique, or the like.
  • Next, insulating layer 23 is formed. Specifically, insulating layer 23 having convex-shaped surface 23 a is formed on each boundary portion between p-type surface 10 bp and n-type surface 10 bn of back surface 10 b of photoelectric conversion body 10 in such a manner that an exposed portion of p-type surface 10 bp and an exposed portion of n-type surface 10 bn are defined by insulating layer 23. A method of forming insulating layer 23 is not particularly limited. For example, in the case where insulating layer 23 is made of an organic insulating material, insulating layer 23 may be formed by, for example, a screen printing method, an inkjet method, a photolithography method, or the like.
  • Subsequently, by plating such as electroplating, p-side electrode 21 p is formed on p-type surface 10 bp and n-side electrode 22 n is formed on n-type surface 10 bn, concurrently. Here, in order to keep p-side electrode 21 p and n-side electrode 22 n from being in contact with each other on insulating layer 23, it is preferable to form insulating layer 23 by using a plating resist.
  • As has been described above, in solar cell 1 a, insulating layer 23 disposed between p-side electrode 21 p and n-side electrode 22 n has convex-shaped surface 23 a. This makes it possible to secure a long distance on back surface 10 b between p-side electrode 21 p and n-side electrode 22 n. Thus, even if the distance in the x-axis direction between p-side electrode 21 p and n-side electrode 22 n is set short, high insulating resistance between p-side electrode 21 p and n-side electrode 22 n can be achieved. This enables achievement of improved photoelectric conversion efficiency.
  • In addition, if no insulating layer 23 is provided and then a p-side electrode and an n-side electrode are formed by plating, the electrodes is formed over an area wider than the seed layers, and the p-side and n-side electrodes may come into contact with each other in some cases. To prevent contact between the p-side electrode and the n-side electrode, a large distance needs to be secured between the first seed layer and the second seed layer.
  • In contrast, since the present embodiment has insulating layer 23 provided, the distance between first seed layer 17 and second seed layer 18 can be made short because p-side electrode 21 p and n-side electrode 22 n are kept from contacting each other. The convex shape of surface 23 a of insulating layer 23 more effectively keeps p-side electrode 21 p and n-side electrode 22 n from contacting each other, and enables a much shorter distance between first seed layer 17 and second seed layer 18. Accordingly, more improved photoelectric conversion efficiency can be achieved.
  • Moreover, the formation of insulating layer 23 by using a plating resist more effectively keeps p-side electrode 21 p and n-side electrode 22 n from contacting each other, and enables a much shorter distance between first seed layer 17 and second seed layer 18. Accordingly, more improved photoelectric conversion efficiency can be achieved.
  • Insulating layer 23 is provided between and on first seed layer 17 and second seed layer 18. Here, a width of insulating layer 23 on the surface plane of first seed layer 17 and second seed layer 18 is longer than a width insulating layer 23 on the surface plane of semiconductor layer 14 p and semiconductor layer 15 n. For this reason, insulating layer 23 can inhibit first and second seed layers 17, 18 from peeling off from photoelectric conversion body 10.
  • (Solar Cell Module 2)
  • FIG. 2 is a schematic cross-sectional diagram of a solar cell module in the first embodiment. As illustrated in FIG. 2, solar cell module 2 includes solar cell 1 a. Solar cell la is sealed by resin encapsulant 30. Light-receiving surface member 31 is provided on a light-receiving surface 10 a side of resin encapsulant 30. On the other hand, back surface member 32 is provided on a back surface 10 b side of resin encapsulant 30.
  • When insulating layer 23 contains a resin, the adherence between insulating layer 23 and resin encapsulant 30 is high. For this reason, resin encapsulant 30 can more suitably seal solar cell 1 a, and can inhibit moisture or the like from reaching solar cell 1 a.
  • To be more specific, in the case where a resist material containing an epoxy material in an amount of 30% is used for insulating layer 23 and an ethylene-vinyl acetate copolymer (EVA) is used for resin encapsulant 30, the adhesive strength between insulating layer 23 and resin encapsulant 30 is 75 N, and the adhesive strength between semiconductor layer 14 p and insulating layer 23 is 75 N or higher. On the other hand, if a solar cell has no insulating layer 23, solar cell module 2 is configured such that semiconductor layer 14 p and resin encapsulant 30 adhere to each other. In this case, the adhesive strength between semiconductor layer 14 p and resin encapsulant 30 is 42 N. Based on the above results, it is found that the provision of insulating layer 23 leads to an increase in the adhesive strength between semiconductor layer 14 p and resin encapsulant 30, and therefore makes it possible to inhibit entry of moisture or the like. Incidentally, the adhesive strengths presented above were each measured by a test of tensile strength between the two kinds of layers.
  • Note that resin encapsulant 30 may be made of a resin such for example as ethylene-vinyl acetate copolymer (EVA), polyvinyl butyral (PVB), polyethylene (PE), or polyurethane (PU). Light-receiving surface member 31 may be formed of, for example, a translucent or transparent glass plate, plastic plate or the like. Back surface member 32 may be formed of, for example, a resin film such as a polyethylene terephthalate (PET) film, a multilayer film in which a metal foil such as an Al foil is inserted between stacked resin films, a steel sheet, or the like.
  • Hereinafter, other preferable embodiments of the invention are described. In the following description, components having substantially the same functions as those in the foregoing first embodiment are referred to with the same reference numerals, and the explanation thereof is omitted.
  • Second Embodiment
  • FIG. 3 is a schematic cross sectional diagram of solar cell 1 b in a second embodiment. As illustrated in FIG. 3, solar cell 1 b in the second embodiment is different from solar cell 1 a in the first embodiment in term of the configuration of photoelectric conversion body 10. The configuration of photoelectric conversion body 10 in the present embodiment is described below.
  • Semiconductor layer 14 i made of a substantially-intrinsic i-type semiconductor is provided between substrate 11 and semiconductor layer 14 p. Semiconductor layer 14 i has a thickness of about several Å to 250 Å, for example, with which semiconductor layer 14 i cannot substantially contribute to power generation. Semiconductor layer 15 i made of a substantially-intrinsic i-type semiconductor is provided between substrate 11 and semiconductor layer 15 n. Semiconductor layer 15 i has a thickness of about several Å to 250 Å, for example, with which semiconductor layer 15 i cannot substantially contribute to power generation.
  • Semiconductor layer 14 i and semiconductor layer 14 p are provided so as to substantially entirely cover second principal surface 11 b including a portion above semiconductor layer 15 n. Thus, Semiconductor layer 14 i and semiconductor layer 14 p are also provided above semiconductor layer 15 n. Recombination layer 19 is provided between semiconductor layer 15 n and semiconductor layer 14 p. In this way, another semiconductor layer maybe further provided on n-type surface 10 bn constituted by semiconductor layer 15 n.
  • Electric charges collected on p-type surface 10 bp are extracted from p-side electrode 21 p in direct contact with semiconductor layer 14 p as in the case of the first embodiment. On the other hand, electrons collected on n-type surface 10 bn are extracted from n-side electrode 22 n via recombination layer 19, semiconductor layer 14 i, and semiconductor layer 14 p
  • Recombination layer 19 may be made of a material such as a semiconductor material in which many midgap levels exist in energy bands, or a metallic material capable of coming in ohmic contact with a p-type semiconductor layer. The selection of such a material makes it possible to reduce a loss of electrons extracted from n-side electrode 22 n. More specifically, recombination layer 19 may be made of, for example, p-type or n-type amorphous silicon, p-type or n-type microcrystalline silicon, or the like.
  • P-type surface 10 bp and n-type surface 10 bn are connected with semiconductor layer 14 i and semiconductor layer 14 p interposed in between. However, semiconductor layer 14 i and semiconductor layer 14 p have such small film thicknesses as to have high resistance that allows only a small current to flow. This configuration enables generated electric current to be efficiently extracted from p-side electrode 21 p and n-side electrode 22 n without needing the processes of forming semiconductor layer 14 i and semiconductor layer 14 p. Also, solar cell 1 b can produce the same effects as solar cell 1 a. Moreover, solar cell 1 b does not need a patterning process of semiconductor layer 14 p and the like. Accordingly, the manufacturing cost can be reduced.
  • Third Embodiment
  • FIG. 4 is a schematic cross sectional diagram of solar cell 1 c according to a third embodiment. As illustrated in FIG. 4, solar cell 1 c includes insulating layer 23 protruding from p-side electrode 21 p and n-side electrode 22 n. Insulating layer 23 is made of an elastic body such as a resin. For this reason, if multiple solar cells 1 c are stacked as illustrated in FIG. 5, only insulating layers 23 made of the elastic bodies contact neighboring solar cells 1 c. The parts of solar cells 1 c other than insulating layers 23 are kept from contacting neighboring solar cells 1 c. This inhibits solar cells 1 c from being damaged even if solar cells 1 c are stacked without resin sheets or the like inserted therebetween. As a result, solar cells 1 c are easy to store, which enables reduction in the manufacturing costs for solar cell module 2 as well.
  • Incidentally, all insulating layers 23 do not necessarily have to protrude from p-side electrode 21 p and n-side electrode 22 n, but only some of insulating layers 23 may protrude from p-side electrode 21 p and n-side electrode 22 n.
  • Fourth Embodiment
  • FIG. 6 is a schematic cross sectional diagram of solar cell 1 d according to a fourth embodiment. In solar cell 1 c, insulating layer 23 is formed before the formation of p-side electrode 21 p and n-side electrode 22 n. In contrast, in solar cell 1 d, insulating layer 23 is formed after the formation of p-side electrode 21 p and n-side electrode 22 n. Even in this case, the same effects as those described in the third embodiment can be obtained.

Claims (10)

1. A solar cell, comprising:
a photoelectric conversion body including one principal surface provided with a p-type surface and an n-type surface;
a p-side electrode disposed on the p-type surface;
an n-side electrode disposed on the n-type surface; and
an insulating layer disposed between the p-side electrode and the n-side electrode, and including a surface formed in a convex shape.
2. The solar cell according to claim 1, wherein the p-side electrode and the n-side electrode each include a plating film.
3. The solar cell according to claim 2, further comprising:
a first seed layer disposed between the p-type surface and the p-side electrode; and
a second seed layer disposed between the n-type surface and the n-side electrode, wherein
the insulating layer is provided between and on top of neighboring end portions of the first seed layer and the second seed layer.
4. The solar cell according to claim 1, wherein
the photoelectric conversion body includes:
a substrate made of a semiconductor material;
a p-type amorphous silicon layer disposed on one principal surface of the substrate and forming the p-type surface; and
an n-type amorphous silicon layer disposed on the one principal surface of the substrate and forming the n-type surface.
5. The solar cell according to claim 1, wherein
the insulating layer is formed of an elastic body, and
the insulating layer protrudes from the p-side electrode and the n-side electrode.
6. A solar cell module comprising:
the solar cell according to claim 1; and
a resin encapsulant that seals the solar cell, wherein
the insulating layer contains a resin.
7. A method of manufacturing a solar cell, comprising:
preparing a photoelectric conversion body including one principal surface provided with a p-type surface and an n-type surface;
forming an insulating layer on a border portion between the p-type surface and the n-type surface in the one principal surface of the photoelectric conversion body in such a way that an exposed portion of the p-type surface and an exposed portion of the n-type surface are defined by the insulating layer; and
after forming the insulating layer, forming a p-side electrode on the p-type surface and an n-side electrode on the n-type surface by plating.
8. The method of manufacturing a solar cell according to claim 7, wherein in the forming of an insulating layer, a surface of the insulating layer is formed into a convex shape.
9. The method of manufacturing a solar cell according to claim 7, wherein in the forming of an insulating layer, the insulating layer is formed of a resist material containing an epoxy resin.
10. The method of manufacturing a solar cell according to claim 7, further comprising forming a first seed layer on the p-type surface and a second seed layer on the n-type surface concurrently, wherein
the insulating layer is formed between and on top of neighboring end portions of the first seed layer and the second seed layer.
US14/453,769 2011-12-02 2014-08-07 Solar cell, solar cell module and method of manufacturing solar cell Abandoned US20150027532A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2011-264659 2011-12-02
JP2011264659 2011-12-02
JP2012-031464 2012-02-16
JP2012031464 2012-02-16
PCT/JP2012/081086 WO2013081104A1 (en) 2011-12-02 2012-11-30 Solar cell, solar cell module, and method for manufacturing solar cell

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/081086 Continuation WO2013081104A1 (en) 2011-12-02 2012-11-30 Solar cell, solar cell module, and method for manufacturing solar cell

Publications (1)

Publication Number Publication Date
US20150027532A1 true US20150027532A1 (en) 2015-01-29

Family

ID=48535552

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/453,769 Abandoned US20150027532A1 (en) 2011-12-02 2014-08-07 Solar cell, solar cell module and method of manufacturing solar cell

Country Status (3)

Country Link
US (1) US20150027532A1 (en)
JP (1) JP6029023B2 (en)
WO (1) WO2013081104A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180347410A1 (en) * 2015-11-03 2018-12-06 Carlos Alberto Hernandez Abarca System for recovering thermal energy produced in pyrometallurgical process plants or similar, to convert same into, or generate, electrical energy
US10475946B2 (en) * 2015-09-30 2019-11-12 Panasonic Intellectual Property Management Co., Ltd. Method of manufacturing back surface junction type solar cell

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015118740A1 (en) * 2014-02-06 2015-08-13 パナソニックIpマネジメント株式会社 Solar cell

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4543441A (en) * 1983-02-14 1985-09-24 Hitachi, Ltd. Solar battery using amorphous silicon
US20040200520A1 (en) * 2003-04-10 2004-10-14 Sunpower Corporation Metal contact structure for solar cell and method of manufacture
US20080173347A1 (en) * 2007-01-23 2008-07-24 General Electric Company Method And Apparatus For A Semiconductor Structure
US20090223562A1 (en) * 2006-10-27 2009-09-10 Kyocera Corporation Solar Cell Element Manufacturing Method and Solar Cell Element
US20100139764A1 (en) * 2008-12-04 2010-06-10 Smith David D Backside Contact Solar Cell With Formed Polysilicon Doped Regions

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02177379A (en) * 1988-12-27 1990-07-10 Kyocera Corp Infrared photodetector
JP3998619B2 (en) * 2003-09-24 2007-10-31 三洋電機株式会社 Photovoltaic element and manufacturing method thereof
JP4155899B2 (en) * 2003-09-24 2008-09-24 三洋電機株式会社 Photovoltaic element manufacturing method
US20090139868A1 (en) * 2007-12-03 2009-06-04 Palo Alto Research Center Incorporated Method of Forming Conductive Lines and Similar Features
WO2009096539A1 (en) * 2008-01-30 2009-08-06 Kyocera Corporation Solar battery element and solar battery element manufacturing method
JP2010147324A (en) * 2008-12-19 2010-07-01 Kyocera Corp Solar cell element and method of manufacturing solar cell element
JP4678698B2 (en) * 2009-09-15 2011-04-27 シャープ株式会社 Solar cell module and manufacturing method thereof
KR20110071375A (en) * 2009-12-21 2011-06-29 현대중공업 주식회사 Back contact type hetero-junction solar cell and method of fabricating the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4543441A (en) * 1983-02-14 1985-09-24 Hitachi, Ltd. Solar battery using amorphous silicon
US20040200520A1 (en) * 2003-04-10 2004-10-14 Sunpower Corporation Metal contact structure for solar cell and method of manufacture
US20090223562A1 (en) * 2006-10-27 2009-09-10 Kyocera Corporation Solar Cell Element Manufacturing Method and Solar Cell Element
US20080173347A1 (en) * 2007-01-23 2008-07-24 General Electric Company Method And Apparatus For A Semiconductor Structure
US20100139764A1 (en) * 2008-12-04 2010-06-10 Smith David D Backside Contact Solar Cell With Formed Polysilicon Doped Regions

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10475946B2 (en) * 2015-09-30 2019-11-12 Panasonic Intellectual Property Management Co., Ltd. Method of manufacturing back surface junction type solar cell
US20180347410A1 (en) * 2015-11-03 2018-12-06 Carlos Alberto Hernandez Abarca System for recovering thermal energy produced in pyrometallurgical process plants or similar, to convert same into, or generate, electrical energy

Also Published As

Publication number Publication date
JP6029023B2 (en) 2016-11-24
WO2013081104A1 (en) 2013-06-06
JPWO2013081104A1 (en) 2015-04-27

Similar Documents

Publication Publication Date Title
US9349897B2 (en) Solar cell module and manufacturing method therefor
TWI495124B (en) Solar battery and solar battery module
WO2012102188A1 (en) Solar cell and solar cell module
US20110132426A1 (en) Solar cell module
US20110155210A1 (en) Solar cell module
US10014426B2 (en) Solar cell and solar cell module
KR101923658B1 (en) Solar cell module
US10217887B2 (en) Crystalline silicon-based solar cell, crystalline-silicon solar cell module, and manufacturing methods therefor
JP7291715B2 (en) Solar cell device and solar cell module
KR20180053993A (en) Solar cell module and manufacturing method thereof
JP6677801B2 (en) Crystalline silicon-based solar cell, method of manufacturing the same, and solar cell module
US20150027532A1 (en) Solar cell, solar cell module and method of manufacturing solar cell
EP2752884B1 (en) Solar cell module
US20110132425A1 (en) Solar cell module
US9640677B2 (en) Solar cell, solar cell module
JP2013077749A (en) Solar cell module
US9972728B2 (en) Solar cell, solar cell module, and method for manufacturing solar cell
CN115020519B (en) Solar laminated battery, battery assembly and photovoltaic system
JP6191995B2 (en) Solar cell module
KR20170000338U (en) Sollar cell module
JP2014072210A (en) Photoelectric conversion element
CN117957933A (en) Solar cell device and solar cell module
JP2011222836A (en) Solar battery module
WO2013046338A1 (en) Solar cell and solar cell module
WO2013042242A1 (en) Solar cell, solar cell module, and methods for manufacturing solar cell and solar cell module

Legal Events

Date Code Title Description
AS Assignment

Owner name: SANYO ELECTRIC CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YAMAGUCHI, TSUTOMU;ONO, MASAYOSHI;MATSUBARA, NAOTERU;AND OTHERS;SIGNING DATES FROM 20140924 TO 20140929;REEL/FRAME:033961/0643

AS Assignment

Owner name: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LT

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PANASONIC CORPORATION;REEL/FRAME:035071/0508

Effective date: 20150130

Owner name: PANASONIC CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANYO ELECTRIC CO., LTD.;REEL/FRAME:035071/0276

Effective date: 20150130

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION