US20140264224A1

US20140264224A1 - Performance Enhancement of Forming-Free ReRAM Devices Using 3D Nanoparticles

Info

Publication number: US20140264224A1
Application number: US13/969,469
Authority: US
Inventors: Xuena Zhang; Sergey Barabash; Charlene Chen; Dipankar Pramanik
Original assignee: Intermolecular Inc
Current assignee: Intermolecular Inc
Priority date: 2013-03-14
Filing date: 2013-08-16
Publication date: 2014-09-18
Also published as: US20140269004A1; US20150140772A1; US20140264241A1; US9177996B2; US8981335B2; US9029187B1; US9025360B2; US8933429B2; US20140264239A1; US20140273300A1

Abstract

Resistive random access memory (ReRAM) cells can include an embedded metal nanoparticle switching layer and electrodes. The metal nanoparticles can be formed using a micelle solution. The generation of the nanoparticles can be controlled in multiple dimensions to achieve desirable performance characteristics, such as low power consumption as well as low and consistent switching currents.

Description

This application claims priority to U.S. Provisional Patent Application No. 61/785,069 entitled “ReRAM Materials” filed on Mar. 14, 2013, which is incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates generally to nonvolatile memory elements, and more particularly, to methods for forming resistive switching memory elements used in nonvolatile memory devices

BACKGROUND

Nonvolatile memory elements are used in systems in which persistent storage is required. For example, digital cameras use nonvolatile memory cards to store images and digital music players use nonvolatile memory to store audio data. Nonvolatile memory is also used to persistently store data in computer environments. Nonvolatile memory is often formed using electrically-erasable programmable read only memory (EPROM) technology. This type of nonvolatile memory contains floating gate transistors that can be selectively programmed or erased by application of suitable voltages to their terminals.
As fabrication techniques improve, it is becoming possible to fabricate nonvolatile memory elements with increasingly smaller dimensions. However, as device dimensions shrink, scaling issues are posing challenges for traditional nonvolatile memory technology. This has led to the investigation of alternative nonvolatile memory technologies, including resistive switching nonvolatile memory.
Resistive memory device, e.g., resistive switching nonvolatile random access memory (ReRAM) is formed using memory elements that have two or more stable states with different resistances. Bistable memory has two stable states. A bistable memory element can be placed in a high resistance state or a low resistance state by application of suitable voltages or currents. Voltage pulses are typically used to switch the memory element from one resistance state to the other. Nondestructive read operations can be performed to ascertain the value of a data bit that is stored in a memory cell.
Resistive switching based on transition metal oxide switching elements formed of metal oxide films has been demonstrated. Although metal oxide films such as these exhibit bistability, the resistance of these films and the ratio of the high-to-low resistance states can be insufficient to be of use within a practical nonvolatile memory device. For instance, the resistance states of the metal oxide film should preferably be significant as compared to that of the system (e.g., the memory device and associated circuitry) so that any change in the resistance state change is perceptible. The variation of the difference in resistive states is related to the resistance of the resistive switching layer. Therefore, a low resistance metal oxide film may not form a reliable nonvolatile memory device. For example, in a nonvolatile memory that has conductive lines formed of a relatively high resistance metal such as tungsten, the resistance of the conductive lines may overwhelm the resistance of the metal oxide resistive switching element. Therefore, the state of the bistable metal oxide resistive switching element may be difficult or impossible to sense.
Therefore, there is a need for a memory device that can meet the design criteria for advanced memory devices.

SUMMARY

In some embodiments, methods and devices for forming resistive memory devices are provided. The resistive memory devices can include one or more array of metal nanoparticles in a switching layer, which is disposed between two electrodes. The switching layer may be deposited using various techniques, such as sputtering and atomic layer deposition (ALD).
In some embodiments, a resistive random access memory cell includes a first layer operable as a first electrode, a second layer operable as a second electrode, and a third layer operable as a resistive switching layer and disposed between the first layer and the second layer. The third layer includes arrays of metal nanoparticles. The arrays of metal nanoparticles can be formed using a micelle solution.
The generation of the nanoparticles can be controlled in multiple dimensions to achieve desirable performance characteristics, such as low power consumption as well as low and consistent switching currents. For example, the vertical spacing of the nanoparticles can be achieved by the thickness of the portion of the switching layer between two adjacent arrays. The lateral spacing of the nanoparticles can be achieved by the preparation of the micelle solution, such as using surfactant solutions with different copolymer chain length. The size of the nanoparticles can also be achieved by the preparation of the micelle solution, such as the concentration of metal in the micelle solution.

BRIEF DESCRIPTION OF THE DRAWINGS

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The drawings are not to scale and the relative dimensions of various elements in the drawings are depicted schematically and not necessarily to scale.

The techniques of the present invention can readily be understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

FIGS. 1A-1C illustrate a schematic representation of a ReRAM operation according to some embodiments.

FIG. 2 illustrates a plot of a current passing through a unipolar ReRAM cell as a function of a voltage applied to the ReRAM cell according to some embodiments.

FIGS. 3A-3C illustrate a schematic representation of an operation of an embedded nanoparticles memory structure according to some embodiments.

FIG. 4 illustrates a plot of a current passing through a unipolar ReRAM cell having embedded nanoparticles according to some embodiments.

FIGS. 5A-5F illustrate various configurations of memory structures having embedded nanoparticles according to some embodiments.

FIGS. 6A-6H illustrate a process flow for forming a memory structure having embedded nanoparticles according to some embodiments.

FIG. 7 illustrates a flowchart for forming a memory device according to some embodiments.

FIG. 8 illustrates a micelle solution according to some embodiments.

FIG. 9 illustrates a schematic representation of atomic layer deposition apparatus for fabricating ReRAM cells according to some embodiments.

FIGS. 10A-10B illustrate a schematic representation of resistive switching ReRAM cell according to some embodiments.

FIGS. 11A-11B illustrate flowcharts for fabricating a resistive switching layer of a memory device according to some embodiments.

FIG. 12 illustrates a flowchart for forming a memory device according to some embodiments.

FIG. 13A-13B illustrates memory arrays according to some embodiments.

DETAILED DESCRIPTION

A detailed description of one or more embodiments is provided below along with accompanying figures. The detailed description is provided in connection with such embodiments, but is not limited to any particular example. The scope is limited only by the claims and numerous alternatives, modifications, and equivalents are encompassed. Numerous specific details are set forth in the following description in order to provide a thorough understanding. These details are provided for the purpose of example and the described techniques may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the embodiments has not been described in detail to avoid unnecessarily obscuring the description.
In some embodiments, methods to fabricate resistive memory devices, and the resistive memory devices fabricated from the methods, are provided. The resistive memory devices can include two electrodes covering a switching layer having embedded metal nanoparticles. The metal nanoparticles can act as seeds for the conductive filaments in the switching layer, which can cause the change in resistance of the switching layer due to the formation and rupture of the conductive filaments. The incorporation of metal nanoparticles in the switching layer can be controlled in a 3D deposition process, e.g., the lateral spacing of the nanoparticles along the surface of the devices and the vertical spacing of the nanoparticles in the direction between the electrodes.
The embedded metal nanoparticles can facilitate the formation of the conductive filaments, for example, due to the formation of the conductive filaments between the metal nanoparticles. Since the distances between the nanoparticles can be controlled during the device fabrication process, the initial formation of the conductive filaments, e.g., the application of a forming voltage to create the conductive filaments, can be reduced or eliminated. Further, the power requirement for the memory devices can be reduced due to the reduced distances of the conductive filaments.
The embedded metal nanoparticles can also confine the locations of the conductive filaments. Thus the resistive memory devices can have controlled filament nucleation and growth to provide improved uniformity of resistive switching properties.
A ReRAM cell exhibiting resistive switching characteristics generally includes multiple layers formed into a stack. The structure of this stack is sometimes described as a Metal-Insulator-Metal (MIM) structure. Specifically, the stack includes two conductive layers operating as electrodes. These layers may include metals and/or other conductive materials. The stack also includes an insulator layer disposed in between the electrode. The insulator layer exhibits resistive switching properties characterized by different resistive states of the material forming this layer. As such, this insulator layer is often referred to as a resistive switching layer. These resistive states may be used to represent one or more bits of information. The resistance switching properties of the insulator layer are believed to depend on various defects' presence and distribution inside this layer. For example, different distribution of oxygen vacancies in the layer may reflect different resistance states of the layer, and these states may be sufficiently stable for memory application.
To achieve a certain concentration of defects in the resistance switching layer, the layer has been conventionally deposited with defects already present in the layer, i.e., with preformed defects. In other words, defects are introduced into the layer during its formation. For example, tightly controlled Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or some other low-temperature process to remain within a Back End of Line (BEOL) thermal budget may be used to deposit the insulator layer of the stack. It may be difficult to precisely and repeatedly control formation of these defects particularly in very thin resistance switching layers (e.g., less than 100 Angstroms). For example, when ALD is used to form resistance switching layers, some unreacted precursors may leave carbon-containing residues that impact resistance characteristics of the deposition layers and ReRAM cells including these layers. Furthermore, achieving precise partial saturation repeatedly may be very difficult if possible at all. In the case of PVD, sputtering targets tend to wear out influencing the deposition rates and creating variation in resulting resistance switching layers.
A brief description of ReRAM cells and their switching mechanisms are provided for better understanding of various features and structures associated with methods of forming nonvolatile memory elements further described below. ReRAM is a non-volatile memory type that includes dielectric material exhibiting resistive switching characteristics. A dielectric, which is normally insulator, can be made to conduct through one or more filaments or conduction paths formed after application of a sufficiently high voltage. The conduction path formation can arise from different mechanisms, including defects, metal migration, and other mechanisms further described below. Once the one or more filaments or conduction paths are formed in the dielectric component of a memory device, these filaments or conduction paths may be reset (or broken resulting in a high resistance) or set (or re-formed resulting in a lower resistance) by applying certain voltages. Without being restricted to any particular theory, it is believed that resistive switching corresponds to migration of defects within the resistive switching layer and, in some embodiments, across one interface formed by the resistive switching voltage, when a switching voltage is applied to the layer.
FIGS. 1A-1C illustrate a schematic representation of a ReRAM operation according to some embodiments. A basic building unit of a memory device is a stack having a capacitor like structure. A ReRAM cell includes two electrodes and a dielectric positioned in between these two electrodes. FIG. 1A illustrates a schematic representation of ReRAM cell 100 including top electrode 102, bottom electrode 106, and resistance switching layer 104 provided in between top electrode 102 and bottom electrode 106. It should be noted that the “top” and “bottom” references for electrodes 102 and 106 are used solely for differentiation and not to imply any particular spatial orientation of these electrodes. Often other references, such as “first formed” and “second formed” electrodes or simply “first” and “second”, are used identify the two electrodes. ReRAM cell 100 may also include other components, such as an embedded resistor, diode, and other components. ReRAM cell 100 is sometimes referred to as a memory element or a memory unit.
Top electrode 102 and bottom electrode 106 may be used as conductive lines within a memory array or other types of devices that ReRAM cell is integrated into. As such, electrode 102 and 106 are generally formed from conductive materials. As stated above, one of the electrodes may be reactive electrode and act as a source and as a reservoir of defects for the resistive switching layer. That is, defects may travel through an interface formed by this electrode with the resistive switching layer (i.e., the reactive interface). The other interface of the resistive switching layer may be inert and may be formed with an inert electrode or a diffusion barrier layer.
Resistance switching layer 104 which may be initially formed from a dielectric material and later can be made to conduct through one or more conductive paths formed within the layer by applying first a forming voltage and then a switching voltage. To provide this resistive switching functionality, resistance switching layer 104 includes a concentration of electrically active defects 108, which may be at least partially provided into the layer during its fabrication. For example, some atoms may be absent from their native structures (i.e., creating vacancies) and/or additional atoms may be inserted into the native structures (i.e., creating interstitial defects). Charge carriers may be also introduced as dopants, stressing lattices, and other techniques. Regardless of the types all charge carriers are referred to as defects 108.
In some embodiments, these defects may be utilized for ReRAM cells operating according to a valence change mechanism, which may occur in specific transition metal oxides, nitrides, and oxy-nitrides. For example, defects may be oxygen vacancies triggered by migration of oxygen anions. Migrations of oxygen anions correspond to the motion of corresponding oxygen vacancies that are used to create and break conductive paths. A subsequent change of the stoichiometry in the transition metal oxides leads to a redox reaction expressed by a valence change of the cation sublattice and a change in the electrical conductivity. In this example, the polarity of the pulse used to perform this change determines the direction of the change, i.e., reduction or oxidation. Other resistive switching mechanisms include bipolar electrochemical metallization mechanisms and thermochemical mechanisms, which leads to a change of the stoichiometry due to a current-induced increase of the temperature. Some of these mechanisms will be further described below with reference to FIGS. 1A-1C. In the described examples, top electrode 102 is reactive, while bottom electrode 106 is inert or is separated from resistive switching layer 104 by a diffusion barrier layer (not shown). One having ordinary skills in the art would understand that other arrangements are possible as well and within the scope of this disclosure.
Specifically, FIG. 1A is a schematic representation of ReRAM cell 100 prior to initial formation of conductive paths, in accordance with some embodiments. Resistive switching layer 104 may include some defects 108. Additional defects 108 may be provided within top electrode 102 and may be later transferred to resistive switching layer 104 during the formation operation. In some embodiments, the resistive switching layer 104 has substantially no defects prior to the forming operation and all defects are provided from top electrode 102 during forming. Bottom electrode 106 may or may not have any defects. It should be noted that regardless of the presence or absence of defects in bottom electrode 106, substantially no defects are exchanged between bottom electrode 106 and resistive switching layer 104 during forming and/or switching operations.
During the forming operation, ReRAM cell 100 changes its structure from the one shown in FIG. 1A to the one shown in FIG. 1B. This change corresponds to defects 108 being arranged into one or more continuous paths within resistive switching layer 104 as, for example, schematically illustrated in FIG. 1B. Without being restricted to any particular theory, it is believed that defects 108 can be reoriented within resistance switching layer 104 to form these conductive paths 110 as, for example, schematically shown in FIG. 1B. Furthermore, some or all defects 108 forming the conductive paths may enter resistive switching layer 104 from top electrode 102. For simplicity, all these phenomena are collectively referred to as reorientation of defects within ReRAM cell 100. This reorientation of defects 108 occurs when a certain forming voltage 104 is applied to electrodes 102 and 106. In some embodiments, the forming operation also conducted at elevated temperatures to enhanced mobility of the defects within ReRAM cell 100. In general, the forming operation is considered to be a part of the fabrication of ReRAM cell 100, while subsequent resistive switching is considered to be a part of operation of ReRAM cell.
Resistive switching involves breaking and reforming conductive paths through resistive switching layer 104, i.e., switching between the state schematically illustrated in FIG. 1B and the state schematically illustrated in FIG. 1C. The resistive switching is performed by applying switching voltages to electrodes 102 and 106. Depending on magnitude and polarity of these voltages, conductive path 110 may be broken or re-formed. These voltages may be substantially lower than forming voltages (i.e., voltages used in the forming operation) since much less mobility of defects is needed during switching operations. For example, hafnium oxide based resistive layers may need about 7 Volts during their forming but can be switched using voltages less than 4 Volts.
The state of resistive switching layer 104 illustrated in FIG. 1B is referred to as a low resistance state (LRS), while the state illustrated in FIG. 1C is referred to as a high resistance state (HRS). The resistance difference between the LRS and HRS is due to different number and/or conductivity of conductive paths that exists in these states, i.e., resistive switching layer 104 has more conductive paths and/or less resistive conductive paths when it is in the LRS than when it is in the HRS. It should be noted that resistive switching layer 104 may still have some conductive paths while it is in the HRS, but these conductive paths are fewer and/or more resistive than the ones corresponding to the LRS.
When switching from its LRS to HRS, which is often referred to as a reset operation, resistive switching layer 104 may release some defects into top electrode 102. Furthermore, there may be some mobility of defects within resistive switching layer 104. This may lead to thinning and, in some embodiments, breakages of conductive paths as shown in FIG. 1C. Depending on mobility within resistive switching layer 104 and diffusion through the interface formed by resistive switching layer 104 and top electrode 102, the conductive paths may break closer to the interface with bottom electrode 106, somewhere within resistive switching layer 104, or at the interface with top electrode 102. This breakage generally does not correspond to complete dispersion of defects forming these conductive paths and may be a self limiting process, i.e., the process may stop after some initial breakage occurs.
When switching from its HRS to LRS, which is often referred to as a set operation, resistive switching layer 104 may receive some defects from top electrode 102. Similar to the reset operation described above, there may be some mobility of defects within resistive switching layer 104. This may lead to thickening and, in some embodiments, reforming of conductive paths as shown in FIG. 1B. In some embodiments, a voltage applied to electrodes 102 and 104 during the set operation has the same polarity as a voltage applied during the reset operation. This type of switching is referred to as unipolar switching. Some examples of cells that exhibit unipolar switching behavior include resistive switching layers formed from most metal oxide and having inert electrodes at both sides, e.g., Pt/MeO_x/Pt. Alternatively, a voltage applied to electrodes 102 and 104 during the set operation may have different polarity as a voltage applied during the reset operation. This type of switching is referred to as bipolar switching. Some examples of cells that exhibit bipolar switching behavior include resistive switching layers formed from MeOx having one inert electrode and one reactive electrode, e.g., TiN/MeOx/Pt and TiN/MeOx/poly-Si.
FIG. 2 illustrates a plot of a current passing through a unipolar ReRAM cell as a function of a voltage applied to the ReRAM cell according to some embodiments. A metal-insulator-metal (MIM) structure 210 can be first fabricated with an amount of defects embedded in the insulator layer. A voltage or current 220 can be applied to the MIM structure to form a resistive memory device from the MIM structure, for example, by making the insulator layer becoming a switching layer. By applying a forming voltage V_form, the randomly distributed defects can be transitioned 250 to lower resistance configurations, for example, in the form of filaments 230.
The lower resistance configurations can be characterized as a low resistance state (LRS) 234 for the resistive memory device, which persists even when the voltage is reduced. The LRS can represent a logic state of the memory device, such as a logic zero (“0”).
At LRS, when another voltage, e.g., V_resetis applied, the resistance can be transitioned 235 to a high resistance state (HRS), which persists even when the voltage is reduced. The HRS can represent another logic state of the memory device, such as a logic one (“1”). The reset voltage V_resetis smaller then the forming voltage V_form.
At HRS, when another voltage, e.g., V_setis applied, the resistance can be transitioned 215 back to the low resistance state (LRS), which persists even when the voltage is reduced. The set voltage V_setis also smaller then the forming voltage V_form.
Overall, the ReRAM cell may be switched back and forth between its LRS and HRS many times. For example, when it is desired to turn “ON” the cell, e.g., to have a LRS, a set operation can be performed through the application of a set voltage V_setto the electrodes. Applying the set voltage forms one or more conductive paths in the resistance switching layer as shown in 230. If it is desired to turn “OFF” the ReRAM cell, e.g., to change to HRS, a reset operation can be preformed through the application of a reset voltage V_resetto the electrodes. Applying the reset voltage can destroy the conductive paths in the resistance switching layer as shown in 250.
The polarity of the reset voltage and the set voltage may be the same in unipolar memory devices, or may be different in bipolar devices (not shown). Without being restricted to any particular theory, it is believed that the resistive switching occurs due to filament formation and destruction caused by the application of electrical field.
Read operations may be performed in each of these states (between the switching operations) one or more times or not performed at all. During the read operation, the state of the ReRAM cell or, more specifically, the resistive state of its resistance of resistance switching layer can be sensed by applying a sensing voltage to its electrodes. The sensing voltage is sometimes referred to as a read voltage V_read.
In some embodiments, the set voltage V_setis between about 100 mV and 10V or, more specifically, between about 500 mV and 5V. The length of set voltage pulses may be less than about 100 milliseconds or, more specifically, less than about 5 milliseconds and even less than about 100 nanoseconds. The read voltage V_readmay be between about 0.1 and 0.5 of the set voltage V_set. In some embodiments, the read currents (I_ONand I_OFF) are greater than about 1 mA or, more specifically, is greater than about 5 mA to allow for a fast detection of the state by reasonably small sense amplifiers. The length of read voltage pulse may be comparable to the length of the corresponding set voltage pulse or may be shorter than the write voltage pulse. ReRAM cells should be able to cycle between LRS and HRS between at least about 10³times or, more specifically, at least about 10⁷times without failure. A data retention time should be at least about 5 years or, more specifically, at least about 10 years at a thermal stress up to 85° C. and small electrical stress, such as a constant application of the read voltage. Other considerations may include low current leakage, such as less than about 40 A/cm²measured at 0.5 V per 20 Å of oxide thickness in HRS.
Practical applications of ReRAM cells require certain switching, data retention, and other characteristics. For example, ReRAM cells need to have low leakage, low switching currents, stable performance over a large number of switching cycles. It has been found that a composition, morphology, and deposition process of resistive switching layers, together with appropriate electrode materials, have to be specifically tuned to meet these requirements.
In some embodiments, ReRAM cells and methods to fabricate ReRAM cells are provided with metal oxide switching layers having embedded nanoparticles disposed between electrodes. The embedded nanoparticles metal oxide layers can be deposited by atomic layer deposition, with pre-prepared nanoparticles coating during the deposition. The embedded nanoparticles can be specifically designed to provide a metal oxide layer with desirable performance characteristics. In some embodiments, the forming process can be eliminated, e.g., the as-deposited memory cells can be readily programmed without the application of a forming voltage. In some embodiments, an operating voltage, e.g., a switching voltage, can be less than about 2 V, while the corresponding switching current can be less than about 100 μA, which can provide improved (lower) power characteristics.
The switching layers can include a metal oxide layer, such as hafnium oxide, aluminum oxide, or a combination of hafnium oxide and aluminum oxide. Other metal oxides can be used, such as titanium oxide and zirconium oxide. Other impurities can be provided to the switching layers, such as nitrogen. The addition of nitrogen may be used for controlling the amount of oxygen vacancies in the switching layer and for maintaining this layer in an amorphous state.
The switching layer may be deposited using various techniques, such as sputtering and atomic layer deposition (ALD). The ALD approaches may be further divided into nanolamination ALD or staggered pulse ALD. The following description of these approaches is directed to formation of hafnium-aluminum metal oxides. However, one having ordinary skills in the art would understand that such processes may be varied to form other metal oxides, such as hafnium oxide, aluminum oxide, titanium oxide, zirconium oxide, or any combinations thereof.
Nanolamination may involve deposition of one or more hafnium oxide layers and, separately, one or more aluminum oxide layers to form a stack. The stack is then annealed in order to intermix these layers. In some embodiments, the resulting layer (i.e., after the annealing) is substantially homogeneous. For example, a hafnium containing precursor, such as Tetrakis Dimethylamino Hafnium (TDMAHf), Tetrakis Ethylmethylamino Hafnium (TEMAHf), and/or hafnium tetrachloride may be introduced into an ALD chamber followed by an oxidizer, such as water or ozone. A hafnium oxide layer may be formed at this point. This hafnium precursor—oxidizer cycle may be repeated multiple times depending on a desired concentration of hafnium in a resulting base layer (and subsequently in the resistive switching layer). An aluminum containing precursor, such as a Trimethyl aluminum (TMA), is then introduced into a chamber, followed by introduction of an oxidizer, such as water or ozone. As such, a separate layer of aluminum oxide is formed over one or more layers of hafnium oxide. Of course, this deposition order may be reversed, and one or more aluminum oxide layers may be deposited prior to deposition of one or more hafnium oxide layers. Furthermore, deposition of one or more aluminum oxides layers and one or more hafnium oxide layers may be repeated a number of times until the switching layer becomes sufficiently thick. The composition of the switching layer can be modified by controlling how many aluminum oxides layers and how many hafnium oxides layers are deposited and form the switching layer. For example, a switching layer may be formed by alternating depositions of five hafnium oxide layers per one aluminum oxide layer. Furthermore, distribution of hafnium, aluminum, oxygen, and nitrogen in the resulting resistive switching layer may be controlled by specific order of ALD cycles.
A staggered pulse deposition may involve introducing a hafnium containing precursor into an ALD chamber followed by introducing an aluminum containing precursor into the ALD chamber. It should be noted that both metal precursors are introduced into the chamber prior to any oxidation of any one of the two precursors. In some embodiments, an aluminum containing precursor is introduced into the chamber prior to introducing a hafnium containing precursor. This order depends on the type of metal precursors (their adsorption characteristics, size, reactivity, and other like characteristics) and desired composition of the resulting switching layer. For example, if TMA is introduced into the chamber prior to TDMAHf, then the resulting switching layer contains predominantly aluminum oxide with very little hafnium present. However, if TDMAHf is introduced into the chamber prior to TMA, then the resulting switching layer can contain more hafnium than aluminum, e.g., higher atomic percent of hafnium oxide relative to the total amount of metals present in the layer.
Once both metal precursors are allowed to adsorb on the surface, an oxidizer is introduced into the chamber to convert both precursors into corresponding oxides. As such, a film containing both aluminum and hafnium oxides may be formed. This cycle including introduction of two metal precursors followed by introduction of an oxidizer may be repeated a number of times to build a switching layer having a desired thickness. The switching layer composition generally depends on the nature of precursors used in this approach. The resulting switching layer can be annealed, for example, at temperatures between 400 and 750 C.
FIGS. 3A-3C illustrate a schematic representation of an operation of an embedded nanoparticles memory structure according to some embodiments. In FIG. 3A, a ReRAM cell 300 including top electrode 330, bottom electrode 310, and resistance switching layer 320 provided in between top electrode 330 and bottom electrode 310. ReRAM cell 300 may also include other components, such as an embedded resistor, diode, and other components. ReRAM cell 300 is sometimes referred to as a memory element or a memory unit.
As discussed above with respect to FIGS. 1A-1C, electrode 330 and 310 can be formed from conductive materials. Resistance switching layer 320 can be formed from a dielectric material, which includes a concentration of electrically active defects 321, which may be at least partially provided into the layer during its fabrication. These defects can be used to form conductive filaments.
The resistance switching layer 320 can further include metal nanoparticles 322 and/or 323. For example, the nanoparticles 322 can include multiple particles distributed along the direction between the two electrodes 310 and 330. The nanoparticles 323 can be distributed with difference spacing. Other arrangements are possible as well and within the scope of this disclosure, such as one layer of nanoparticles distributed in the switching layer, or multiple layers of nanoparticles. The spacing of the nanoparticles can be configured to improve a performance of the memory cell, such as lower power consumption. The metal nanoparticles can include metal materials such as Au, Cu, Ag, or any other metals. The size of the nanoparticles can be less than 100 nm, such as between 2 and 10 nm, or between 2 and 5 nm.
During a forming operation, ReRAM cell 300 can change its structure to include conductive filaments 353 and 352, as shown in FIG. 3B. Since the lengths of the conductive filaments 352 and 353 are shorter than the lengths of the conductive filaments that occur in a switching layer without embedded nanoparticles (such as the filaments shown in FIG. 1B), the forming voltage can be reduced or eliminated, e.g., the forming voltage can be reduced to the programming voltage (e.g., a set voltage V_set). For example, short filaments 353 can require a lower forming voltage, which is less than the forming voltage for a switching layer without embedded nanoparticles, but can be still higher than the programming voltage. Shorter filaments 352 can require an even lower forming voltage, which can be similar to the programming voltage, and thus the forming process can be eliminated. The memory cells can be formed during the programming phase, for example, when the memory cell is first used.
The conductive filaments can be broken, for example, by applying a programming voltage such as a reset voltage V_reset. FIG. 3C shows the broken state 352 and 353 of the filaments. Repeated switching can be performed by applying set and reset voltages, creating and breaking conductive filaments connecting the two electrodes.
FIG. 4 illustrates a plot of a current passing through a unipolar ReRAM cell having embedded nanoparticles according to some embodiments. A metal-insulator-metal (MIM) structure 410 can be fabricated with an amount of metal nanoparticles 450 embedded in the insulator layer.
During operation, programming voltages or currents can be applied to the MIM structure 410 to change its resistance. For example, a programming voltage, e.g., V_set, can be applied to make a transition 415 from the initial configuration 410 to the low resistance state (LRS) 434. The MIM structure 430 of the low resistance state 434 can include conductive filaments in the insulator layer, with the nanoparticles acting as seed elements.
When another programming voltage, e.g., V_reset, is applied, the resistance can be transitioned 435 to a high resistance state (HRS) 412. The MIM structure 450 of the high resistance state 412 can include broken conductive filaments. The ReRAM cell may be programmed, e.g., switched back and forth between its LRS and HRS many times through the applications of set and reset voltages. Applying the set voltage forms one or more conductive paths in the resistance switching layer as shown in 430. Applying the reset voltage can destroy the conductive paths in the resistance switching layer as shown in 450.
In the figure, the polarity of the reset voltage and the set voltage are the same, which represents unipolar memory devices. Also, the set voltage is shown as being higher than the reset voltage. Other configurations can also be used, for example, the reset voltage can be higher than the set voltage, or the polarity of the reset voltage and the set voltage can be different, as in the case of bipolar devices. Further, the above description is served as an illustration of the possible operating mechanism, and is intended as a hypothesis for a model of the present embedded nanoparticle memory structures, and should not affect the validity of the present invention.
In some embodiments, the incorporation of metal nanoparticles can allow forming-free memory devices, e.g., the fabrication of memory devices that does not need the forming operation of applying a forming voltage. For example, by providing nanoparticles with a very close spacing, the formation of the conductive filaments can be performed during the device programming, e.g., by applying the set voltage. Alternatively, the nanoparticles can allow a reduction in forming voltage. For example, by providing nanoparticles in the switching layer with any spacing or distribution, the formation of the conductive filaments can be facilitated during the device forming process, e.g., allowing a lower forming voltage.
FIGS. 5A-5F illustrate various configurations of memory structures having embedded nanoparticles according to some embodiments. In FIG. 5A, a memory structure is shown, including a switching layer 520 disposed between two electrodes 510 and 530. Nanoparticles 522 are distributed within the switching layer 520. The nanoparticles can form multiple levels between the two electrodes, for example, to reduce the spacing, e.g., the lengths, of the conductive filaments. In the figure, two levels of nanoparticles are shown, but one or more levels can also be used. Further, one column of nanoparticles is shown, but more columns can also be used, e.g., arrays of nanoparticles distributed in rows and columns in the switching layer 520.
In FIG. 5B, nanoparticles 523 can be distributed in a staggered configuration, which can vary the spacing between the nanoparticles, and as a result, varying the lengths of the conductive filaments when formed. In FIG. 5C, nanoparticles 524 can be distributed in the middle of the switching layer. Nanoparticles 525 can be placed near the interfaces of the switching layer with the electrodes. The nanoparticles 525 can be disposed in the switching layer and touching the electrodes. For example, after the bottom electrode 510 is deposited, the nanoparticles can be provided on the electrode surface, before or during the deposition of the switching layer 520. Alternatively, the nanoparticles 525 can be disposed in the switching layer and separated from the electrodes. For example, after the bottom electrode 510 is deposited, a thin layer of switching layer can be deposited before providing the nanoparticles. Afterward, additional portions of the switching layer can be deposited, covering the nanoparticles
In FIG. 5D, nanoparticles 541 can be disposed in the electrodes, for example, top electrode 530, in addition to other nanoparticles 526 in the switching layer 520. For example, at the beginning of the deposition of the electrode 530, nanoparticles 541 can be provided so that the nanoparticles 541 can be at least partially embedded in the electrode 530. In FIG. 5E, in addition to nanoparticles 542 embedded in electrode 530, the nanoparticles 527 can be distributed in rows and columns or can be distributed in a staggered configuration. In FIG. 5F, nanoparticles 543 can be disposed at least partially embedded in top electrode 530, and nanoparticles 544 can be disposed at least partially embedded in bottom electrode 510. The nanoparticles 528 can be distributed in rows and columns or can be distributed in a staggered configuration. The configurations shown are only for illustrations and examples, and other configurations can also be used. For example, multiple nanoparticles can be arranged in one or more rows in directions parallel to the surface of the electrodes. Multiple nanoparticles can also be arranged in one or more columns in directions perpendicular to the surface of the electrodes.
FIGS. 6A-6H illustrate a process flow for forming a memory structure having embedded nanoparticles according to some embodiments. In FIG. 6A, a bottom electrode 610 is provided. For example, the electrode 610 can be deposited on a substrate, or the electrode 610 can be part of the substrate, e.g., a component of an underlying structure on the substrate. In FIG. 6B, nanoparticles 642 can be deposited on the electrode 610. Nanoparticles 642 can be deposited by themselves, or can be embedded in a deposited layer 640. For example, nanoparticles 642 can be provided in a solution, which then can be coated on the surface of the electrode 610. The solution then can be dried, e.g., evaporated, leaving the nanoparticles on the surface (FIG. 6C). In FIG. 6D, an insulator layer 622 can be deposited over the nanoparticles, thus can embedded the nanoparticles in the insulator layer. The process can be repeated, for example, by depositing another layer of nanoparticles 643 (FIG. 6E), another layer of insulator material 623 (FIG. 6F), and another layer of nanoparticles 644 (FIG. 6G). Electrode 630 can be deposited over the stack of insulator layer/nanoparticles (FIG. 6H).
FIG. 7 illustrates a flowchart for forming a memory device according to some embodiments. The described flowchart is a general description of techniques used to form the memory devices described above. The flowchart describes techniques for forming a memory device generally including two electrodes and one or more layers disposed there between. Although certain processing techniques and specifications are described, it is understood that various other techniques and modifications of the techniques described herein may also be used.
In operation 710, a substrate is provided. The substrate can be used for receiving various deposited components of the ReRAM cell. Furthermore, the same substrate often is used for receiving components of multiple ReRAM cells. For example, large memory cell arrays may be formed on the same substrate. Components of multiple ReRAM cells may be formed from the same set of initial layers formed on that substrate. The substrate may include one or more signal lines or contacts. These lines or contacts provide an electrical connection to a bottom electrode. In some embodiments, the bottom electrode formed in a subsequent operation can serve as a signal line. In a similar manner, a top electrode formed in another subsequent operation can function as a signal line or it may be connected to a separate signal line.
The substrate can have a first layer. Alternatively, a first layer can be deposited on the substrate. The first layer can be operable as a first or bottom electrode. The bottom electrode can include titanium nitride or platinum. The bottom electrode may be formed using ALD, CVD, sputtering, or some other techniques. For example, a titanium nitride electrode may be formed using sputtering. Deposition of the titanium nitride electrode may be performed using a titanium target in a nitrogen atmosphere maintained at a pressure of between about 3-20 mTorr. The power may be maintained at 350-500 Watts that may result in a deposition rate of about 0.5-5 Angstroms per second (depending on the size of the target sample and other process parameters). Some of the provided process parameters are for illustrative purposes only and generally depend on deposited materials, tools, deposition rates, and other factors. The bottom electrode may have any thickness, for example between about 5 nm and about 500 nm thick.
In operation 720, a second layer is deposited over the first layer. The second layer can contain a plurality of metal nanoparticles. The metal nanoparticles can include a metal component, such as gold, copper, or silver. The size of the metal nanoparticles can be less than 100 nm, such as less than 50 or 10 nm, or can be between 1 and 5 nm. The second layer can from nanoparticles at the interface of the switching layer with the electrode. The second layer deposition can be omitted, for example, in memory configurations that do not require nanoparticles at the electrode/switching layer interface.
The second layer can be formed by solvent coating. For example, a solution can be prepared, which contains the nanoparticles. The solution can be spread over the first layer, for example, by liquid coating, spray coating, or vapor coating. The solvent can be vaporized, for example, by substrate heating, leaving the nanoparticles dispersed on the first layer.
In some embodiments, the solution can be prepared by micelle technology. For example, to make gold nanoparticles in micelles, a source of gold, such as gold chloride (AuCl), can be dissolved in a solvent solution. For example, the solvent solution can include an organic solvent such as octane or butanol. A surfactant, such as a soap, can be added to the solution to help control the growth of the gold nanoparticles. The surfactant can include molecules with a hydrophobic tail and hydrophilic head. Because of this structure, the molecules can form micelles, which are tiny spheres, arranged on a surface of a sphere. Water can be trapped inside these micelles, which can separate the water inside the micelles from the organic solvent outside the micelles. Since gold chloride is soluble in water, gold chloride can be inside the micelles with the water.
A reactant can be added to reduce gold chloride to gold. For example, sodium borohydride (NaBH₄) can be added to the solution. Since sodium borohydride is also water soluble, it can enter the micelles and react with gold chloride to form metallic gold. The reaction stops when gold chloride is all reduced. The metallic gold can be crystallized into gold nanoparticles.
The size of the gold nanoparticles can be controlled by the concentration of gold chloride. A high concentration of gold chloride in the solution can generate larger gold nanoparticles. Further, the size of the gold nanoparticles can be governed by the choice of surfactant. For example, the reaction to reduce gold chloride to gold can be stopped when reaching the size of the micelles. In some embodiments, the sizes of the metal nanoparticles can be controlled, for example, by controlling the concentration of the metal source. The size of the metal nanoparticles can affect the performance of the memory cells which have the nanoparticles embedded in the switching layers.
The density of gold nanoparticles in the solution can be controlled by the choice of surfactants since the separation between micelles can be controlled by the block copolymer chain length. For example, a surfactant having a long block copolymer chain length can generate a micelle cluster with large separations between the micelles. In some embodiments, the separation of the metal nanoparticles can be controlled, for example, by controlling the block copolymer chain length of the micelles, e.g., the surfactant solution. The separation of the metal nanoparticles can affect the performance of the memory cells which have the nanoparticles embedded in the switching layers. The above description is an illustration of the formation of metal nanoparticles in the memory structures. Other metal sources, solvents, surfactants, and processes can be used to generate metal nanoparticles suitable for memory cell fabrication.
In operation 730, a third layer can be deposited over the second layer. In some embodiments, the second layer can include only the metal nanoparticles, and thus the third layer can be deposited over the first layer in areas not covered by the nanoparticles. The third layer can be operable as a resistive switching layer, or a portion of the resistive switching layer, e.g., additional layers can be deposited to combine with the third layer to form the resistive switching layer. The third layer can include a metal oxide, such as hafnium oxide, aluminum oxide, zirconium oxide, or any combination thereof.
The third layer may be formed using reactive sputtering, ALD, or other techniques. For example, a third layer having hafnium oxide may be formed using reactive sputtering by employing a hafnium target in an oxygen atmosphere. Power of 300-1000 Watts (W) may be used to achieve deposition rates of between about 0.1 and 3.0 Angstroms per second. These process parameters are provided as examples and generally depend on deposited materials, tools, deposition rates, and other factors.
In some embodiments, the third layer is formed using ALD. This technique includes one or more cycles, each involving the following two four steps: introducing one or more first precursors, such as a hafnium containing precursor, into the depositing chamber to form an absorbed layer, followed by purging these precursors reactive agents, and then introducing one or more second precursors, such as a oxidation reactant, that will react with the absorbed layer to form a portion of or the entire third layer, followed by purging the second precursor reactive agents. Selection of precursors and processing conditions depend on desired composition, morphology, and structure of each portion of the electrode.
A layer formed during each atomic layer deposition cycle described above may be between less than about 0.5 nm thick, such as between 0.02 and 0.2 nm. The cycle may be repeated multiple times until the overall second layer (and subsequently the thickness of the resistive switching layer) reaches it desired thickness. In some embodiments, the thickness of the third layer can be less than 30 nm, such as less than 10 or 5 nm, e.g., between 0.2 and 3 nm.
ALD techniques are now briefly described to provide better understanding of various processing features. First precursors can be introduced into the ALD chamber and allowed to flow over the deposition surface (which may have previously deposited ALD layers) provided therein. The first precursors can include one or more precursors. For example, the first precursors can include a hafnium containing precursor. The first precursors can include two or more precursors, such as a hafnium containing precursor and a reactive precursor such as reactive hydrogen or remote plasma hydrogen.
The first precursors can be introduced in the form of pulses. Between the pulses, the reaction chamber is purged, for example, with an inert gas to remove unreacted precursors, reaction products, and other undesirable components from the chamber.
The introduced precursor adsorbs (e.g., chemisorbs) on the deposition surface. Subsequent pulsing with a purging gas removes excess precursor from the deposition chamber. In some embodiments, purging is performed before full saturation of the substrate surface occurs with the precursors. In other words, additional precursor molecules could have been further adsorbed on the substrate surface if the purging was not initiated so early. Without being restricted to any particular theory, it is believed that partial saturation can be used to introduce defects into the formed layer, e.g., during forming of a resistive switching layer.
After the initial precursor pulsing and purging of the first precursors, a subsequent pulse introduces second precursors. The second precursors can act as reactant agent to react with the adsorbed metal containing molecules. The second precursors can include one or more precursors. For example, the second precursors can include an oxidation agent.
Reaction byproducts and excess reactants are then purged from the deposition chamber. The saturation during the reaction and purging stages makes the growth self-limiting. This feature helps to improve deposition uniformity and conformality and allows more precise control of the resulting resistive switching characteristics.
The temperature of the substrate during atomic layer deposition may be between about 200° C. to 350° C. The precursor may be either in gaseous phase, liquid phase, or solid phase. If a liquid or solid precursor is used, then it may be transported into the chamber an inert carrier gas, such as helium or nitrogen.
Some examples of hafnium containing precursors include bis(tert-butylcyclopentadienyl) dimethyl hafnium (C₂₀H₃₂Hf), bis(methyl-η5-cyclopentadienyl) methoxymethyl hafnium (HfCH₃(OCH₃)[C₅H₄(CH₃)]₂), bis(trimethylsilyl) amido hafnium chloride ([[(CH₃)₃Si]₂N]₂HfCl₂), dimethylbis(cyclopentadienyl) hafnium ((C₅H₅)₂Hf(CH₃)₂), hafnium isopropoxide isopropanol adduct (C₁₂H₂₈HfO₄), tetrakis(diethylamido) hafnium ([(CH₂CH₃)₂N]₄Hf)—also known as TEMAH, tetrakis(ethylmethylamido) hafnium ([(CH₃)(C₂H₅)N]₄Hf), tetrakis(dimethylamido) hafnium ([(CH₃)₂N]₄Hf)—also known as TDMAH, and hafnium tert-butoxide (HTB). Some hafnium containing precursors can be represented with a formula (RR′N) 4Hf, where R and R′ are independent hydrogen or alkyl groups and may be the same or different. Some examples of aluminum containing precursors include aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) (Al(OCC(CH₃)₃CHCOC(CH₃)₃)₃), triisobutyl aluminum ([(CH₃)₂CHCH₂]₃Al), trimethyl aluminum ((CH₃)₃Al)—also known as TMA, Tris (dimethyl amido) aluminum (Al(N(CH₃)₂)₃). The nitrogen containing oxidizing agent may include ammonia (NH₃), which in some embodiments may be mixed with carbon monoxide (CO). Some examples of suitable oxidizing agents containing oxygen include water (H2O), peroxides (organic and inorganic, including hydrogen peroxide H₂O₂), oxygen (O₂), ozone (O₃), oxides of nitrogen (NO, N₂O, NO₂, N₂O₅), alcohols (e.g., ROH, where R is a methyl, ethyl, propyl, isopropyl, butyl, secondary butyl, or tertiary butyl group, or other suitable alkyl group), carboxylic acids (RCOOH, where R is any suitable alkyl group as above), and radical oxygen compounds (eg., O, O₂, O₃, and OH radicals produced by heat, hot-wires, and/or plasma).
In some embodiments, the thickness of the third layer can be controlled, for example, by controlling the number of pulses in the ALD process, or by controlling the sputtered deposited time in a sputter deposition process. The third layer thickness can regular the spacing of the metal nanoparticles, which can affect the performance of the memory cells which have the nanoparticles embedded in the switching layers.
In operation 740, a fourth layer is deposited over the third layer. The fourth layer can contain a plurality of metal nanoparticles. The metal nanoparticles can include a metal component, such as gold, copper, silver, tungsten, aluminum, titanium, cobalt, or nickel. The size of the metal nanoparticles can be less than 100 nm, such as less than 50 or 10 nm, or can be between 1 and 5 nm. The fourth layer can from nanoparticles inside the switching layer. The fourth layer deposition can be omitted, for example, in memory configurations that do not require nanoparticles in the switching layer.
The fourth layer can be formed by solvent coating. For example, a solution can be prepared, which contains the nanoparticles. The solution can be spread over the first layer, for example, by liquid coating, spray coating, or vapor coating. The solvent can be vaporized, for example, by substrate heating, leaving the nanoparticles dispersed on the first layer.
The deposition process of the third and fourth layers can be repeated, for example, to form multiple layers of nanoparticles in a layer of switching material. For example, in operation 750, a fifth layer can be deposited over the fourth layer. In some embodiments, the fourth layer can include only the metal nanoparticles, and thus the fifth layer can be deposited over the third layer in areas not covered by the nanoparticles. The fifth layer can be operable as a resistive switching layer, or a portion of the resistive switching layer, e.g., the fifth layer can be combined with the third layer to form the resistive switching layer.
In operation 760, a sixth layer is deposited over the fifth layer. The sixth layer can contain a plurality of metal nanoparticles. The metal nanoparticles can include a metal component, such as gold, copper, or silver. The size of the metal nanoparticles can be less than 100 nm, such as less than 50 or 10 nm, or can be between 1 and 5 nm. The sixth layer can from nanoparticles at the interface of the switching layer with the electrode. The sixth layer deposition can be omitted, for example, in memory configurations that do not require nanoparticles at the electrode/switching layer interface.
In operation 770, a seventh layer can be deposited over the sixth layer. The seventh layer can be operable as a second or top electrode. The top electrode can include titanium nitride or platinum. The top electrode may be formed using ALD, CVD, sputtering, or some other techniques. The top electrode may have any thickness, for example between about 5 nm and about 500 nm thick.
FIG. 8 illustrates a micelle solution according to some embodiments. A solution can be prepared, including a mixture of two components, such as water and solvent. The solvent can be an organic solvent, such as methane, benzene, octane, butanol, and any other types of solvents. A metal containing chemical can be added to the solution. The metal containing chemical can be selected to be soluble in the solution, such as soluble in water. A surfactant can be added to the solution. The surfactant can include molecules with a hydrophobic tail 844 and a hydrophilic head 842. The surfactant molecules can be arranged to form micelles 800, having the surfactant head 842 arranged in a sphere with the tail extended outward. A component of the solution, such as water 846, can be trapped inside the micelles, with the other component, such as the solvent 848, staying outside the micelles. Since the metal containing chemical 840 is soluble in water, the metal containing chemical can also be trapped inside the micelles. After introducing a reduction chemical to the solution, with the reduction chemical also soluble in water, the reduction chemical can react with the metal containing chemical to form metal nanoparticles 840.
The size 824 of the metal nanoparticles 840 can be controlled by the concentration of the metal containing chemical in the solution. For example, the metal in the metal containing chemical 846 that is trapped inside a micelle can all be reduced to form the metal nanoparticles. Thus the size of the metal nanoparticles is dictated by the amount of metal in the micelles.
The spacing 826 between the metal nanoparticles can be dictated by the length of the tail of the surfactant molecules. Thus a surfactant with a long polymer chain can provide a micelle solution with large spacing between metal nanoparticles.
FIG. 9 illustrates a schematic representation of atomic layer deposition apparatus for fabricating ReRAM cells according to some embodiments. For clarity, some components of apparatus 900 are not included in this figure, such as a wafer-loading port, wafer lift pins, and electrical feedthroughs. Apparatus 900 includes deposition chamber 902 connected to processing gas delivery lines 904. While FIG. 9 illustrates three delivery lines 904, any number of delivery lines may be used. Each line may be equipped with a valve and/or mass flow controller 906 for controlling the delivery rates of processing gases into deposition chamber 902. In some embodiments, gases are provided into delivery port 908 prior to exposing substrate 910 to processing gases. Deliver port 908 may be used for premixing gases (e.g., precursors and diluents) and even distribution of gases over the surface of substrate 910. Delivery port 908 is sometimes referred to as a showerhead. Delivery port 908 may include a diffusion plate 909 having with multiple holes for gas distribution.
Deposition chamber 902 encloses substrate support 912 for holding substrate 910 during its processing. Substrate support 912 may be made from a thermally conducting metal (e.g., W, Mo, Al, Ni) or other like materials (e.g., a conductive ceramic) and may be used to maintain the substrate temperature at desired levels. Substrate support 912 may be connected to drive 914 for moving substrate 910 during loading, unloading, process set up, and sometimes even during processing. Deposition chamber 902 may be connected to vacuum pump 916 for evacuating reaction products and unreacted gases from deposition chamber 902 and for maintaining the desirable pressure inside chamber 902.
Apparatus 900 may include system controller 920 for controlling process conditions during electrode and resistive switching layer deposition and other processes. Controller 920 may include one or more memory devices and one or more processors with a CPU or computer, analog and/or digital input/output connections, stepper motor controller boards, etc. In some embodiments, controller 920 executes system control software including sets of instructions for controlling timing, gas flows, chamber pressure, chamber temperature, substrate temperature, RF power levels (if RF components are used, e.g., for process gas dissociation), and other parameters. Other computer programs and instruction stored on memory devices associated with controller may be employed in some embodiments.
FIGS. 10A-10B illustrate a schematic representation of resistive switching ReRAM cell according to some embodiments. FIG. 10A shows a cross section view, and FIG. 10B shows a top view of a ReRAM cell. Resistive switching ReRAM cell 1000 includes substrate 1090, which may include a signal line. Alternatively, bottom electrode 1010 may serve as a signal line. Substrate 1090 provides a surface for deposition of bottom electrode 1010. Bottom electrode 1010 is disposed between substrate 1090 and resistive switching layer 1020. Top electrode 1030 is provided above resistive switching layer 1020.
Resistive switching layer 1020 can include a metal oxide material, such as hafnium oxide, aluminum oxide, zirconium oxide, or a combination thereof. In addition, the switching layer 1020 can include a 3D array of metal nanoparticles 1022, which can be distributed in rows and columns within the switching layer 1020. For example, the metal nanoparticles 1022 can have a lateral spacing 1025, e.g., along the x and y directions parallel to the surface of the switching layer 1020. The metal nanoparticles 1022 can have a vertical spacing 1027, e.g., along the z direction perpendicular to the surface of the switching layer 1020. The metal nanoparticles 1022 can have a size 1024.
The size 1024 of the metal nanoparticles, and the spacing of the metal nanoparticles, e.g., the lateral spacing 1025 and the vertical spacing 1027, can be optimized to improve the performance of the memory device. For example, these parameters can be designed to eliminate the forming operation of the switching layer, and/or reducing the programming voltages of the memory cell, thus reducing the power consumption of the memory devices.
The material of resistive switching layer 1020 can be substantially amorphous or nanocrystalline after formation of this layer. In some embodiments, resistive switching layer 1020 remains substantially amorphous after further processing of the layer, such as annealing, applying a formation voltage, and other operations. Furthermore, in some embodiments, resistive switching layer 1020 remains substantially amorphous during operation of ReRAM cell, i.e., applying switching voltages and reading voltages that drive corresponding currents.
In some embodiments, the thickness of restive switching layer 1020 is less than about 30 nm, such as between about 2 and 30 nm or, more specifically, between about 4 and 7 nm, for example, about 5 nm. The thickness of top and bottom electrodes 1010 and 1030 may be at least about 3 and 300 nm or, more specifically, between about 30 and 50 nm. In some embodiments, the thickness of one or both electrodes is less than 5 nm. Such electrodes may be deposited using ALD techniques.
In some embodiments, the size of the metal nanoparticles can be less than 50 nm, such as between 1 and 10 nm, or between 1 and 5 nm. In some embodiments, the lateral spacing of the metal nanoparticles can be less than 1000 nm, such as less than 100 nm, or can be less than 10 nm. The vertical spacing of the metal nanoparticles can be less than 100 nm, such as between 1 and 10 nm, such as between 1 and 5 nm, or between 0.2 and 3 nm.
In some embodiments, the size of the metal nanoparticles and the lateral spacing of the metal nanoparticles can be controlled in the preparation of a micelle solution. For example, the size of the metal nanoparticles can be regulated by adjusting the concentration of the metal containing chemical in the micelle solution. The lateral spacing of the metal nanoparticles can be regulated by selecting surfactant components having appropriate block copolymer chain. The vertical spacing of the metal nanoparticles can be regulated by controlling the deposition thickness of the portion of the switching layer 1020 between rows of metal nanoparticles. In some embodiments, the deposition thickness is less than 10 nm, such as less than 5 nm, or between 0.2 and 3 nm,
Electrodes 1010 and 1030 provide electronic communication to resistive switching layer 1020 of ReRAM cell 1000. One or both electrodes may directly interface resistive switching layer 1020 or be spaced apart by other layers, such as barrier layers, current limiting layer, and the like. Depending on the materials used for electrode construction, the electrode (e.g., an electrode formed from titanium nitride) itself may also serve as an adhesion layer and/or barrier layer. In some embodiments, one or both electrodes are also function as signal lines (i.e., bit and/or word lines) and are shared by other ReRAM cells.
Some examples of electrode materials include titanium nitride (TiN), and platinum. In some embodiments, barrier layers, adhesion layers, antireflection coatings and/or other layers may be used with the electrodes and to improve device performance and/or aid in device fabrication.
In some embodiments, one electrode may be a higher work function material, and the other electrode may be a lower work function material than the resistive switching layer. For example, an electrode can include titanium nitride and the other electrode can include platinum. Platinum is a noble metal (i.e., a metal with a low absolute value free energy change (|ΔG|) of oxide formation), which may be used for one electrode. The other electrode may be a lower work function material, such as titanium nitride. In some embodiments, the reset pulse at the electrode having the higher work function may be a positive pulse.
In some embodiments, one or both electrodes may be multi-layer electrodes formed by one or more different materials. For example, an electrode can include a base layer and capping layer. The base layer may include platinum, or titanium nitride. The capping layer may include tungsten, tungsten carbon nitride, and/or tungsten carbon. The multi-layer electrodes can be used to improve adhesion properties and performance of memory elements in some configurations and embodiments.
ReRAM cell 1000 may include another layer (not shown) that is operable as a current limiting layer. A material for this layer may have a suitable work function for controlling the electron flow through ReRAM cell. This specific selection may alter the magnitude of the generated switching currents. In some embodiments, the current limiting layer is used to increase or decrease the formed barrier height at the interface with resistive switching layer 1020. This feature is used to improve current flowing characteristics and reduce the magnitude of the switching currents. It should be noted that these changes in the barrier height will generally not affect the current ratio (I_ON/I_OFF), and thus not impacts detectability of different resistive states.
In some embodiments, the current limiting layer is between about 5 and 300 nm thick, such as between about 5 and 20 nm. This layer may be formed from a material that has a resistivity of between about 5 Ω-cm and 500 Ω-cm, such as between about 50 Ω-cm and 350 Ω-cm. In some embodiments, the current limiting layer is formed such that its resistance (R_RL) is between about 30 kΩ and about 30 MΩ, such as between about 300 kΩ and about 3 MΩ.
Resistivity is an intrinsic property of the material and can be controlled by adjusting the composition of the material. Some specific examples include adding alloying elements or doping atoms and/or adjusting the morphological structure of the materials, (e.g., shifting from amorphous to crystal structure). In some embodiments, a current limiting layer may include titanium oxide doped with niobium, tin oxide doped with antimony, or zinc oxide doped with aluminum.
Other examples of materials suitable for the current limiting layer include titanium nitride (Ti_xN_y), tantalum nitride (Ta_xN_y), silicon nitride (Si_xN_y), hafnium nitride (Hf_xN_y) or titanium aluminum nitride (Ti_xAl_yN_z) layer. Such layers may be formed using an ALD, CVD or PVD process as further described below.
FIGS. 11A-11B illustrate flowcharts for fabricating a resistive switching layer of a memory device according to some embodiments. In FIG. 11A, an array of metal nanoparticles can be formed on a layer using a micelle solution (operation 1110). The array of nanoparticles can be a 2D array along the exposed surface of the layer. The layer can include an electrode layer, and the array of metal nanoparticles can form at the surface of the electrode layer. Thus after a subsequent switching layer is deposited on the electrode, the array of metal nanoparticles can be disposed at the interface of the electrode and the switching layer. The layer can include a switching layer, and the array of metal nanoparticles can form at the surface of the switching layer. Thus after a second electrode layer is deposited on the switching layer, the array of metal nanoparticles can be disposed at the interface of the second electrode and the switching layer. The layer can include a first portion of a switching layer. Thus after a second portion of the switching layer is deposited on the first portion, the array of metal nanoparticles can be disposed inside the switching layer.
The micelle solution can be prepared to have metal nanoparticles embedded within the micelles. For example, a micelle solution having gold nanoparticles in the micelles can be prepared using gold chloride, soap surfactant, solution mixture of water, octane and butanol, and sodium borohydride as described above. The spacing between the micelles can be controlled by using polymer having different chain length. For example, different surfactant can create micelles with different tail's lengths, which can determine the spacing between the micelles.
The spacing between the micelles can be configured to improve a performance characteristic of a memory cell using the metal nanoparticles, such as a power consumption characteristic or a repeatability or reliability characteristic. For example, denser micelles, e.g., micelles with shorter spacing between them, can form denser array of metal nanoparticles, which can provide more seed locations for conductive filaments. The high density of conductive filaments can lower a programming voltage for the memory cell, since defects in the switching layer can have a shorter time to travel to the seed locations. The lower programming voltage can improve a power requirement characteristic of the memory cell, thus can improve the performance of the memory cell. Denser array of metal nanoparticles can also improve the repeatability or the reliability of the memory cell, for example, due to the simpler or easier to form filaments.
In FIG. 11B, 3D control of the metal nanoparticles can be achieved. The control of the lateral spacing can be achieved by the block copolymer chain length of the micelles in the micelle solution, as described above. In addition, the control of the vertical spacing can be achieved by the deposition process of the portions of the switching layer. The multiple dimension control of the metal nanoparticles can lead to the multiple controls of the filament formation, which can provide optimization of the memory cells having the embedded nanoparticles.
In operation 1120, a first layer is deposited. The first layer can be deposited on a substrate, on an electrode, on an electrode having an array of metal nanoparticles, on a portion of a switching layer, or on a portion of a switching layer having an array of metal nanoparticles. The first layer can be a portion of a switching layer. The first layer can be deposited by ALD. The thickness of the first layer can be configured to improve a performance characteristic of a memory device such as a power consumption characteristic or a repeatability or reliability characteristic. For example, the thickness of the first layer can determine the vertical spacing of metal nanoparticles, such as the separation between a bottom array and a top array of nanoparticles. Controlling the vertical spacing of the nanoparticles can provide an improvement or an optimization of a power consumption or a reliability of the memory cells.
In operation 1130, an array of metal nanoparticles can be formed on the first layer by a micelle solution. The lateral spacing of the nanoparticles can be controlled by the preparation of the micelle solution, as described above. The spacing between the micelles can also be configured to improve a performance characteristic of a memory device.
In operation 1140, the process can be repeated. For example, another first layer can be deposited, with the thickness configured to improve a performance characteristic of a memory device. Alternatively, another first layer and another array of nanoparticles can be formed on the existing first layer and first array of nanoparticles.
FIG. 12 illustrates a flowchart for forming a memory device according to some embodiments. In operation 1210, a substrate is provided wherein the substrate comprises a first layer, wherein the first layer is operable as a first electrode. In operation 1220, a second layer is deposited on the first layer, wherein the second is operable as a resistive switching layer. In operation 1230, a third layer is deposited on the second layer, wherein the third layer comprises metal nanoparticles disposed in micelles. The third layer can include an array of nanoparticles. In operation 1240, the process is repeated, e.g., another first layer and another second layer are formed on the existing first and second layers. In operation 1250, a fourth layer is deposited on the third layer, wherein the fourth layer is operable as a resistive switching layer. In operation 1260, a fifth layer is deposited on the fourth layer, wherein the fifth layer is operable as a second electrode.
In some embodiments, the embedded nanoparticles memory structures can be used in memory arrays, such as cross point memory arrays. FIG. 13A-13B illustrates memory arrays according to some embodiments. A brief description of memory arrays will now be described with reference to FIGS. 13A and 13B to provide better understanding to various aspects of thermally isolating structures provided adjacent to ReRAM cells and, in some examples, surrounding the ReRAM cells. ReRAM cells described above may be used in memory devices or larger integrated circuits (IC) that may take a form of arrays. FIG. 13A illustrates a memory array including nine ReRAM cells according to some embodiments. In general, any number of ReRAM cells may be arranged into one array. Connections to each ReRAM cell 1302 are provided by signal lines 1304 and 1306, which may be arranged orthogonally to each other. ReRAM cells 1302 are positioned at crossings of signal lines 1304 and 1306 that typically define boundaries of each ReRAM cell in array 1300.
Signal lines 1304 and 1306 are sometimes referred to as word lines and bit lines. These lines are used to read and write data into each ReRAM cell 1302 of array 1300 by individually connecting ReRAM cells to read and write controllers. Individual ReRAM cells 1302 or groups of ReRAM cells 1302 can be addressed by using appropriate sets of signal lines 1304 and 1306. Each ReRAM cell 1302 typically includes multiple layers, such as top and bottom electrodes, resistive switching layer, embedded resistors, embedded current steering elements, and the like, some of which are further described elsewhere in this document. In some embodiments, a ReRAM cell includes multiple resistive switching layers provided in between a crossing pair of signal lines 1304 and 1306.
As stated above, various read and write controllers may be used to control operations of ReRAM cells 1302. A suitable controller is connected to ReRAM cells 1302 by signal lines 1304 and 1306 and may be a part of the same memory device and circuitry. In some embodiments, a read and write controller is a separate memory device capable of controlling multiple memory devices each one containing an array of ReRAM cells. Any suitable read and write controller and array layout scheme may be used to construct a memory device from multiple ReRAM cells. In some embodiments, other electrical components may be associated with the overall array 1300 or each ReRAM cell 1302. For example, to avoid the parasitic-path-problem, i.e., signal bypasses by ReRAM cells in their low resistance state (LRS), serial elements with a particular non-linearity must be added at each node or, more specifically, into each element. Depending on the switching scheme of the ReRAM cell, these elements can be diodes or varistor-type elements with a specific degree of non-linearity. In the same other embodiments, an array is organized as an active matrix, in which a transistor is positioned at each node or, more specifically, embedded into each cell to decouple the cell if it is not addressed. This approach significantly reduces crosstalk in the matrix of the memory device.
In some embodiments, a memory device may include multiple array layers as, for example, illustrated in FIG. 13B. In this example, five sets of signal lines 1314 a-b and 1316 a-c are shared by four ReRAM arrays 1312 a-c. As with the previous example, each ReRAM array is supported by two sets of signal lines, e.g., array 1312 a is supported by 1314 a and 1316 a. However, middle signal lines 1314 a-b and 1316 b, each is shared by two sets ReRAM arrays. For example, signal line set 1314 a provides connections to arrays 1312 a and 1312 b. Top and bottom sets of signal lines 1316 a and 1316 c are only used for making electrical connections to one array. This 3-D arrangement of the memory device should be distinguished from various 3-D arrangements in each individual ReRAM cell.
Although the foregoing examples have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed examples are illustrative and not restrictive.

Claims

What is claimed is:

1. A resistive random access memory cell comprising:

a first layer operable as a first electrode;

a second layer operable as a resistive switching layer, wherein the second layer is disposed above the first layer, wherein the second layer comprises one or more arrays of metal nanoparticles, wherein the arrays of metal nanoparticles are disposed inside the second layer;

a third layer operable as a second electrode, wherein the third layer is disposed above the second layer.

2. A memory cell as in claim 1, wherein the array of metal nanoparticles is disposed at an interface of the switching layer and an electrode.

3. A memory cell as in claim 1, wherein a spacing between the array of metal nanoparticles and an electrode is between 1 and 10 nm.

4. A memory cell as in claim 1, wherein the second layer comprises two or more arrays of metal nanoparticles, wherein a spacing between the two arrays of metal nanoparticles is between 1 and 10 nm.

5. A memory cell as in claim 1, wherein a spacing between metal particles in the array of metal nanoparticles is between 1 and 10 nm.

6. A memory cell as in claim 1, wherein a size of the metal particles is between 1 and 5 nm.

7. A memory cell as in claim 1, wherein the second layer comprises two or more arrays of metal nanoparticles, wherein the two or more arrays of metal nanoparticles are aligned between the two electrodes.

8. A memory cell as in claim 1, wherein the second layer comprises two or more arrays of metal nanoparticles, wherein the two or more arrays of metal nanoparticles are staggered between the two electrodes.

9. A method of forming a resistive random access memory cell, the method comprising:

providing a substrate comprising a first layer, wherein the first layer is operable as a first electrode;

depositing a second layer over the first layer, wherein the second layer comprises a first material which is operable as a resistive switching layer;

depositing an array of metal nanoparticles on the second layer;

depositing a third layer on the array of metal nanoparticles, wherein the third layer comprises the first material;

depositing a fourth layer over the third layer, wherein the fourth layer is operable as a second electrode.

10. A method as in claim 9, further comprising

depositing a second array of metal nanoparticles on the first layer before forming the second layer.

11. A method as in claim 9, further comprising

repeating the steps of depositing an array of metal nanoparticles and depositing the third layer.

12. A method as in claim 9, further comprising

depositing a third array of metal nanoparticles before forming the fourth layer.

13. A method as in claim 9, further comprising

annealing the first, second, and third layers at a temperature between 400 and 750 C.

14. A method as in claim 9, wherein depositing the second layer comprises using atomic layer deposition (ALD).

15. A method as in claim 9, wherein depositing the array of metal nanoparticles comprises coating with a micelle solution, wherein the micelle solution comprises micelles, wherein micelles comprises metal nanoparticles.

16. A method of improving a performance of a resistive random access memory cell, wherein the resistive memory cell comprises a switching layer disposed between two electrodes, the method comprising:

forming an array of metal nanoparticles in the switching layer;

controlling a vertical spacing of the metal nanoparticles, wherein the vertical spacing comprises a distance along a direction perpendicular to a surface of the electrodes;

controlling a lateral spacing of the metal nanoparticles, wherein the lateral spacing comprises a distance along a direction parallel to a surface of the electrodes.

17. A method as in claim 18, wherein controlling a vertical spacing of the metal nanoparticles comprises controlling a deposition thickness of the switching layer.

18. A method as in claim 18, wherein controlling a lateral spacing of the metal nanoparticles comprises controlling a separation of the metal nanoparticles in a micelle solution, wherein the micelle solution is used to form the array of metal nanoparticles in the switching layer.

19. A memory cell as in claim 18, wherein the deposition thickness of the switching layer is less than 10 nm.

20. A memory cell as in claim 18, wherein the separation of the metal nanoparticles in a micelle solution is less than 10 nm.