US20140210012A1 - Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions - Google Patents
Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions Download PDFInfo
- Publication number
- US20140210012A1 US20140210012A1 US13/756,134 US201313756134A US2014210012A1 US 20140210012 A1 US20140210012 A1 US 20140210012A1 US 201313756134 A US201313756134 A US 201313756134A US 2014210012 A1 US2014210012 A1 US 2014210012A1
- Authority
- US
- United States
- Prior art keywords
- gate
- substrate region
- source
- substrate
- drain regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 42
- 230000000295 complement effect Effects 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 94
- 239000004065 semiconductor Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 16
- 239000007943 implant Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 238000002513 implantation Methods 0.000 abstract description 8
- 230000008569 process Effects 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000013459 approach Methods 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 206010010144 Completed suicide Diseases 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Definitions
- the embodiments described herein generally relate to the manufacturing of integrated circuits.
- a non-volatile memory such as Flash memory, retains stored data even if power to the memory is removed.
- a non-volatile memory cell stores data, for example, by storing electrical charge in an electrically isolated floating gate or in a charge-trapping layer underlying a control gate of a field-effect transistor (FET). The stored electrical charge Controls the threshold of the FET, thereby controlling the memory state of the cell.
- FET field-effect transistor
- non-memory devices perform, for example, decoding, charge-pumping, and other functions related to memory operations.
- the substrate may also include non-memory devices to provide functions that are not related to memory operations.
- Such non-memory devices incorporated on the same substrate as the memory cells may include transistors tailored for high-speed operations, while other transistors are tailored for handling high operating voltages. Integrating the processing of memory cells, such as a split-gate memory cell, with the processing of one or more types of non-memory transistors on the same substrate is challenging as each requires different fabrication parameters.
- analog devices pose manufacturing challenges.
- Many analog devices such as a low noise amplifier, have more stringent noise tolerances than FET devices used in digital logic.
- Mixed signal electronics those with integrated digital and analog signals, can be found in music players, cameras and cellular telephones.
- these analog devices pose fabrication challenges due to the different fabrication parameters. Accordingly, there is a need for device and methods for integrating field effect transistors and other devices on the same substrate to facilitate improved cost, performance, reliability, or manufacturability.
- Embodiments described herein include methods, systems and devices for forming high voltage gates in a computer memory or other integrated circuitry.
- a method is described wherein a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor.
- a high energy implantation is forming lightly doped source and drain regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing.
- a method of manufacturing a semiconductor device that includes a first substrate region and a second substrate region.
- a gate layer is disposed on the first and second substrate regions.
- a first gate is formed in the first substrate region from the gate layer.
- a second gate is formed in the second substrate region from the gate layer.
- First lightly doped source and drain regions are formed substantially adjacent to the second gate.
- a third gate is formed in the second substrate region from the gate layer.
- Second lightly doped source and drain regions are formed substantially adjacent to the third gate.
- the second lightly doped source and drain regions are of complementary conductivity type to the first lightly doped source and drain regions.
- the third gate is formed after the first source and drain regions are formed.
- a semiconductor device in an embodiment, includes a first substrate region and a second substrate region. There is a first gate in the first substrate region. There is a second gate in the second substrate region. There is a third gate in the second substrate region. There are first lightly doped source and drain regions substantially adjacent to the second gate. There are second lightly doped source and drain regions, substantially adjacent to the third gate. In the embodiment, the second lightly doped source and drain regions are of a complementary conductivity type to the first lightly doped source and drain regions. The second gate and the third gate are configured to withstand the same amount of voltage, which is more than the first gate is configured to withstand. Additionally, the first lightly doped drain region is older than (i.e., formed before) the third gate.
- a method of manufacturing a semiconductor device that includes a first substrate region and a second substrate region.
- a thin poly layer is disposed on the first and second substrate regions.
- a first gate is formed in the first substrate region from the thin poly layer.
- a first photoresist mask is disposed on the thin poly layer, across both the first substrate region and the second substrate region.
- a second gate is etched in the second substrate region through the first photoresist mask.
- a first high energy implant is performed through the first photoresist mask while the photoresist mask protects the poly in both the first and second substrate regions. The first photoresist mask is removed.
- a second photoresist mask is disposed on the thin poly layer, across both the first substrate region and the second substrate region.
- a third gate is etched in the second substrate region through the second photoresist mask.
- a second high energy implant is performed through the second photoresist mask while the photoresist mask protects the poly in both the first and second substrate regions.
- the second photoresist mask is removed. According to this method, lightly doped source and drain regions of complementary conductivity types can be formed without the need of a hard mask.
- FIG. 1 illustrates an example of a split-gate non-volatile memory cell, according to an embodiment.
- FIG. 2 illustrates an example circuit diagram of memory cell including connections to various metal layers in a semiconductor device, according to an embodiment.
- FIG. 3 illustrates an example semiconductor device that includes both memory and peripheral circuitry embedded in the same substrate, according to an embodiment.
- FIGS. 4A-4J illustrate a semiconductor device in various stages of manufacturing, according to an embodiment.
- etch or “etching” is used herein to generally describe a fabrication process of patterning a material, such that at least a portion of the material remains after the etch is completed.
- the process of etching silicon involves the steps of patterning a masking layer (e.g., photoresist or a hard mask) above the silicon, and then removing the areas of silicon no longer protected by the masking layer. As such, the areas of silicon protected by the mask would remain behind after the etch process is complete.
- etching may also refer to a process that does not use a mask, but still leaves behind at least a portion of the material after the etch process is complete.
- etching When etching a material, at least a portion of the material remains behind after the process is completed. However, “removing” is considered to be a broad term that may incorporate etching.
- regions of the substrate upon which the field-effect devices are fabricated are mentioned. It should be understood that these regions may exist anywhere on the substrate and furthermore that the regions may not be mutually exclusive. That is, in some embodiments, portions of one or more regions may overlap. Although up to three different regions are described herein, it should be understood that any number of regions may exist on the substrate and may designate areas having certain types of devices or materials. In general, the regions are used to conveniently describe areas of the substrate that include similar devices and should not limit the scope or spirit of the described embodiments.
- deposit or “dispose” are used herein to describe the act of applying a layer of material to the substrate. Such terms are meant to describe any possible layer-forming technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.
- substrate as used throughout the descriptions is most commonly thought to be silicon. However, the substrate may also be any of a wide array of semiconductor materials such as germanium, gallium arsenide, indium phosphide, etc. In other embodiments, the substrate may be electrically non-conductive such as a glass or sapphire wafer.
- Poly as used throughout the descriptions is most commonly thought to be polycrystalline silicon. Poly comprises multiple small crystals, as opposed to being a single monocrystal. Poly can be doped, or may have metal or a metal suicide deposited over it.
- Poly in this application is used as one example of a gate conductor. Other conductors may be used to form the gates, for example metals, alloys other doped semiconductors or conducting materials as would become apparent to a person having ordinary skill in the art. The use of “poly” in the description of the embodiments is not to be limiting.
- a non-volatile memory cell is programmed using, for example, hot carrier injection to place charge into a storage layer.
- High drain and gate voltages are used to facilitate the programming process, and the memory cell conducts relatively high current during programming, which can be undesirable in low voltage or low power applications.
- a split-gate memory cell is a type of non-volatile memory cell, in which a select gate is placed adjacent a memory gate.
- the select gate is biased at a relatively low voltage, and only the memory gate is biased at the high voltage to provide the vertical electric field necessary for hot-carrier injection. Since acceleration of the carriers takes place in the channel region mostly under the select gate, the relatively low voltage on the select gate results in more efficient carrier acceleration in the horizontal direction compared to a conventional Flash memory cell. That makes hot-carrier injection more efficient with lower current and lower power consumption during programming operation.
- a split-gate memory cell may be programmed using techniques other than hot-carrier injection, and depending on the technique, any advantage over the conventional Flash memory cell during programming operation may vary.
- the erased state of the memory gate can be near or in depletion mode (i.e., threshold voltage, Vt, less than zero volt). Even when the erased memory gate is in such depletion mode, the select gate in the off state prevents the channel from conducting substantial current. With the threshold voltage of the erased state near or below zero, the threshold voltage of the programmed state does not need to be very high while still providing a reasonable read margin between erased and programmed states. Accordingly, the voltages applied to both select gate and memory gate in read operation can be less than or equal, to the supply voltage. Therefore, not having to pump the supply voltage to a higher level makes the read operation faster.
- Vt threshold voltage
- FIG. 1 illustrates an example of a split-gate non-volatile memory cell 100 according to an embodiment.
- Memory cell 100 is formed on a substrate 102 , such as silicon.
- substrate 102 is commonly p-type or a p-type well while a first doped source/drain region 104 and a second doped source/drain region 106 are n-type.
- substrate 102 it is also possible for substrate 102 to be n-type while regions 104 and 106 are p-type.
- Memory cell 100 includes two gates, a select gate 108 and a memory gate 110 .
- Each gate may be a doped poly layer formed by well known, for example, deposit and etch techniques to define the gate structure.
- Select gate 108 is disposed over a dielectric layer 112 .
- Memory gate 110 is disposed over a charge trapping dielectric 114 having one or more dielectric layers.
- charge trapping dielectric 114 includes a silicon nitride layer sandwiched between two silicon dioxide layers to create a three-layer stack collectively and commonly referred to as “ONO”.
- Other charge trapping dielectrics may include a silicon-rich nitride film, or any film that includes, but is not limited to, silicon, oxygen, and nitrogen in various stoichiometries.
- a vertical dielectric 116 is also disposed between select gate 108 and memory gate 110 for electrical isolation between the two gates.
- vertical dielectric 116 and charge trapping dielectric 114 are the same dielectric, while other examples form one dielectric before the other (e.g., they can have different dielectric properties.) As such, vertical dielectric 116 need not include the same film structure as charge trapping dielectric 114 .
- regions 104 and 106 are created by implanting dopants using, for example, an ion implantation technique. Regions 104 and 106 form the source or drain of the split-gate transistor depending on what potentials are applied to each.
- region 104 is commonly referred to as the drain, while region 106 is commonly referred to as the source, independent of the relative biases. It is to be understood that this description is meant to provide a general overview of a common split-gate architecture and that, in actual practice, many more detailed steps and layers are provided to form the final memory cell 100 .
- a positive voltage on the order of 5 volts is applied to region 106 while region 104 and substrate 102 are grounded.
- a low positive voltage on the order of 1.5 volts, for example, is applied to select gate 108 while a higher positive voltage on the order of 8 volts, for example, is applied to memory gate 110 .
- charge trapping dielectric 114 the electrons are trapped within a nitride layer of charge trapping dielectric 114 .
- This nitride layer is also commonly referred to as the charge trapping layer.
- the trapped charge within charge trapping dielectric 114 store the “high” bit within memory cell 100 , even after the various supply voltages are removed.
- a positive voltage on the order of 5 volts is applied to region 106 while region 104 is floated or at a certain bias, and select gate 108 and substrate 102 are typically grounded.
- a high negative voltage on the order of ⁇ 8 volts, for example, is applied to memory gate 110 .
- the bias conditions between memory gate 110 and region 106 generate holes through band-to-band tunneling. The generated holes are sufficiently energized by the strong electric field under memory gate 110 and are injected upwards into charge trapping dielectric 114 . The injected holes effectively erase the memory cell 100 to the “low” bit state.
- a low voltage is applied to each of the select gate, memory gate, and region 104 in the range between zero and 3 volts, for example, while region 106 and substrate 102 are typically grounded.
- the low voltage applied to the memory gate is chosen so that it lies substantially equidistant between the threshold voltage necessary to turn on the transistor when storing a “high” bit and the threshold voltage necessary to turn on the transistor when storing a “low” bit in order to clearly distinguish between the two states.
- the memory cell holds a “low” bit and if the application of the low voltage during the “read” operation does not cause substantial current to flow between regions 104 and 106 , then the memory cell holds a “high” bit.
- FIG. 2 illustrates an example circuit diagram of memory cell 100 including connections to various metal layers in a semiconductor device. Only a single memory cell 100 is illustrated, however, as evidenced by the ellipses in both the X and Y direction, an array of memory cells may be connected by the various lines running in both the X and Y directions. In this way, one or more memory cells 100 may be selected for reading, writing, and erasing bits based on the bit line (BL) and source line (SL) used.
- BL bit line
- SL source line
- Source line (SL) runs along the X direction and is formed in a first metal layer (M1).
- Source line (SL) may be used to make electrical connection with doped region 106 of each memory cell 100 along a row extending in the X direction.
- Bit line (BL) runs along the Y direction and is formed in a second metal layer (M2).
- Bit line (BL) may be used to make electrical connection with doped region 104 of each memory cell 100 along a column extending in the Y direction.
- circuit connections shown in FIG. 2 are only exemplary and that the various connections could be made in different metal layers than those illustrated.
- memory cells 100 may be arrayed in the Z direction as well formed within multiple stacked layers.
- FIG. 3 illustrates an example semiconductor device that includes both memory and peripheral circuitry in the same substrate.
- substrate 102 includes a core region 302 and a periphery region 304 .
- Core region 302 includes a plurality of memory cells 100 that may operate similarly to those previously described. It should be understood that the cross-section of FIG. 3 is only exemplary, and that core region 302 and periphery region 304 may be located in any area of substrate 102 and may be made up of various different regions. Furthermore, core region 302 and periphery region 304 may exist in the same general area of substrate 102 .
- Periphery region 304 may include integrated circuit components such as resistors, capacitors, inductors, etc., as well as transistors.
- periphery region 304 includes a plurality of high-voltage transistors 306 and low-voltage transistors 308 .
- high-voltage transistors 306 exist in a separate region of substrate 102 than low-voltage transistors 308 .
- High-voltage transistors 306 are capable of handling voltages up to 25 volts in magnitude, for example, while low-voltage transistors 308 operate at a faster speed, but cannot operate at the same high voltages as high-voltage transistors 306 .
- low voltage transistors 308 are designed to have a shorter gate length than high voltage transistors 306 .
- High-voltage transistors 306 are commonly characterized as having a thicker gate dielectric 310 than the gate dielectric of low-voltage transistors 308 .
- High energy implants are often performed with more than 80,000 electron volts depending on implant species.
- a high-energy implant to form the lightly-doped drain in high voltage transistors 306 can penetrate the entire thickness of the thin poly and adversely affect the doping profile of the transistor channel region below the poly gate.
- a thin poly layer can be from 40 nanometers (nm) to 100 nm thick, and is preferably 80 nm thick.
- One approach to protecting the thin poly is described in co-pending application Ser. No. 13/715,739, entitled “High Voltage Gate Formation,” which is herein incorporated by reference in its entirety.
- the co-pending application's approach uses a hard mask to protect against the high energy implantation.
- the co-pending application's approach also used three blanket resist processes to create the high voltage transistors 306 (i.e., the blanket resist to etch the low voltage transistor 308 would be a fourth blanket resist).
- One additional manufacturing advantage to not having a hard mask is that, as poly becomes thinner, the appropriate hard masks approach becomes more difficult to make compatible with an advanced logic process flow.
- FIGS. 4A-4J collectively illustrate an example fabrication process for forming a semiconductor device 400 , according to an embodiment of the present invention. It should be understood that the various layers and structures are not necessarily drawn to scale, and that other processing steps may be performed between those steps illustrated and described herein, as would be understood by one skilled in the art given the present disclosure.
- FIG. 4A illustrates a substrate 402 comprising silicon, or the like, and shallow trench isolations 404 formed therein.
- a poly layer 408 is formed on the substrate 402 .
- the poly layer 408 is an example of a gate layer.
- Two instances of a photoresist mask 406 are patterned on the poly layer 408 .
- One way to form a photoresist is to spin on a blanket resist, use a photomask to expose certain sections of the blanket resist to ultra-violet light, and then apply a developer to the blanket resist.
- the gate layer can comprise a metal layer.
- a poly layer may be disposed before the metal layer is disposed. This poly layer may serve as a sacrificial gate to be replaced by a metal gate at a later step.
- One approach to creating a metal gate is described in co-pending application Ser. No. 11/735,241, entitled “Memory System with Poly Metal Gate,” which is herein incorporated by reference in its entirety.
- etching for example, is used to remove the portions of the poly layer 408 that are unprotected by the photoresist mask 406 .
- the etching defines a section of poly that, with a source, a drain and wiring, can serve as a low voltage transistor 410 .
- the photoresist 406 is then stripped.
- the low voltage transistor 410 may instead serve as a memory cell.
- a dielectric on the region of the substrate 402 before disposing the poly layer 408 . If there were a dielectric underneath the low voltage transistor 410 , the low voltage transistor 410 could serve as a select gate.
- a charge trapping layer such as ONO, could be added followed by an additional layer of poly to form a memory gate to complete the memory cell. This approach is an example of forming the first substrate region as a memory substrate region.
- a memory cell may be formed in the same region of the substrate 402 as the low voltage transistor 410 , as described in co-pending application Ser. No. 13/715,739.
- This approach is an example of forming the first substrate region as a combination of memory and low voltage regions.
- Such a first substrate region can be larger than the one illustrated in FIG. 4B .
- a second photoresist mask 412 is disposed.
- One way to apply the second photoresist mask 412 is a spin-coating.
- etching for example, is used to remove the portions of the poly layer 408 that are unprotected by the photoresist mask 412 .
- the etching defines a section of poly that, with a source, a drain and wiring, can serve as a high voltage transistor 414 .
- lightly doped source and drain regions 416 are implanted adjacent to the high voltage transistor 414 .
- the lightly doped regions 416 are preferably formed from an edge of the high voltage transistor 414 , or even from slightly underneath the high voltage transistor 414 , and extend to the shallow trench isolation 404 .
- the source and drain regions 416 may be a n-type lightly doped drain region (i.e., using an n ⁇ conductivity type dopant) or a p-type lightly doped drain region (i.e., using a p ⁇ conductivity type dopant).
- a doped region's status as a source or drain is determined, in part, by electrical connections commonly formed later in the manufacturing process. Therefore, while this application distinguishes between source and drain regions, the two may be considered interchangeable.
- the photoresist mask 412 is stripped.
- One advantage of removing the photoresist mask 412 at this step is that the photoresist mask 412 can he reused both for the etching in FIG. 4D and again for implanting the lightly' doped source and drain regions in FIG. 4E .
- a third photoresist mask 418 is disposed.
- etching for example, is used to remove the portions of the poly layer 408 that are unprotected by the photoresist mask 418 .
- the etching defines a section of poly that, with a source, a drain and wiring, can serve as a second high voltage transistor 420 .
- a second set of lightly doped source and drain regions 422 are implanted adjacent to the second high voltage transistor 420 .
- the second set of lightly doped regions 422 are preferably formed from an edge of the second high voltage transistor 420 , or even from slightly underneath the second high voltage transistor 420 , and extend to the shallow trench isolation 404 . It is preferred that the second set of lightly doped regions 422 are of complementary conductivity type to the first source and drain regions 416 .
- the first source and drain regions 416 are p-type lightly doped regions (i.e., using a p ⁇ conductivity type dopant)
- the second set of lightly doped regions 422 are n-type lightly doped regions (i.e., using an n ⁇ conductivity type dopant).
- the photoresist mask 418 is stripped. Similar to the second photoresist mask 412 , the third photoresist mask 418 has been used for both etching a high voltage transistor 420 and for implanting lightly doped source and drain regions 422 .
- the region of the substrate 402 to the left of the leftmost shallow trench isolation 404 A is an example of a first substrate region.
- the low voltage transistor 410 in this substrate region is an example of a first gate.
- the poly layer 408 is an example of a thin poly layer.
- the region of the substrate 402 to the right of the left most shallow trench isolation 404 A is an example of a second substrate region.
- the first high voltage transistor 414 is an example of a second gate.
- the lightly doped source and drain regions 416 adjacent to the first high voltage transistor 414 are examples of first source and drain regions substantially adjacent to the second gate.
- the second high voltage transistor 420 is an example of a third gate in the second substrate region.
- the lightly doped source and drain regions 422 adjacent to the second high voltage transistor 420 are an example of second source and drain regions being substantially adjacent to the third gate.
- steps can include, spacers, low energy source and drain implantations for the high voltage transistors 414 and 420 and low voltage transistor 410 . Additional steps include silicide, inter-metal dielectric layers, contacts, metals and the like.
- FIG. 4J shows a specific number of transistors 410 , 414 and 420 being formed, other, presumably larger, numbers of these transistors may be formed according to this process. Further, memory cells may also be formed according to one of the processes described in co-pending application Ser. No. 13/715,739.
- the high voltage transistors 414 and 420 may be formed before the low voltage transistor 410 is formed. In effect, the steps of FIGS. 4A and 4B would be moved to the end of the method.
- FIGS. 4A-4J may be applicable to analog semiconductor designs as well.
- the use of photoresists to protect thin poly from high energy implants may be relevant to analog circuitry, such as an operational amplifier, where high energy implants can be used to form transistors that will conduct amplified amounts of power, but thin poly may be desired to improve the response time of the differential amplifier.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
- 1. Technical Field
- The embodiments described herein generally relate to the manufacturing of integrated circuits.
- 2. Background
- A non-volatile memory, such as Flash memory, retains stored data even if power to the memory is removed. A non-volatile memory cell stores data, for example, by storing electrical charge in an electrically isolated floating gate or in a charge-trapping layer underlying a control gate of a field-effect transistor (FET). The stored electrical charge Controls the threshold of the FET, thereby controlling the memory state of the cell.
- It is common to monolithically incorporate multiple types of field-effect devices on the same substrate as memory cells. Those non-memory devices perform, for example, decoding, charge-pumping, and other functions related to memory operations. The substrate may also include non-memory devices to provide functions that are not related to memory operations. Such non-memory devices incorporated on the same substrate as the memory cells may include transistors tailored for high-speed operations, while other transistors are tailored for handling high operating voltages. Integrating the processing of memory cells, such as a split-gate memory cell, with the processing of one or more types of non-memory transistors on the same substrate is challenging as each requires different fabrication parameters.
- Additional types of integrated circuits, such as analog devices, pose manufacturing challenges. Many analog devices, such as a low noise amplifier, have more stringent noise tolerances than FET devices used in digital logic. Mixed signal electronics, those with integrated digital and analog signals, can be found in music players, cameras and cellular telephones. As with the memory cells, these analog devices pose fabrication challenges due to the different fabrication parameters. Accordingly, there is a need for device and methods for integrating field effect transistors and other devices on the same substrate to facilitate improved cost, performance, reliability, or manufacturability.
- It is desirable to obviate or mitigate at least one of the problems, whether identified herein or elsewhere, or to provide an alternative to existing apparatuses or methods. Embodiments described herein include methods, systems and devices for forming high voltage gates in a computer memory or other integrated circuitry.
- In particular, a method is described wherein a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and drain regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing.
- In an embodiment, a method of manufacturing a semiconductor device that includes a first substrate region and a second substrate region. A gate layer is disposed on the first and second substrate regions. A first gate is formed in the first substrate region from the gate layer. A second gate is formed in the second substrate region from the gate layer. First lightly doped source and drain regions are formed substantially adjacent to the second gate. A third gate is formed in the second substrate region from the gate layer. Second lightly doped source and drain regions are formed substantially adjacent to the third gate. In this method, the second lightly doped source and drain regions are of complementary conductivity type to the first lightly doped source and drain regions. Additionally, the third gate is formed after the first source and drain regions are formed.
- In an embodiment, a semiconductor device includes a first substrate region and a second substrate region. There is a first gate in the first substrate region. There is a second gate in the second substrate region. There is a third gate in the second substrate region. There are first lightly doped source and drain regions substantially adjacent to the second gate. There are second lightly doped source and drain regions, substantially adjacent to the third gate. In the embodiment, the second lightly doped source and drain regions are of a complementary conductivity type to the first lightly doped source and drain regions. The second gate and the third gate are configured to withstand the same amount of voltage, which is more than the first gate is configured to withstand. Additionally, the first lightly doped drain region is older than (i.e., formed before) the third gate.
- In an embodiment, a method of manufacturing a semiconductor device that includes a first substrate region and a second substrate region. A thin poly layer is disposed on the first and second substrate regions. A first gate is formed in the first substrate region from the thin poly layer. A first photoresist mask is disposed on the thin poly layer, across both the first substrate region and the second substrate region. A second gate is etched in the second substrate region through the first photoresist mask. A first high energy implant is performed through the first photoresist mask while the photoresist mask protects the poly in both the first and second substrate regions. The first photoresist mask is removed. A second photoresist mask is disposed on the thin poly layer, across both the first substrate region and the second substrate region. A third gate is etched in the second substrate region through the second photoresist mask. A second high energy implant is performed through the second photoresist mask while the photoresist mask protects the poly in both the first and second substrate regions. The second photoresist mask is removed. According to this method, lightly doped source and drain regions of complementary conductivity types can be formed without the need of a hard mask.
- These and other advantages and features will become readily apparent in view of the following detailed description of embodiments of the invention. Note that the Summary and Abstract sections may set forth one or more, but not all exemplary embodiments of the present invention as contemplated by the inventor(s). It is to he appreciated that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims.
- The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the present invention and to enable a person skilled in the relevant art(s) to make and use the present invention.
-
FIG. 1 illustrates an example of a split-gate non-volatile memory cell, according to an embodiment. -
FIG. 2 illustrates an example circuit diagram of memory cell including connections to various metal layers in a semiconductor device, according to an embodiment. -
FIG. 3 illustrates an example semiconductor device that includes both memory and peripheral circuitry embedded in the same substrate, according to an embodiment. -
FIGS. 4A-4J illustrate a semiconductor device in various stages of manufacturing, according to an embodiment. - The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.
- This specification discloses one or more embodiments that incorporate the features of this invention. The disclosed embodiment(s) merely exemplify the present invention. The scope of the present invention is not limited to the disclosed embodiment(s). The present invention is defined by the claims appended hereto.
- The embodiment(s) described, and references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
- Before describing the various embodiments in more detail, further explanation shall be given regarding certain terms that may be used throughout the descriptions.
- The term “etch” or “etching” is used herein to generally describe a fabrication process of patterning a material, such that at least a portion of the material remains after the etch is completed. For example, it should be understood that the process of etching silicon involves the steps of patterning a masking layer (e.g., photoresist or a hard mask) above the silicon, and then removing the areas of silicon no longer protected by the masking layer. As such, the areas of silicon protected by the mask would remain behind after the etch process is complete. However, in another example, etching may also refer to a process that does not use a mask, but still leaves behind at least a portion of the material after the etch process is complete.
- The above description serves to distinguish the term “etching” from “removing.” When etching a material, at least a portion of the material remains behind after the process is completed. However, “removing” is considered to be a broad term that may incorporate etching.
- During the descriptions herein, various regions of the substrate upon which the field-effect devices are fabricated are mentioned. It should be understood that these regions may exist anywhere on the substrate and furthermore that the regions may not be mutually exclusive. That is, in some embodiments, portions of one or more regions may overlap. Although up to three different regions are described herein, it should be understood that any number of regions may exist on the substrate and may designate areas having certain types of devices or materials. In general, the regions are used to conveniently describe areas of the substrate that include similar devices and should not limit the scope or spirit of the described embodiments.
- The terms “deposit” or “dispose” are used herein to describe the act of applying a layer of material to the substrate. Such terms are meant to describe any possible layer-forming technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.
- The term “substrate” as used throughout the descriptions is most commonly thought to be silicon. However, the substrate may also be any of a wide array of semiconductor materials such as germanium, gallium arsenide, indium phosphide, etc. In other embodiments, the substrate may be electrically non-conductive such as a glass or sapphire wafer.
- The term “poly” as used throughout the descriptions is most commonly thought to be polycrystalline silicon. Poly comprises multiple small crystals, as opposed to being a single monocrystal. Poly can be doped, or may have metal or a metal suicide deposited over it.
- “Poly” in this application is used as one example of a gate conductor. Other conductors may be used to form the gates, for example metals, alloys other doped semiconductors or conducting materials as would become apparent to a person having ordinary skill in the art. The use of “poly” in the description of the embodiments is not to be limiting.
- A non-volatile memory cell is programmed using, for example, hot carrier injection to place charge into a storage layer. High drain and gate voltages are used to facilitate the programming process, and the memory cell conducts relatively high current during programming, which can be undesirable in low voltage or low power applications.
- A split-gate memory cell is a type of non-volatile memory cell, in which a select gate is placed adjacent a memory gate. During programming of a split-gate memory cell, the select gate is biased at a relatively low voltage, and only the memory gate is biased at the high voltage to provide the vertical electric field necessary for hot-carrier injection. Since acceleration of the carriers takes place in the channel region mostly under the select gate, the relatively low voltage on the select gate results in more efficient carrier acceleration in the horizontal direction compared to a conventional Flash memory cell. That makes hot-carrier injection more efficient with lower current and lower power consumption during programming operation. A split-gate memory cell may be programmed using techniques other than hot-carrier injection, and depending on the technique, any advantage over the conventional Flash memory cell during programming operation may vary.
- Fast read time is another advantage of a split-gate memory cell. Because the select gate is in series with the memory gate, the erased state of the memory gate can be near or in depletion mode (i.e., threshold voltage, Vt, less than zero volt). Even when the erased memory gate is in such depletion mode, the select gate in the off state prevents the channel from conducting substantial current. With the threshold voltage of the erased state near or below zero, the threshold voltage of the programmed state does not need to be very high while still providing a reasonable read margin between erased and programmed states. Accordingly, the voltages applied to both select gate and memory gate in read operation can be less than or equal, to the supply voltage. Therefore, not having to pump the supply voltage to a higher level makes the read operation faster.
-
FIG. 1 illustrates an example of a split-gatenon-volatile memory cell 100 according to an embodiment.Memory cell 100 is formed on asubstrate 102, such as silicon.Substrate 102 is commonly p-type or a p-type well while a first doped source/drain region 104 and a second doped source/drain region 106 are n-type. However, it is also possible forsubstrate 102 to be n-type whileregions 104 and 106 are p-type. -
Memory cell 100 includes two gates, aselect gate 108 and amemory gate 110. Each gate may be a doped poly layer formed by well known, for example, deposit and etch techniques to define the gate structure.Select gate 108 is disposed over adielectric layer 112.Memory gate 110 is disposed over a charge trapping dielectric 114 having one or more dielectric layers. In one example,charge trapping dielectric 114 includes a silicon nitride layer sandwiched between two silicon dioxide layers to create a three-layer stack collectively and commonly referred to as “ONO”. Other charge trapping dielectrics may include a silicon-rich nitride film, or any film that includes, but is not limited to, silicon, oxygen, and nitrogen in various stoichiometries. Avertical dielectric 116 is also disposed betweenselect gate 108 andmemory gate 110 for electrical isolation between the two gates. In some examples,vertical dielectric 116 and charge trapping dielectric 114 are the same dielectric, while other examples form one dielectric before the other (e.g., they can have different dielectric properties.) As such,vertical dielectric 116 need not include the same film structure ascharge trapping dielectric 114. After the gates have been defined,regions 104 and 106 are created by implanting dopants using, for example, an ion implantation technique.Regions 104 and 106 form the source or drain of the split-gate transistor depending on what potentials are applied to each. In split gate transistors, for convenience, region 104 is commonly referred to as the drain, whileregion 106 is commonly referred to as the source, independent of the relative biases. It is to be understood that this description is meant to provide a general overview of a common split-gate architecture and that, in actual practice, many more detailed steps and layers are provided to form thefinal memory cell 100. - An example write, read, and erase operation will now be described as it relates to
memory cell 100. In order to write a bit inmemory cell 100, a positive voltage on the order of 5 volts, for example, is applied toregion 106 while region 104 andsubstrate 102 are grounded. A low positive voltage on the order of 1.5 volts, for example, is applied to selectgate 108 while a higher positive voltage on the order of 8 volts, for example, is applied tomemory gate 110. As electrons are accelerated within a channel region between the source and drain, some of them will acquire sufficient energy to be injected upwards and get trapped insidecharge trapping dielectric 114. This is known as hot electron injection. In one example ofcharge trapping dielectric 114, the electrons are trapped within a nitride layer ofcharge trapping dielectric 114. This nitride layer is also commonly referred to as the charge trapping layer. The trapped charge within charge trapping dielectric 114 store the “high” bit withinmemory cell 100, even after the various supply voltages are removed. - In order to “erase” the stored charge within
memory cell 100 and return the state ofmemory cell 100 to a “low” bit, a positive voltage on the order of 5 volts, for example, is applied toregion 106 while region 104 is floated or at a certain bias, andselect gate 108 andsubstrate 102 are typically grounded. A high negative voltage on the order of −8 volts, for example, is applied tomemory gate 110. The bias conditions betweenmemory gate 110 andregion 106 generate holes through band-to-band tunneling. The generated holes are sufficiently energized by the strong electric field undermemory gate 110 and are injected upwards intocharge trapping dielectric 114. The injected holes effectively erase thememory cell 100 to the “low” bit state. - In order to “read” the stored bit of
memory cell 100, a low voltage is applied to each of the select gate, memory gate, and region 104 in the range between zero and 3 volts, for example, whileregion 106 andsubstrate 102 are typically grounded. The low voltage applied to the memory gate is chosen so that it lies substantially equidistant between the threshold voltage necessary to turn on the transistor when storing a “high” bit and the threshold voltage necessary to turn on the transistor when storing a “low” bit in order to clearly distinguish between the two states. For example, if the application of the low voltage during the “read” operation caused substantial current to flow betweenregions 104 and 106, then the memory cell holds a “low” bit and if the application of the low voltage during the “read” operation does not cause substantial current to flow betweenregions 104 and 106, then the memory cell holds a “high” bit. -
FIG. 2 illustrates an example circuit diagram ofmemory cell 100 including connections to various metal layers in a semiconductor device. Only asingle memory cell 100 is illustrated, however, as evidenced by the ellipses in both the X and Y direction, an array of memory cells may be connected by the various lines running in both the X and Y directions. In this way, one ormore memory cells 100 may be selected for reading, writing, and erasing bits based on the bit line (BL) and source line (SL) used. - An example source line (SL) runs along the X direction and is formed in a first metal layer (M1). Source line (SL) may be used to make electrical connection with doped
region 106 of eachmemory cell 100 along a row extending in the X direction. - An example bit line (BL) runs along the Y direction and is formed in a second metal layer (M2). Bit line (BL) may be used to make electrical connection with doped region 104 of each
memory cell 100 along a column extending in the Y direction. - It is to be understood that the circuit connections shown in
FIG. 2 are only exemplary and that the various connections could be made in different metal layers than those illustrated. Furthermore, although not depicted,memory cells 100 may be arrayed in the Z direction as well formed within multiple stacked layers. -
FIG. 3 illustrates an example semiconductor device that includes both memory and peripheral circuitry in the same substrate. In this example,substrate 102 includes acore region 302 and aperiphery region 304.Core region 302 includes a plurality ofmemory cells 100 that may operate similarly to those previously described. It should be understood that the cross-section ofFIG. 3 is only exemplary, and thatcore region 302 andperiphery region 304 may be located in any area ofsubstrate 102 and may be made up of various different regions. Furthermore,core region 302 andperiphery region 304 may exist in the same general area ofsubstrate 102. -
Periphery region 304 may include integrated circuit components such as resistors, capacitors, inductors, etc., as well as transistors. In the illustrated embodiment,periphery region 304 includes a plurality of high-voltage transistors 306 and low-voltage transistors 308. In one example, high-voltage transistors 306 exist in a separate region ofsubstrate 102 than low-voltage transistors 308. High-voltage transistors 306 are capable of handling voltages up to 25 volts in magnitude, for example, while low-voltage transistors 308 operate at a faster speed, but cannot operate at the same high voltages as high-voltage transistors 306. In an embodiment,low voltage transistors 308 are designed to have a shorter gate length thanhigh voltage transistors 306. High-voltage transistors 306 are commonly characterized as having athicker gate dielectric 310 than the gate dielectric of low-voltage transistors 308. - With charge trapping memory, there is a desire to manufacture
low voltage transistors 308 andmemory cells 100 from a thin poly layer because the thin layer allows for improved performance. However, given that semiconductor device manufacturing generally occurs as a series of steps involving disposing layers, it would be impractical to manufacture thehigh voltage transistors 306 from a different layer of poly than thelow voltage transistors 308, thus constraining thehigh voltage transistors 306 to have the same thickness as thelow voltage transistors 308. Where thinness improves the performance of alow voltage transistor 308, thinness can leavetransistors high voltage transistors 306 receive a high energy implant to form the lightly doped drains and source. High energy implants are often performed with more than 80,000 electron volts depending on implant species. A high-energy implant to form the lightly-doped drain inhigh voltage transistors 306 can penetrate the entire thickness of the thin poly and adversely affect the doping profile of the transistor channel region below the poly gate. A thin poly layer can be from 40 nanometers (nm) to 100 nm thick, and is preferably 80 nm thick. One approach to protecting the thin poly is described in co-pending application Ser. No. 13/715,739, entitled “High Voltage Gate Formation,” which is herein incorporated by reference in its entirety. - The co-pending application's approach, however, uses a hard mask to protect against the high energy implantation. The co-pending application's approach also used three blanket resist processes to create the high voltage transistors 306 (i.e., the blanket resist to etch the
low voltage transistor 308 would be a fourth blanket resist). There may be significant cost savings if a hard mask or one of the blanket resists could be avoided. One additional manufacturing advantage to not having a hard mask is that, as poly becomes thinner, the appropriate hard masks approach becomes more difficult to make compatible with an advanced logic process flow. -
FIGS. 4A-4J collectively illustrate an example fabrication process for forming asemiconductor device 400, according to an embodiment of the present invention. It should be understood that the various layers and structures are not necessarily drawn to scale, and that other processing steps may be performed between those steps illustrated and described herein, as would be understood by one skilled in the art given the present disclosure. - Prior to the step of
FIG. 4A , many steps are required to create the structures on thesubstrate 402, such as disposing layers, masking, stripping, and the like, as would be apparent to a person having ordinary skill in the art. -
FIG. 4A illustrates asubstrate 402 comprising silicon, or the like, and shallow trench isolations 404 formed therein. Apoly layer 408 is formed on thesubstrate 402. Thepoly layer 408 is an example of a gate layer. Two instances of a photoresist mask 406 are patterned on thepoly layer 408. One way to form a photoresist is to spin on a blanket resist, use a photomask to expose certain sections of the blanket resist to ultra-violet light, and then apply a developer to the blanket resist. - In another embodiment, the gate layer can comprise a metal layer. In an embodiment employing a metal layer, a poly layer may be disposed before the metal layer is disposed. This poly layer may serve as a sacrificial gate to be replaced by a metal gate at a later step. One approach to creating a metal gate is described in co-pending application Ser. No. 11/735,241, entitled “Memory System with Poly Metal Gate,” which is herein incorporated by reference in its entirety.
- As illustrated by
FIG. 4B , etching, for example, is used to remove the portions of thepoly layer 408 that are unprotected by the photoresist mask 406. The etching defines a section of poly that, with a source, a drain and wiring, can serve as alow voltage transistor 410. The photoresist 406 is then stripped. - In another embodiment, the
low voltage transistor 410 may instead serve as a memory cell. To create a memory cell instead of thelow voltage transistor 410, it is preferred to dispose a dielectric on the region of thesubstrate 402 before disposing thepoly layer 408. If there were a dielectric underneath thelow voltage transistor 410, thelow voltage transistor 410 could serve as a select gate. As described in co-pending application Ser. No. 13/715,739, a charge trapping layer, such as ONO, could be added followed by an additional layer of poly to form a memory gate to complete the memory cell. This approach is an example of forming the first substrate region as a memory substrate region. - In another embodiment, a memory cell may be formed in the same region of the
substrate 402 as thelow voltage transistor 410, as described in co-pending application Ser. No. 13/715,739. This approach is an example of forming the first substrate region as a combination of memory and low voltage regions. Such a first substrate region can be larger than the one illustrated inFIG. 4B . - As illustrated by
FIG. 4C , a second photoresist mask 412 is disposed. One way to apply the second photoresist mask 412 is a spin-coating. - As illustrated by
FIG. 4D , etching, for example, is used to remove the portions of thepoly layer 408 that are unprotected by the photoresist mask 412. The etching defines a section of poly that, with a source, a drain and wiring, can serve as ahigh voltage transistor 414. - As illustrated by
FIG. 4E , lightly doped source and drain regions 416 are implanted adjacent to thehigh voltage transistor 414. The lightly doped regions 416 are preferably formed from an edge of thehigh voltage transistor 414, or even from slightly underneath thehigh voltage transistor 414, and extend to the shallow trench isolation 404. The source and drain regions 416 may be a n-type lightly doped drain region (i.e., using an n− conductivity type dopant) or a p-type lightly doped drain region (i.e., using a p− conductivity type dopant). A doped region's status as a source or drain is determined, in part, by electrical connections commonly formed later in the manufacturing process. Therefore, while this application distinguishes between source and drain regions, the two may be considered interchangeable. - As illustrated by FIG, 4F, the photoresist mask 412 is stripped. One advantage of removing the photoresist mask 412 at this step is that the photoresist mask 412 can he reused both for the etching in
FIG. 4D and again for implanting the lightly' doped source and drain regions inFIG. 4E . - As illustrated by
FIG. 4G , a third photoresist mask 418 is disposed. - As illustrated by FIG, 4H, etching, for example, is used to remove the portions of the
poly layer 408 that are unprotected by the photoresist mask 418. The etching defines a section of poly that, with a source, a drain and wiring, can serve as a secondhigh voltage transistor 420. - As illustrated by
FIG. 4I , a second set of lightly doped source and drain regions 422 are implanted adjacent to the secondhigh voltage transistor 420. The second set of lightly doped regions 422 are preferably formed from an edge of the secondhigh voltage transistor 420, or even from slightly underneath the secondhigh voltage transistor 420, and extend to the shallow trench isolation 404. It is preferred that the second set of lightly doped regions 422 are of complementary conductivity type to the first source and drain regions 416. For example, if the first source and drain regions 416 are p-type lightly doped regions (i.e., using a p− conductivity type dopant), then the second set of lightly doped regions 422 are n-type lightly doped regions (i.e., using an n− conductivity type dopant). - As illustrated by
FIG. 4J , the photoresist mask 418 is stripped. Similar to the second photoresist mask 412, the third photoresist mask 418 has been used for both etching ahigh voltage transistor 420 and for implanting lightly doped source and drain regions 422. - The region of the
substrate 402 to the left of the leftmostshallow trench isolation 404A is an example of a first substrate region. Thelow voltage transistor 410 in this substrate region is an example of a first gate. Thepoly layer 408 is an example of a thin poly layer. The region of thesubstrate 402 to the right of the left mostshallow trench isolation 404A is an example of a second substrate region. The firsthigh voltage transistor 414 is an example of a second gate. The lightly doped source and drain regions 416 adjacent to the firsthigh voltage transistor 414 are examples of first source and drain regions substantially adjacent to the second gate. The secondhigh voltage transistor 420 is an example of a third gate in the second substrate region. The lightly doped source and drain regions 422 adjacent to the secondhigh voltage transistor 420 are an example of second source and drain regions being substantially adjacent to the third gate. - Following the step of
FIG. 4J , traditional manufacturing steps may be performed. These steps can include, spacers, low energy source and drain implantations for thehigh voltage transistors low voltage transistor 410. Additional steps include silicide, inter-metal dielectric layers, contacts, metals and the like. - Though
FIG. 4J shows a specific number oftransistors - In an alternate method to the one illustrated in
FIGS. 4A-4J , thehigh voltage transistors low voltage transistor 410 is formed. In effect, the steps ofFIGS. 4A and 4B would be moved to the end of the method. - The techniques described with reference to
FIGS. 4A-4J may be applicable to analog semiconductor designs as well. In particular, the use of photoresists to protect thin poly from high energy implants may be relevant to analog circuitry, such as an operational amplifier, where high energy implants can be used to form transistors that will conduct amplified amounts of power, but thin poly may be desired to improve the response time of the differential amplifier. - Embodiments of the present invention have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
- The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
- The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (20)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/756,134 US20140210012A1 (en) | 2013-01-31 | 2013-01-31 | Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions |
JP2015556129A JP6581507B2 (en) | 2013-01-31 | 2014-01-30 | Fabrication of FET devices with lightly doped drain and source regions |
PCT/US2014/013853 WO2014120924A1 (en) | 2013-01-31 | 2014-01-30 | Manufacturing of fet devices having lightly doped drain and source regions |
EP14746768.2A EP2951857A4 (en) | 2013-01-31 | 2014-01-30 | Manufacturing of fet devices having lightly doped drain and source regions |
US15/487,141 US10177040B2 (en) | 2013-01-31 | 2017-04-13 | Manufacturing of FET devices having lightly doped drain and source regions |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/756,134 US20140210012A1 (en) | 2013-01-31 | 2013-01-31 | Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/487,141 Division US10177040B2 (en) | 2013-01-31 | 2017-04-13 | Manufacturing of FET devices having lightly doped drain and source regions |
Publications (1)
Publication Number | Publication Date |
---|---|
US20140210012A1 true US20140210012A1 (en) | 2014-07-31 |
Family
ID=51222001
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/756,134 Abandoned US20140210012A1 (en) | 2013-01-31 | 2013-01-31 | Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions |
US15/487,141 Active US10177040B2 (en) | 2013-01-31 | 2017-04-13 | Manufacturing of FET devices having lightly doped drain and source regions |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/487,141 Active US10177040B2 (en) | 2013-01-31 | 2017-04-13 | Manufacturing of FET devices having lightly doped drain and source regions |
Country Status (4)
Country | Link |
---|---|
US (2) | US20140210012A1 (en) |
EP (1) | EP2951857A4 (en) |
JP (1) | JP6581507B2 (en) |
WO (1) | WO2014120924A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180219018A1 (en) * | 2015-11-05 | 2018-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nitride-free spacer or oxide spacer for embedded flash memory |
KR20190122345A (en) * | 2018-04-20 | 2019-10-30 | 삼성전자주식회사 | Vertical-type memory device |
CN110785845A (en) * | 2017-07-19 | 2020-02-11 | 赛普拉斯半导体公司 | Embedded non-volatile memory device and method of manufacturing the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070187797A1 (en) * | 2006-02-14 | 2007-08-16 | Yoshiko Kato | Semiconductor device and method of manufacturing the same |
US20100144108A1 (en) * | 2004-06-30 | 2010-06-10 | Takeshi Sakai | Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61225859A (en) | 1985-03-29 | 1986-10-07 | Sharp Corp | Manufacture of complementary mos semiconductor device |
JPS6276668A (en) * | 1985-09-30 | 1987-04-08 | Toshiba Corp | Semiconductor memory device |
US5023190A (en) * | 1990-08-03 | 1991-06-11 | Micron Technology, Inc. | CMOS processes |
JP3030963B2 (en) * | 1991-08-23 | 2000-04-10 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US6346439B1 (en) * | 1996-07-09 | 2002-02-12 | Micron Technology, Inc. | Semiconductor transistor devices and methods for forming semiconductor transistor devices |
US5824584A (en) | 1997-06-16 | 1998-10-20 | Motorola, Inc. | Method of making and accessing split gate memory device |
US5969383A (en) | 1997-06-16 | 1999-10-19 | Motorola, Inc. | Split-gate memory device and method for accessing the same |
TW473834B (en) * | 1998-05-01 | 2002-01-21 | Ibm | Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor |
US6103559A (en) * | 1999-03-30 | 2000-08-15 | Amd, Inc. (Advanced Micro Devices) | Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication |
US7560779B2 (en) * | 1999-11-30 | 2009-07-14 | Texas Instruments Incorporated | Method for forming a mixed voltage circuit having complementary devices |
JP2002118177A (en) * | 2000-10-11 | 2002-04-19 | Toshiba Corp | Semiconductor device and its fabricating method |
TW546840B (en) | 2001-07-27 | 2003-08-11 | Hitachi Ltd | Non-volatile semiconductor memory device |
JP4601287B2 (en) | 2002-12-26 | 2010-12-22 | ルネサスエレクトロニクス株式会社 | Nonvolatile semiconductor memory device |
JP4546117B2 (en) | 2004-03-10 | 2010-09-15 | ルネサスエレクトロニクス株式会社 | Nonvolatile semiconductor memory device |
JP2006041354A (en) | 2004-07-29 | 2006-02-09 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
JP5116987B2 (en) | 2005-05-23 | 2013-01-09 | ルネサスエレクトロニクス株式会社 | Integrated semiconductor nonvolatile memory device |
JP4659527B2 (en) | 2005-06-20 | 2011-03-30 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
CN100442476C (en) | 2005-09-29 | 2008-12-10 | 中芯国际集成电路制造(上海)有限公司 | Nano-device with enhanced strain inductive transferring rate for CMOS technology and its process |
JP2007194511A (en) | 2006-01-23 | 2007-08-02 | Renesas Technology Corp | Non-volatile semiconductor memory device and method for manufacturing the same |
CN101034671B (en) * | 2006-03-02 | 2010-12-08 | 沃特拉半导体公司 | Lateral double-diffused mosfet (LDMOS) transistor and a method of fabricating the same |
JP4928825B2 (en) | 2006-05-10 | 2012-05-09 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP5278320B2 (en) * | 2007-07-31 | 2013-09-04 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
JP5315779B2 (en) * | 2008-05-09 | 2013-10-16 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
KR20100012643A (en) * | 2008-07-29 | 2010-02-08 | 주식회사 동부하이텍 | Method for manufacturing of image sensor |
JP5550286B2 (en) * | 2009-08-26 | 2014-07-16 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP5538828B2 (en) * | 2009-11-11 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
JP2011181124A (en) | 2010-02-26 | 2011-09-15 | Renesas Electronics Corp | Nonvolatile semiconductor memory device and operation method thereof |
US9368606B2 (en) * | 2012-12-14 | 2016-06-14 | Cypress Semiconductor Corporation | Memory first process flow and device |
JP6276668B2 (en) | 2014-09-02 | 2018-02-07 | 株式会社日立製作所 | Failure analysis system |
-
2013
- 2013-01-31 US US13/756,134 patent/US20140210012A1/en not_active Abandoned
-
2014
- 2014-01-30 JP JP2015556129A patent/JP6581507B2/en active Active
- 2014-01-30 EP EP14746768.2A patent/EP2951857A4/en not_active Withdrawn
- 2014-01-30 WO PCT/US2014/013853 patent/WO2014120924A1/en active Application Filing
-
2017
- 2017-04-13 US US15/487,141 patent/US10177040B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100144108A1 (en) * | 2004-06-30 | 2010-06-10 | Takeshi Sakai | Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device |
US20070187797A1 (en) * | 2006-02-14 | 2007-08-16 | Yoshiko Kato | Semiconductor device and method of manufacturing the same |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180219018A1 (en) * | 2015-11-05 | 2018-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nitride-free spacer or oxide spacer for embedded flash memory |
US10347649B2 (en) * | 2015-11-05 | 2019-07-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nitride-free spacer or oxide spacer for embedded flash memory |
US10475805B2 (en) | 2015-11-05 | 2019-11-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nitride-free spacer or oxide spacer for embedded flash memory |
US10847530B2 (en) | 2015-11-05 | 2020-11-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nitride-free spacer or oxide spacer for embedded flash memory |
US11264400B2 (en) | 2015-11-05 | 2022-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-free spacer or oxide spacer for embedded flash memory |
CN110785845A (en) * | 2017-07-19 | 2020-02-11 | 赛普拉斯半导体公司 | Embedded non-volatile memory device and method of manufacturing the same |
KR20190122345A (en) * | 2018-04-20 | 2019-10-30 | 삼성전자주식회사 | Vertical-type memory device |
US10950620B2 (en) * | 2018-04-20 | 2021-03-16 | Samsung Electronics Co., Ltd. | Vertical-type memory device |
KR102600999B1 (en) | 2018-04-20 | 2023-11-13 | 삼성전자주식회사 | Vertical-type memory device |
Also Published As
Publication number | Publication date |
---|---|
JP6581507B2 (en) | 2019-09-25 |
US10177040B2 (en) | 2019-01-08 |
EP2951857A4 (en) | 2016-11-23 |
WO2014120924A1 (en) | 2014-08-07 |
EP2951857A1 (en) | 2015-12-09 |
US20170221768A1 (en) | 2017-08-03 |
JP2016511540A (en) | 2016-04-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20150140766A1 (en) | Method of forming and structure of a non-volatile memory cell | |
US9368606B2 (en) | Memory first process flow and device | |
US9922833B2 (en) | Charge trapping split gate embedded flash memory and associated methods | |
US10923601B2 (en) | Charge trapping split gate device and method of fabricating same | |
US20160218113A1 (en) | Integrated Circuits with Non-Volatile Memory and Methods for Manufacture | |
US10177040B2 (en) | Manufacturing of FET devices having lightly doped drain and source regions | |
JP2009049300A (en) | Manufacturing method of semiconductor storage device | |
US8822289B2 (en) | High voltage gate formation | |
US20160218227A1 (en) | Gate Formation Memory by Planarization | |
US9209197B2 (en) | Memory gate landing pad made from dummy features | |
US11450680B2 (en) | Split gate charge trapping memory cells having different select gate and memory gate heights | |
US20140167136A1 (en) | Charge Trapping Device with Improved Select Gate to Memory Gate Isoloation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SPANSION LLC, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FANG, SHENQING;KIM, UNSOON;REEL/FRAME:029743/0192 Effective date: 20130129 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., NEW YORK Free format text: SECURITY INTEREST;ASSIGNORS:CYPRESS SEMICONDUCTOR CORPORATION;SPANSION LLC;REEL/FRAME:035240/0429 Effective date: 20150312 |
|
AS | Assignment |
Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SPANSION LLC;REEL/FRAME:035945/0766 Effective date: 20150601 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., NEW YORK Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST;ASSIGNORS:CYPRESS SEMICONDUCTOR CORPORATION;SPANSION LLC;REEL/FRAME:058002/0470 Effective date: 20150312 |